1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * iio/adc/max1027.c 4 * Copyright (C) 2014 Philippe Reynes 5 * 6 * based on linux/drivers/iio/ad7923.c 7 * Copyright 2011 Analog Devices Inc (from AD7923 Driver) 8 * Copyright 2012 CS Systemes d'Information 9 * 10 * max1027.c 11 * 12 * Partial support for max1027 and similar chips. 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/spi/spi.h> 18 #include <linux/delay.h> 19 20 #include <linux/iio/iio.h> 21 #include <linux/iio/buffer.h> 22 #include <linux/iio/trigger.h> 23 #include <linux/iio/trigger_consumer.h> 24 #include <linux/iio/triggered_buffer.h> 25 26 #define MAX1027_CONV_REG BIT(7) 27 #define MAX1027_SETUP_REG BIT(6) 28 #define MAX1027_AVG_REG BIT(5) 29 #define MAX1027_RST_REG BIT(4) 30 31 /* conversion register */ 32 #define MAX1027_TEMP BIT(0) 33 #define MAX1027_SCAN_0_N (0x00 << 1) 34 #define MAX1027_SCAN_N_M (0x01 << 1) 35 #define MAX1027_SCAN_N (0x02 << 1) 36 #define MAX1027_NOSCAN (0x03 << 1) 37 #define MAX1027_CHAN(n) ((n) << 3) 38 39 /* setup register */ 40 #define MAX1027_UNIPOLAR 0x02 41 #define MAX1027_BIPOLAR 0x03 42 #define MAX1027_REF_MODE0 (0x00 << 2) 43 #define MAX1027_REF_MODE1 (0x01 << 2) 44 #define MAX1027_REF_MODE2 (0x02 << 2) 45 #define MAX1027_REF_MODE3 (0x03 << 2) 46 #define MAX1027_CKS_MODE0 (0x00 << 4) 47 #define MAX1027_CKS_MODE1 (0x01 << 4) 48 #define MAX1027_CKS_MODE2 (0x02 << 4) 49 #define MAX1027_CKS_MODE3 (0x03 << 4) 50 51 /* averaging register */ 52 #define MAX1027_NSCAN_4 0x00 53 #define MAX1027_NSCAN_8 0x01 54 #define MAX1027_NSCAN_12 0x02 55 #define MAX1027_NSCAN_16 0x03 56 #define MAX1027_NAVG_4 (0x00 << 2) 57 #define MAX1027_NAVG_8 (0x01 << 2) 58 #define MAX1027_NAVG_16 (0x02 << 2) 59 #define MAX1027_NAVG_32 (0x03 << 2) 60 #define MAX1027_AVG_EN BIT(4) 61 62 enum max1027_id { 63 max1027, 64 max1029, 65 max1031, 66 max1227, 67 max1229, 68 max1231, 69 }; 70 71 static const struct spi_device_id max1027_id[] = { 72 {"max1027", max1027}, 73 {"max1029", max1029}, 74 {"max1031", max1031}, 75 {"max1227", max1227}, 76 {"max1229", max1229}, 77 {"max1231", max1231}, 78 {} 79 }; 80 MODULE_DEVICE_TABLE(spi, max1027_id); 81 82 #ifdef CONFIG_OF 83 static const struct of_device_id max1027_adc_dt_ids[] = { 84 { .compatible = "maxim,max1027" }, 85 { .compatible = "maxim,max1029" }, 86 { .compatible = "maxim,max1031" }, 87 { .compatible = "maxim,max1227" }, 88 { .compatible = "maxim,max1229" }, 89 { .compatible = "maxim,max1231" }, 90 {}, 91 }; 92 MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids); 93 #endif 94 95 #define MAX1027_V_CHAN(index, depth) \ 96 { \ 97 .type = IIO_VOLTAGE, \ 98 .indexed = 1, \ 99 .channel = index, \ 100 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 101 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 102 .scan_index = index + 1, \ 103 .scan_type = { \ 104 .sign = 'u', \ 105 .realbits = depth, \ 106 .storagebits = 16, \ 107 .shift = 2, \ 108 .endianness = IIO_BE, \ 109 }, \ 110 } 111 112 #define MAX1027_T_CHAN \ 113 { \ 114 .type = IIO_TEMP, \ 115 .channel = 0, \ 116 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 117 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 118 .scan_index = 0, \ 119 .scan_type = { \ 120 .sign = 'u', \ 121 .realbits = 12, \ 122 .storagebits = 16, \ 123 .endianness = IIO_BE, \ 124 }, \ 125 } 126 127 #define MAX1X27_CHANNELS(depth) \ 128 MAX1027_T_CHAN, \ 129 MAX1027_V_CHAN(0, depth), \ 130 MAX1027_V_CHAN(1, depth), \ 131 MAX1027_V_CHAN(2, depth), \ 132 MAX1027_V_CHAN(3, depth), \ 133 MAX1027_V_CHAN(4, depth), \ 134 MAX1027_V_CHAN(5, depth), \ 135 MAX1027_V_CHAN(6, depth), \ 136 MAX1027_V_CHAN(7, depth) 137 138 #define MAX1X29_CHANNELS(depth) \ 139 MAX1X27_CHANNELS(depth), \ 140 MAX1027_V_CHAN(8, depth), \ 141 MAX1027_V_CHAN(9, depth), \ 142 MAX1027_V_CHAN(10, depth), \ 143 MAX1027_V_CHAN(11, depth) 144 145 #define MAX1X31_CHANNELS(depth) \ 146 MAX1X27_CHANNELS(depth), \ 147 MAX1X29_CHANNELS(depth), \ 148 MAX1027_V_CHAN(12, depth), \ 149 MAX1027_V_CHAN(13, depth), \ 150 MAX1027_V_CHAN(14, depth), \ 151 MAX1027_V_CHAN(15, depth) 152 153 static const struct iio_chan_spec max1027_channels[] = { 154 MAX1X27_CHANNELS(10), 155 }; 156 157 static const struct iio_chan_spec max1029_channels[] = { 158 MAX1X29_CHANNELS(10), 159 }; 160 161 static const struct iio_chan_spec max1031_channels[] = { 162 MAX1X31_CHANNELS(10), 163 }; 164 165 static const struct iio_chan_spec max1227_channels[] = { 166 MAX1X27_CHANNELS(12), 167 }; 168 169 static const struct iio_chan_spec max1229_channels[] = { 170 MAX1X29_CHANNELS(12), 171 }; 172 173 static const struct iio_chan_spec max1231_channels[] = { 174 MAX1X31_CHANNELS(12), 175 }; 176 177 static const unsigned long max1027_available_scan_masks[] = { 178 0x000001ff, 179 0x00000000, 180 }; 181 182 static const unsigned long max1029_available_scan_masks[] = { 183 0x00001fff, 184 0x00000000, 185 }; 186 187 static const unsigned long max1031_available_scan_masks[] = { 188 0x0001ffff, 189 0x00000000, 190 }; 191 192 struct max1027_chip_info { 193 const struct iio_chan_spec *channels; 194 unsigned int num_channels; 195 const unsigned long *available_scan_masks; 196 }; 197 198 static const struct max1027_chip_info max1027_chip_info_tbl[] = { 199 [max1027] = { 200 .channels = max1027_channels, 201 .num_channels = ARRAY_SIZE(max1027_channels), 202 .available_scan_masks = max1027_available_scan_masks, 203 }, 204 [max1029] = { 205 .channels = max1029_channels, 206 .num_channels = ARRAY_SIZE(max1029_channels), 207 .available_scan_masks = max1029_available_scan_masks, 208 }, 209 [max1031] = { 210 .channels = max1031_channels, 211 .num_channels = ARRAY_SIZE(max1031_channels), 212 .available_scan_masks = max1031_available_scan_masks, 213 }, 214 [max1227] = { 215 .channels = max1227_channels, 216 .num_channels = ARRAY_SIZE(max1227_channels), 217 .available_scan_masks = max1027_available_scan_masks, 218 }, 219 [max1229] = { 220 .channels = max1229_channels, 221 .num_channels = ARRAY_SIZE(max1229_channels), 222 .available_scan_masks = max1029_available_scan_masks, 223 }, 224 [max1231] = { 225 .channels = max1231_channels, 226 .num_channels = ARRAY_SIZE(max1231_channels), 227 .available_scan_masks = max1031_available_scan_masks, 228 }, 229 }; 230 231 struct max1027_state { 232 const struct max1027_chip_info *info; 233 struct spi_device *spi; 234 struct iio_trigger *trig; 235 __be16 *buffer; 236 struct mutex lock; 237 238 u8 reg ____cacheline_aligned; 239 }; 240 241 static int max1027_read_single_value(struct iio_dev *indio_dev, 242 struct iio_chan_spec const *chan, 243 int *val) 244 { 245 int ret; 246 struct max1027_state *st = iio_priv(indio_dev); 247 248 if (iio_buffer_enabled(indio_dev)) { 249 dev_warn(&indio_dev->dev, "trigger mode already enabled"); 250 return -EBUSY; 251 } 252 253 /* Start acquisition on conversion register write */ 254 st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2 | MAX1027_CKS_MODE2; 255 ret = spi_write(st->spi, &st->reg, 1); 256 if (ret < 0) { 257 dev_err(&indio_dev->dev, 258 "Failed to configure setup register\n"); 259 return ret; 260 } 261 262 /* Configure conversion register with the requested chan */ 263 st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) | 264 MAX1027_NOSCAN; 265 if (chan->type == IIO_TEMP) 266 st->reg |= MAX1027_TEMP; 267 ret = spi_write(st->spi, &st->reg, 1); 268 if (ret < 0) { 269 dev_err(&indio_dev->dev, 270 "Failed to configure conversion register\n"); 271 return ret; 272 } 273 274 /* 275 * For an unknown reason, when we use the mode "10" (write 276 * conversion register), the interrupt doesn't occur every time. 277 * So we just wait 1 ms. 278 */ 279 mdelay(1); 280 281 /* Read result */ 282 ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2); 283 if (ret < 0) 284 return ret; 285 286 *val = be16_to_cpu(st->buffer[0]); 287 288 return IIO_VAL_INT; 289 } 290 291 static int max1027_read_raw(struct iio_dev *indio_dev, 292 struct iio_chan_spec const *chan, 293 int *val, int *val2, long mask) 294 { 295 int ret = 0; 296 struct max1027_state *st = iio_priv(indio_dev); 297 298 mutex_lock(&st->lock); 299 300 switch (mask) { 301 case IIO_CHAN_INFO_RAW: 302 ret = max1027_read_single_value(indio_dev, chan, val); 303 break; 304 case IIO_CHAN_INFO_SCALE: 305 switch (chan->type) { 306 case IIO_TEMP: 307 *val = 1; 308 *val2 = 8; 309 ret = IIO_VAL_FRACTIONAL; 310 break; 311 case IIO_VOLTAGE: 312 *val = 2500; 313 *val2 = chan->scan_type.realbits; 314 ret = IIO_VAL_FRACTIONAL_LOG2; 315 break; 316 default: 317 ret = -EINVAL; 318 break; 319 } 320 break; 321 default: 322 ret = -EINVAL; 323 break; 324 } 325 326 mutex_unlock(&st->lock); 327 328 return ret; 329 } 330 331 static int max1027_debugfs_reg_access(struct iio_dev *indio_dev, 332 unsigned reg, unsigned writeval, 333 unsigned *readval) 334 { 335 struct max1027_state *st = iio_priv(indio_dev); 336 u8 *val = (u8 *)st->buffer; 337 338 if (readval) { 339 int ret = spi_read(st->spi, val, 2); 340 *readval = be16_to_cpu(st->buffer[0]); 341 return ret; 342 } 343 344 *val = (u8)writeval; 345 return spi_write(st->spi, val, 1); 346 } 347 348 static int max1027_validate_trigger(struct iio_dev *indio_dev, 349 struct iio_trigger *trig) 350 { 351 struct max1027_state *st = iio_priv(indio_dev); 352 353 if (st->trig != trig) 354 return -EINVAL; 355 356 return 0; 357 } 358 359 static int max1027_set_trigger_state(struct iio_trigger *trig, bool state) 360 { 361 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 362 struct max1027_state *st = iio_priv(indio_dev); 363 int ret; 364 365 if (state) { 366 /* Start acquisition on cnvst */ 367 st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE0 | 368 MAX1027_REF_MODE2; 369 ret = spi_write(st->spi, &st->reg, 1); 370 if (ret < 0) 371 return ret; 372 373 /* Scan from 0 to max */ 374 st->reg = MAX1027_CONV_REG | MAX1027_CHAN(0) | 375 MAX1027_SCAN_N_M | MAX1027_TEMP; 376 ret = spi_write(st->spi, &st->reg, 1); 377 if (ret < 0) 378 return ret; 379 } else { 380 /* Start acquisition on conversion register write */ 381 st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE2 | 382 MAX1027_REF_MODE2; 383 ret = spi_write(st->spi, &st->reg, 1); 384 if (ret < 0) 385 return ret; 386 } 387 388 return 0; 389 } 390 391 static irqreturn_t max1027_trigger_handler(int irq, void *private) 392 { 393 struct iio_poll_func *pf = private; 394 struct iio_dev *indio_dev = pf->indio_dev; 395 struct max1027_state *st = iio_priv(indio_dev); 396 397 pr_debug("%s(irq=%d, private=0x%p)\n", __func__, irq, private); 398 399 /* fill buffer with all channel */ 400 spi_read(st->spi, st->buffer, indio_dev->masklength * 2); 401 402 iio_push_to_buffers(indio_dev, st->buffer); 403 404 iio_trigger_notify_done(indio_dev->trig); 405 406 return IRQ_HANDLED; 407 } 408 409 static const struct iio_trigger_ops max1027_trigger_ops = { 410 .validate_device = &iio_trigger_validate_own_device, 411 .set_trigger_state = &max1027_set_trigger_state, 412 }; 413 414 static const struct iio_info max1027_info = { 415 .read_raw = &max1027_read_raw, 416 .validate_trigger = &max1027_validate_trigger, 417 .debugfs_reg_access = &max1027_debugfs_reg_access, 418 }; 419 420 static int max1027_probe(struct spi_device *spi) 421 { 422 int ret; 423 struct iio_dev *indio_dev; 424 struct max1027_state *st; 425 426 pr_debug("%s: probe(spi = 0x%p)\n", __func__, spi); 427 428 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 429 if (indio_dev == NULL) { 430 pr_err("Can't allocate iio device\n"); 431 return -ENOMEM; 432 } 433 434 spi_set_drvdata(spi, indio_dev); 435 436 st = iio_priv(indio_dev); 437 st->spi = spi; 438 st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data]; 439 440 mutex_init(&st->lock); 441 442 indio_dev->name = spi_get_device_id(spi)->name; 443 indio_dev->dev.parent = &spi->dev; 444 indio_dev->dev.of_node = spi->dev.of_node; 445 indio_dev->info = &max1027_info; 446 indio_dev->modes = INDIO_DIRECT_MODE; 447 indio_dev->channels = st->info->channels; 448 indio_dev->num_channels = st->info->num_channels; 449 indio_dev->available_scan_masks = st->info->available_scan_masks; 450 451 st->buffer = devm_kmalloc_array(&indio_dev->dev, 452 indio_dev->num_channels, 2, 453 GFP_KERNEL); 454 if (st->buffer == NULL) { 455 dev_err(&indio_dev->dev, "Can't allocate buffer\n"); 456 return -ENOMEM; 457 } 458 459 if (spi->irq) { 460 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, 461 &iio_pollfunc_store_time, 462 &max1027_trigger_handler, 463 NULL); 464 if (ret < 0) { 465 dev_err(&indio_dev->dev, "Failed to setup buffer\n"); 466 return ret; 467 } 468 469 st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger", 470 indio_dev->name); 471 if (st->trig == NULL) { 472 ret = -ENOMEM; 473 dev_err(&indio_dev->dev, 474 "Failed to allocate iio trigger\n"); 475 return ret; 476 } 477 478 st->trig->ops = &max1027_trigger_ops; 479 st->trig->dev.parent = &spi->dev; 480 iio_trigger_set_drvdata(st->trig, indio_dev); 481 iio_trigger_register(st->trig); 482 483 ret = devm_request_threaded_irq(&spi->dev, spi->irq, 484 iio_trigger_generic_data_rdy_poll, 485 NULL, 486 IRQF_TRIGGER_FALLING, 487 spi->dev.driver->name, 488 st->trig); 489 if (ret < 0) { 490 dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n"); 491 return ret; 492 } 493 } 494 495 /* Internal reset */ 496 st->reg = MAX1027_RST_REG; 497 ret = spi_write(st->spi, &st->reg, 1); 498 if (ret < 0) { 499 dev_err(&indio_dev->dev, "Failed to reset the ADC\n"); 500 return ret; 501 } 502 503 /* Disable averaging */ 504 st->reg = MAX1027_AVG_REG; 505 ret = spi_write(st->spi, &st->reg, 1); 506 if (ret < 0) { 507 dev_err(&indio_dev->dev, "Failed to configure averaging register\n"); 508 return ret; 509 } 510 511 return devm_iio_device_register(&spi->dev, indio_dev); 512 } 513 514 static struct spi_driver max1027_driver = { 515 .driver = { 516 .name = "max1027", 517 .of_match_table = of_match_ptr(max1027_adc_dt_ids), 518 }, 519 .probe = max1027_probe, 520 .id_table = max1027_id, 521 }; 522 module_spi_driver(max1027_driver); 523 524 MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>"); 525 MODULE_DESCRIPTION("MAX1X27/MAX1X29/MAX1X31 ADC"); 526 MODULE_LICENSE("GPL v2"); 527