1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * lpc32xx_adc.c - Support for ADC in LPC32XX 4 * 5 * 3-channel, 10-bit ADC 6 * 7 * Copyright (C) 2011, 2012 Roland Stigge <stigge@antcom.de> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/interrupt.h> 13 #include <linux/device.h> 14 #include <linux/kernel.h> 15 #include <linux/slab.h> 16 #include <linux/io.h> 17 #include <linux/clk.h> 18 #include <linux/err.h> 19 #include <linux/completion.h> 20 #include <linux/of.h> 21 22 #include <linux/iio/iio.h> 23 #include <linux/iio/sysfs.h> 24 25 /* 26 * LPC32XX registers definitions 27 */ 28 #define LPC32XXAD_SELECT(x) ((x) + 0x04) 29 #define LPC32XXAD_CTRL(x) ((x) + 0x08) 30 #define LPC32XXAD_VALUE(x) ((x) + 0x48) 31 32 /* Bit definitions for LPC32XXAD_SELECT: */ 33 /* constant, always write this value! */ 34 #define LPC32XXAD_REFm 0x00000200 35 /* constant, always write this value! */ 36 #define LPC32XXAD_REFp 0x00000080 37 /* multiple of this is the channel number: 0, 1, 2 */ 38 #define LPC32XXAD_IN 0x00000010 39 /* constant, always write this value! */ 40 #define LPC32XXAD_INTERNAL 0x00000004 41 42 /* Bit definitions for LPC32XXAD_CTRL: */ 43 #define LPC32XXAD_STROBE 0x00000002 44 #define LPC32XXAD_PDN_CTRL 0x00000004 45 46 /* Bit definitions for LPC32XXAD_VALUE: */ 47 #define LPC32XXAD_VALUE_MASK 0x000003FF 48 49 #define LPC32XXAD_NAME "lpc32xx-adc" 50 51 struct lpc32xx_adc_state { 52 void __iomem *adc_base; 53 struct clk *clk; 54 struct completion completion; 55 56 u32 value; 57 }; 58 59 static int lpc32xx_read_raw(struct iio_dev *indio_dev, 60 struct iio_chan_spec const *chan, 61 int *val, 62 int *val2, 63 long mask) 64 { 65 struct lpc32xx_adc_state *st = iio_priv(indio_dev); 66 int ret; 67 if (mask == IIO_CHAN_INFO_RAW) { 68 mutex_lock(&indio_dev->mlock); 69 ret = clk_prepare_enable(st->clk); 70 if (ret) { 71 mutex_unlock(&indio_dev->mlock); 72 return ret; 73 } 74 /* Measurement setup */ 75 __raw_writel(LPC32XXAD_INTERNAL | (chan->address) | 76 LPC32XXAD_REFp | LPC32XXAD_REFm, 77 LPC32XXAD_SELECT(st->adc_base)); 78 /* Trigger conversion */ 79 __raw_writel(LPC32XXAD_PDN_CTRL | LPC32XXAD_STROBE, 80 LPC32XXAD_CTRL(st->adc_base)); 81 wait_for_completion(&st->completion); /* set by ISR */ 82 clk_disable_unprepare(st->clk); 83 *val = st->value; 84 mutex_unlock(&indio_dev->mlock); 85 86 return IIO_VAL_INT; 87 } 88 89 return -EINVAL; 90 } 91 92 static const struct iio_info lpc32xx_adc_iio_info = { 93 .read_raw = &lpc32xx_read_raw, 94 }; 95 96 #define LPC32XX_ADC_CHANNEL(_index) { \ 97 .type = IIO_VOLTAGE, \ 98 .indexed = 1, \ 99 .channel = _index, \ 100 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 101 .address = LPC32XXAD_IN * _index, \ 102 .scan_index = _index, \ 103 } 104 105 static const struct iio_chan_spec lpc32xx_adc_iio_channels[] = { 106 LPC32XX_ADC_CHANNEL(0), 107 LPC32XX_ADC_CHANNEL(1), 108 LPC32XX_ADC_CHANNEL(2), 109 }; 110 111 static irqreturn_t lpc32xx_adc_isr(int irq, void *dev_id) 112 { 113 struct lpc32xx_adc_state *st = dev_id; 114 115 /* Read value and clear irq */ 116 st->value = __raw_readl(LPC32XXAD_VALUE(st->adc_base)) & 117 LPC32XXAD_VALUE_MASK; 118 complete(&st->completion); 119 120 return IRQ_HANDLED; 121 } 122 123 static int lpc32xx_adc_probe(struct platform_device *pdev) 124 { 125 struct lpc32xx_adc_state *st = NULL; 126 struct resource *res; 127 int retval = -ENODEV; 128 struct iio_dev *iodev = NULL; 129 int irq; 130 131 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 132 if (!res) { 133 dev_err(&pdev->dev, "failed to get platform I/O memory\n"); 134 return -ENXIO; 135 } 136 137 iodev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); 138 if (!iodev) 139 return -ENOMEM; 140 141 st = iio_priv(iodev); 142 143 st->adc_base = devm_ioremap(&pdev->dev, res->start, 144 resource_size(res)); 145 if (!st->adc_base) { 146 dev_err(&pdev->dev, "failed mapping memory\n"); 147 return -EBUSY; 148 } 149 150 st->clk = devm_clk_get(&pdev->dev, NULL); 151 if (IS_ERR(st->clk)) { 152 dev_err(&pdev->dev, "failed getting clock\n"); 153 return PTR_ERR(st->clk); 154 } 155 156 irq = platform_get_irq(pdev, 0); 157 if (irq <= 0) { 158 dev_err(&pdev->dev, "failed getting interrupt resource\n"); 159 return -ENXIO; 160 } 161 162 retval = devm_request_irq(&pdev->dev, irq, lpc32xx_adc_isr, 0, 163 LPC32XXAD_NAME, st); 164 if (retval < 0) { 165 dev_err(&pdev->dev, "failed requesting interrupt\n"); 166 return retval; 167 } 168 169 platform_set_drvdata(pdev, iodev); 170 171 init_completion(&st->completion); 172 173 iodev->name = LPC32XXAD_NAME; 174 iodev->dev.parent = &pdev->dev; 175 iodev->info = &lpc32xx_adc_iio_info; 176 iodev->modes = INDIO_DIRECT_MODE; 177 iodev->channels = lpc32xx_adc_iio_channels; 178 iodev->num_channels = ARRAY_SIZE(lpc32xx_adc_iio_channels); 179 180 retval = devm_iio_device_register(&pdev->dev, iodev); 181 if (retval) 182 return retval; 183 184 dev_info(&pdev->dev, "LPC32XX ADC driver loaded, IRQ %d\n", irq); 185 186 return 0; 187 } 188 189 #ifdef CONFIG_OF 190 static const struct of_device_id lpc32xx_adc_match[] = { 191 { .compatible = "nxp,lpc3220-adc" }, 192 {}, 193 }; 194 MODULE_DEVICE_TABLE(of, lpc32xx_adc_match); 195 #endif 196 197 static struct platform_driver lpc32xx_adc_driver = { 198 .probe = lpc32xx_adc_probe, 199 .driver = { 200 .name = LPC32XXAD_NAME, 201 .of_match_table = of_match_ptr(lpc32xx_adc_match), 202 }, 203 }; 204 205 module_platform_driver(lpc32xx_adc_driver); 206 207 MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); 208 MODULE_DESCRIPTION("LPC32XX ADC driver"); 209 MODULE_LICENSE("GPL"); 210