1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * NXP i.MX8QXP ADC driver 4 * 5 * Based on the work of Haibo Chen <haibo.chen@nxp.com> 6 * The initial developer of the original code is Haibo Chen. 7 * Portions created by Haibo Chen are Copyright (C) 2018 NXP. 8 * All Rights Reserved. 9 * 10 * Copyright (C) 2018 NXP 11 * Copyright (C) 2021 Cai Huoqing 12 */ 13 #include <linux/bitfield.h> 14 #include <linux/bits.h> 15 #include <linux/clk.h> 16 #include <linux/completion.h> 17 #include <linux/delay.h> 18 #include <linux/err.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/kernel.h> 22 #include <linux/mod_devicetable.h> 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/regulator/consumer.h> 27 28 #include <linux/iio/iio.h> 29 30 #define ADC_DRIVER_NAME "imx8qxp-adc" 31 32 /* Register map definition */ 33 #define IMX8QXP_ADR_ADC_CTRL 0x10 34 #define IMX8QXP_ADR_ADC_STAT 0x14 35 #define IMX8QXP_ADR_ADC_IE 0x18 36 #define IMX8QXP_ADR_ADC_DE 0x1c 37 #define IMX8QXP_ADR_ADC_CFG 0x20 38 #define IMX8QXP_ADR_ADC_FCTRL 0x30 39 #define IMX8QXP_ADR_ADC_SWTRIG 0x34 40 #define IMX8QXP_ADR_ADC_TCTRL(tid) (0xc0 + (tid) * 4) 41 #define IMX8QXP_ADR_ADC_CMDH(cid) (0x100 + (cid) * 8) 42 #define IMX8QXP_ADR_ADC_CMDL(cid) (0x104 + (cid) * 8) 43 #define IMX8QXP_ADR_ADC_RESFIFO 0x300 44 #define IMX8QXP_ADR_ADC_TST 0xffc 45 46 /* ADC bit shift */ 47 #define IMX8QXP_ADC_IE_FWMIE_MASK GENMASK(1, 0) 48 #define IMX8QXP_ADC_CTRL_FIFO_RESET_MASK BIT(8) 49 #define IMX8QXP_ADC_CTRL_SOFTWARE_RESET_MASK BIT(1) 50 #define IMX8QXP_ADC_CTRL_ADC_EN_MASK BIT(0) 51 #define IMX8QXP_ADC_TCTRL_TCMD_MASK GENMASK(31, 24) 52 #define IMX8QXP_ADC_TCTRL_TDLY_MASK GENMASK(23, 16) 53 #define IMX8QXP_ADC_TCTRL_TPRI_MASK GENMASK(15, 8) 54 #define IMX8QXP_ADC_TCTRL_HTEN_MASK GENMASK(7, 0) 55 #define IMX8QXP_ADC_CMDL_CSCALE_MASK GENMASK(13, 8) 56 #define IMX8QXP_ADC_CMDL_MODE_MASK BIT(7) 57 #define IMX8QXP_ADC_CMDL_DIFF_MASK BIT(6) 58 #define IMX8QXP_ADC_CMDL_ABSEL_MASK BIT(5) 59 #define IMX8QXP_ADC_CMDL_ADCH_MASK GENMASK(2, 0) 60 #define IMX8QXP_ADC_CMDH_NEXT_MASK GENMASK(31, 24) 61 #define IMX8QXP_ADC_CMDH_LOOP_MASK GENMASK(23, 16) 62 #define IMX8QXP_ADC_CMDH_AVGS_MASK GENMASK(15, 12) 63 #define IMX8QXP_ADC_CMDH_STS_MASK BIT(8) 64 #define IMX8QXP_ADC_CMDH_LWI_MASK GENMASK(7, 7) 65 #define IMX8QXP_ADC_CMDH_CMPEN_MASK GENMASK(0, 0) 66 #define IMX8QXP_ADC_CFG_PWREN_MASK BIT(28) 67 #define IMX8QXP_ADC_CFG_PUDLY_MASK GENMASK(23, 16) 68 #define IMX8QXP_ADC_CFG_REFSEL_MASK GENMASK(7, 6) 69 #define IMX8QXP_ADC_CFG_PWRSEL_MASK GENMASK(5, 4) 70 #define IMX8QXP_ADC_CFG_TPRICTRL_MASK GENMASK(3, 0) 71 #define IMX8QXP_ADC_FCTRL_FWMARK_MASK GENMASK(20, 16) 72 #define IMX8QXP_ADC_FCTRL_FCOUNT_MASK GENMASK(4, 0) 73 #define IMX8QXP_ADC_RESFIFO_VAL_MASK GENMASK(18, 3) 74 75 /* ADC PARAMETER*/ 76 #define IMX8QXP_ADC_CMDL_CHANNEL_SCALE_FULL GENMASK(5, 0) 77 #define IMX8QXP_ADC_CMDL_SEL_A_A_B_CHANNEL 0 78 #define IMX8QXP_ADC_CMDL_STANDARD_RESOLUTION 0 79 #define IMX8QXP_ADC_CMDL_MODE_SINGLE 0 80 #define IMX8QXP_ADC_CMDH_LWI_INCREMENT_DIS 0 81 #define IMX8QXP_ADC_CMDH_CMPEN_DIS 0 82 #define IMX8QXP_ADC_PAUSE_EN BIT(31) 83 #define IMX8QXP_ADC_TCTRL_TPRI_PRIORITY_HIGH 0 84 85 #define IMX8QXP_ADC_TCTRL_HTEN_HW_TIRG_DIS 0 86 87 #define IMX8QXP_ADC_TIMEOUT msecs_to_jiffies(100) 88 89 struct imx8qxp_adc { 90 struct device *dev; 91 void __iomem *regs; 92 struct clk *clk; 93 struct clk *ipg_clk; 94 struct regulator *vref; 95 /* Serialise ADC channel reads */ 96 struct mutex lock; 97 struct completion completion; 98 }; 99 100 #define IMX8QXP_ADC_CHAN(_idx) { \ 101 .type = IIO_VOLTAGE, \ 102 .indexed = 1, \ 103 .channel = (_idx), \ 104 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 105 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 106 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 107 } 108 109 static const struct iio_chan_spec imx8qxp_adc_iio_channels[] = { 110 IMX8QXP_ADC_CHAN(0), 111 IMX8QXP_ADC_CHAN(1), 112 IMX8QXP_ADC_CHAN(2), 113 IMX8QXP_ADC_CHAN(3), 114 IMX8QXP_ADC_CHAN(4), 115 IMX8QXP_ADC_CHAN(5), 116 IMX8QXP_ADC_CHAN(6), 117 IMX8QXP_ADC_CHAN(7), 118 }; 119 120 static void imx8qxp_adc_reset(struct imx8qxp_adc *adc) 121 { 122 u32 ctrl; 123 124 /*software reset, need to clear the set bit*/ 125 ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL); 126 ctrl |= FIELD_PREP(IMX8QXP_ADC_CTRL_SOFTWARE_RESET_MASK, 1); 127 writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL); 128 udelay(10); 129 ctrl &= ~FIELD_PREP(IMX8QXP_ADC_CTRL_SOFTWARE_RESET_MASK, 1); 130 writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL); 131 132 /* reset the fifo */ 133 ctrl |= FIELD_PREP(IMX8QXP_ADC_CTRL_FIFO_RESET_MASK, 1); 134 writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL); 135 } 136 137 static void imx8qxp_adc_reg_config(struct imx8qxp_adc *adc, int channel) 138 { 139 u32 adc_cfg, adc_tctrl, adc_cmdl, adc_cmdh; 140 141 /* ADC configuration */ 142 adc_cfg = FIELD_PREP(IMX8QXP_ADC_CFG_PWREN_MASK, 1) | 143 FIELD_PREP(IMX8QXP_ADC_CFG_PUDLY_MASK, 0x80)| 144 FIELD_PREP(IMX8QXP_ADC_CFG_REFSEL_MASK, 0) | 145 FIELD_PREP(IMX8QXP_ADC_CFG_PWRSEL_MASK, 3) | 146 FIELD_PREP(IMX8QXP_ADC_CFG_TPRICTRL_MASK, 0); 147 writel(adc_cfg, adc->regs + IMX8QXP_ADR_ADC_CFG); 148 149 /* config the trigger control */ 150 adc_tctrl = FIELD_PREP(IMX8QXP_ADC_TCTRL_TCMD_MASK, 1) | 151 FIELD_PREP(IMX8QXP_ADC_TCTRL_TDLY_MASK, 0) | 152 FIELD_PREP(IMX8QXP_ADC_TCTRL_TPRI_MASK, IMX8QXP_ADC_TCTRL_TPRI_PRIORITY_HIGH) | 153 FIELD_PREP(IMX8QXP_ADC_TCTRL_HTEN_MASK, IMX8QXP_ADC_TCTRL_HTEN_HW_TIRG_DIS); 154 writel(adc_tctrl, adc->regs + IMX8QXP_ADR_ADC_TCTRL(0)); 155 156 /* config the cmd */ 157 adc_cmdl = FIELD_PREP(IMX8QXP_ADC_CMDL_CSCALE_MASK, IMX8QXP_ADC_CMDL_CHANNEL_SCALE_FULL) | 158 FIELD_PREP(IMX8QXP_ADC_CMDL_MODE_MASK, IMX8QXP_ADC_CMDL_STANDARD_RESOLUTION) | 159 FIELD_PREP(IMX8QXP_ADC_CMDL_DIFF_MASK, IMX8QXP_ADC_CMDL_MODE_SINGLE) | 160 FIELD_PREP(IMX8QXP_ADC_CMDL_ABSEL_MASK, IMX8QXP_ADC_CMDL_SEL_A_A_B_CHANNEL) | 161 FIELD_PREP(IMX8QXP_ADC_CMDL_ADCH_MASK, channel); 162 writel(adc_cmdl, adc->regs + IMX8QXP_ADR_ADC_CMDL(0)); 163 164 adc_cmdh = FIELD_PREP(IMX8QXP_ADC_CMDH_NEXT_MASK, 0) | 165 FIELD_PREP(IMX8QXP_ADC_CMDH_LOOP_MASK, 0) | 166 FIELD_PREP(IMX8QXP_ADC_CMDH_AVGS_MASK, 7) | 167 FIELD_PREP(IMX8QXP_ADC_CMDH_STS_MASK, 0) | 168 FIELD_PREP(IMX8QXP_ADC_CMDH_LWI_MASK, IMX8QXP_ADC_CMDH_LWI_INCREMENT_DIS) | 169 FIELD_PREP(IMX8QXP_ADC_CMDH_CMPEN_MASK, IMX8QXP_ADC_CMDH_CMPEN_DIS); 170 writel(adc_cmdh, adc->regs + IMX8QXP_ADR_ADC_CMDH(0)); 171 } 172 173 static void imx8qxp_adc_fifo_config(struct imx8qxp_adc *adc) 174 { 175 u32 fifo_ctrl, interrupt_en; 176 177 fifo_ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_FCTRL); 178 fifo_ctrl &= ~IMX8QXP_ADC_FCTRL_FWMARK_MASK; 179 /* set the watermark level to 1 */ 180 fifo_ctrl |= FIELD_PREP(IMX8QXP_ADC_FCTRL_FWMARK_MASK, 0); 181 writel(fifo_ctrl, adc->regs + IMX8QXP_ADR_ADC_FCTRL); 182 183 /* FIFO Watermark Interrupt Enable */ 184 interrupt_en = readl(adc->regs + IMX8QXP_ADR_ADC_IE); 185 interrupt_en |= FIELD_PREP(IMX8QXP_ADC_IE_FWMIE_MASK, 1); 186 writel(interrupt_en, adc->regs + IMX8QXP_ADR_ADC_IE); 187 } 188 189 static void imx8qxp_adc_disable(struct imx8qxp_adc *adc) 190 { 191 u32 ctrl; 192 193 ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL); 194 ctrl &= ~FIELD_PREP(IMX8QXP_ADC_CTRL_ADC_EN_MASK, 1); 195 writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL); 196 } 197 198 static int imx8qxp_adc_read_raw(struct iio_dev *indio_dev, 199 struct iio_chan_spec const *chan, 200 int *val, int *val2, long mask) 201 { 202 struct imx8qxp_adc *adc = iio_priv(indio_dev); 203 struct device *dev = adc->dev; 204 205 u32 ctrl, vref_uv; 206 long ret; 207 208 switch (mask) { 209 case IIO_CHAN_INFO_RAW: 210 pm_runtime_get_sync(dev); 211 212 mutex_lock(&adc->lock); 213 reinit_completion(&adc->completion); 214 215 imx8qxp_adc_reg_config(adc, chan->channel); 216 217 imx8qxp_adc_fifo_config(adc); 218 219 /* adc enable */ 220 ctrl = readl(adc->regs + IMX8QXP_ADR_ADC_CTRL); 221 ctrl |= FIELD_PREP(IMX8QXP_ADC_CTRL_ADC_EN_MASK, 1); 222 writel(ctrl, adc->regs + IMX8QXP_ADR_ADC_CTRL); 223 /* adc start */ 224 writel(1, adc->regs + IMX8QXP_ADR_ADC_SWTRIG); 225 226 ret = wait_for_completion_interruptible_timeout(&adc->completion, 227 IMX8QXP_ADC_TIMEOUT); 228 229 pm_runtime_mark_last_busy(dev); 230 pm_runtime_put_sync_autosuspend(dev); 231 232 if (ret == 0) { 233 mutex_unlock(&adc->lock); 234 return -ETIMEDOUT; 235 } 236 if (ret < 0) { 237 mutex_unlock(&adc->lock); 238 return ret; 239 } 240 241 *val = FIELD_GET(IMX8QXP_ADC_RESFIFO_VAL_MASK, 242 readl(adc->regs + IMX8QXP_ADR_ADC_RESFIFO)); 243 244 mutex_unlock(&adc->lock); 245 return IIO_VAL_INT; 246 247 case IIO_CHAN_INFO_SCALE: 248 vref_uv = regulator_get_voltage(adc->vref); 249 *val = vref_uv / 1000; 250 *val2 = 12; 251 return IIO_VAL_FRACTIONAL_LOG2; 252 253 case IIO_CHAN_INFO_SAMP_FREQ: 254 *val = clk_get_rate(adc->clk) / 3; 255 return IIO_VAL_INT; 256 257 default: 258 return -EINVAL; 259 } 260 } 261 262 static irqreturn_t imx8qxp_adc_isr(int irq, void *dev_id) 263 { 264 struct imx8qxp_adc *adc = dev_id; 265 u32 fifo_count; 266 267 fifo_count = FIELD_GET(IMX8QXP_ADC_FCTRL_FCOUNT_MASK, 268 readl(adc->regs + IMX8QXP_ADR_ADC_FCTRL)); 269 270 if (fifo_count) 271 complete(&adc->completion); 272 273 return IRQ_HANDLED; 274 } 275 276 static int imx8qxp_adc_reg_access(struct iio_dev *indio_dev, unsigned int reg, 277 unsigned int writeval, unsigned int *readval) 278 { 279 struct imx8qxp_adc *adc = iio_priv(indio_dev); 280 struct device *dev = adc->dev; 281 282 if (!readval || reg % 4 || reg > IMX8QXP_ADR_ADC_TST) 283 return -EINVAL; 284 285 pm_runtime_get_sync(dev); 286 287 *readval = readl(adc->regs + reg); 288 289 pm_runtime_mark_last_busy(dev); 290 pm_runtime_put_sync_autosuspend(dev); 291 292 return 0; 293 } 294 295 static const struct iio_info imx8qxp_adc_iio_info = { 296 .read_raw = &imx8qxp_adc_read_raw, 297 .debugfs_reg_access = &imx8qxp_adc_reg_access, 298 }; 299 300 static int imx8qxp_adc_probe(struct platform_device *pdev) 301 { 302 struct imx8qxp_adc *adc; 303 struct iio_dev *indio_dev; 304 struct device *dev = &pdev->dev; 305 int irq; 306 int ret; 307 308 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); 309 if (!indio_dev) { 310 dev_err(dev, "Failed allocating iio device\n"); 311 return -ENOMEM; 312 } 313 314 adc = iio_priv(indio_dev); 315 adc->dev = dev; 316 317 mutex_init(&adc->lock); 318 adc->regs = devm_platform_ioremap_resource(pdev, 0); 319 if (IS_ERR(adc->regs)) 320 return PTR_ERR(adc->regs); 321 322 irq = platform_get_irq(pdev, 0); 323 if (irq < 0) 324 return irq; 325 326 adc->clk = devm_clk_get(dev, "per"); 327 if (IS_ERR(adc->clk)) 328 return dev_err_probe(dev, PTR_ERR(adc->clk), "Failed getting clock\n"); 329 330 adc->ipg_clk = devm_clk_get(dev, "ipg"); 331 if (IS_ERR(adc->ipg_clk)) 332 return dev_err_probe(dev, PTR_ERR(adc->ipg_clk), "Failed getting clock\n"); 333 334 adc->vref = devm_regulator_get(dev, "vref"); 335 if (IS_ERR(adc->vref)) 336 return dev_err_probe(dev, PTR_ERR(adc->vref), "Failed getting reference voltage\n"); 337 338 ret = regulator_enable(adc->vref); 339 if (ret) { 340 dev_err(dev, "Can't enable adc reference top voltage\n"); 341 return ret; 342 } 343 344 platform_set_drvdata(pdev, indio_dev); 345 346 init_completion(&adc->completion); 347 348 indio_dev->name = ADC_DRIVER_NAME; 349 indio_dev->info = &imx8qxp_adc_iio_info; 350 indio_dev->modes = INDIO_DIRECT_MODE; 351 indio_dev->channels = imx8qxp_adc_iio_channels; 352 indio_dev->num_channels = ARRAY_SIZE(imx8qxp_adc_iio_channels); 353 354 ret = clk_prepare_enable(adc->clk); 355 if (ret) { 356 dev_err(&pdev->dev, "Could not prepare or enable the clock.\n"); 357 goto error_regulator_disable; 358 } 359 360 ret = clk_prepare_enable(adc->ipg_clk); 361 if (ret) { 362 dev_err(&pdev->dev, "Could not prepare or enable the clock.\n"); 363 goto error_adc_clk_disable; 364 } 365 366 ret = devm_request_irq(dev, irq, imx8qxp_adc_isr, 0, ADC_DRIVER_NAME, adc); 367 if (ret < 0) { 368 dev_err(dev, "Failed requesting irq, irq = %d\n", irq); 369 goto error_ipg_clk_disable; 370 } 371 372 imx8qxp_adc_reset(adc); 373 374 ret = iio_device_register(indio_dev); 375 if (ret) { 376 imx8qxp_adc_disable(adc); 377 dev_err(dev, "Couldn't register the device.\n"); 378 goto error_ipg_clk_disable; 379 } 380 381 pm_runtime_set_active(dev); 382 pm_runtime_set_autosuspend_delay(dev, 50); 383 pm_runtime_use_autosuspend(dev); 384 pm_runtime_enable(dev); 385 386 return 0; 387 388 error_ipg_clk_disable: 389 clk_disable_unprepare(adc->ipg_clk); 390 error_adc_clk_disable: 391 clk_disable_unprepare(adc->clk); 392 error_regulator_disable: 393 regulator_disable(adc->vref); 394 395 return ret; 396 } 397 398 static int imx8qxp_adc_remove(struct platform_device *pdev) 399 { 400 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 401 struct imx8qxp_adc *adc = iio_priv(indio_dev); 402 struct device *dev = adc->dev; 403 404 pm_runtime_get_sync(dev); 405 406 iio_device_unregister(indio_dev); 407 408 imx8qxp_adc_disable(adc); 409 410 clk_disable_unprepare(adc->clk); 411 clk_disable_unprepare(adc->ipg_clk); 412 regulator_disable(adc->vref); 413 414 pm_runtime_disable(dev); 415 pm_runtime_put_noidle(dev); 416 417 return 0; 418 } 419 420 static int imx8qxp_adc_runtime_suspend(struct device *dev) 421 { 422 struct iio_dev *indio_dev = dev_get_drvdata(dev); 423 struct imx8qxp_adc *adc = iio_priv(indio_dev); 424 425 imx8qxp_adc_disable(adc); 426 427 clk_disable_unprepare(adc->clk); 428 clk_disable_unprepare(adc->ipg_clk); 429 regulator_disable(adc->vref); 430 431 return 0; 432 } 433 434 static int imx8qxp_adc_runtime_resume(struct device *dev) 435 { 436 struct iio_dev *indio_dev = dev_get_drvdata(dev); 437 struct imx8qxp_adc *adc = iio_priv(indio_dev); 438 int ret; 439 440 ret = regulator_enable(adc->vref); 441 if (ret) { 442 dev_err(dev, "Can't enable adc reference top voltage, err = %d\n", ret); 443 return ret; 444 } 445 446 ret = clk_prepare_enable(adc->clk); 447 if (ret) { 448 dev_err(dev, "Could not prepare or enable clock.\n"); 449 goto err_disable_reg; 450 } 451 452 ret = clk_prepare_enable(adc->ipg_clk); 453 if (ret) { 454 dev_err(dev, "Could not prepare or enable clock.\n"); 455 goto err_unprepare_clk; 456 } 457 458 imx8qxp_adc_reset(adc); 459 460 return 0; 461 462 err_unprepare_clk: 463 clk_disable_unprepare(adc->clk); 464 465 err_disable_reg: 466 regulator_disable(adc->vref); 467 468 return ret; 469 } 470 471 static DEFINE_RUNTIME_DEV_PM_OPS(imx8qxp_adc_pm_ops, 472 imx8qxp_adc_runtime_suspend, 473 imx8qxp_adc_runtime_resume, NULL); 474 475 static const struct of_device_id imx8qxp_adc_match[] = { 476 { .compatible = "nxp,imx8qxp-adc", }, 477 { /* sentinel */ } 478 }; 479 MODULE_DEVICE_TABLE(of, imx8qxp_adc_match); 480 481 static struct platform_driver imx8qxp_adc_driver = { 482 .probe = imx8qxp_adc_probe, 483 .remove = imx8qxp_adc_remove, 484 .driver = { 485 .name = ADC_DRIVER_NAME, 486 .of_match_table = imx8qxp_adc_match, 487 .pm = pm_ptr(&imx8qxp_adc_pm_ops), 488 }, 489 }; 490 491 module_platform_driver(imx8qxp_adc_driver); 492 493 MODULE_DESCRIPTION("i.MX8QuadXPlus ADC driver"); 494 MODULE_LICENSE("GPL v2"); 495