1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Holt Integrated Circuits HI-8435 threshold detector driver 4 * 5 * Copyright (C) 2015 Zodiac Inflight Innovations 6 * Copyright (C) 2015 Cogent Embedded, Inc. 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/iio/events.h> 11 #include <linux/iio/iio.h> 12 #include <linux/iio/sysfs.h> 13 #include <linux/iio/trigger.h> 14 #include <linux/iio/trigger_consumer.h> 15 #include <linux/iio/triggered_event.h> 16 #include <linux/interrupt.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_device.h> 20 #include <linux/of_gpio.h> 21 #include <linux/spi/spi.h> 22 #include <linux/gpio/consumer.h> 23 24 #define DRV_NAME "hi8435" 25 26 /* Register offsets for HI-8435 */ 27 #define HI8435_CTRL_REG 0x02 28 #define HI8435_PSEN_REG 0x04 29 #define HI8435_TMDATA_REG 0x1E 30 #define HI8435_GOCENHYS_REG 0x3A 31 #define HI8435_SOCENHYS_REG 0x3C 32 #define HI8435_SO7_0_REG 0x10 33 #define HI8435_SO15_8_REG 0x12 34 #define HI8435_SO23_16_REG 0x14 35 #define HI8435_SO31_24_REG 0x16 36 #define HI8435_SO31_0_REG 0x78 37 38 #define HI8435_WRITE_OPCODE 0x00 39 #define HI8435_READ_OPCODE 0x80 40 41 /* CTRL register bits */ 42 #define HI8435_CTRL_TEST 0x01 43 #define HI8435_CTRL_SRST 0x02 44 45 struct hi8435_priv { 46 struct spi_device *spi; 47 struct mutex lock; 48 49 unsigned long event_scan_mask; /* soft mask/unmask channels events */ 50 unsigned int event_prev_val; 51 52 unsigned threshold_lo[2]; /* GND-Open and Supply-Open thresholds */ 53 unsigned threshold_hi[2]; /* GND-Open and Supply-Open thresholds */ 54 u8 reg_buffer[3] ____cacheline_aligned; 55 }; 56 57 static int hi8435_readb(struct hi8435_priv *priv, u8 reg, u8 *val) 58 { 59 reg |= HI8435_READ_OPCODE; 60 return spi_write_then_read(priv->spi, ®, 1, val, 1); 61 } 62 63 static int hi8435_readw(struct hi8435_priv *priv, u8 reg, u16 *val) 64 { 65 int ret; 66 __be16 be_val; 67 68 reg |= HI8435_READ_OPCODE; 69 ret = spi_write_then_read(priv->spi, ®, 1, &be_val, 2); 70 *val = be16_to_cpu(be_val); 71 72 return ret; 73 } 74 75 static int hi8435_readl(struct hi8435_priv *priv, u8 reg, u32 *val) 76 { 77 int ret; 78 __be32 be_val; 79 80 reg |= HI8435_READ_OPCODE; 81 ret = spi_write_then_read(priv->spi, ®, 1, &be_val, 4); 82 *val = be32_to_cpu(be_val); 83 84 return ret; 85 } 86 87 static int hi8435_writeb(struct hi8435_priv *priv, u8 reg, u8 val) 88 { 89 priv->reg_buffer[0] = reg | HI8435_WRITE_OPCODE; 90 priv->reg_buffer[1] = val; 91 92 return spi_write(priv->spi, priv->reg_buffer, 2); 93 } 94 95 static int hi8435_writew(struct hi8435_priv *priv, u8 reg, u16 val) 96 { 97 priv->reg_buffer[0] = reg | HI8435_WRITE_OPCODE; 98 priv->reg_buffer[1] = (val >> 8) & 0xff; 99 priv->reg_buffer[2] = val & 0xff; 100 101 return spi_write(priv->spi, priv->reg_buffer, 3); 102 } 103 104 static int hi8435_read_raw(struct iio_dev *idev, 105 const struct iio_chan_spec *chan, 106 int *val, int *val2, long mask) 107 { 108 struct hi8435_priv *priv = iio_priv(idev); 109 u32 tmp; 110 int ret; 111 112 switch (mask) { 113 case IIO_CHAN_INFO_RAW: 114 ret = hi8435_readl(priv, HI8435_SO31_0_REG, &tmp); 115 if (ret < 0) 116 return ret; 117 *val = !!(tmp & BIT(chan->channel)); 118 return IIO_VAL_INT; 119 default: 120 return -EINVAL; 121 } 122 } 123 124 static int hi8435_read_event_config(struct iio_dev *idev, 125 const struct iio_chan_spec *chan, 126 enum iio_event_type type, 127 enum iio_event_direction dir) 128 { 129 struct hi8435_priv *priv = iio_priv(idev); 130 131 return !!(priv->event_scan_mask & BIT(chan->channel)); 132 } 133 134 static int hi8435_write_event_config(struct iio_dev *idev, 135 const struct iio_chan_spec *chan, 136 enum iio_event_type type, 137 enum iio_event_direction dir, int state) 138 { 139 struct hi8435_priv *priv = iio_priv(idev); 140 int ret; 141 u32 tmp; 142 143 if (state) { 144 ret = hi8435_readl(priv, HI8435_SO31_0_REG, &tmp); 145 if (ret < 0) 146 return ret; 147 if (tmp & BIT(chan->channel)) 148 priv->event_prev_val |= BIT(chan->channel); 149 else 150 priv->event_prev_val &= ~BIT(chan->channel); 151 152 priv->event_scan_mask |= BIT(chan->channel); 153 } else 154 priv->event_scan_mask &= ~BIT(chan->channel); 155 156 return 0; 157 } 158 159 static int hi8435_read_event_value(struct iio_dev *idev, 160 const struct iio_chan_spec *chan, 161 enum iio_event_type type, 162 enum iio_event_direction dir, 163 enum iio_event_info info, 164 int *val, int *val2) 165 { 166 struct hi8435_priv *priv = iio_priv(idev); 167 int ret; 168 u8 mode, psen; 169 u16 reg; 170 171 ret = hi8435_readb(priv, HI8435_PSEN_REG, &psen); 172 if (ret < 0) 173 return ret; 174 175 /* Supply-Open or GND-Open sensing mode */ 176 mode = !!(psen & BIT(chan->channel / 8)); 177 178 ret = hi8435_readw(priv, mode ? HI8435_SOCENHYS_REG : 179 HI8435_GOCENHYS_REG, ®); 180 if (ret < 0) 181 return ret; 182 183 if (dir == IIO_EV_DIR_FALLING) 184 *val = ((reg & 0xff) - (reg >> 8)) / 2; 185 else if (dir == IIO_EV_DIR_RISING) 186 *val = ((reg & 0xff) + (reg >> 8)) / 2; 187 188 return IIO_VAL_INT; 189 } 190 191 static int hi8435_write_event_value(struct iio_dev *idev, 192 const struct iio_chan_spec *chan, 193 enum iio_event_type type, 194 enum iio_event_direction dir, 195 enum iio_event_info info, 196 int val, int val2) 197 { 198 struct hi8435_priv *priv = iio_priv(idev); 199 int ret; 200 u8 mode, psen; 201 u16 reg; 202 203 ret = hi8435_readb(priv, HI8435_PSEN_REG, &psen); 204 if (ret < 0) 205 return ret; 206 207 /* Supply-Open or GND-Open sensing mode */ 208 mode = !!(psen & BIT(chan->channel / 8)); 209 210 ret = hi8435_readw(priv, mode ? HI8435_SOCENHYS_REG : 211 HI8435_GOCENHYS_REG, ®); 212 if (ret < 0) 213 return ret; 214 215 if (dir == IIO_EV_DIR_FALLING) { 216 /* falling threshold range 2..21V, hysteresis minimum 2V */ 217 if (val < 2 || val > 21 || (val + 2) > priv->threshold_hi[mode]) 218 return -EINVAL; 219 220 if (val == priv->threshold_lo[mode]) 221 return 0; 222 223 priv->threshold_lo[mode] = val; 224 225 /* hysteresis must not be odd */ 226 if ((priv->threshold_hi[mode] - priv->threshold_lo[mode]) % 2) 227 priv->threshold_hi[mode]--; 228 } else if (dir == IIO_EV_DIR_RISING) { 229 /* rising threshold range 3..22V, hysteresis minimum 2V */ 230 if (val < 3 || val > 22 || val < (priv->threshold_lo[mode] + 2)) 231 return -EINVAL; 232 233 if (val == priv->threshold_hi[mode]) 234 return 0; 235 236 priv->threshold_hi[mode] = val; 237 238 /* hysteresis must not be odd */ 239 if ((priv->threshold_hi[mode] - priv->threshold_lo[mode]) % 2) 240 priv->threshold_lo[mode]++; 241 } 242 243 /* program thresholds */ 244 mutex_lock(&priv->lock); 245 246 ret = hi8435_readw(priv, mode ? HI8435_SOCENHYS_REG : 247 HI8435_GOCENHYS_REG, ®); 248 if (ret < 0) { 249 mutex_unlock(&priv->lock); 250 return ret; 251 } 252 253 /* hysteresis */ 254 reg = priv->threshold_hi[mode] - priv->threshold_lo[mode]; 255 reg <<= 8; 256 /* threshold center */ 257 reg |= (priv->threshold_hi[mode] + priv->threshold_lo[mode]); 258 259 ret = hi8435_writew(priv, mode ? HI8435_SOCENHYS_REG : 260 HI8435_GOCENHYS_REG, reg); 261 262 mutex_unlock(&priv->lock); 263 264 return ret; 265 } 266 267 static int hi8435_debugfs_reg_access(struct iio_dev *idev, 268 unsigned reg, unsigned writeval, 269 unsigned *readval) 270 { 271 struct hi8435_priv *priv = iio_priv(idev); 272 int ret; 273 u8 val; 274 275 if (readval != NULL) { 276 ret = hi8435_readb(priv, reg, &val); 277 *readval = val; 278 } else { 279 val = (u8)writeval; 280 ret = hi8435_writeb(priv, reg, val); 281 } 282 283 return ret; 284 } 285 286 static const struct iio_event_spec hi8435_events[] = { 287 { 288 .type = IIO_EV_TYPE_THRESH, 289 .dir = IIO_EV_DIR_RISING, 290 .mask_separate = BIT(IIO_EV_INFO_VALUE), 291 }, { 292 .type = IIO_EV_TYPE_THRESH, 293 .dir = IIO_EV_DIR_FALLING, 294 .mask_separate = BIT(IIO_EV_INFO_VALUE), 295 }, { 296 .type = IIO_EV_TYPE_THRESH, 297 .dir = IIO_EV_DIR_EITHER, 298 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 299 }, 300 }; 301 302 static int hi8435_get_sensing_mode(struct iio_dev *idev, 303 const struct iio_chan_spec *chan) 304 { 305 struct hi8435_priv *priv = iio_priv(idev); 306 int ret; 307 u8 reg; 308 309 ret = hi8435_readb(priv, HI8435_PSEN_REG, ®); 310 if (ret < 0) 311 return ret; 312 313 return !!(reg & BIT(chan->channel / 8)); 314 } 315 316 static int hi8435_set_sensing_mode(struct iio_dev *idev, 317 const struct iio_chan_spec *chan, 318 unsigned int mode) 319 { 320 struct hi8435_priv *priv = iio_priv(idev); 321 int ret; 322 u8 reg; 323 324 mutex_lock(&priv->lock); 325 326 ret = hi8435_readb(priv, HI8435_PSEN_REG, ®); 327 if (ret < 0) { 328 mutex_unlock(&priv->lock); 329 return ret; 330 } 331 332 reg &= ~BIT(chan->channel / 8); 333 if (mode) 334 reg |= BIT(chan->channel / 8); 335 336 ret = hi8435_writeb(priv, HI8435_PSEN_REG, reg); 337 338 mutex_unlock(&priv->lock); 339 340 return ret; 341 } 342 343 static const char * const hi8435_sensing_modes[] = { "GND-Open", 344 "Supply-Open" }; 345 346 static const struct iio_enum hi8435_sensing_mode = { 347 .items = hi8435_sensing_modes, 348 .num_items = ARRAY_SIZE(hi8435_sensing_modes), 349 .get = hi8435_get_sensing_mode, 350 .set = hi8435_set_sensing_mode, 351 }; 352 353 static const struct iio_chan_spec_ext_info hi8435_ext_info[] = { 354 IIO_ENUM("sensing_mode", IIO_SEPARATE, &hi8435_sensing_mode), 355 IIO_ENUM_AVAILABLE("sensing_mode", &hi8435_sensing_mode), 356 {}, 357 }; 358 359 #define HI8435_VOLTAGE_CHANNEL(num) \ 360 { \ 361 .type = IIO_VOLTAGE, \ 362 .indexed = 1, \ 363 .channel = num, \ 364 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 365 .event_spec = hi8435_events, \ 366 .num_event_specs = ARRAY_SIZE(hi8435_events), \ 367 .ext_info = hi8435_ext_info, \ 368 } 369 370 static const struct iio_chan_spec hi8435_channels[] = { 371 HI8435_VOLTAGE_CHANNEL(0), 372 HI8435_VOLTAGE_CHANNEL(1), 373 HI8435_VOLTAGE_CHANNEL(2), 374 HI8435_VOLTAGE_CHANNEL(3), 375 HI8435_VOLTAGE_CHANNEL(4), 376 HI8435_VOLTAGE_CHANNEL(5), 377 HI8435_VOLTAGE_CHANNEL(6), 378 HI8435_VOLTAGE_CHANNEL(7), 379 HI8435_VOLTAGE_CHANNEL(8), 380 HI8435_VOLTAGE_CHANNEL(9), 381 HI8435_VOLTAGE_CHANNEL(10), 382 HI8435_VOLTAGE_CHANNEL(11), 383 HI8435_VOLTAGE_CHANNEL(12), 384 HI8435_VOLTAGE_CHANNEL(13), 385 HI8435_VOLTAGE_CHANNEL(14), 386 HI8435_VOLTAGE_CHANNEL(15), 387 HI8435_VOLTAGE_CHANNEL(16), 388 HI8435_VOLTAGE_CHANNEL(17), 389 HI8435_VOLTAGE_CHANNEL(18), 390 HI8435_VOLTAGE_CHANNEL(19), 391 HI8435_VOLTAGE_CHANNEL(20), 392 HI8435_VOLTAGE_CHANNEL(21), 393 HI8435_VOLTAGE_CHANNEL(22), 394 HI8435_VOLTAGE_CHANNEL(23), 395 HI8435_VOLTAGE_CHANNEL(24), 396 HI8435_VOLTAGE_CHANNEL(25), 397 HI8435_VOLTAGE_CHANNEL(26), 398 HI8435_VOLTAGE_CHANNEL(27), 399 HI8435_VOLTAGE_CHANNEL(28), 400 HI8435_VOLTAGE_CHANNEL(29), 401 HI8435_VOLTAGE_CHANNEL(30), 402 HI8435_VOLTAGE_CHANNEL(31), 403 IIO_CHAN_SOFT_TIMESTAMP(32), 404 }; 405 406 static const struct iio_info hi8435_info = { 407 .read_raw = hi8435_read_raw, 408 .read_event_config = hi8435_read_event_config, 409 .write_event_config = hi8435_write_event_config, 410 .read_event_value = hi8435_read_event_value, 411 .write_event_value = hi8435_write_event_value, 412 .debugfs_reg_access = hi8435_debugfs_reg_access, 413 }; 414 415 static void hi8435_iio_push_event(struct iio_dev *idev, unsigned int val) 416 { 417 struct hi8435_priv *priv = iio_priv(idev); 418 enum iio_event_direction dir; 419 unsigned int i; 420 unsigned int status = priv->event_prev_val ^ val; 421 422 if (!status) 423 return; 424 425 for_each_set_bit(i, &priv->event_scan_mask, 32) { 426 if (status & BIT(i)) { 427 dir = val & BIT(i) ? IIO_EV_DIR_RISING : 428 IIO_EV_DIR_FALLING; 429 iio_push_event(idev, 430 IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, i, 431 IIO_EV_TYPE_THRESH, dir), 432 iio_get_time_ns(idev)); 433 } 434 } 435 436 priv->event_prev_val = val; 437 } 438 439 static irqreturn_t hi8435_trigger_handler(int irq, void *private) 440 { 441 struct iio_poll_func *pf = private; 442 struct iio_dev *idev = pf->indio_dev; 443 struct hi8435_priv *priv = iio_priv(idev); 444 u32 val; 445 int ret; 446 447 ret = hi8435_readl(priv, HI8435_SO31_0_REG, &val); 448 if (ret < 0) 449 goto err_read; 450 451 hi8435_iio_push_event(idev, val); 452 453 err_read: 454 iio_trigger_notify_done(idev->trig); 455 456 return IRQ_HANDLED; 457 } 458 459 static int hi8435_probe(struct spi_device *spi) 460 { 461 struct iio_dev *idev; 462 struct hi8435_priv *priv; 463 struct gpio_desc *reset_gpio; 464 int ret; 465 466 idev = devm_iio_device_alloc(&spi->dev, sizeof(*priv)); 467 if (!idev) 468 return -ENOMEM; 469 470 priv = iio_priv(idev); 471 priv->spi = spi; 472 473 reset_gpio = devm_gpiod_get(&spi->dev, NULL, GPIOD_OUT_LOW); 474 if (IS_ERR(reset_gpio)) { 475 /* chip s/w reset if h/w reset failed */ 476 hi8435_writeb(priv, HI8435_CTRL_REG, HI8435_CTRL_SRST); 477 hi8435_writeb(priv, HI8435_CTRL_REG, 0); 478 } else { 479 udelay(5); 480 gpiod_set_value(reset_gpio, 1); 481 } 482 483 spi_set_drvdata(spi, idev); 484 mutex_init(&priv->lock); 485 486 idev->dev.parent = &spi->dev; 487 idev->dev.of_node = spi->dev.of_node; 488 idev->name = spi_get_device_id(spi)->name; 489 idev->modes = INDIO_DIRECT_MODE; 490 idev->info = &hi8435_info; 491 idev->channels = hi8435_channels; 492 idev->num_channels = ARRAY_SIZE(hi8435_channels); 493 494 /* unmask all events */ 495 priv->event_scan_mask = ~(0); 496 /* 497 * There is a restriction in the chip - the hysteresis can not be odd. 498 * If the hysteresis is set to odd value then chip gets into lock state 499 * and not functional anymore. 500 * After chip reset the thresholds are in undefined state, so we need to 501 * initialize thresholds to some initial values and then prevent 502 * userspace setting odd hysteresis. 503 * 504 * Set threshold low voltage to 2V, threshold high voltage to 4V 505 * for both GND-Open and Supply-Open sensing modes. 506 */ 507 priv->threshold_lo[0] = priv->threshold_lo[1] = 2; 508 priv->threshold_hi[0] = priv->threshold_hi[1] = 4; 509 hi8435_writew(priv, HI8435_GOCENHYS_REG, 0x206); 510 hi8435_writew(priv, HI8435_SOCENHYS_REG, 0x206); 511 512 ret = iio_triggered_event_setup(idev, NULL, hi8435_trigger_handler); 513 if (ret) 514 return ret; 515 516 ret = iio_device_register(idev); 517 if (ret < 0) { 518 dev_err(&spi->dev, "unable to register device\n"); 519 goto unregister_triggered_event; 520 } 521 522 return 0; 523 524 unregister_triggered_event: 525 iio_triggered_event_cleanup(idev); 526 return ret; 527 } 528 529 static int hi8435_remove(struct spi_device *spi) 530 { 531 struct iio_dev *idev = spi_get_drvdata(spi); 532 533 iio_device_unregister(idev); 534 iio_triggered_event_cleanup(idev); 535 536 return 0; 537 } 538 539 static const struct of_device_id hi8435_dt_ids[] = { 540 { .compatible = "holt,hi8435" }, 541 {}, 542 }; 543 MODULE_DEVICE_TABLE(of, hi8435_dt_ids); 544 545 static const struct spi_device_id hi8435_id[] = { 546 { "hi8435", 0}, 547 { } 548 }; 549 MODULE_DEVICE_TABLE(spi, hi8435_id); 550 551 static struct spi_driver hi8435_driver = { 552 .driver = { 553 .name = DRV_NAME, 554 .of_match_table = of_match_ptr(hi8435_dt_ids), 555 }, 556 .probe = hi8435_probe, 557 .remove = hi8435_remove, 558 .id_table = hi8435_id, 559 }; 560 module_spi_driver(hi8435_driver); 561 562 MODULE_LICENSE("GPL"); 563 MODULE_AUTHOR("Vladimir Barinov"); 564 MODULE_DESCRIPTION("HI-8435 threshold detector"); 565