1 /* 2 * exynos_adc.c - Support for ADC in EXYNOS SoCs 3 * 4 * 8 ~ 10 channel, 10/12-bit ADC 5 * 6 * Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/interrupt.h> 26 #include <linux/delay.h> 27 #include <linux/kernel.h> 28 #include <linux/slab.h> 29 #include <linux/io.h> 30 #include <linux/clk.h> 31 #include <linux/completion.h> 32 #include <linux/of.h> 33 #include <linux/of_irq.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/of_platform.h> 36 #include <linux/err.h> 37 38 #include <linux/iio/iio.h> 39 #include <linux/iio/machine.h> 40 #include <linux/iio/driver.h> 41 42 enum adc_version { 43 ADC_V1, 44 ADC_V2 45 }; 46 47 /* EXYNOS4412/5250 ADC_V1 registers definitions */ 48 #define ADC_V1_CON(x) ((x) + 0x00) 49 #define ADC_V1_DLY(x) ((x) + 0x08) 50 #define ADC_V1_DATX(x) ((x) + 0x0C) 51 #define ADC_V1_INTCLR(x) ((x) + 0x18) 52 #define ADC_V1_MUX(x) ((x) + 0x1c) 53 54 /* Future ADC_V2 registers definitions */ 55 #define ADC_V2_CON1(x) ((x) + 0x00) 56 #define ADC_V2_CON2(x) ((x) + 0x04) 57 #define ADC_V2_STAT(x) ((x) + 0x08) 58 #define ADC_V2_INT_EN(x) ((x) + 0x10) 59 #define ADC_V2_INT_ST(x) ((x) + 0x14) 60 #define ADC_V2_VER(x) ((x) + 0x20) 61 62 /* Bit definitions for ADC_V1 */ 63 #define ADC_V1_CON_RES (1u << 16) 64 #define ADC_V1_CON_PRSCEN (1u << 14) 65 #define ADC_V1_CON_PRSCLV(x) (((x) & 0xFF) << 6) 66 #define ADC_V1_CON_STANDBY (1u << 2) 67 68 /* Bit definitions for ADC_V2 */ 69 #define ADC_V2_CON1_SOFT_RESET (1u << 2) 70 71 #define ADC_V2_CON2_OSEL (1u << 10) 72 #define ADC_V2_CON2_ESEL (1u << 9) 73 #define ADC_V2_CON2_HIGHF (1u << 8) 74 #define ADC_V2_CON2_C_TIME(x) (((x) & 7) << 4) 75 #define ADC_V2_CON2_ACH_SEL(x) (((x) & 0xF) << 0) 76 #define ADC_V2_CON2_ACH_MASK 0xF 77 78 #define MAX_ADC_V2_CHANNELS 10 79 #define MAX_ADC_V1_CHANNELS 8 80 81 /* Bit definitions common for ADC_V1 and ADC_V2 */ 82 #define ADC_CON_EN_START (1u << 0) 83 #define ADC_DATX_MASK 0xFFF 84 85 #define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100)) 86 87 struct exynos_adc { 88 void __iomem *regs; 89 void __iomem *enable_reg; 90 struct clk *clk; 91 unsigned int irq; 92 struct regulator *vdd; 93 94 struct completion completion; 95 96 u32 value; 97 unsigned int version; 98 }; 99 100 static const struct of_device_id exynos_adc_match[] = { 101 { .compatible = "samsung,exynos-adc-v1", .data = (void *)ADC_V1 }, 102 { .compatible = "samsung,exynos-adc-v2", .data = (void *)ADC_V2 }, 103 {}, 104 }; 105 MODULE_DEVICE_TABLE(of, exynos_adc_match); 106 107 static inline unsigned int exynos_adc_get_version(struct platform_device *pdev) 108 { 109 const struct of_device_id *match; 110 111 match = of_match_node(exynos_adc_match, pdev->dev.of_node); 112 return (unsigned int)match->data; 113 } 114 115 static void exynos_adc_hw_init(struct exynos_adc *info) 116 { 117 u32 con1, con2; 118 119 if (info->version == ADC_V2) { 120 con1 = ADC_V2_CON1_SOFT_RESET; 121 writel(con1, ADC_V2_CON1(info->regs)); 122 123 con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL | 124 ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0); 125 writel(con2, ADC_V2_CON2(info->regs)); 126 127 /* Enable interrupts */ 128 writel(1, ADC_V2_INT_EN(info->regs)); 129 } else { 130 /* set default prescaler values and Enable prescaler */ 131 con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN; 132 133 /* Enable 12-bit ADC resolution */ 134 con1 |= ADC_V1_CON_RES; 135 writel(con1, ADC_V1_CON(info->regs)); 136 } 137 } 138 139 static int exynos_read_raw(struct iio_dev *indio_dev, 140 struct iio_chan_spec const *chan, 141 int *val, 142 int *val2, 143 long mask) 144 { 145 struct exynos_adc *info = iio_priv(indio_dev); 146 unsigned long timeout; 147 u32 con1, con2; 148 int ret; 149 150 if (mask != IIO_CHAN_INFO_RAW) 151 return -EINVAL; 152 153 mutex_lock(&indio_dev->mlock); 154 reinit_completion(&info->completion); 155 156 /* Select the channel to be used and Trigger conversion */ 157 if (info->version == ADC_V2) { 158 con2 = readl(ADC_V2_CON2(info->regs)); 159 con2 &= ~ADC_V2_CON2_ACH_MASK; 160 con2 |= ADC_V2_CON2_ACH_SEL(chan->address); 161 writel(con2, ADC_V2_CON2(info->regs)); 162 163 con1 = readl(ADC_V2_CON1(info->regs)); 164 writel(con1 | ADC_CON_EN_START, 165 ADC_V2_CON1(info->regs)); 166 } else { 167 writel(chan->address, ADC_V1_MUX(info->regs)); 168 169 con1 = readl(ADC_V1_CON(info->regs)); 170 writel(con1 | ADC_CON_EN_START, 171 ADC_V1_CON(info->regs)); 172 } 173 174 timeout = wait_for_completion_timeout 175 (&info->completion, EXYNOS_ADC_TIMEOUT); 176 if (timeout == 0) { 177 dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n"); 178 exynos_adc_hw_init(info); 179 ret = -ETIMEDOUT; 180 } else { 181 *val = info->value; 182 *val2 = 0; 183 ret = IIO_VAL_INT; 184 } 185 186 mutex_unlock(&indio_dev->mlock); 187 188 return ret; 189 } 190 191 static irqreturn_t exynos_adc_isr(int irq, void *dev_id) 192 { 193 struct exynos_adc *info = (struct exynos_adc *)dev_id; 194 195 /* Read value */ 196 info->value = readl(ADC_V1_DATX(info->regs)) & 197 ADC_DATX_MASK; 198 /* clear irq */ 199 if (info->version == ADC_V2) 200 writel(1, ADC_V2_INT_ST(info->regs)); 201 else 202 writel(1, ADC_V1_INTCLR(info->regs)); 203 204 complete(&info->completion); 205 206 return IRQ_HANDLED; 207 } 208 209 static int exynos_adc_reg_access(struct iio_dev *indio_dev, 210 unsigned reg, unsigned writeval, 211 unsigned *readval) 212 { 213 struct exynos_adc *info = iio_priv(indio_dev); 214 215 if (readval == NULL) 216 return -EINVAL; 217 218 *readval = readl(info->regs + reg); 219 220 return 0; 221 } 222 223 static const struct iio_info exynos_adc_iio_info = { 224 .read_raw = &exynos_read_raw, 225 .debugfs_reg_access = &exynos_adc_reg_access, 226 .driver_module = THIS_MODULE, 227 }; 228 229 #define ADC_CHANNEL(_index, _id) { \ 230 .type = IIO_VOLTAGE, \ 231 .indexed = 1, \ 232 .channel = _index, \ 233 .address = _index, \ 234 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 235 .datasheet_name = _id, \ 236 } 237 238 static const struct iio_chan_spec exynos_adc_iio_channels[] = { 239 ADC_CHANNEL(0, "adc0"), 240 ADC_CHANNEL(1, "adc1"), 241 ADC_CHANNEL(2, "adc2"), 242 ADC_CHANNEL(3, "adc3"), 243 ADC_CHANNEL(4, "adc4"), 244 ADC_CHANNEL(5, "adc5"), 245 ADC_CHANNEL(6, "adc6"), 246 ADC_CHANNEL(7, "adc7"), 247 ADC_CHANNEL(8, "adc8"), 248 ADC_CHANNEL(9, "adc9"), 249 }; 250 251 static int exynos_adc_remove_devices(struct device *dev, void *c) 252 { 253 struct platform_device *pdev = to_platform_device(dev); 254 255 platform_device_unregister(pdev); 256 257 return 0; 258 } 259 260 static int exynos_adc_probe(struct platform_device *pdev) 261 { 262 struct exynos_adc *info = NULL; 263 struct device_node *np = pdev->dev.of_node; 264 struct iio_dev *indio_dev = NULL; 265 struct resource *mem; 266 int ret = -ENODEV; 267 int irq; 268 269 if (!np) 270 return ret; 271 272 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct exynos_adc)); 273 if (!indio_dev) { 274 dev_err(&pdev->dev, "failed allocating iio device\n"); 275 return -ENOMEM; 276 } 277 278 info = iio_priv(indio_dev); 279 280 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 281 info->regs = devm_ioremap_resource(&pdev->dev, mem); 282 if (IS_ERR(info->regs)) 283 return PTR_ERR(info->regs); 284 285 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); 286 info->enable_reg = devm_ioremap_resource(&pdev->dev, mem); 287 if (IS_ERR(info->enable_reg)) 288 return PTR_ERR(info->enable_reg); 289 290 irq = platform_get_irq(pdev, 0); 291 if (irq < 0) { 292 dev_err(&pdev->dev, "no irq resource?\n"); 293 return irq; 294 } 295 296 info->irq = irq; 297 298 init_completion(&info->completion); 299 300 info->clk = devm_clk_get(&pdev->dev, "adc"); 301 if (IS_ERR(info->clk)) { 302 dev_err(&pdev->dev, "failed getting clock, err = %ld\n", 303 PTR_ERR(info->clk)); 304 return PTR_ERR(info->clk); 305 } 306 307 info->vdd = devm_regulator_get(&pdev->dev, "vdd"); 308 if (IS_ERR(info->vdd)) { 309 dev_err(&pdev->dev, "failed getting regulator, err = %ld\n", 310 PTR_ERR(info->vdd)); 311 return PTR_ERR(info->vdd); 312 } 313 314 ret = regulator_enable(info->vdd); 315 if (ret) 316 return ret; 317 318 ret = clk_prepare_enable(info->clk); 319 if (ret) 320 goto err_disable_reg; 321 322 writel(1, info->enable_reg); 323 324 info->version = exynos_adc_get_version(pdev); 325 326 platform_set_drvdata(pdev, indio_dev); 327 328 indio_dev->name = dev_name(&pdev->dev); 329 indio_dev->dev.parent = &pdev->dev; 330 indio_dev->dev.of_node = pdev->dev.of_node; 331 indio_dev->info = &exynos_adc_iio_info; 332 indio_dev->modes = INDIO_DIRECT_MODE; 333 indio_dev->channels = exynos_adc_iio_channels; 334 335 if (info->version == ADC_V1) 336 indio_dev->num_channels = MAX_ADC_V1_CHANNELS; 337 else 338 indio_dev->num_channels = MAX_ADC_V2_CHANNELS; 339 340 ret = request_irq(info->irq, exynos_adc_isr, 341 0, dev_name(&pdev->dev), info); 342 if (ret < 0) { 343 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", 344 info->irq); 345 goto err_disable_clk; 346 } 347 348 ret = iio_device_register(indio_dev); 349 if (ret) 350 goto err_irq; 351 352 exynos_adc_hw_init(info); 353 354 ret = of_platform_populate(np, exynos_adc_match, NULL, &indio_dev->dev); 355 if (ret < 0) { 356 dev_err(&pdev->dev, "failed adding child nodes\n"); 357 goto err_of_populate; 358 } 359 360 return 0; 361 362 err_of_populate: 363 device_for_each_child(&indio_dev->dev, NULL, 364 exynos_adc_remove_devices); 365 iio_device_unregister(indio_dev); 366 err_irq: 367 free_irq(info->irq, info); 368 err_disable_clk: 369 writel(0, info->enable_reg); 370 clk_disable_unprepare(info->clk); 371 err_disable_reg: 372 regulator_disable(info->vdd); 373 return ret; 374 } 375 376 static int exynos_adc_remove(struct platform_device *pdev) 377 { 378 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 379 struct exynos_adc *info = iio_priv(indio_dev); 380 381 device_for_each_child(&indio_dev->dev, NULL, 382 exynos_adc_remove_devices); 383 iio_device_unregister(indio_dev); 384 free_irq(info->irq, info); 385 writel(0, info->enable_reg); 386 clk_disable_unprepare(info->clk); 387 regulator_disable(info->vdd); 388 389 return 0; 390 } 391 392 #ifdef CONFIG_PM_SLEEP 393 static int exynos_adc_suspend(struct device *dev) 394 { 395 struct iio_dev *indio_dev = dev_get_drvdata(dev); 396 struct exynos_adc *info = iio_priv(indio_dev); 397 u32 con; 398 399 if (info->version == ADC_V2) { 400 con = readl(ADC_V2_CON1(info->regs)); 401 con &= ~ADC_CON_EN_START; 402 writel(con, ADC_V2_CON1(info->regs)); 403 } else { 404 con = readl(ADC_V1_CON(info->regs)); 405 con |= ADC_V1_CON_STANDBY; 406 writel(con, ADC_V1_CON(info->regs)); 407 } 408 409 writel(0, info->enable_reg); 410 clk_disable_unprepare(info->clk); 411 regulator_disable(info->vdd); 412 413 return 0; 414 } 415 416 static int exynos_adc_resume(struct device *dev) 417 { 418 struct iio_dev *indio_dev = dev_get_drvdata(dev); 419 struct exynos_adc *info = iio_priv(indio_dev); 420 int ret; 421 422 ret = regulator_enable(info->vdd); 423 if (ret) 424 return ret; 425 426 ret = clk_prepare_enable(info->clk); 427 if (ret) 428 return ret; 429 430 writel(1, info->enable_reg); 431 exynos_adc_hw_init(info); 432 433 return 0; 434 } 435 #endif 436 437 static SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops, 438 exynos_adc_suspend, 439 exynos_adc_resume); 440 441 static struct platform_driver exynos_adc_driver = { 442 .probe = exynos_adc_probe, 443 .remove = exynos_adc_remove, 444 .driver = { 445 .name = "exynos-adc", 446 .owner = THIS_MODULE, 447 .of_match_table = exynos_adc_match, 448 .pm = &exynos_adc_pm_ops, 449 }, 450 }; 451 452 module_platform_driver(exynos_adc_driver); 453 454 MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>"); 455 MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver"); 456 MODULE_LICENSE("GPL v2"); 457