1 /* 2 * exynos_adc.c - Support for ADC in EXYNOS SoCs 3 * 4 * 8 ~ 10 channel, 10/12-bit ADC 5 * 6 * Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/interrupt.h> 26 #include <linux/delay.h> 27 #include <linux/errno.h> 28 #include <linux/kernel.h> 29 #include <linux/slab.h> 30 #include <linux/io.h> 31 #include <linux/clk.h> 32 #include <linux/completion.h> 33 #include <linux/of.h> 34 #include <linux/of_irq.h> 35 #include <linux/regulator/consumer.h> 36 #include <linux/of_platform.h> 37 #include <linux/err.h> 38 #include <linux/input.h> 39 40 #include <linux/iio/iio.h> 41 #include <linux/iio/machine.h> 42 #include <linux/iio/driver.h> 43 #include <linux/mfd/syscon.h> 44 #include <linux/regmap.h> 45 46 #include <linux/platform_data/touchscreen-s3c2410.h> 47 48 /* S3C/EXYNOS4412/5250 ADC_V1 registers definitions */ 49 #define ADC_V1_CON(x) ((x) + 0x00) 50 #define ADC_V1_TSC(x) ((x) + 0x04) 51 #define ADC_V1_DLY(x) ((x) + 0x08) 52 #define ADC_V1_DATX(x) ((x) + 0x0C) 53 #define ADC_V1_DATY(x) ((x) + 0x10) 54 #define ADC_V1_UPDN(x) ((x) + 0x14) 55 #define ADC_V1_INTCLR(x) ((x) + 0x18) 56 #define ADC_V1_MUX(x) ((x) + 0x1c) 57 #define ADC_V1_CLRINTPNDNUP(x) ((x) + 0x20) 58 59 /* S3C2410 ADC registers definitions */ 60 #define ADC_S3C2410_MUX(x) ((x) + 0x18) 61 62 /* Future ADC_V2 registers definitions */ 63 #define ADC_V2_CON1(x) ((x) + 0x00) 64 #define ADC_V2_CON2(x) ((x) + 0x04) 65 #define ADC_V2_STAT(x) ((x) + 0x08) 66 #define ADC_V2_INT_EN(x) ((x) + 0x10) 67 #define ADC_V2_INT_ST(x) ((x) + 0x14) 68 #define ADC_V2_VER(x) ((x) + 0x20) 69 70 /* Bit definitions for ADC_V1 */ 71 #define ADC_V1_CON_RES (1u << 16) 72 #define ADC_V1_CON_PRSCEN (1u << 14) 73 #define ADC_V1_CON_PRSCLV(x) (((x) & 0xFF) << 6) 74 #define ADC_V1_CON_STANDBY (1u << 2) 75 76 /* Bit definitions for S3C2410 ADC */ 77 #define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3) 78 #define ADC_S3C2410_DATX_MASK 0x3FF 79 #define ADC_S3C2416_CON_RES_SEL (1u << 3) 80 81 /* touch screen always uses channel 0 */ 82 #define ADC_S3C2410_MUX_TS 0 83 84 /* ADCTSC Register Bits */ 85 #define ADC_S3C2443_TSC_UD_SEN (1u << 8) 86 #define ADC_S3C2410_TSC_YM_SEN (1u << 7) 87 #define ADC_S3C2410_TSC_YP_SEN (1u << 6) 88 #define ADC_S3C2410_TSC_XM_SEN (1u << 5) 89 #define ADC_S3C2410_TSC_XP_SEN (1u << 4) 90 #define ADC_S3C2410_TSC_PULL_UP_DISABLE (1u << 3) 91 #define ADC_S3C2410_TSC_AUTO_PST (1u << 2) 92 #define ADC_S3C2410_TSC_XY_PST(x) (((x) & 0x3) << 0) 93 94 #define ADC_TSC_WAIT4INT (ADC_S3C2410_TSC_YM_SEN | \ 95 ADC_S3C2410_TSC_YP_SEN | \ 96 ADC_S3C2410_TSC_XP_SEN | \ 97 ADC_S3C2410_TSC_XY_PST(3)) 98 99 #define ADC_TSC_AUTOPST (ADC_S3C2410_TSC_YM_SEN | \ 100 ADC_S3C2410_TSC_YP_SEN | \ 101 ADC_S3C2410_TSC_XP_SEN | \ 102 ADC_S3C2410_TSC_AUTO_PST | \ 103 ADC_S3C2410_TSC_XY_PST(0)) 104 105 /* Bit definitions for ADC_V2 */ 106 #define ADC_V2_CON1_SOFT_RESET (1u << 2) 107 108 #define ADC_V2_CON2_OSEL (1u << 10) 109 #define ADC_V2_CON2_ESEL (1u << 9) 110 #define ADC_V2_CON2_HIGHF (1u << 8) 111 #define ADC_V2_CON2_C_TIME(x) (((x) & 7) << 4) 112 #define ADC_V2_CON2_ACH_SEL(x) (((x) & 0xF) << 0) 113 #define ADC_V2_CON2_ACH_MASK 0xF 114 115 #define MAX_ADC_V2_CHANNELS 10 116 #define MAX_ADC_V1_CHANNELS 8 117 #define MAX_EXYNOS3250_ADC_CHANNELS 2 118 #define MAX_S5PV210_ADC_CHANNELS 10 119 120 /* Bit definitions common for ADC_V1 and ADC_V2 */ 121 #define ADC_CON_EN_START (1u << 0) 122 #define ADC_CON_EN_START_MASK (0x3 << 0) 123 #define ADC_DATX_PRESSED (1u << 15) 124 #define ADC_DATX_MASK 0xFFF 125 #define ADC_DATY_MASK 0xFFF 126 127 #define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100)) 128 129 #define EXYNOS_ADCV1_PHY_OFFSET 0x0718 130 #define EXYNOS_ADCV2_PHY_OFFSET 0x0720 131 132 struct exynos_adc { 133 struct exynos_adc_data *data; 134 struct device *dev; 135 struct input_dev *input; 136 void __iomem *regs; 137 struct regmap *pmu_map; 138 struct clk *clk; 139 struct clk *sclk; 140 unsigned int irq; 141 unsigned int tsirq; 142 unsigned int delay; 143 struct regulator *vdd; 144 145 struct completion completion; 146 147 u32 value; 148 unsigned int version; 149 150 bool read_ts; 151 u32 ts_x; 152 u32 ts_y; 153 }; 154 155 struct exynos_adc_data { 156 int num_channels; 157 bool needs_sclk; 158 bool needs_adc_phy; 159 int phy_offset; 160 u32 mask; 161 162 void (*init_hw)(struct exynos_adc *info); 163 void (*exit_hw)(struct exynos_adc *info); 164 void (*clear_irq)(struct exynos_adc *info); 165 void (*start_conv)(struct exynos_adc *info, unsigned long addr); 166 }; 167 168 static void exynos_adc_unprepare_clk(struct exynos_adc *info) 169 { 170 if (info->data->needs_sclk) 171 clk_unprepare(info->sclk); 172 clk_unprepare(info->clk); 173 } 174 175 static int exynos_adc_prepare_clk(struct exynos_adc *info) 176 { 177 int ret; 178 179 ret = clk_prepare(info->clk); 180 if (ret) { 181 dev_err(info->dev, "failed preparing adc clock: %d\n", ret); 182 return ret; 183 } 184 185 if (info->data->needs_sclk) { 186 ret = clk_prepare(info->sclk); 187 if (ret) { 188 clk_unprepare(info->clk); 189 dev_err(info->dev, 190 "failed preparing sclk_adc clock: %d\n", ret); 191 return ret; 192 } 193 } 194 195 return 0; 196 } 197 198 static void exynos_adc_disable_clk(struct exynos_adc *info) 199 { 200 if (info->data->needs_sclk) 201 clk_disable(info->sclk); 202 clk_disable(info->clk); 203 } 204 205 static int exynos_adc_enable_clk(struct exynos_adc *info) 206 { 207 int ret; 208 209 ret = clk_enable(info->clk); 210 if (ret) { 211 dev_err(info->dev, "failed enabling adc clock: %d\n", ret); 212 return ret; 213 } 214 215 if (info->data->needs_sclk) { 216 ret = clk_enable(info->sclk); 217 if (ret) { 218 clk_disable(info->clk); 219 dev_err(info->dev, 220 "failed enabling sclk_adc clock: %d\n", ret); 221 return ret; 222 } 223 } 224 225 return 0; 226 } 227 228 static void exynos_adc_v1_init_hw(struct exynos_adc *info) 229 { 230 u32 con1; 231 232 if (info->data->needs_adc_phy) 233 regmap_write(info->pmu_map, info->data->phy_offset, 1); 234 235 /* set default prescaler values and Enable prescaler */ 236 con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN; 237 238 /* Enable 12-bit ADC resolution */ 239 con1 |= ADC_V1_CON_RES; 240 writel(con1, ADC_V1_CON(info->regs)); 241 242 /* set touchscreen delay */ 243 writel(info->delay, ADC_V1_DLY(info->regs)); 244 } 245 246 static void exynos_adc_v1_exit_hw(struct exynos_adc *info) 247 { 248 u32 con; 249 250 if (info->data->needs_adc_phy) 251 regmap_write(info->pmu_map, info->data->phy_offset, 0); 252 253 con = readl(ADC_V1_CON(info->regs)); 254 con |= ADC_V1_CON_STANDBY; 255 writel(con, ADC_V1_CON(info->regs)); 256 } 257 258 static void exynos_adc_v1_clear_irq(struct exynos_adc *info) 259 { 260 writel(1, ADC_V1_INTCLR(info->regs)); 261 } 262 263 static void exynos_adc_v1_start_conv(struct exynos_adc *info, 264 unsigned long addr) 265 { 266 u32 con1; 267 268 writel(addr, ADC_V1_MUX(info->regs)); 269 270 con1 = readl(ADC_V1_CON(info->regs)); 271 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); 272 } 273 274 static const struct exynos_adc_data exynos_adc_v1_data = { 275 .num_channels = MAX_ADC_V1_CHANNELS, 276 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 277 .needs_adc_phy = true, 278 .phy_offset = EXYNOS_ADCV1_PHY_OFFSET, 279 280 .init_hw = exynos_adc_v1_init_hw, 281 .exit_hw = exynos_adc_v1_exit_hw, 282 .clear_irq = exynos_adc_v1_clear_irq, 283 .start_conv = exynos_adc_v1_start_conv, 284 }; 285 286 static const struct exynos_adc_data exynos_adc_s5pv210_data = { 287 .num_channels = MAX_S5PV210_ADC_CHANNELS, 288 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 289 290 .init_hw = exynos_adc_v1_init_hw, 291 .exit_hw = exynos_adc_v1_exit_hw, 292 .clear_irq = exynos_adc_v1_clear_irq, 293 .start_conv = exynos_adc_v1_start_conv, 294 }; 295 296 static void exynos_adc_s3c2416_start_conv(struct exynos_adc *info, 297 unsigned long addr) 298 { 299 u32 con1; 300 301 /* Enable 12 bit ADC resolution */ 302 con1 = readl(ADC_V1_CON(info->regs)); 303 con1 |= ADC_S3C2416_CON_RES_SEL; 304 writel(con1, ADC_V1_CON(info->regs)); 305 306 /* Select channel for S3C2416 */ 307 writel(addr, ADC_S3C2410_MUX(info->regs)); 308 309 con1 = readl(ADC_V1_CON(info->regs)); 310 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); 311 } 312 313 static struct exynos_adc_data const exynos_adc_s3c2416_data = { 314 .num_channels = MAX_ADC_V1_CHANNELS, 315 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 316 317 .init_hw = exynos_adc_v1_init_hw, 318 .exit_hw = exynos_adc_v1_exit_hw, 319 .start_conv = exynos_adc_s3c2416_start_conv, 320 }; 321 322 static void exynos_adc_s3c2443_start_conv(struct exynos_adc *info, 323 unsigned long addr) 324 { 325 u32 con1; 326 327 /* Select channel for S3C2433 */ 328 writel(addr, ADC_S3C2410_MUX(info->regs)); 329 330 con1 = readl(ADC_V1_CON(info->regs)); 331 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); 332 } 333 334 static struct exynos_adc_data const exynos_adc_s3c2443_data = { 335 .num_channels = MAX_ADC_V1_CHANNELS, 336 .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */ 337 338 .init_hw = exynos_adc_v1_init_hw, 339 .exit_hw = exynos_adc_v1_exit_hw, 340 .start_conv = exynos_adc_s3c2443_start_conv, 341 }; 342 343 static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info, 344 unsigned long addr) 345 { 346 u32 con1; 347 348 con1 = readl(ADC_V1_CON(info->regs)); 349 con1 &= ~ADC_S3C2410_CON_SELMUX(0x7); 350 con1 |= ADC_S3C2410_CON_SELMUX(addr); 351 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); 352 } 353 354 static struct exynos_adc_data const exynos_adc_s3c24xx_data = { 355 .num_channels = MAX_ADC_V1_CHANNELS, 356 .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */ 357 358 .init_hw = exynos_adc_v1_init_hw, 359 .exit_hw = exynos_adc_v1_exit_hw, 360 .start_conv = exynos_adc_s3c64xx_start_conv, 361 }; 362 363 static struct exynos_adc_data const exynos_adc_s3c64xx_data = { 364 .num_channels = MAX_ADC_V1_CHANNELS, 365 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 366 367 .init_hw = exynos_adc_v1_init_hw, 368 .exit_hw = exynos_adc_v1_exit_hw, 369 .clear_irq = exynos_adc_v1_clear_irq, 370 .start_conv = exynos_adc_s3c64xx_start_conv, 371 }; 372 373 static void exynos_adc_v2_init_hw(struct exynos_adc *info) 374 { 375 u32 con1, con2; 376 377 if (info->data->needs_adc_phy) 378 regmap_write(info->pmu_map, info->data->phy_offset, 1); 379 380 con1 = ADC_V2_CON1_SOFT_RESET; 381 writel(con1, ADC_V2_CON1(info->regs)); 382 383 con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL | 384 ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0); 385 writel(con2, ADC_V2_CON2(info->regs)); 386 387 /* Enable interrupts */ 388 writel(1, ADC_V2_INT_EN(info->regs)); 389 } 390 391 static void exynos_adc_v2_exit_hw(struct exynos_adc *info) 392 { 393 u32 con; 394 395 if (info->data->needs_adc_phy) 396 regmap_write(info->pmu_map, info->data->phy_offset, 0); 397 398 con = readl(ADC_V2_CON1(info->regs)); 399 con &= ~ADC_CON_EN_START; 400 writel(con, ADC_V2_CON1(info->regs)); 401 } 402 403 static void exynos_adc_v2_clear_irq(struct exynos_adc *info) 404 { 405 writel(1, ADC_V2_INT_ST(info->regs)); 406 } 407 408 static void exynos_adc_v2_start_conv(struct exynos_adc *info, 409 unsigned long addr) 410 { 411 u32 con1, con2; 412 413 con2 = readl(ADC_V2_CON2(info->regs)); 414 con2 &= ~ADC_V2_CON2_ACH_MASK; 415 con2 |= ADC_V2_CON2_ACH_SEL(addr); 416 writel(con2, ADC_V2_CON2(info->regs)); 417 418 con1 = readl(ADC_V2_CON1(info->regs)); 419 writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs)); 420 } 421 422 static const struct exynos_adc_data exynos_adc_v2_data = { 423 .num_channels = MAX_ADC_V2_CHANNELS, 424 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 425 .needs_adc_phy = true, 426 .phy_offset = EXYNOS_ADCV2_PHY_OFFSET, 427 428 .init_hw = exynos_adc_v2_init_hw, 429 .exit_hw = exynos_adc_v2_exit_hw, 430 .clear_irq = exynos_adc_v2_clear_irq, 431 .start_conv = exynos_adc_v2_start_conv, 432 }; 433 434 static const struct exynos_adc_data exynos3250_adc_data = { 435 .num_channels = MAX_EXYNOS3250_ADC_CHANNELS, 436 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 437 .needs_sclk = true, 438 .needs_adc_phy = true, 439 .phy_offset = EXYNOS_ADCV1_PHY_OFFSET, 440 441 .init_hw = exynos_adc_v2_init_hw, 442 .exit_hw = exynos_adc_v2_exit_hw, 443 .clear_irq = exynos_adc_v2_clear_irq, 444 .start_conv = exynos_adc_v2_start_conv, 445 }; 446 447 static void exynos_adc_exynos7_init_hw(struct exynos_adc *info) 448 { 449 u32 con1, con2; 450 451 if (info->data->needs_adc_phy) 452 regmap_write(info->pmu_map, info->data->phy_offset, 1); 453 454 con1 = ADC_V2_CON1_SOFT_RESET; 455 writel(con1, ADC_V2_CON1(info->regs)); 456 457 con2 = readl(ADC_V2_CON2(info->regs)); 458 con2 &= ~ADC_V2_CON2_C_TIME(7); 459 con2 |= ADC_V2_CON2_C_TIME(0); 460 writel(con2, ADC_V2_CON2(info->regs)); 461 462 /* Enable interrupts */ 463 writel(1, ADC_V2_INT_EN(info->regs)); 464 } 465 466 static const struct exynos_adc_data exynos7_adc_data = { 467 .num_channels = MAX_ADC_V1_CHANNELS, 468 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 469 470 .init_hw = exynos_adc_exynos7_init_hw, 471 .exit_hw = exynos_adc_v2_exit_hw, 472 .clear_irq = exynos_adc_v2_clear_irq, 473 .start_conv = exynos_adc_v2_start_conv, 474 }; 475 476 static const struct of_device_id exynos_adc_match[] = { 477 { 478 .compatible = "samsung,s3c2410-adc", 479 .data = &exynos_adc_s3c24xx_data, 480 }, { 481 .compatible = "samsung,s3c2416-adc", 482 .data = &exynos_adc_s3c2416_data, 483 }, { 484 .compatible = "samsung,s3c2440-adc", 485 .data = &exynos_adc_s3c24xx_data, 486 }, { 487 .compatible = "samsung,s3c2443-adc", 488 .data = &exynos_adc_s3c2443_data, 489 }, { 490 .compatible = "samsung,s3c6410-adc", 491 .data = &exynos_adc_s3c64xx_data, 492 }, { 493 .compatible = "samsung,s5pv210-adc", 494 .data = &exynos_adc_s5pv210_data, 495 }, { 496 .compatible = "samsung,exynos-adc-v1", 497 .data = &exynos_adc_v1_data, 498 }, { 499 .compatible = "samsung,exynos-adc-v2", 500 .data = &exynos_adc_v2_data, 501 }, { 502 .compatible = "samsung,exynos3250-adc", 503 .data = &exynos3250_adc_data, 504 }, { 505 .compatible = "samsung,exynos7-adc", 506 .data = &exynos7_adc_data, 507 }, 508 {}, 509 }; 510 MODULE_DEVICE_TABLE(of, exynos_adc_match); 511 512 static struct exynos_adc_data *exynos_adc_get_data(struct platform_device *pdev) 513 { 514 const struct of_device_id *match; 515 516 match = of_match_node(exynos_adc_match, pdev->dev.of_node); 517 return (struct exynos_adc_data *)match->data; 518 } 519 520 static int exynos_read_raw(struct iio_dev *indio_dev, 521 struct iio_chan_spec const *chan, 522 int *val, 523 int *val2, 524 long mask) 525 { 526 struct exynos_adc *info = iio_priv(indio_dev); 527 unsigned long timeout; 528 int ret; 529 530 if (mask != IIO_CHAN_INFO_RAW) 531 return -EINVAL; 532 533 mutex_lock(&indio_dev->mlock); 534 reinit_completion(&info->completion); 535 536 /* Select the channel to be used and Trigger conversion */ 537 if (info->data->start_conv) 538 info->data->start_conv(info, chan->address); 539 540 timeout = wait_for_completion_timeout(&info->completion, 541 EXYNOS_ADC_TIMEOUT); 542 if (timeout == 0) { 543 dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n"); 544 if (info->data->init_hw) 545 info->data->init_hw(info); 546 ret = -ETIMEDOUT; 547 } else { 548 *val = info->value; 549 *val2 = 0; 550 ret = IIO_VAL_INT; 551 } 552 553 mutex_unlock(&indio_dev->mlock); 554 555 return ret; 556 } 557 558 static int exynos_read_s3c64xx_ts(struct iio_dev *indio_dev, int *x, int *y) 559 { 560 struct exynos_adc *info = iio_priv(indio_dev); 561 unsigned long timeout; 562 int ret; 563 564 mutex_lock(&indio_dev->mlock); 565 info->read_ts = true; 566 567 reinit_completion(&info->completion); 568 569 writel(ADC_S3C2410_TSC_PULL_UP_DISABLE | ADC_TSC_AUTOPST, 570 ADC_V1_TSC(info->regs)); 571 572 /* Select the ts channel to be used and Trigger conversion */ 573 info->data->start_conv(info, ADC_S3C2410_MUX_TS); 574 575 timeout = wait_for_completion_timeout(&info->completion, 576 EXYNOS_ADC_TIMEOUT); 577 if (timeout == 0) { 578 dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n"); 579 if (info->data->init_hw) 580 info->data->init_hw(info); 581 ret = -ETIMEDOUT; 582 } else { 583 *x = info->ts_x; 584 *y = info->ts_y; 585 ret = 0; 586 } 587 588 info->read_ts = false; 589 mutex_unlock(&indio_dev->mlock); 590 591 return ret; 592 } 593 594 static irqreturn_t exynos_adc_isr(int irq, void *dev_id) 595 { 596 struct exynos_adc *info = dev_id; 597 u32 mask = info->data->mask; 598 599 /* Read value */ 600 if (info->read_ts) { 601 info->ts_x = readl(ADC_V1_DATX(info->regs)); 602 info->ts_y = readl(ADC_V1_DATY(info->regs)); 603 writel(ADC_TSC_WAIT4INT | ADC_S3C2443_TSC_UD_SEN, ADC_V1_TSC(info->regs)); 604 } else { 605 info->value = readl(ADC_V1_DATX(info->regs)) & mask; 606 } 607 608 /* clear irq */ 609 if (info->data->clear_irq) 610 info->data->clear_irq(info); 611 612 complete(&info->completion); 613 614 return IRQ_HANDLED; 615 } 616 617 /* 618 * Here we (ab)use a threaded interrupt handler to stay running 619 * for as long as the touchscreen remains pressed, we report 620 * a new event with the latest data and then sleep until the 621 * next timer tick. This mirrors the behavior of the old 622 * driver, with much less code. 623 */ 624 static irqreturn_t exynos_ts_isr(int irq, void *dev_id) 625 { 626 struct exynos_adc *info = dev_id; 627 struct iio_dev *dev = dev_get_drvdata(info->dev); 628 u32 x, y; 629 bool pressed; 630 int ret; 631 632 while (info->input->users) { 633 ret = exynos_read_s3c64xx_ts(dev, &x, &y); 634 if (ret == -ETIMEDOUT) 635 break; 636 637 pressed = x & y & ADC_DATX_PRESSED; 638 if (!pressed) { 639 input_report_key(info->input, BTN_TOUCH, 0); 640 input_sync(info->input); 641 break; 642 } 643 644 input_report_abs(info->input, ABS_X, x & ADC_DATX_MASK); 645 input_report_abs(info->input, ABS_Y, y & ADC_DATY_MASK); 646 input_report_key(info->input, BTN_TOUCH, 1); 647 input_sync(info->input); 648 649 usleep_range(1000, 1100); 650 }; 651 652 writel(0, ADC_V1_CLRINTPNDNUP(info->regs)); 653 654 return IRQ_HANDLED; 655 } 656 657 static int exynos_adc_reg_access(struct iio_dev *indio_dev, 658 unsigned reg, unsigned writeval, 659 unsigned *readval) 660 { 661 struct exynos_adc *info = iio_priv(indio_dev); 662 663 if (readval == NULL) 664 return -EINVAL; 665 666 *readval = readl(info->regs + reg); 667 668 return 0; 669 } 670 671 static const struct iio_info exynos_adc_iio_info = { 672 .read_raw = &exynos_read_raw, 673 .debugfs_reg_access = &exynos_adc_reg_access, 674 }; 675 676 #define ADC_CHANNEL(_index, _id) { \ 677 .type = IIO_VOLTAGE, \ 678 .indexed = 1, \ 679 .channel = _index, \ 680 .address = _index, \ 681 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 682 .datasheet_name = _id, \ 683 } 684 685 static const struct iio_chan_spec exynos_adc_iio_channels[] = { 686 ADC_CHANNEL(0, "adc0"), 687 ADC_CHANNEL(1, "adc1"), 688 ADC_CHANNEL(2, "adc2"), 689 ADC_CHANNEL(3, "adc3"), 690 ADC_CHANNEL(4, "adc4"), 691 ADC_CHANNEL(5, "adc5"), 692 ADC_CHANNEL(6, "adc6"), 693 ADC_CHANNEL(7, "adc7"), 694 ADC_CHANNEL(8, "adc8"), 695 ADC_CHANNEL(9, "adc9"), 696 }; 697 698 static int exynos_adc_remove_devices(struct device *dev, void *c) 699 { 700 struct platform_device *pdev = to_platform_device(dev); 701 702 platform_device_unregister(pdev); 703 704 return 0; 705 } 706 707 static int exynos_adc_ts_open(struct input_dev *dev) 708 { 709 struct exynos_adc *info = input_get_drvdata(dev); 710 711 enable_irq(info->tsirq); 712 713 return 0; 714 } 715 716 static void exynos_adc_ts_close(struct input_dev *dev) 717 { 718 struct exynos_adc *info = input_get_drvdata(dev); 719 720 disable_irq(info->tsirq); 721 } 722 723 static int exynos_adc_ts_init(struct exynos_adc *info) 724 { 725 int ret; 726 727 if (info->tsirq <= 0) 728 return -ENODEV; 729 730 info->input = input_allocate_device(); 731 if (!info->input) 732 return -ENOMEM; 733 734 info->input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); 735 info->input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH); 736 737 input_set_abs_params(info->input, ABS_X, 0, 0x3FF, 0, 0); 738 input_set_abs_params(info->input, ABS_Y, 0, 0x3FF, 0, 0); 739 740 info->input->name = "S3C24xx TouchScreen"; 741 info->input->id.bustype = BUS_HOST; 742 info->input->open = exynos_adc_ts_open; 743 info->input->close = exynos_adc_ts_close; 744 745 input_set_drvdata(info->input, info); 746 747 ret = input_register_device(info->input); 748 if (ret) { 749 input_free_device(info->input); 750 return ret; 751 } 752 753 disable_irq(info->tsirq); 754 ret = request_threaded_irq(info->tsirq, NULL, exynos_ts_isr, 755 IRQF_ONESHOT, "touchscreen", info); 756 if (ret) 757 input_unregister_device(info->input); 758 759 return ret; 760 } 761 762 static int exynos_adc_probe(struct platform_device *pdev) 763 { 764 struct exynos_adc *info = NULL; 765 struct device_node *np = pdev->dev.of_node; 766 struct s3c2410_ts_mach_info *pdata = dev_get_platdata(&pdev->dev); 767 struct iio_dev *indio_dev = NULL; 768 struct resource *mem; 769 bool has_ts = false; 770 int ret = -ENODEV; 771 int irq; 772 773 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct exynos_adc)); 774 if (!indio_dev) { 775 dev_err(&pdev->dev, "failed allocating iio device\n"); 776 return -ENOMEM; 777 } 778 779 info = iio_priv(indio_dev); 780 781 info->data = exynos_adc_get_data(pdev); 782 if (!info->data) { 783 dev_err(&pdev->dev, "failed getting exynos_adc_data\n"); 784 return -EINVAL; 785 } 786 787 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 788 info->regs = devm_ioremap_resource(&pdev->dev, mem); 789 if (IS_ERR(info->regs)) 790 return PTR_ERR(info->regs); 791 792 793 if (info->data->needs_adc_phy) { 794 info->pmu_map = syscon_regmap_lookup_by_phandle( 795 pdev->dev.of_node, 796 "samsung,syscon-phandle"); 797 if (IS_ERR(info->pmu_map)) { 798 dev_err(&pdev->dev, "syscon regmap lookup failed.\n"); 799 return PTR_ERR(info->pmu_map); 800 } 801 } 802 803 irq = platform_get_irq(pdev, 0); 804 if (irq < 0) { 805 dev_err(&pdev->dev, "no irq resource?\n"); 806 return irq; 807 } 808 info->irq = irq; 809 810 irq = platform_get_irq(pdev, 1); 811 if (irq == -EPROBE_DEFER) 812 return irq; 813 814 info->tsirq = irq; 815 816 info->dev = &pdev->dev; 817 818 init_completion(&info->completion); 819 820 info->clk = devm_clk_get(&pdev->dev, "adc"); 821 if (IS_ERR(info->clk)) { 822 dev_err(&pdev->dev, "failed getting clock, err = %ld\n", 823 PTR_ERR(info->clk)); 824 return PTR_ERR(info->clk); 825 } 826 827 if (info->data->needs_sclk) { 828 info->sclk = devm_clk_get(&pdev->dev, "sclk"); 829 if (IS_ERR(info->sclk)) { 830 dev_err(&pdev->dev, 831 "failed getting sclk clock, err = %ld\n", 832 PTR_ERR(info->sclk)); 833 return PTR_ERR(info->sclk); 834 } 835 } 836 837 info->vdd = devm_regulator_get(&pdev->dev, "vdd"); 838 if (IS_ERR(info->vdd)) { 839 dev_err(&pdev->dev, "failed getting regulator, err = %ld\n", 840 PTR_ERR(info->vdd)); 841 return PTR_ERR(info->vdd); 842 } 843 844 ret = regulator_enable(info->vdd); 845 if (ret) 846 return ret; 847 848 ret = exynos_adc_prepare_clk(info); 849 if (ret) 850 goto err_disable_reg; 851 852 ret = exynos_adc_enable_clk(info); 853 if (ret) 854 goto err_unprepare_clk; 855 856 platform_set_drvdata(pdev, indio_dev); 857 858 indio_dev->name = dev_name(&pdev->dev); 859 indio_dev->dev.parent = &pdev->dev; 860 indio_dev->dev.of_node = pdev->dev.of_node; 861 indio_dev->info = &exynos_adc_iio_info; 862 indio_dev->modes = INDIO_DIRECT_MODE; 863 indio_dev->channels = exynos_adc_iio_channels; 864 indio_dev->num_channels = info->data->num_channels; 865 866 ret = request_irq(info->irq, exynos_adc_isr, 867 0, dev_name(&pdev->dev), info); 868 if (ret < 0) { 869 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", 870 info->irq); 871 goto err_disable_clk; 872 } 873 874 ret = iio_device_register(indio_dev); 875 if (ret) 876 goto err_irq; 877 878 if (info->data->init_hw) 879 info->data->init_hw(info); 880 881 /* leave out any TS related code if unreachable */ 882 if (IS_REACHABLE(CONFIG_INPUT)) { 883 has_ts = of_property_read_bool(pdev->dev.of_node, 884 "has-touchscreen") || pdata; 885 } 886 887 if (pdata) 888 info->delay = pdata->delay; 889 else 890 info->delay = 10000; 891 892 if (has_ts) 893 ret = exynos_adc_ts_init(info); 894 if (ret) 895 goto err_iio; 896 897 ret = of_platform_populate(np, exynos_adc_match, NULL, &indio_dev->dev); 898 if (ret < 0) { 899 dev_err(&pdev->dev, "failed adding child nodes\n"); 900 goto err_of_populate; 901 } 902 903 return 0; 904 905 err_of_populate: 906 device_for_each_child(&indio_dev->dev, NULL, 907 exynos_adc_remove_devices); 908 if (has_ts) { 909 input_unregister_device(info->input); 910 free_irq(info->tsirq, info); 911 } 912 err_iio: 913 iio_device_unregister(indio_dev); 914 err_irq: 915 free_irq(info->irq, info); 916 err_disable_clk: 917 if (info->data->exit_hw) 918 info->data->exit_hw(info); 919 exynos_adc_disable_clk(info); 920 err_unprepare_clk: 921 exynos_adc_unprepare_clk(info); 922 err_disable_reg: 923 regulator_disable(info->vdd); 924 return ret; 925 } 926 927 static int exynos_adc_remove(struct platform_device *pdev) 928 { 929 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 930 struct exynos_adc *info = iio_priv(indio_dev); 931 932 if (IS_REACHABLE(CONFIG_INPUT)) { 933 free_irq(info->tsirq, info); 934 input_unregister_device(info->input); 935 } 936 device_for_each_child(&indio_dev->dev, NULL, 937 exynos_adc_remove_devices); 938 iio_device_unregister(indio_dev); 939 free_irq(info->irq, info); 940 if (info->data->exit_hw) 941 info->data->exit_hw(info); 942 exynos_adc_disable_clk(info); 943 exynos_adc_unprepare_clk(info); 944 regulator_disable(info->vdd); 945 946 return 0; 947 } 948 949 #ifdef CONFIG_PM_SLEEP 950 static int exynos_adc_suspend(struct device *dev) 951 { 952 struct iio_dev *indio_dev = dev_get_drvdata(dev); 953 struct exynos_adc *info = iio_priv(indio_dev); 954 955 if (info->data->exit_hw) 956 info->data->exit_hw(info); 957 exynos_adc_disable_clk(info); 958 regulator_disable(info->vdd); 959 960 return 0; 961 } 962 963 static int exynos_adc_resume(struct device *dev) 964 { 965 struct iio_dev *indio_dev = dev_get_drvdata(dev); 966 struct exynos_adc *info = iio_priv(indio_dev); 967 int ret; 968 969 ret = regulator_enable(info->vdd); 970 if (ret) 971 return ret; 972 973 ret = exynos_adc_enable_clk(info); 974 if (ret) 975 return ret; 976 977 if (info->data->init_hw) 978 info->data->init_hw(info); 979 980 return 0; 981 } 982 #endif 983 984 static SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops, 985 exynos_adc_suspend, 986 exynos_adc_resume); 987 988 static struct platform_driver exynos_adc_driver = { 989 .probe = exynos_adc_probe, 990 .remove = exynos_adc_remove, 991 .driver = { 992 .name = "exynos-adc", 993 .of_match_table = exynos_adc_match, 994 .pm = &exynos_adc_pm_ops, 995 }, 996 }; 997 998 module_platform_driver(exynos_adc_driver); 999 1000 MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>"); 1001 MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver"); 1002 MODULE_LICENSE("GPL v2"); 1003