1 /* 2 * exynos_adc.c - Support for ADC in EXYNOS SoCs 3 * 4 * 8 ~ 10 channel, 10/12-bit ADC 5 * 6 * Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 21 */ 22 23 #include <linux/module.h> 24 #include <linux/platform_device.h> 25 #include <linux/interrupt.h> 26 #include <linux/delay.h> 27 #include <linux/kernel.h> 28 #include <linux/slab.h> 29 #include <linux/io.h> 30 #include <linux/clk.h> 31 #include <linux/completion.h> 32 #include <linux/of.h> 33 #include <linux/of_irq.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/of_platform.h> 36 37 #include <linux/iio/iio.h> 38 #include <linux/iio/machine.h> 39 #include <linux/iio/driver.h> 40 41 enum adc_version { 42 ADC_V1, 43 ADC_V2 44 }; 45 46 /* EXYNOS4412/5250 ADC_V1 registers definitions */ 47 #define ADC_V1_CON(x) ((x) + 0x00) 48 #define ADC_V1_DLY(x) ((x) + 0x08) 49 #define ADC_V1_DATX(x) ((x) + 0x0C) 50 #define ADC_V1_INTCLR(x) ((x) + 0x18) 51 #define ADC_V1_MUX(x) ((x) + 0x1c) 52 53 /* Future ADC_V2 registers definitions */ 54 #define ADC_V2_CON1(x) ((x) + 0x00) 55 #define ADC_V2_CON2(x) ((x) + 0x04) 56 #define ADC_V2_STAT(x) ((x) + 0x08) 57 #define ADC_V2_INT_EN(x) ((x) + 0x10) 58 #define ADC_V2_INT_ST(x) ((x) + 0x14) 59 #define ADC_V2_VER(x) ((x) + 0x20) 60 61 /* Bit definitions for ADC_V1 */ 62 #define ADC_V1_CON_RES (1u << 16) 63 #define ADC_V1_CON_PRSCEN (1u << 14) 64 #define ADC_V1_CON_PRSCLV(x) (((x) & 0xFF) << 6) 65 #define ADC_V1_CON_STANDBY (1u << 2) 66 67 /* Bit definitions for ADC_V2 */ 68 #define ADC_V2_CON1_SOFT_RESET (1u << 2) 69 70 #define ADC_V2_CON2_OSEL (1u << 10) 71 #define ADC_V2_CON2_ESEL (1u << 9) 72 #define ADC_V2_CON2_HIGHF (1u << 8) 73 #define ADC_V2_CON2_C_TIME(x) (((x) & 7) << 4) 74 #define ADC_V2_CON2_ACH_SEL(x) (((x) & 0xF) << 0) 75 #define ADC_V2_CON2_ACH_MASK 0xF 76 77 #define MAX_ADC_V2_CHANNELS 10 78 #define MAX_ADC_V1_CHANNELS 8 79 80 /* Bit definitions common for ADC_V1 and ADC_V2 */ 81 #define ADC_CON_EN_START (1u << 0) 82 #define ADC_DATX_MASK 0xFFF 83 84 #define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(1000)) 85 86 struct exynos_adc { 87 void __iomem *regs; 88 void __iomem *enable_reg; 89 struct clk *clk; 90 unsigned int irq; 91 struct regulator *vdd; 92 93 struct completion completion; 94 95 u32 value; 96 unsigned int version; 97 }; 98 99 static const struct of_device_id exynos_adc_match[] = { 100 { .compatible = "samsung,exynos-adc-v1", .data = (void *)ADC_V1 }, 101 { .compatible = "samsung,exynos-adc-v2", .data = (void *)ADC_V2 }, 102 {}, 103 }; 104 MODULE_DEVICE_TABLE(of, exynos_adc_match); 105 106 static inline unsigned int exynos_adc_get_version(struct platform_device *pdev) 107 { 108 const struct of_device_id *match; 109 110 match = of_match_node(exynos_adc_match, pdev->dev.of_node); 111 return (unsigned int)match->data; 112 } 113 114 static int exynos_read_raw(struct iio_dev *indio_dev, 115 struct iio_chan_spec const *chan, 116 int *val, 117 int *val2, 118 long mask) 119 { 120 struct exynos_adc *info = iio_priv(indio_dev); 121 unsigned long timeout; 122 u32 con1, con2; 123 124 if (mask != IIO_CHAN_INFO_RAW) 125 return -EINVAL; 126 127 mutex_lock(&indio_dev->mlock); 128 129 /* Select the channel to be used and Trigger conversion */ 130 if (info->version == ADC_V2) { 131 con2 = readl(ADC_V2_CON2(info->regs)); 132 con2 &= ~ADC_V2_CON2_ACH_MASK; 133 con2 |= ADC_V2_CON2_ACH_SEL(chan->address); 134 writel(con2, ADC_V2_CON2(info->regs)); 135 136 con1 = readl(ADC_V2_CON1(info->regs)); 137 writel(con1 | ADC_CON_EN_START, 138 ADC_V2_CON1(info->regs)); 139 } else { 140 writel(chan->address, ADC_V1_MUX(info->regs)); 141 142 con1 = readl(ADC_V1_CON(info->regs)); 143 writel(con1 | ADC_CON_EN_START, 144 ADC_V1_CON(info->regs)); 145 } 146 147 timeout = wait_for_completion_interruptible_timeout 148 (&info->completion, EXYNOS_ADC_TIMEOUT); 149 *val = info->value; 150 151 mutex_unlock(&indio_dev->mlock); 152 153 if (timeout == 0) 154 return -ETIMEDOUT; 155 156 return IIO_VAL_INT; 157 } 158 159 static irqreturn_t exynos_adc_isr(int irq, void *dev_id) 160 { 161 struct exynos_adc *info = (struct exynos_adc *)dev_id; 162 163 /* Read value */ 164 info->value = readl(ADC_V1_DATX(info->regs)) & 165 ADC_DATX_MASK; 166 /* clear irq */ 167 if (info->version == ADC_V2) 168 writel(1, ADC_V2_INT_ST(info->regs)); 169 else 170 writel(1, ADC_V1_INTCLR(info->regs)); 171 172 complete(&info->completion); 173 174 return IRQ_HANDLED; 175 } 176 177 static int exynos_adc_reg_access(struct iio_dev *indio_dev, 178 unsigned reg, unsigned writeval, 179 unsigned *readval) 180 { 181 struct exynos_adc *info = iio_priv(indio_dev); 182 183 if (readval == NULL) 184 return -EINVAL; 185 186 *readval = readl(info->regs + reg); 187 188 return 0; 189 } 190 191 static const struct iio_info exynos_adc_iio_info = { 192 .read_raw = &exynos_read_raw, 193 .debugfs_reg_access = &exynos_adc_reg_access, 194 .driver_module = THIS_MODULE, 195 }; 196 197 #define ADC_CHANNEL(_index, _id) { \ 198 .type = IIO_VOLTAGE, \ 199 .indexed = 1, \ 200 .channel = _index, \ 201 .address = _index, \ 202 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 203 .datasheet_name = _id, \ 204 } 205 206 static const struct iio_chan_spec exynos_adc_iio_channels[] = { 207 ADC_CHANNEL(0, "adc0"), 208 ADC_CHANNEL(1, "adc1"), 209 ADC_CHANNEL(2, "adc2"), 210 ADC_CHANNEL(3, "adc3"), 211 ADC_CHANNEL(4, "adc4"), 212 ADC_CHANNEL(5, "adc5"), 213 ADC_CHANNEL(6, "adc6"), 214 ADC_CHANNEL(7, "adc7"), 215 ADC_CHANNEL(8, "adc8"), 216 ADC_CHANNEL(9, "adc9"), 217 }; 218 219 static int exynos_adc_remove_devices(struct device *dev, void *c) 220 { 221 struct platform_device *pdev = to_platform_device(dev); 222 223 platform_device_unregister(pdev); 224 225 return 0; 226 } 227 228 static void exynos_adc_hw_init(struct exynos_adc *info) 229 { 230 u32 con1, con2; 231 232 if (info->version == ADC_V2) { 233 con1 = ADC_V2_CON1_SOFT_RESET; 234 writel(con1, ADC_V2_CON1(info->regs)); 235 236 con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL | 237 ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0); 238 writel(con2, ADC_V2_CON2(info->regs)); 239 240 /* Enable interrupts */ 241 writel(1, ADC_V2_INT_EN(info->regs)); 242 } else { 243 /* set default prescaler values and Enable prescaler */ 244 con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN; 245 246 /* Enable 12-bit ADC resolution */ 247 con1 |= ADC_V1_CON_RES; 248 writel(con1, ADC_V1_CON(info->regs)); 249 } 250 } 251 252 static int exynos_adc_probe(struct platform_device *pdev) 253 { 254 struct exynos_adc *info = NULL; 255 struct device_node *np = pdev->dev.of_node; 256 struct iio_dev *indio_dev = NULL; 257 struct resource *mem; 258 int ret = -ENODEV; 259 int irq; 260 261 if (!np) 262 return ret; 263 264 indio_dev = iio_device_alloc(sizeof(struct exynos_adc)); 265 if (!indio_dev) { 266 dev_err(&pdev->dev, "failed allocating iio device\n"); 267 return -ENOMEM; 268 } 269 270 info = iio_priv(indio_dev); 271 272 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 273 info->regs = devm_ioremap_resource(&pdev->dev, mem); 274 if (IS_ERR(info->regs)) { 275 ret = PTR_ERR(info->regs); 276 goto err_iio; 277 } 278 279 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1); 280 info->enable_reg = devm_ioremap_resource(&pdev->dev, mem); 281 if (IS_ERR(info->enable_reg)) { 282 ret = PTR_ERR(info->enable_reg); 283 goto err_iio; 284 } 285 286 irq = platform_get_irq(pdev, 0); 287 if (irq < 0) { 288 dev_err(&pdev->dev, "no irq resource?\n"); 289 ret = irq; 290 goto err_iio; 291 } 292 293 info->irq = irq; 294 295 init_completion(&info->completion); 296 297 ret = request_irq(info->irq, exynos_adc_isr, 298 0, dev_name(&pdev->dev), info); 299 if (ret < 0) { 300 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", 301 info->irq); 302 goto err_iio; 303 } 304 305 writel(1, info->enable_reg); 306 307 info->clk = devm_clk_get(&pdev->dev, "adc"); 308 if (IS_ERR(info->clk)) { 309 dev_err(&pdev->dev, "failed getting clock, err = %ld\n", 310 PTR_ERR(info->clk)); 311 ret = PTR_ERR(info->clk); 312 goto err_irq; 313 } 314 315 info->vdd = devm_regulator_get(&pdev->dev, "vdd"); 316 if (IS_ERR(info->vdd)) { 317 dev_err(&pdev->dev, "failed getting regulator, err = %ld\n", 318 PTR_ERR(info->vdd)); 319 ret = PTR_ERR(info->vdd); 320 goto err_irq; 321 } 322 323 info->version = exynos_adc_get_version(pdev); 324 325 platform_set_drvdata(pdev, indio_dev); 326 327 indio_dev->name = dev_name(&pdev->dev); 328 indio_dev->dev.parent = &pdev->dev; 329 indio_dev->dev.of_node = pdev->dev.of_node; 330 indio_dev->info = &exynos_adc_iio_info; 331 indio_dev->modes = INDIO_DIRECT_MODE; 332 indio_dev->channels = exynos_adc_iio_channels; 333 334 if (info->version == ADC_V1) 335 indio_dev->num_channels = MAX_ADC_V1_CHANNELS; 336 else 337 indio_dev->num_channels = MAX_ADC_V2_CHANNELS; 338 339 ret = iio_device_register(indio_dev); 340 if (ret) 341 goto err_irq; 342 343 ret = regulator_enable(info->vdd); 344 if (ret) 345 goto err_iio_dev; 346 347 clk_prepare_enable(info->clk); 348 349 exynos_adc_hw_init(info); 350 351 ret = of_platform_populate(np, exynos_adc_match, NULL, &pdev->dev); 352 if (ret < 0) { 353 dev_err(&pdev->dev, "failed adding child nodes\n"); 354 goto err_of_populate; 355 } 356 357 return 0; 358 359 err_of_populate: 360 device_for_each_child(&pdev->dev, NULL, 361 exynos_adc_remove_devices); 362 regulator_disable(info->vdd); 363 clk_disable_unprepare(info->clk); 364 err_iio_dev: 365 iio_device_unregister(indio_dev); 366 err_irq: 367 free_irq(info->irq, info); 368 err_iio: 369 iio_device_free(indio_dev); 370 return ret; 371 } 372 373 static int exynos_adc_remove(struct platform_device *pdev) 374 { 375 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 376 struct exynos_adc *info = iio_priv(indio_dev); 377 378 device_for_each_child(&pdev->dev, NULL, 379 exynos_adc_remove_devices); 380 regulator_disable(info->vdd); 381 clk_disable_unprepare(info->clk); 382 writel(0, info->enable_reg); 383 iio_device_unregister(indio_dev); 384 free_irq(info->irq, info); 385 iio_device_free(indio_dev); 386 387 return 0; 388 } 389 390 #ifdef CONFIG_PM_SLEEP 391 static int exynos_adc_suspend(struct device *dev) 392 { 393 struct iio_dev *indio_dev = dev_get_drvdata(dev); 394 struct exynos_adc *info = iio_priv(indio_dev); 395 u32 con; 396 397 if (info->version == ADC_V2) { 398 con = readl(ADC_V2_CON1(info->regs)); 399 con &= ~ADC_CON_EN_START; 400 writel(con, ADC_V2_CON1(info->regs)); 401 } else { 402 con = readl(ADC_V1_CON(info->regs)); 403 con |= ADC_V1_CON_STANDBY; 404 writel(con, ADC_V1_CON(info->regs)); 405 } 406 407 clk_disable_unprepare(info->clk); 408 writel(0, info->enable_reg); 409 regulator_disable(info->vdd); 410 411 return 0; 412 } 413 414 static int exynos_adc_resume(struct device *dev) 415 { 416 struct iio_dev *indio_dev = dev_get_drvdata(dev); 417 struct exynos_adc *info = iio_priv(indio_dev); 418 int ret; 419 420 ret = regulator_enable(info->vdd); 421 if (ret) 422 return ret; 423 424 writel(1, info->enable_reg); 425 clk_prepare_enable(info->clk); 426 427 exynos_adc_hw_init(info); 428 429 return 0; 430 } 431 #endif 432 433 static SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops, 434 exynos_adc_suspend, 435 exynos_adc_resume); 436 437 static struct platform_driver exynos_adc_driver = { 438 .probe = exynos_adc_probe, 439 .remove = exynos_adc_remove, 440 .driver = { 441 .name = "exynos-adc", 442 .owner = THIS_MODULE, 443 .of_match_table = exynos_adc_match, 444 .pm = &exynos_adc_pm_ops, 445 }, 446 }; 447 448 module_platform_driver(exynos_adc_driver); 449 450 MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>"); 451 MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver"); 452 MODULE_LICENSE("GPL v2"); 453