1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * exynos_adc.c - Support for ADC in EXYNOS SoCs 4 * 5 * 8 ~ 10 channel, 10/12-bit ADC 6 * 7 * Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com> 8 */ 9 10 #include <linux/module.h> 11 #include <linux/platform_device.h> 12 #include <linux/interrupt.h> 13 #include <linux/delay.h> 14 #include <linux/errno.h> 15 #include <linux/kernel.h> 16 #include <linux/slab.h> 17 #include <linux/io.h> 18 #include <linux/clk.h> 19 #include <linux/completion.h> 20 #include <linux/of.h> 21 #include <linux/of_irq.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/of_platform.h> 24 #include <linux/err.h> 25 #include <linux/input.h> 26 27 #include <linux/iio/iio.h> 28 #include <linux/iio/machine.h> 29 #include <linux/iio/driver.h> 30 #include <linux/mfd/syscon.h> 31 #include <linux/regmap.h> 32 33 #include <linux/platform_data/touchscreen-s3c2410.h> 34 35 /* S3C/EXYNOS4412/5250 ADC_V1 registers definitions */ 36 #define ADC_V1_CON(x) ((x) + 0x00) 37 #define ADC_V1_TSC(x) ((x) + 0x04) 38 #define ADC_V1_DLY(x) ((x) + 0x08) 39 #define ADC_V1_DATX(x) ((x) + 0x0C) 40 #define ADC_V1_DATY(x) ((x) + 0x10) 41 #define ADC_V1_UPDN(x) ((x) + 0x14) 42 #define ADC_V1_INTCLR(x) ((x) + 0x18) 43 #define ADC_V1_MUX(x) ((x) + 0x1c) 44 #define ADC_V1_CLRINTPNDNUP(x) ((x) + 0x20) 45 46 /* S3C2410 ADC registers definitions */ 47 #define ADC_S3C2410_MUX(x) ((x) + 0x18) 48 49 /* Future ADC_V2 registers definitions */ 50 #define ADC_V2_CON1(x) ((x) + 0x00) 51 #define ADC_V2_CON2(x) ((x) + 0x04) 52 #define ADC_V2_STAT(x) ((x) + 0x08) 53 #define ADC_V2_INT_EN(x) ((x) + 0x10) 54 #define ADC_V2_INT_ST(x) ((x) + 0x14) 55 #define ADC_V2_VER(x) ((x) + 0x20) 56 57 /* Bit definitions for ADC_V1 */ 58 #define ADC_V1_CON_RES (1u << 16) 59 #define ADC_V1_CON_PRSCEN (1u << 14) 60 #define ADC_V1_CON_PRSCLV(x) (((x) & 0xFF) << 6) 61 #define ADC_V1_CON_STANDBY (1u << 2) 62 63 /* Bit definitions for S3C2410 ADC */ 64 #define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3) 65 #define ADC_S3C2410_DATX_MASK 0x3FF 66 #define ADC_S3C2416_CON_RES_SEL (1u << 3) 67 68 /* touch screen always uses channel 0 */ 69 #define ADC_S3C2410_MUX_TS 0 70 71 /* ADCTSC Register Bits */ 72 #define ADC_S3C2443_TSC_UD_SEN (1u << 8) 73 #define ADC_S3C2410_TSC_YM_SEN (1u << 7) 74 #define ADC_S3C2410_TSC_YP_SEN (1u << 6) 75 #define ADC_S3C2410_TSC_XM_SEN (1u << 5) 76 #define ADC_S3C2410_TSC_XP_SEN (1u << 4) 77 #define ADC_S3C2410_TSC_PULL_UP_DISABLE (1u << 3) 78 #define ADC_S3C2410_TSC_AUTO_PST (1u << 2) 79 #define ADC_S3C2410_TSC_XY_PST(x) (((x) & 0x3) << 0) 80 81 #define ADC_TSC_WAIT4INT (ADC_S3C2410_TSC_YM_SEN | \ 82 ADC_S3C2410_TSC_YP_SEN | \ 83 ADC_S3C2410_TSC_XP_SEN | \ 84 ADC_S3C2410_TSC_XY_PST(3)) 85 86 #define ADC_TSC_AUTOPST (ADC_S3C2410_TSC_YM_SEN | \ 87 ADC_S3C2410_TSC_YP_SEN | \ 88 ADC_S3C2410_TSC_XP_SEN | \ 89 ADC_S3C2410_TSC_AUTO_PST | \ 90 ADC_S3C2410_TSC_XY_PST(0)) 91 92 /* Bit definitions for ADC_V2 */ 93 #define ADC_V2_CON1_SOFT_RESET (1u << 2) 94 95 #define ADC_V2_CON2_OSEL (1u << 10) 96 #define ADC_V2_CON2_ESEL (1u << 9) 97 #define ADC_V2_CON2_HIGHF (1u << 8) 98 #define ADC_V2_CON2_C_TIME(x) (((x) & 7) << 4) 99 #define ADC_V2_CON2_ACH_SEL(x) (((x) & 0xF) << 0) 100 #define ADC_V2_CON2_ACH_MASK 0xF 101 102 #define MAX_ADC_V2_CHANNELS 10 103 #define MAX_ADC_V1_CHANNELS 8 104 #define MAX_EXYNOS3250_ADC_CHANNELS 2 105 #define MAX_EXYNOS4212_ADC_CHANNELS 4 106 #define MAX_S5PV210_ADC_CHANNELS 10 107 108 /* Bit definitions common for ADC_V1 and ADC_V2 */ 109 #define ADC_CON_EN_START (1u << 0) 110 #define ADC_CON_EN_START_MASK (0x3 << 0) 111 #define ADC_DATX_PRESSED (1u << 15) 112 #define ADC_DATX_MASK 0xFFF 113 #define ADC_DATY_MASK 0xFFF 114 115 #define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100)) 116 117 #define EXYNOS_ADCV1_PHY_OFFSET 0x0718 118 #define EXYNOS_ADCV2_PHY_OFFSET 0x0720 119 120 struct exynos_adc { 121 struct exynos_adc_data *data; 122 struct device *dev; 123 struct input_dev *input; 124 void __iomem *regs; 125 struct regmap *pmu_map; 126 struct clk *clk; 127 struct clk *sclk; 128 unsigned int irq; 129 unsigned int tsirq; 130 unsigned int delay; 131 struct regulator *vdd; 132 133 struct completion completion; 134 135 u32 value; 136 unsigned int version; 137 138 bool read_ts; 139 u32 ts_x; 140 u32 ts_y; 141 142 /* 143 * Lock to protect from potential concurrent access to the 144 * completion callback during a manual conversion. For this driver 145 * a wait-callback is used to wait for the conversion result, 146 * so in the meantime no other read request (or conversion start) 147 * must be performed, otherwise it would interfere with the 148 * current conversion result. 149 */ 150 struct mutex lock; 151 }; 152 153 struct exynos_adc_data { 154 int num_channels; 155 bool needs_sclk; 156 bool needs_adc_phy; 157 int phy_offset; 158 u32 mask; 159 160 void (*init_hw)(struct exynos_adc *info); 161 void (*exit_hw)(struct exynos_adc *info); 162 void (*clear_irq)(struct exynos_adc *info); 163 void (*start_conv)(struct exynos_adc *info, unsigned long addr); 164 }; 165 166 static void exynos_adc_unprepare_clk(struct exynos_adc *info) 167 { 168 if (info->data->needs_sclk) 169 clk_unprepare(info->sclk); 170 clk_unprepare(info->clk); 171 } 172 173 static int exynos_adc_prepare_clk(struct exynos_adc *info) 174 { 175 int ret; 176 177 ret = clk_prepare(info->clk); 178 if (ret) { 179 dev_err(info->dev, "failed preparing adc clock: %d\n", ret); 180 return ret; 181 } 182 183 if (info->data->needs_sclk) { 184 ret = clk_prepare(info->sclk); 185 if (ret) { 186 clk_unprepare(info->clk); 187 dev_err(info->dev, 188 "failed preparing sclk_adc clock: %d\n", ret); 189 return ret; 190 } 191 } 192 193 return 0; 194 } 195 196 static void exynos_adc_disable_clk(struct exynos_adc *info) 197 { 198 if (info->data->needs_sclk) 199 clk_disable(info->sclk); 200 clk_disable(info->clk); 201 } 202 203 static int exynos_adc_enable_clk(struct exynos_adc *info) 204 { 205 int ret; 206 207 ret = clk_enable(info->clk); 208 if (ret) { 209 dev_err(info->dev, "failed enabling adc clock: %d\n", ret); 210 return ret; 211 } 212 213 if (info->data->needs_sclk) { 214 ret = clk_enable(info->sclk); 215 if (ret) { 216 clk_disable(info->clk); 217 dev_err(info->dev, 218 "failed enabling sclk_adc clock: %d\n", ret); 219 return ret; 220 } 221 } 222 223 return 0; 224 } 225 226 static void exynos_adc_v1_init_hw(struct exynos_adc *info) 227 { 228 u32 con1; 229 230 if (info->data->needs_adc_phy) 231 regmap_write(info->pmu_map, info->data->phy_offset, 1); 232 233 /* set default prescaler values and Enable prescaler */ 234 con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN; 235 236 /* Enable 12-bit ADC resolution */ 237 con1 |= ADC_V1_CON_RES; 238 writel(con1, ADC_V1_CON(info->regs)); 239 240 /* set touchscreen delay */ 241 writel(info->delay, ADC_V1_DLY(info->regs)); 242 } 243 244 static void exynos_adc_v1_exit_hw(struct exynos_adc *info) 245 { 246 u32 con; 247 248 if (info->data->needs_adc_phy) 249 regmap_write(info->pmu_map, info->data->phy_offset, 0); 250 251 con = readl(ADC_V1_CON(info->regs)); 252 con |= ADC_V1_CON_STANDBY; 253 writel(con, ADC_V1_CON(info->regs)); 254 } 255 256 static void exynos_adc_v1_clear_irq(struct exynos_adc *info) 257 { 258 writel(1, ADC_V1_INTCLR(info->regs)); 259 } 260 261 static void exynos_adc_v1_start_conv(struct exynos_adc *info, 262 unsigned long addr) 263 { 264 u32 con1; 265 266 writel(addr, ADC_V1_MUX(info->regs)); 267 268 con1 = readl(ADC_V1_CON(info->regs)); 269 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); 270 } 271 272 /* Exynos4212 and 4412 is like ADCv1 but with four channels only */ 273 static const struct exynos_adc_data exynos4212_adc_data = { 274 .num_channels = MAX_EXYNOS4212_ADC_CHANNELS, 275 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 276 .needs_adc_phy = true, 277 .phy_offset = EXYNOS_ADCV1_PHY_OFFSET, 278 279 .init_hw = exynos_adc_v1_init_hw, 280 .exit_hw = exynos_adc_v1_exit_hw, 281 .clear_irq = exynos_adc_v1_clear_irq, 282 .start_conv = exynos_adc_v1_start_conv, 283 }; 284 285 static const struct exynos_adc_data exynos_adc_v1_data = { 286 .num_channels = MAX_ADC_V1_CHANNELS, 287 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 288 .needs_adc_phy = true, 289 .phy_offset = EXYNOS_ADCV1_PHY_OFFSET, 290 291 .init_hw = exynos_adc_v1_init_hw, 292 .exit_hw = exynos_adc_v1_exit_hw, 293 .clear_irq = exynos_adc_v1_clear_irq, 294 .start_conv = exynos_adc_v1_start_conv, 295 }; 296 297 static const struct exynos_adc_data exynos_adc_s5pv210_data = { 298 .num_channels = MAX_S5PV210_ADC_CHANNELS, 299 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 300 301 .init_hw = exynos_adc_v1_init_hw, 302 .exit_hw = exynos_adc_v1_exit_hw, 303 .clear_irq = exynos_adc_v1_clear_irq, 304 .start_conv = exynos_adc_v1_start_conv, 305 }; 306 307 static void exynos_adc_s3c2416_start_conv(struct exynos_adc *info, 308 unsigned long addr) 309 { 310 u32 con1; 311 312 /* Enable 12 bit ADC resolution */ 313 con1 = readl(ADC_V1_CON(info->regs)); 314 con1 |= ADC_S3C2416_CON_RES_SEL; 315 writel(con1, ADC_V1_CON(info->regs)); 316 317 /* Select channel for S3C2416 */ 318 writel(addr, ADC_S3C2410_MUX(info->regs)); 319 320 con1 = readl(ADC_V1_CON(info->regs)); 321 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); 322 } 323 324 static struct exynos_adc_data const exynos_adc_s3c2416_data = { 325 .num_channels = MAX_ADC_V1_CHANNELS, 326 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 327 328 .init_hw = exynos_adc_v1_init_hw, 329 .exit_hw = exynos_adc_v1_exit_hw, 330 .start_conv = exynos_adc_s3c2416_start_conv, 331 }; 332 333 static void exynos_adc_s3c2443_start_conv(struct exynos_adc *info, 334 unsigned long addr) 335 { 336 u32 con1; 337 338 /* Select channel for S3C2433 */ 339 writel(addr, ADC_S3C2410_MUX(info->regs)); 340 341 con1 = readl(ADC_V1_CON(info->regs)); 342 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); 343 } 344 345 static struct exynos_adc_data const exynos_adc_s3c2443_data = { 346 .num_channels = MAX_ADC_V1_CHANNELS, 347 .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */ 348 349 .init_hw = exynos_adc_v1_init_hw, 350 .exit_hw = exynos_adc_v1_exit_hw, 351 .start_conv = exynos_adc_s3c2443_start_conv, 352 }; 353 354 static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info, 355 unsigned long addr) 356 { 357 u32 con1; 358 359 con1 = readl(ADC_V1_CON(info->regs)); 360 con1 &= ~ADC_S3C2410_CON_SELMUX(0x7); 361 con1 |= ADC_S3C2410_CON_SELMUX(addr); 362 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs)); 363 } 364 365 static struct exynos_adc_data const exynos_adc_s3c24xx_data = { 366 .num_channels = MAX_ADC_V1_CHANNELS, 367 .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */ 368 369 .init_hw = exynos_adc_v1_init_hw, 370 .exit_hw = exynos_adc_v1_exit_hw, 371 .start_conv = exynos_adc_s3c64xx_start_conv, 372 }; 373 374 static struct exynos_adc_data const exynos_adc_s3c64xx_data = { 375 .num_channels = MAX_ADC_V1_CHANNELS, 376 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 377 378 .init_hw = exynos_adc_v1_init_hw, 379 .exit_hw = exynos_adc_v1_exit_hw, 380 .clear_irq = exynos_adc_v1_clear_irq, 381 .start_conv = exynos_adc_s3c64xx_start_conv, 382 }; 383 384 static void exynos_adc_v2_init_hw(struct exynos_adc *info) 385 { 386 u32 con1, con2; 387 388 if (info->data->needs_adc_phy) 389 regmap_write(info->pmu_map, info->data->phy_offset, 1); 390 391 con1 = ADC_V2_CON1_SOFT_RESET; 392 writel(con1, ADC_V2_CON1(info->regs)); 393 394 con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL | 395 ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0); 396 writel(con2, ADC_V2_CON2(info->regs)); 397 398 /* Enable interrupts */ 399 writel(1, ADC_V2_INT_EN(info->regs)); 400 } 401 402 static void exynos_adc_v2_exit_hw(struct exynos_adc *info) 403 { 404 u32 con; 405 406 if (info->data->needs_adc_phy) 407 regmap_write(info->pmu_map, info->data->phy_offset, 0); 408 409 con = readl(ADC_V2_CON1(info->regs)); 410 con &= ~ADC_CON_EN_START; 411 writel(con, ADC_V2_CON1(info->regs)); 412 } 413 414 static void exynos_adc_v2_clear_irq(struct exynos_adc *info) 415 { 416 writel(1, ADC_V2_INT_ST(info->regs)); 417 } 418 419 static void exynos_adc_v2_start_conv(struct exynos_adc *info, 420 unsigned long addr) 421 { 422 u32 con1, con2; 423 424 con2 = readl(ADC_V2_CON2(info->regs)); 425 con2 &= ~ADC_V2_CON2_ACH_MASK; 426 con2 |= ADC_V2_CON2_ACH_SEL(addr); 427 writel(con2, ADC_V2_CON2(info->regs)); 428 429 con1 = readl(ADC_V2_CON1(info->regs)); 430 writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs)); 431 } 432 433 static const struct exynos_adc_data exynos_adc_v2_data = { 434 .num_channels = MAX_ADC_V2_CHANNELS, 435 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 436 .needs_adc_phy = true, 437 .phy_offset = EXYNOS_ADCV2_PHY_OFFSET, 438 439 .init_hw = exynos_adc_v2_init_hw, 440 .exit_hw = exynos_adc_v2_exit_hw, 441 .clear_irq = exynos_adc_v2_clear_irq, 442 .start_conv = exynos_adc_v2_start_conv, 443 }; 444 445 static const struct exynos_adc_data exynos3250_adc_data = { 446 .num_channels = MAX_EXYNOS3250_ADC_CHANNELS, 447 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 448 .needs_sclk = true, 449 .needs_adc_phy = true, 450 .phy_offset = EXYNOS_ADCV1_PHY_OFFSET, 451 452 .init_hw = exynos_adc_v2_init_hw, 453 .exit_hw = exynos_adc_v2_exit_hw, 454 .clear_irq = exynos_adc_v2_clear_irq, 455 .start_conv = exynos_adc_v2_start_conv, 456 }; 457 458 static void exynos_adc_exynos7_init_hw(struct exynos_adc *info) 459 { 460 u32 con1, con2; 461 462 con1 = ADC_V2_CON1_SOFT_RESET; 463 writel(con1, ADC_V2_CON1(info->regs)); 464 465 con2 = readl(ADC_V2_CON2(info->regs)); 466 con2 &= ~ADC_V2_CON2_C_TIME(7); 467 con2 |= ADC_V2_CON2_C_TIME(0); 468 writel(con2, ADC_V2_CON2(info->regs)); 469 470 /* Enable interrupts */ 471 writel(1, ADC_V2_INT_EN(info->regs)); 472 } 473 474 static const struct exynos_adc_data exynos7_adc_data = { 475 .num_channels = MAX_ADC_V1_CHANNELS, 476 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */ 477 478 .init_hw = exynos_adc_exynos7_init_hw, 479 .exit_hw = exynos_adc_v2_exit_hw, 480 .clear_irq = exynos_adc_v2_clear_irq, 481 .start_conv = exynos_adc_v2_start_conv, 482 }; 483 484 static const struct of_device_id exynos_adc_match[] = { 485 { 486 .compatible = "samsung,s3c2410-adc", 487 .data = &exynos_adc_s3c24xx_data, 488 }, { 489 .compatible = "samsung,s3c2416-adc", 490 .data = &exynos_adc_s3c2416_data, 491 }, { 492 .compatible = "samsung,s3c2440-adc", 493 .data = &exynos_adc_s3c24xx_data, 494 }, { 495 .compatible = "samsung,s3c2443-adc", 496 .data = &exynos_adc_s3c2443_data, 497 }, { 498 .compatible = "samsung,s3c6410-adc", 499 .data = &exynos_adc_s3c64xx_data, 500 }, { 501 .compatible = "samsung,s5pv210-adc", 502 .data = &exynos_adc_s5pv210_data, 503 }, { 504 .compatible = "samsung,exynos4212-adc", 505 .data = &exynos4212_adc_data, 506 }, { 507 .compatible = "samsung,exynos-adc-v1", 508 .data = &exynos_adc_v1_data, 509 }, { 510 .compatible = "samsung,exynos-adc-v2", 511 .data = &exynos_adc_v2_data, 512 }, { 513 .compatible = "samsung,exynos3250-adc", 514 .data = &exynos3250_adc_data, 515 }, { 516 .compatible = "samsung,exynos7-adc", 517 .data = &exynos7_adc_data, 518 }, 519 {}, 520 }; 521 MODULE_DEVICE_TABLE(of, exynos_adc_match); 522 523 static struct exynos_adc_data *exynos_adc_get_data(struct platform_device *pdev) 524 { 525 const struct of_device_id *match; 526 527 match = of_match_node(exynos_adc_match, pdev->dev.of_node); 528 return (struct exynos_adc_data *)match->data; 529 } 530 531 static int exynos_read_raw(struct iio_dev *indio_dev, 532 struct iio_chan_spec const *chan, 533 int *val, 534 int *val2, 535 long mask) 536 { 537 struct exynos_adc *info = iio_priv(indio_dev); 538 unsigned long timeout; 539 int ret; 540 541 if (mask == IIO_CHAN_INFO_SCALE) { 542 ret = regulator_get_voltage(info->vdd); 543 if (ret < 0) 544 return ret; 545 546 /* Regulator voltage is in uV, but need mV */ 547 *val = ret / 1000; 548 *val2 = info->data->mask; 549 550 return IIO_VAL_FRACTIONAL; 551 } else if (mask != IIO_CHAN_INFO_RAW) { 552 return -EINVAL; 553 } 554 555 mutex_lock(&info->lock); 556 reinit_completion(&info->completion); 557 558 /* Select the channel to be used and Trigger conversion */ 559 if (info->data->start_conv) 560 info->data->start_conv(info, chan->address); 561 562 timeout = wait_for_completion_timeout(&info->completion, 563 EXYNOS_ADC_TIMEOUT); 564 if (timeout == 0) { 565 dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n"); 566 if (info->data->init_hw) 567 info->data->init_hw(info); 568 ret = -ETIMEDOUT; 569 } else { 570 *val = info->value; 571 *val2 = 0; 572 ret = IIO_VAL_INT; 573 } 574 575 mutex_unlock(&info->lock); 576 577 return ret; 578 } 579 580 static int exynos_read_s3c64xx_ts(struct iio_dev *indio_dev, int *x, int *y) 581 { 582 struct exynos_adc *info = iio_priv(indio_dev); 583 unsigned long timeout; 584 int ret; 585 586 mutex_lock(&info->lock); 587 info->read_ts = true; 588 589 reinit_completion(&info->completion); 590 591 writel(ADC_S3C2410_TSC_PULL_UP_DISABLE | ADC_TSC_AUTOPST, 592 ADC_V1_TSC(info->regs)); 593 594 /* Select the ts channel to be used and Trigger conversion */ 595 info->data->start_conv(info, ADC_S3C2410_MUX_TS); 596 597 timeout = wait_for_completion_timeout(&info->completion, 598 EXYNOS_ADC_TIMEOUT); 599 if (timeout == 0) { 600 dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n"); 601 if (info->data->init_hw) 602 info->data->init_hw(info); 603 ret = -ETIMEDOUT; 604 } else { 605 *x = info->ts_x; 606 *y = info->ts_y; 607 ret = 0; 608 } 609 610 info->read_ts = false; 611 mutex_unlock(&info->lock); 612 613 return ret; 614 } 615 616 static irqreturn_t exynos_adc_isr(int irq, void *dev_id) 617 { 618 struct exynos_adc *info = dev_id; 619 u32 mask = info->data->mask; 620 621 /* Read value */ 622 if (info->read_ts) { 623 info->ts_x = readl(ADC_V1_DATX(info->regs)); 624 info->ts_y = readl(ADC_V1_DATY(info->regs)); 625 writel(ADC_TSC_WAIT4INT | ADC_S3C2443_TSC_UD_SEN, ADC_V1_TSC(info->regs)); 626 } else { 627 info->value = readl(ADC_V1_DATX(info->regs)) & mask; 628 } 629 630 /* clear irq */ 631 if (info->data->clear_irq) 632 info->data->clear_irq(info); 633 634 complete(&info->completion); 635 636 return IRQ_HANDLED; 637 } 638 639 /* 640 * Here we (ab)use a threaded interrupt handler to stay running 641 * for as long as the touchscreen remains pressed, we report 642 * a new event with the latest data and then sleep until the 643 * next timer tick. This mirrors the behavior of the old 644 * driver, with much less code. 645 */ 646 static irqreturn_t exynos_ts_isr(int irq, void *dev_id) 647 { 648 struct exynos_adc *info = dev_id; 649 struct iio_dev *dev = dev_get_drvdata(info->dev); 650 u32 x, y; 651 bool pressed; 652 int ret; 653 654 while (info->input->users) { 655 ret = exynos_read_s3c64xx_ts(dev, &x, &y); 656 if (ret == -ETIMEDOUT) 657 break; 658 659 pressed = x & y & ADC_DATX_PRESSED; 660 if (!pressed) { 661 input_report_key(info->input, BTN_TOUCH, 0); 662 input_sync(info->input); 663 break; 664 } 665 666 input_report_abs(info->input, ABS_X, x & ADC_DATX_MASK); 667 input_report_abs(info->input, ABS_Y, y & ADC_DATY_MASK); 668 input_report_key(info->input, BTN_TOUCH, 1); 669 input_sync(info->input); 670 671 usleep_range(1000, 1100); 672 } 673 674 writel(0, ADC_V1_CLRINTPNDNUP(info->regs)); 675 676 return IRQ_HANDLED; 677 } 678 679 static int exynos_adc_reg_access(struct iio_dev *indio_dev, 680 unsigned reg, unsigned writeval, 681 unsigned *readval) 682 { 683 struct exynos_adc *info = iio_priv(indio_dev); 684 685 if (readval == NULL) 686 return -EINVAL; 687 688 *readval = readl(info->regs + reg); 689 690 return 0; 691 } 692 693 static const struct iio_info exynos_adc_iio_info = { 694 .read_raw = &exynos_read_raw, 695 .debugfs_reg_access = &exynos_adc_reg_access, 696 }; 697 698 #define ADC_CHANNEL(_index, _id) { \ 699 .type = IIO_VOLTAGE, \ 700 .indexed = 1, \ 701 .channel = _index, \ 702 .address = _index, \ 703 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 704 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE), \ 705 .datasheet_name = _id, \ 706 } 707 708 static const struct iio_chan_spec exynos_adc_iio_channels[] = { 709 ADC_CHANNEL(0, "adc0"), 710 ADC_CHANNEL(1, "adc1"), 711 ADC_CHANNEL(2, "adc2"), 712 ADC_CHANNEL(3, "adc3"), 713 ADC_CHANNEL(4, "adc4"), 714 ADC_CHANNEL(5, "adc5"), 715 ADC_CHANNEL(6, "adc6"), 716 ADC_CHANNEL(7, "adc7"), 717 ADC_CHANNEL(8, "adc8"), 718 ADC_CHANNEL(9, "adc9"), 719 }; 720 721 static int exynos_adc_remove_devices(struct device *dev, void *c) 722 { 723 struct platform_device *pdev = to_platform_device(dev); 724 725 platform_device_unregister(pdev); 726 727 return 0; 728 } 729 730 static int exynos_adc_ts_open(struct input_dev *dev) 731 { 732 struct exynos_adc *info = input_get_drvdata(dev); 733 734 enable_irq(info->tsirq); 735 736 return 0; 737 } 738 739 static void exynos_adc_ts_close(struct input_dev *dev) 740 { 741 struct exynos_adc *info = input_get_drvdata(dev); 742 743 disable_irq(info->tsirq); 744 } 745 746 static int exynos_adc_ts_init(struct exynos_adc *info) 747 { 748 int ret; 749 750 if (info->tsirq <= 0) 751 return -ENODEV; 752 753 info->input = input_allocate_device(); 754 if (!info->input) 755 return -ENOMEM; 756 757 info->input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS); 758 info->input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH); 759 760 input_set_abs_params(info->input, ABS_X, 0, 0x3FF, 0, 0); 761 input_set_abs_params(info->input, ABS_Y, 0, 0x3FF, 0, 0); 762 763 info->input->name = "S3C24xx TouchScreen"; 764 info->input->id.bustype = BUS_HOST; 765 info->input->open = exynos_adc_ts_open; 766 info->input->close = exynos_adc_ts_close; 767 768 input_set_drvdata(info->input, info); 769 770 ret = input_register_device(info->input); 771 if (ret) { 772 input_free_device(info->input); 773 return ret; 774 } 775 776 disable_irq(info->tsirq); 777 ret = request_threaded_irq(info->tsirq, NULL, exynos_ts_isr, 778 IRQF_ONESHOT, "touchscreen", info); 779 if (ret) 780 input_unregister_device(info->input); 781 782 return ret; 783 } 784 785 static int exynos_adc_probe(struct platform_device *pdev) 786 { 787 struct exynos_adc *info = NULL; 788 struct device_node *np = pdev->dev.of_node; 789 struct s3c2410_ts_mach_info *pdata = dev_get_platdata(&pdev->dev); 790 struct iio_dev *indio_dev = NULL; 791 bool has_ts = false; 792 int ret = -ENODEV; 793 int irq; 794 795 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct exynos_adc)); 796 if (!indio_dev) { 797 dev_err(&pdev->dev, "failed allocating iio device\n"); 798 return -ENOMEM; 799 } 800 801 info = iio_priv(indio_dev); 802 803 info->data = exynos_adc_get_data(pdev); 804 if (!info->data) { 805 dev_err(&pdev->dev, "failed getting exynos_adc_data\n"); 806 return -EINVAL; 807 } 808 809 info->regs = devm_platform_ioremap_resource(pdev, 0); 810 if (IS_ERR(info->regs)) 811 return PTR_ERR(info->regs); 812 813 814 if (info->data->needs_adc_phy) { 815 info->pmu_map = syscon_regmap_lookup_by_phandle( 816 pdev->dev.of_node, 817 "samsung,syscon-phandle"); 818 if (IS_ERR(info->pmu_map)) { 819 dev_err(&pdev->dev, "syscon regmap lookup failed.\n"); 820 return PTR_ERR(info->pmu_map); 821 } 822 } 823 824 irq = platform_get_irq(pdev, 0); 825 if (irq < 0) 826 return irq; 827 info->irq = irq; 828 829 irq = platform_get_irq(pdev, 1); 830 if (irq == -EPROBE_DEFER) 831 return irq; 832 833 info->tsirq = irq; 834 835 info->dev = &pdev->dev; 836 837 init_completion(&info->completion); 838 839 info->clk = devm_clk_get(&pdev->dev, "adc"); 840 if (IS_ERR(info->clk)) { 841 dev_err(&pdev->dev, "failed getting clock, err = %ld\n", 842 PTR_ERR(info->clk)); 843 return PTR_ERR(info->clk); 844 } 845 846 if (info->data->needs_sclk) { 847 info->sclk = devm_clk_get(&pdev->dev, "sclk"); 848 if (IS_ERR(info->sclk)) { 849 dev_err(&pdev->dev, 850 "failed getting sclk clock, err = %ld\n", 851 PTR_ERR(info->sclk)); 852 return PTR_ERR(info->sclk); 853 } 854 } 855 856 info->vdd = devm_regulator_get(&pdev->dev, "vdd"); 857 if (IS_ERR(info->vdd)) 858 return dev_err_probe(&pdev->dev, PTR_ERR(info->vdd), 859 "failed getting regulator"); 860 861 ret = regulator_enable(info->vdd); 862 if (ret) 863 return ret; 864 865 ret = exynos_adc_prepare_clk(info); 866 if (ret) 867 goto err_disable_reg; 868 869 ret = exynos_adc_enable_clk(info); 870 if (ret) 871 goto err_unprepare_clk; 872 873 platform_set_drvdata(pdev, indio_dev); 874 875 indio_dev->name = dev_name(&pdev->dev); 876 indio_dev->info = &exynos_adc_iio_info; 877 indio_dev->modes = INDIO_DIRECT_MODE; 878 indio_dev->channels = exynos_adc_iio_channels; 879 indio_dev->num_channels = info->data->num_channels; 880 881 mutex_init(&info->lock); 882 883 ret = request_irq(info->irq, exynos_adc_isr, 884 0, dev_name(&pdev->dev), info); 885 if (ret < 0) { 886 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", 887 info->irq); 888 goto err_disable_clk; 889 } 890 891 ret = iio_device_register(indio_dev); 892 if (ret) 893 goto err_irq; 894 895 if (info->data->init_hw) 896 info->data->init_hw(info); 897 898 /* leave out any TS related code if unreachable */ 899 if (IS_REACHABLE(CONFIG_INPUT)) { 900 has_ts = of_property_read_bool(pdev->dev.of_node, 901 "has-touchscreen") || pdata; 902 } 903 904 if (pdata) 905 info->delay = pdata->delay; 906 else 907 info->delay = 10000; 908 909 if (has_ts) 910 ret = exynos_adc_ts_init(info); 911 if (ret) 912 goto err_iio; 913 914 ret = of_platform_populate(np, exynos_adc_match, NULL, &indio_dev->dev); 915 if (ret < 0) { 916 dev_err(&pdev->dev, "failed adding child nodes\n"); 917 goto err_of_populate; 918 } 919 920 return 0; 921 922 err_of_populate: 923 device_for_each_child(&indio_dev->dev, NULL, 924 exynos_adc_remove_devices); 925 if (has_ts) { 926 input_unregister_device(info->input); 927 free_irq(info->tsirq, info); 928 } 929 err_iio: 930 iio_device_unregister(indio_dev); 931 err_irq: 932 free_irq(info->irq, info); 933 err_disable_clk: 934 if (info->data->exit_hw) 935 info->data->exit_hw(info); 936 exynos_adc_disable_clk(info); 937 err_unprepare_clk: 938 exynos_adc_unprepare_clk(info); 939 err_disable_reg: 940 regulator_disable(info->vdd); 941 return ret; 942 } 943 944 static int exynos_adc_remove(struct platform_device *pdev) 945 { 946 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 947 struct exynos_adc *info = iio_priv(indio_dev); 948 949 if (IS_REACHABLE(CONFIG_INPUT) && info->input) { 950 free_irq(info->tsirq, info); 951 input_unregister_device(info->input); 952 } 953 device_for_each_child(&indio_dev->dev, NULL, 954 exynos_adc_remove_devices); 955 iio_device_unregister(indio_dev); 956 free_irq(info->irq, info); 957 if (info->data->exit_hw) 958 info->data->exit_hw(info); 959 exynos_adc_disable_clk(info); 960 exynos_adc_unprepare_clk(info); 961 regulator_disable(info->vdd); 962 963 return 0; 964 } 965 966 #ifdef CONFIG_PM_SLEEP 967 static int exynos_adc_suspend(struct device *dev) 968 { 969 struct iio_dev *indio_dev = dev_get_drvdata(dev); 970 struct exynos_adc *info = iio_priv(indio_dev); 971 972 if (info->data->exit_hw) 973 info->data->exit_hw(info); 974 exynos_adc_disable_clk(info); 975 regulator_disable(info->vdd); 976 977 return 0; 978 } 979 980 static int exynos_adc_resume(struct device *dev) 981 { 982 struct iio_dev *indio_dev = dev_get_drvdata(dev); 983 struct exynos_adc *info = iio_priv(indio_dev); 984 int ret; 985 986 ret = regulator_enable(info->vdd); 987 if (ret) 988 return ret; 989 990 ret = exynos_adc_enable_clk(info); 991 if (ret) 992 return ret; 993 994 if (info->data->init_hw) 995 info->data->init_hw(info); 996 997 return 0; 998 } 999 #endif 1000 1001 static SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops, 1002 exynos_adc_suspend, 1003 exynos_adc_resume); 1004 1005 static struct platform_driver exynos_adc_driver = { 1006 .probe = exynos_adc_probe, 1007 .remove = exynos_adc_remove, 1008 .driver = { 1009 .name = "exynos-adc", 1010 .of_match_table = exynos_adc_match, 1011 .pm = &exynos_adc_pm_ops, 1012 }, 1013 }; 1014 1015 module_platform_driver(exynos_adc_driver); 1016 1017 MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>"); 1018 MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver"); 1019 MODULE_LICENSE("GPL v2"); 1020