xref: /openbmc/linux/drivers/iio/adc/exynos_adc.c (revision 6774def6)
1 /*
2  *  exynos_adc.c - Support for ADC in EXYNOS SoCs
3  *
4  *  8 ~ 10 channel, 10/12-bit ADC
5  *
6  *  Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com>
7  *
8  *  This program is free software; you can redistribute it and/or modify
9  *  it under the terms of the GNU General Public License as published by
10  *  the Free Software Foundation; either version 2 of the License, or
11  *  (at your option) any later version.
12  *
13  *  This program is distributed in the hope that it will be useful,
14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  *  GNU General Public License for more details.
17  *
18  *  You should have received a copy of the GNU General Public License
19  *  along with this program; if not, write to the Free Software
20  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21  */
22 
23 #include <linux/module.h>
24 #include <linux/platform_device.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/errno.h>
28 #include <linux/kernel.h>
29 #include <linux/slab.h>
30 #include <linux/io.h>
31 #include <linux/clk.h>
32 #include <linux/completion.h>
33 #include <linux/of.h>
34 #include <linux/of_irq.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/of_platform.h>
37 #include <linux/err.h>
38 
39 #include <linux/iio/iio.h>
40 #include <linux/iio/machine.h>
41 #include <linux/iio/driver.h>
42 
43 /* S3C/EXYNOS4412/5250 ADC_V1 registers definitions */
44 #define ADC_V1_CON(x)		((x) + 0x00)
45 #define ADC_V1_DLY(x)		((x) + 0x08)
46 #define ADC_V1_DATX(x)		((x) + 0x0C)
47 #define ADC_V1_INTCLR(x)	((x) + 0x18)
48 #define ADC_V1_MUX(x)		((x) + 0x1c)
49 
50 /* S3C2410 ADC registers definitions */
51 #define ADC_S3C2410_MUX(x)	((x) + 0x18)
52 
53 /* Future ADC_V2 registers definitions */
54 #define ADC_V2_CON1(x)		((x) + 0x00)
55 #define ADC_V2_CON2(x)		((x) + 0x04)
56 #define ADC_V2_STAT(x)		((x) + 0x08)
57 #define ADC_V2_INT_EN(x)	((x) + 0x10)
58 #define ADC_V2_INT_ST(x)	((x) + 0x14)
59 #define ADC_V2_VER(x)		((x) + 0x20)
60 
61 /* Bit definitions for ADC_V1 */
62 #define ADC_V1_CON_RES		(1u << 16)
63 #define ADC_V1_CON_PRSCEN	(1u << 14)
64 #define ADC_V1_CON_PRSCLV(x)	(((x) & 0xFF) << 6)
65 #define ADC_V1_CON_STANDBY	(1u << 2)
66 
67 /* Bit definitions for S3C2410 ADC */
68 #define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3)
69 #define ADC_S3C2410_DATX_MASK	0x3FF
70 #define ADC_S3C2416_CON_RES_SEL	(1u << 3)
71 
72 /* Bit definitions for ADC_V2 */
73 #define ADC_V2_CON1_SOFT_RESET	(1u << 2)
74 
75 #define ADC_V2_CON2_OSEL	(1u << 10)
76 #define ADC_V2_CON2_ESEL	(1u << 9)
77 #define ADC_V2_CON2_HIGHF	(1u << 8)
78 #define ADC_V2_CON2_C_TIME(x)	(((x) & 7) << 4)
79 #define ADC_V2_CON2_ACH_SEL(x)	(((x) & 0xF) << 0)
80 #define ADC_V2_CON2_ACH_MASK	0xF
81 
82 #define MAX_ADC_V2_CHANNELS		10
83 #define MAX_ADC_V1_CHANNELS		8
84 #define MAX_EXYNOS3250_ADC_CHANNELS	2
85 
86 /* Bit definitions common for ADC_V1 and ADC_V2 */
87 #define ADC_CON_EN_START	(1u << 0)
88 #define ADC_CON_EN_START_MASK	(0x3 << 0)
89 #define ADC_DATX_MASK		0xFFF
90 
91 #define EXYNOS_ADC_TIMEOUT	(msecs_to_jiffies(100))
92 
93 struct exynos_adc {
94 	struct exynos_adc_data	*data;
95 	struct device		*dev;
96 	void __iomem		*regs;
97 	void __iomem		*enable_reg;
98 	struct clk		*clk;
99 	struct clk		*sclk;
100 	unsigned int		irq;
101 	struct regulator	*vdd;
102 
103 	struct completion	completion;
104 
105 	u32			value;
106 	unsigned int            version;
107 };
108 
109 struct exynos_adc_data {
110 	int num_channels;
111 	bool needs_sclk;
112 	bool needs_adc_phy;
113 	u32 mask;
114 
115 	void (*init_hw)(struct exynos_adc *info);
116 	void (*exit_hw)(struct exynos_adc *info);
117 	void (*clear_irq)(struct exynos_adc *info);
118 	void (*start_conv)(struct exynos_adc *info, unsigned long addr);
119 };
120 
121 static void exynos_adc_unprepare_clk(struct exynos_adc *info)
122 {
123 	if (info->data->needs_sclk)
124 		clk_unprepare(info->sclk);
125 	clk_unprepare(info->clk);
126 }
127 
128 static int exynos_adc_prepare_clk(struct exynos_adc *info)
129 {
130 	int ret;
131 
132 	ret = clk_prepare(info->clk);
133 	if (ret) {
134 		dev_err(info->dev, "failed preparing adc clock: %d\n", ret);
135 		return ret;
136 	}
137 
138 	if (info->data->needs_sclk) {
139 		ret = clk_prepare(info->sclk);
140 		if (ret) {
141 			clk_unprepare(info->clk);
142 			dev_err(info->dev,
143 				"failed preparing sclk_adc clock: %d\n", ret);
144 			return ret;
145 		}
146 	}
147 
148 	return 0;
149 }
150 
151 static void exynos_adc_disable_clk(struct exynos_adc *info)
152 {
153 	if (info->data->needs_sclk)
154 		clk_disable(info->sclk);
155 	clk_disable(info->clk);
156 }
157 
158 static int exynos_adc_enable_clk(struct exynos_adc *info)
159 {
160 	int ret;
161 
162 	ret = clk_enable(info->clk);
163 	if (ret) {
164 		dev_err(info->dev, "failed enabling adc clock: %d\n", ret);
165 		return ret;
166 	}
167 
168 	if (info->data->needs_sclk) {
169 		ret = clk_enable(info->sclk);
170 		if (ret) {
171 			clk_disable(info->clk);
172 			dev_err(info->dev,
173 				"failed enabling sclk_adc clock: %d\n", ret);
174 			return ret;
175 		}
176 	}
177 
178 	return 0;
179 }
180 
181 static void exynos_adc_v1_init_hw(struct exynos_adc *info)
182 {
183 	u32 con1;
184 
185 	if (info->data->needs_adc_phy)
186 		writel(1, info->enable_reg);
187 
188 	/* set default prescaler values and Enable prescaler */
189 	con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
190 
191 	/* Enable 12-bit ADC resolution */
192 	con1 |= ADC_V1_CON_RES;
193 	writel(con1, ADC_V1_CON(info->regs));
194 }
195 
196 static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
197 {
198 	u32 con;
199 
200 	if (info->data->needs_adc_phy)
201 		writel(0, info->enable_reg);
202 
203 	con = readl(ADC_V1_CON(info->regs));
204 	con |= ADC_V1_CON_STANDBY;
205 	writel(con, ADC_V1_CON(info->regs));
206 }
207 
208 static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
209 {
210 	writel(1, ADC_V1_INTCLR(info->regs));
211 }
212 
213 static void exynos_adc_v1_start_conv(struct exynos_adc *info,
214 				     unsigned long addr)
215 {
216 	u32 con1;
217 
218 	writel(addr, ADC_V1_MUX(info->regs));
219 
220 	con1 = readl(ADC_V1_CON(info->regs));
221 	writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
222 }
223 
224 static const struct exynos_adc_data exynos_adc_v1_data = {
225 	.num_channels	= MAX_ADC_V1_CHANNELS,
226 	.mask		= ADC_DATX_MASK,	/* 12 bit ADC resolution */
227 	.needs_adc_phy	= true,
228 
229 	.init_hw	= exynos_adc_v1_init_hw,
230 	.exit_hw	= exynos_adc_v1_exit_hw,
231 	.clear_irq	= exynos_adc_v1_clear_irq,
232 	.start_conv	= exynos_adc_v1_start_conv,
233 };
234 
235 static void exynos_adc_s3c2416_start_conv(struct exynos_adc *info,
236 					  unsigned long addr)
237 {
238 	u32 con1;
239 
240 	/* Enable 12 bit ADC resolution */
241 	con1 = readl(ADC_V1_CON(info->regs));
242 	con1 |= ADC_S3C2416_CON_RES_SEL;
243 	writel(con1, ADC_V1_CON(info->regs));
244 
245 	/* Select channel for S3C2416 */
246 	writel(addr, ADC_S3C2410_MUX(info->regs));
247 
248 	con1 = readl(ADC_V1_CON(info->regs));
249 	writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
250 }
251 
252 static struct exynos_adc_data const exynos_adc_s3c2416_data = {
253 	.num_channels	= MAX_ADC_V1_CHANNELS,
254 	.mask		= ADC_DATX_MASK,	/* 12 bit ADC resolution */
255 
256 	.init_hw	= exynos_adc_v1_init_hw,
257 	.exit_hw	= exynos_adc_v1_exit_hw,
258 	.start_conv	= exynos_adc_s3c2416_start_conv,
259 };
260 
261 static void exynos_adc_s3c2443_start_conv(struct exynos_adc *info,
262 					  unsigned long addr)
263 {
264 	u32 con1;
265 
266 	/* Select channel for S3C2433 */
267 	writel(addr, ADC_S3C2410_MUX(info->regs));
268 
269 	con1 = readl(ADC_V1_CON(info->regs));
270 	writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
271 }
272 
273 static struct exynos_adc_data const exynos_adc_s3c2443_data = {
274 	.num_channels	= MAX_ADC_V1_CHANNELS,
275 	.mask		= ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
276 
277 	.init_hw	= exynos_adc_v1_init_hw,
278 	.exit_hw	= exynos_adc_v1_exit_hw,
279 	.start_conv	= exynos_adc_s3c2443_start_conv,
280 };
281 
282 static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
283 					  unsigned long addr)
284 {
285 	u32 con1;
286 
287 	con1 = readl(ADC_V1_CON(info->regs));
288 	con1 &= ~ADC_S3C2410_CON_SELMUX(0x7);
289 	con1 |= ADC_S3C2410_CON_SELMUX(addr);
290 	writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
291 }
292 
293 static struct exynos_adc_data const exynos_adc_s3c24xx_data = {
294 	.num_channels	= MAX_ADC_V1_CHANNELS,
295 	.mask		= ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
296 
297 	.init_hw	= exynos_adc_v1_init_hw,
298 	.exit_hw	= exynos_adc_v1_exit_hw,
299 	.start_conv	= exynos_adc_s3c64xx_start_conv,
300 };
301 
302 static struct exynos_adc_data const exynos_adc_s3c64xx_data = {
303 	.num_channels	= MAX_ADC_V1_CHANNELS,
304 	.mask		= ADC_DATX_MASK,	/* 12 bit ADC resolution */
305 
306 	.init_hw	= exynos_adc_v1_init_hw,
307 	.exit_hw	= exynos_adc_v1_exit_hw,
308 	.clear_irq	= exynos_adc_v1_clear_irq,
309 	.start_conv	= exynos_adc_s3c64xx_start_conv,
310 };
311 
312 static void exynos_adc_v2_init_hw(struct exynos_adc *info)
313 {
314 	u32 con1, con2;
315 
316 	if (info->data->needs_adc_phy)
317 		writel(1, info->enable_reg);
318 
319 	con1 = ADC_V2_CON1_SOFT_RESET;
320 	writel(con1, ADC_V2_CON1(info->regs));
321 
322 	con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
323 		ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
324 	writel(con2, ADC_V2_CON2(info->regs));
325 
326 	/* Enable interrupts */
327 	writel(1, ADC_V2_INT_EN(info->regs));
328 }
329 
330 static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
331 {
332 	u32 con;
333 
334 	if (info->data->needs_adc_phy)
335 		writel(0, info->enable_reg);
336 
337 	con = readl(ADC_V2_CON1(info->regs));
338 	con &= ~ADC_CON_EN_START;
339 	writel(con, ADC_V2_CON1(info->regs));
340 }
341 
342 static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
343 {
344 	writel(1, ADC_V2_INT_ST(info->regs));
345 }
346 
347 static void exynos_adc_v2_start_conv(struct exynos_adc *info,
348 				     unsigned long addr)
349 {
350 	u32 con1, con2;
351 
352 	con2 = readl(ADC_V2_CON2(info->regs));
353 	con2 &= ~ADC_V2_CON2_ACH_MASK;
354 	con2 |= ADC_V2_CON2_ACH_SEL(addr);
355 	writel(con2, ADC_V2_CON2(info->regs));
356 
357 	con1 = readl(ADC_V2_CON1(info->regs));
358 	writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs));
359 }
360 
361 static const struct exynos_adc_data exynos_adc_v2_data = {
362 	.num_channels	= MAX_ADC_V2_CHANNELS,
363 	.mask		= ADC_DATX_MASK, /* 12 bit ADC resolution */
364 	.needs_adc_phy	= true,
365 
366 	.init_hw	= exynos_adc_v2_init_hw,
367 	.exit_hw	= exynos_adc_v2_exit_hw,
368 	.clear_irq	= exynos_adc_v2_clear_irq,
369 	.start_conv	= exynos_adc_v2_start_conv,
370 };
371 
372 static const struct exynos_adc_data exynos3250_adc_data = {
373 	.num_channels	= MAX_EXYNOS3250_ADC_CHANNELS,
374 	.mask		= ADC_DATX_MASK, /* 12 bit ADC resolution */
375 	.needs_sclk	= true,
376 	.needs_adc_phy	= true,
377 
378 	.init_hw	= exynos_adc_v2_init_hw,
379 	.exit_hw	= exynos_adc_v2_exit_hw,
380 	.clear_irq	= exynos_adc_v2_clear_irq,
381 	.start_conv	= exynos_adc_v2_start_conv,
382 };
383 
384 static const struct of_device_id exynos_adc_match[] = {
385 	{
386 		.compatible = "samsung,s3c2410-adc",
387 		.data = &exynos_adc_s3c24xx_data,
388 	}, {
389 		.compatible = "samsung,s3c2416-adc",
390 		.data = &exynos_adc_s3c2416_data,
391 	}, {
392 		.compatible = "samsung,s3c2440-adc",
393 		.data = &exynos_adc_s3c24xx_data,
394 	}, {
395 		.compatible = "samsung,s3c2443-adc",
396 		.data = &exynos_adc_s3c2443_data,
397 	}, {
398 		.compatible = "samsung,s3c6410-adc",
399 		.data = &exynos_adc_s3c64xx_data,
400 	}, {
401 		.compatible = "samsung,exynos-adc-v1",
402 		.data = &exynos_adc_v1_data,
403 	}, {
404 		.compatible = "samsung,exynos-adc-v2",
405 		.data = &exynos_adc_v2_data,
406 	}, {
407 		.compatible = "samsung,exynos3250-adc",
408 		.data = &exynos3250_adc_data,
409 	},
410 	{},
411 };
412 MODULE_DEVICE_TABLE(of, exynos_adc_match);
413 
414 static struct exynos_adc_data *exynos_adc_get_data(struct platform_device *pdev)
415 {
416 	const struct of_device_id *match;
417 
418 	match = of_match_node(exynos_adc_match, pdev->dev.of_node);
419 	return (struct exynos_adc_data *)match->data;
420 }
421 
422 static int exynos_read_raw(struct iio_dev *indio_dev,
423 				struct iio_chan_spec const *chan,
424 				int *val,
425 				int *val2,
426 				long mask)
427 {
428 	struct exynos_adc *info = iio_priv(indio_dev);
429 	unsigned long timeout;
430 	int ret;
431 
432 	if (mask != IIO_CHAN_INFO_RAW)
433 		return -EINVAL;
434 
435 	mutex_lock(&indio_dev->mlock);
436 	reinit_completion(&info->completion);
437 
438 	/* Select the channel to be used and Trigger conversion */
439 	if (info->data->start_conv)
440 		info->data->start_conv(info, chan->address);
441 
442 	timeout = wait_for_completion_timeout
443 			(&info->completion, EXYNOS_ADC_TIMEOUT);
444 	if (timeout == 0) {
445 		dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n");
446 		if (info->data->init_hw)
447 			info->data->init_hw(info);
448 		ret = -ETIMEDOUT;
449 	} else {
450 		*val = info->value;
451 		*val2 = 0;
452 		ret = IIO_VAL_INT;
453 	}
454 
455 	mutex_unlock(&indio_dev->mlock);
456 
457 	return ret;
458 }
459 
460 static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
461 {
462 	struct exynos_adc *info = (struct exynos_adc *)dev_id;
463 	u32 mask = info->data->mask;
464 
465 	/* Read value */
466 	info->value = readl(ADC_V1_DATX(info->regs)) & mask;
467 
468 	/* clear irq */
469 	if (info->data->clear_irq)
470 		info->data->clear_irq(info);
471 
472 	complete(&info->completion);
473 
474 	return IRQ_HANDLED;
475 }
476 
477 static int exynos_adc_reg_access(struct iio_dev *indio_dev,
478 			      unsigned reg, unsigned writeval,
479 			      unsigned *readval)
480 {
481 	struct exynos_adc *info = iio_priv(indio_dev);
482 
483 	if (readval == NULL)
484 		return -EINVAL;
485 
486 	*readval = readl(info->regs + reg);
487 
488 	return 0;
489 }
490 
491 static const struct iio_info exynos_adc_iio_info = {
492 	.read_raw = &exynos_read_raw,
493 	.debugfs_reg_access = &exynos_adc_reg_access,
494 	.driver_module = THIS_MODULE,
495 };
496 
497 #define ADC_CHANNEL(_index, _id) {			\
498 	.type = IIO_VOLTAGE,				\
499 	.indexed = 1,					\
500 	.channel = _index,				\
501 	.address = _index,				\
502 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),	\
503 	.datasheet_name = _id,				\
504 }
505 
506 static const struct iio_chan_spec exynos_adc_iio_channels[] = {
507 	ADC_CHANNEL(0, "adc0"),
508 	ADC_CHANNEL(1, "adc1"),
509 	ADC_CHANNEL(2, "adc2"),
510 	ADC_CHANNEL(3, "adc3"),
511 	ADC_CHANNEL(4, "adc4"),
512 	ADC_CHANNEL(5, "adc5"),
513 	ADC_CHANNEL(6, "adc6"),
514 	ADC_CHANNEL(7, "adc7"),
515 	ADC_CHANNEL(8, "adc8"),
516 	ADC_CHANNEL(9, "adc9"),
517 };
518 
519 static int exynos_adc_remove_devices(struct device *dev, void *c)
520 {
521 	struct platform_device *pdev = to_platform_device(dev);
522 
523 	platform_device_unregister(pdev);
524 
525 	return 0;
526 }
527 
528 static int exynos_adc_probe(struct platform_device *pdev)
529 {
530 	struct exynos_adc *info = NULL;
531 	struct device_node *np = pdev->dev.of_node;
532 	struct iio_dev *indio_dev = NULL;
533 	struct resource	*mem;
534 	int ret = -ENODEV;
535 	int irq;
536 
537 	if (!np)
538 		return ret;
539 
540 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct exynos_adc));
541 	if (!indio_dev) {
542 		dev_err(&pdev->dev, "failed allocating iio device\n");
543 		return -ENOMEM;
544 	}
545 
546 	info = iio_priv(indio_dev);
547 
548 	info->data = exynos_adc_get_data(pdev);
549 	if (!info->data) {
550 		dev_err(&pdev->dev, "failed getting exynos_adc_data\n");
551 		return -EINVAL;
552 	}
553 
554 	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
555 	info->regs = devm_ioremap_resource(&pdev->dev, mem);
556 	if (IS_ERR(info->regs))
557 		return PTR_ERR(info->regs);
558 
559 
560 	if (info->data->needs_adc_phy) {
561 		mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
562 		info->enable_reg = devm_ioremap_resource(&pdev->dev, mem);
563 		if (IS_ERR(info->enable_reg))
564 			return PTR_ERR(info->enable_reg);
565 	}
566 
567 	irq = platform_get_irq(pdev, 0);
568 	if (irq < 0) {
569 		dev_err(&pdev->dev, "no irq resource?\n");
570 		return irq;
571 	}
572 
573 	info->irq = irq;
574 	info->dev = &pdev->dev;
575 
576 	init_completion(&info->completion);
577 
578 	info->clk = devm_clk_get(&pdev->dev, "adc");
579 	if (IS_ERR(info->clk)) {
580 		dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
581 							PTR_ERR(info->clk));
582 		return PTR_ERR(info->clk);
583 	}
584 
585 	if (info->data->needs_sclk) {
586 		info->sclk = devm_clk_get(&pdev->dev, "sclk");
587 		if (IS_ERR(info->sclk)) {
588 			dev_err(&pdev->dev,
589 				"failed getting sclk clock, err = %ld\n",
590 				PTR_ERR(info->sclk));
591 			return PTR_ERR(info->sclk);
592 		}
593 	}
594 
595 	info->vdd = devm_regulator_get(&pdev->dev, "vdd");
596 	if (IS_ERR(info->vdd)) {
597 		dev_err(&pdev->dev, "failed getting regulator, err = %ld\n",
598 							PTR_ERR(info->vdd));
599 		return PTR_ERR(info->vdd);
600 	}
601 
602 	ret = regulator_enable(info->vdd);
603 	if (ret)
604 		return ret;
605 
606 	ret = exynos_adc_prepare_clk(info);
607 	if (ret)
608 		goto err_disable_reg;
609 
610 	ret = exynos_adc_enable_clk(info);
611 	if (ret)
612 		goto err_unprepare_clk;
613 
614 	platform_set_drvdata(pdev, indio_dev);
615 
616 	indio_dev->name = dev_name(&pdev->dev);
617 	indio_dev->dev.parent = &pdev->dev;
618 	indio_dev->dev.of_node = pdev->dev.of_node;
619 	indio_dev->info = &exynos_adc_iio_info;
620 	indio_dev->modes = INDIO_DIRECT_MODE;
621 	indio_dev->channels = exynos_adc_iio_channels;
622 	indio_dev->num_channels = info->data->num_channels;
623 
624 	ret = request_irq(info->irq, exynos_adc_isr,
625 					0, dev_name(&pdev->dev), info);
626 	if (ret < 0) {
627 		dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
628 							info->irq);
629 		goto err_disable_clk;
630 	}
631 
632 	ret = iio_device_register(indio_dev);
633 	if (ret)
634 		goto err_irq;
635 
636 	if (info->data->init_hw)
637 		info->data->init_hw(info);
638 
639 	ret = of_platform_populate(np, exynos_adc_match, NULL, &indio_dev->dev);
640 	if (ret < 0) {
641 		dev_err(&pdev->dev, "failed adding child nodes\n");
642 		goto err_of_populate;
643 	}
644 
645 	return 0;
646 
647 err_of_populate:
648 	device_for_each_child(&indio_dev->dev, NULL,
649 				exynos_adc_remove_devices);
650 	iio_device_unregister(indio_dev);
651 err_irq:
652 	free_irq(info->irq, info);
653 err_disable_clk:
654 	if (info->data->exit_hw)
655 		info->data->exit_hw(info);
656 	exynos_adc_disable_clk(info);
657 err_unprepare_clk:
658 	exynos_adc_unprepare_clk(info);
659 err_disable_reg:
660 	regulator_disable(info->vdd);
661 	return ret;
662 }
663 
664 static int exynos_adc_remove(struct platform_device *pdev)
665 {
666 	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
667 	struct exynos_adc *info = iio_priv(indio_dev);
668 
669 	device_for_each_child(&indio_dev->dev, NULL,
670 				exynos_adc_remove_devices);
671 	iio_device_unregister(indio_dev);
672 	free_irq(info->irq, info);
673 	if (info->data->exit_hw)
674 		info->data->exit_hw(info);
675 	exynos_adc_disable_clk(info);
676 	exynos_adc_unprepare_clk(info);
677 	regulator_disable(info->vdd);
678 
679 	return 0;
680 }
681 
682 #ifdef CONFIG_PM_SLEEP
683 static int exynos_adc_suspend(struct device *dev)
684 {
685 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
686 	struct exynos_adc *info = iio_priv(indio_dev);
687 
688 	if (info->data->exit_hw)
689 		info->data->exit_hw(info);
690 	exynos_adc_disable_clk(info);
691 	regulator_disable(info->vdd);
692 
693 	return 0;
694 }
695 
696 static int exynos_adc_resume(struct device *dev)
697 {
698 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
699 	struct exynos_adc *info = iio_priv(indio_dev);
700 	int ret;
701 
702 	ret = regulator_enable(info->vdd);
703 	if (ret)
704 		return ret;
705 
706 	ret = exynos_adc_enable_clk(info);
707 	if (ret)
708 		return ret;
709 
710 	if (info->data->init_hw)
711 		info->data->init_hw(info);
712 
713 	return 0;
714 }
715 #endif
716 
717 static SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops,
718 			exynos_adc_suspend,
719 			exynos_adc_resume);
720 
721 static struct platform_driver exynos_adc_driver = {
722 	.probe		= exynos_adc_probe,
723 	.remove		= exynos_adc_remove,
724 	.driver		= {
725 		.name	= "exynos-adc",
726 		.of_match_table = exynos_adc_match,
727 		.pm	= &exynos_adc_pm_ops,
728 	},
729 };
730 
731 module_platform_driver(exynos_adc_driver);
732 
733 MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
734 MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver");
735 MODULE_LICENSE("GPL v2");
736