1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Driver for the Diolan DLN-2 USB-ADC adapter 4 * 5 * Copyright (c) 2017 Jack Andersen 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/types.h> 11 #include <linux/platform_device.h> 12 #include <linux/mfd/dln2.h> 13 14 #include <linux/iio/iio.h> 15 #include <linux/iio/sysfs.h> 16 #include <linux/iio/trigger.h> 17 #include <linux/iio/trigger_consumer.h> 18 #include <linux/iio/triggered_buffer.h> 19 #include <linux/iio/buffer.h> 20 #include <linux/iio/kfifo_buf.h> 21 22 #define DLN2_ADC_MOD_NAME "dln2-adc" 23 24 #define DLN2_ADC_ID 0x06 25 26 #define DLN2_ADC_GET_CHANNEL_COUNT DLN2_CMD(0x01, DLN2_ADC_ID) 27 #define DLN2_ADC_ENABLE DLN2_CMD(0x02, DLN2_ADC_ID) 28 #define DLN2_ADC_DISABLE DLN2_CMD(0x03, DLN2_ADC_ID) 29 #define DLN2_ADC_CHANNEL_ENABLE DLN2_CMD(0x05, DLN2_ADC_ID) 30 #define DLN2_ADC_CHANNEL_DISABLE DLN2_CMD(0x06, DLN2_ADC_ID) 31 #define DLN2_ADC_SET_RESOLUTION DLN2_CMD(0x08, DLN2_ADC_ID) 32 #define DLN2_ADC_CHANNEL_GET_VAL DLN2_CMD(0x0A, DLN2_ADC_ID) 33 #define DLN2_ADC_CHANNEL_GET_ALL_VAL DLN2_CMD(0x0B, DLN2_ADC_ID) 34 #define DLN2_ADC_CHANNEL_SET_CFG DLN2_CMD(0x0C, DLN2_ADC_ID) 35 #define DLN2_ADC_CHANNEL_GET_CFG DLN2_CMD(0x0D, DLN2_ADC_ID) 36 #define DLN2_ADC_CONDITION_MET_EV DLN2_CMD(0x10, DLN2_ADC_ID) 37 38 #define DLN2_ADC_EVENT_NONE 0 39 #define DLN2_ADC_EVENT_BELOW 1 40 #define DLN2_ADC_EVENT_LEVEL_ABOVE 2 41 #define DLN2_ADC_EVENT_OUTSIDE 3 42 #define DLN2_ADC_EVENT_INSIDE 4 43 #define DLN2_ADC_EVENT_ALWAYS 5 44 45 #define DLN2_ADC_MAX_CHANNELS 8 46 #define DLN2_ADC_DATA_BITS 10 47 48 /* 49 * Plays similar role to iio_demux_table in subsystem core; except allocated 50 * in a fixed 8-element array. 51 */ 52 struct dln2_adc_demux_table { 53 unsigned int from; 54 unsigned int to; 55 unsigned int length; 56 }; 57 58 struct dln2_adc { 59 struct platform_device *pdev; 60 struct iio_chan_spec iio_channels[DLN2_ADC_MAX_CHANNELS + 1]; 61 int port, trigger_chan; 62 struct iio_trigger *trig; 63 struct mutex mutex; 64 /* Cached sample period in milliseconds */ 65 unsigned int sample_period; 66 /* Demux table */ 67 unsigned int demux_count; 68 struct dln2_adc_demux_table demux[DLN2_ADC_MAX_CHANNELS]; 69 /* Precomputed timestamp padding offset and length */ 70 unsigned int ts_pad_offset, ts_pad_length; 71 }; 72 73 struct dln2_adc_port_chan { 74 u8 port; 75 u8 chan; 76 }; 77 78 struct dln2_adc_get_all_vals { 79 __le16 channel_mask; 80 __le16 values[DLN2_ADC_MAX_CHANNELS]; 81 }; 82 83 static void dln2_adc_add_demux(struct dln2_adc *dln2, 84 unsigned int in_loc, unsigned int out_loc, 85 unsigned int length) 86 { 87 struct dln2_adc_demux_table *p = dln2->demux_count ? 88 &dln2->demux[dln2->demux_count - 1] : NULL; 89 90 if (p && p->from + p->length == in_loc && 91 p->to + p->length == out_loc) { 92 p->length += length; 93 } else if (dln2->demux_count < DLN2_ADC_MAX_CHANNELS) { 94 p = &dln2->demux[dln2->demux_count++]; 95 p->from = in_loc; 96 p->to = out_loc; 97 p->length = length; 98 } 99 } 100 101 static void dln2_adc_update_demux(struct dln2_adc *dln2) 102 { 103 int in_ind = -1, out_ind; 104 unsigned int in_loc = 0, out_loc = 0; 105 struct iio_dev *indio_dev = platform_get_drvdata(dln2->pdev); 106 107 /* Clear out any old demux */ 108 dln2->demux_count = 0; 109 110 /* Optimize all 8-channels case */ 111 if (indio_dev->masklength && 112 (*indio_dev->active_scan_mask & 0xff) == 0xff) { 113 dln2_adc_add_demux(dln2, 0, 0, 16); 114 dln2->ts_pad_offset = 0; 115 dln2->ts_pad_length = 0; 116 return; 117 } 118 119 /* Build demux table from fixed 8-channels to active_scan_mask */ 120 for_each_set_bit(out_ind, 121 indio_dev->active_scan_mask, 122 indio_dev->masklength) { 123 /* Handle timestamp separately */ 124 if (out_ind == DLN2_ADC_MAX_CHANNELS) 125 break; 126 for (++in_ind; in_ind != out_ind; ++in_ind) 127 in_loc += 2; 128 dln2_adc_add_demux(dln2, in_loc, out_loc, 2); 129 out_loc += 2; 130 in_loc += 2; 131 } 132 133 if (indio_dev->scan_timestamp) { 134 size_t ts_offset = indio_dev->scan_bytes / sizeof(int64_t) - 1; 135 136 dln2->ts_pad_offset = out_loc; 137 dln2->ts_pad_length = ts_offset * sizeof(int64_t) - out_loc; 138 } else { 139 dln2->ts_pad_offset = 0; 140 dln2->ts_pad_length = 0; 141 } 142 } 143 144 static int dln2_adc_get_chan_count(struct dln2_adc *dln2) 145 { 146 int ret; 147 u8 port = dln2->port; 148 u8 count; 149 int olen = sizeof(count); 150 151 ret = dln2_transfer(dln2->pdev, DLN2_ADC_GET_CHANNEL_COUNT, 152 &port, sizeof(port), &count, &olen); 153 if (ret < 0) { 154 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__); 155 return ret; 156 } 157 if (olen < sizeof(count)) 158 return -EPROTO; 159 160 return count; 161 } 162 163 static int dln2_adc_set_port_resolution(struct dln2_adc *dln2) 164 { 165 int ret; 166 struct dln2_adc_port_chan port_chan = { 167 .port = dln2->port, 168 .chan = DLN2_ADC_DATA_BITS, 169 }; 170 171 ret = dln2_transfer_tx(dln2->pdev, DLN2_ADC_SET_RESOLUTION, 172 &port_chan, sizeof(port_chan)); 173 if (ret < 0) 174 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__); 175 176 return ret; 177 } 178 179 static int dln2_adc_set_chan_enabled(struct dln2_adc *dln2, 180 int channel, bool enable) 181 { 182 int ret; 183 struct dln2_adc_port_chan port_chan = { 184 .port = dln2->port, 185 .chan = channel, 186 }; 187 u16 cmd = enable ? DLN2_ADC_CHANNEL_ENABLE : DLN2_ADC_CHANNEL_DISABLE; 188 189 ret = dln2_transfer_tx(dln2->pdev, cmd, &port_chan, sizeof(port_chan)); 190 if (ret < 0) 191 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__); 192 193 return ret; 194 } 195 196 static int dln2_adc_set_port_enabled(struct dln2_adc *dln2, bool enable, 197 u16 *conflict_out) 198 { 199 int ret; 200 u8 port = dln2->port; 201 __le16 conflict; 202 int olen = sizeof(conflict); 203 u16 cmd = enable ? DLN2_ADC_ENABLE : DLN2_ADC_DISABLE; 204 205 if (conflict_out) 206 *conflict_out = 0; 207 208 ret = dln2_transfer(dln2->pdev, cmd, &port, sizeof(port), 209 &conflict, &olen); 210 if (ret < 0) { 211 dev_dbg(&dln2->pdev->dev, "Problem in %s(%d)\n", 212 __func__, (int)enable); 213 if (conflict_out && enable && olen >= sizeof(conflict)) 214 *conflict_out = le16_to_cpu(conflict); 215 return ret; 216 } 217 if (enable && olen < sizeof(conflict)) 218 return -EPROTO; 219 220 return ret; 221 } 222 223 static int dln2_adc_set_chan_period(struct dln2_adc *dln2, 224 unsigned int channel, unsigned int period) 225 { 226 int ret; 227 struct { 228 struct dln2_adc_port_chan port_chan; 229 __u8 type; 230 __le16 period; 231 __le16 low; 232 __le16 high; 233 } __packed set_cfg = { 234 .port_chan.port = dln2->port, 235 .port_chan.chan = channel, 236 .type = period ? DLN2_ADC_EVENT_ALWAYS : DLN2_ADC_EVENT_NONE, 237 .period = cpu_to_le16(period) 238 }; 239 240 ret = dln2_transfer_tx(dln2->pdev, DLN2_ADC_CHANNEL_SET_CFG, 241 &set_cfg, sizeof(set_cfg)); 242 if (ret < 0) 243 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__); 244 245 return ret; 246 } 247 248 static int dln2_adc_read(struct dln2_adc *dln2, unsigned int channel) 249 { 250 int ret, i; 251 struct iio_dev *indio_dev = platform_get_drvdata(dln2->pdev); 252 u16 conflict; 253 __le16 value; 254 int olen = sizeof(value); 255 struct dln2_adc_port_chan port_chan = { 256 .port = dln2->port, 257 .chan = channel, 258 }; 259 260 ret = iio_device_claim_direct_mode(indio_dev); 261 if (ret < 0) 262 return ret; 263 264 ret = dln2_adc_set_chan_enabled(dln2, channel, true); 265 if (ret < 0) 266 goto release_direct; 267 268 ret = dln2_adc_set_port_enabled(dln2, true, &conflict); 269 if (ret < 0) { 270 if (conflict) { 271 dev_err(&dln2->pdev->dev, 272 "ADC pins conflict with mask %04X\n", 273 (int)conflict); 274 ret = -EBUSY; 275 } 276 goto disable_chan; 277 } 278 279 /* 280 * Call GET_VAL twice due to initial zero-return immediately after 281 * enabling channel. 282 */ 283 for (i = 0; i < 2; ++i) { 284 ret = dln2_transfer(dln2->pdev, DLN2_ADC_CHANNEL_GET_VAL, 285 &port_chan, sizeof(port_chan), 286 &value, &olen); 287 if (ret < 0) { 288 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__); 289 goto disable_port; 290 } 291 if (olen < sizeof(value)) { 292 ret = -EPROTO; 293 goto disable_port; 294 } 295 } 296 297 ret = le16_to_cpu(value); 298 299 disable_port: 300 dln2_adc_set_port_enabled(dln2, false, NULL); 301 disable_chan: 302 dln2_adc_set_chan_enabled(dln2, channel, false); 303 release_direct: 304 iio_device_release_direct_mode(indio_dev); 305 306 return ret; 307 } 308 309 static int dln2_adc_read_all(struct dln2_adc *dln2, 310 struct dln2_adc_get_all_vals *get_all_vals) 311 { 312 int ret; 313 __u8 port = dln2->port; 314 int olen = sizeof(*get_all_vals); 315 316 ret = dln2_transfer(dln2->pdev, DLN2_ADC_CHANNEL_GET_ALL_VAL, 317 &port, sizeof(port), get_all_vals, &olen); 318 if (ret < 0) { 319 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__); 320 return ret; 321 } 322 if (olen < sizeof(*get_all_vals)) 323 return -EPROTO; 324 325 return ret; 326 } 327 328 static int dln2_adc_read_raw(struct iio_dev *indio_dev, 329 struct iio_chan_spec const *chan, 330 int *val, 331 int *val2, 332 long mask) 333 { 334 int ret; 335 unsigned int microhertz; 336 struct dln2_adc *dln2 = iio_priv(indio_dev); 337 338 switch (mask) { 339 case IIO_CHAN_INFO_RAW: 340 mutex_lock(&dln2->mutex); 341 ret = dln2_adc_read(dln2, chan->channel); 342 mutex_unlock(&dln2->mutex); 343 344 if (ret < 0) 345 return ret; 346 347 *val = ret; 348 return IIO_VAL_INT; 349 350 case IIO_CHAN_INFO_SCALE: 351 /* 352 * Voltage reference is fixed at 3.3v 353 * 3.3 / (1 << 10) * 1000000000 354 */ 355 *val = 0; 356 *val2 = 3222656; 357 return IIO_VAL_INT_PLUS_NANO; 358 359 case IIO_CHAN_INFO_SAMP_FREQ: 360 if (dln2->sample_period) { 361 microhertz = 1000000000 / dln2->sample_period; 362 *val = microhertz / 1000000; 363 *val2 = microhertz % 1000000; 364 } else { 365 *val = 0; 366 *val2 = 0; 367 } 368 369 return IIO_VAL_INT_PLUS_MICRO; 370 371 default: 372 return -EINVAL; 373 } 374 } 375 376 static int dln2_adc_write_raw(struct iio_dev *indio_dev, 377 struct iio_chan_spec const *chan, 378 int val, 379 int val2, 380 long mask) 381 { 382 int ret; 383 unsigned int microhertz; 384 struct dln2_adc *dln2 = iio_priv(indio_dev); 385 386 switch (mask) { 387 case IIO_CHAN_INFO_SAMP_FREQ: 388 microhertz = 1000000 * val + val2; 389 390 mutex_lock(&dln2->mutex); 391 392 dln2->sample_period = 393 microhertz ? 1000000000 / microhertz : UINT_MAX; 394 if (dln2->sample_period > 65535) { 395 dln2->sample_period = 65535; 396 dev_warn(&dln2->pdev->dev, 397 "clamping period to 65535ms\n"); 398 } 399 400 /* 401 * The first requested channel is arbitrated as a shared 402 * trigger source, so only one event is registered with the 403 * DLN. The event handler will then read all enabled channel 404 * values using DLN2_ADC_CHANNEL_GET_ALL_VAL to maintain 405 * synchronization between ADC readings. 406 */ 407 if (dln2->trigger_chan != -1) 408 ret = dln2_adc_set_chan_period(dln2, 409 dln2->trigger_chan, dln2->sample_period); 410 else 411 ret = 0; 412 413 mutex_unlock(&dln2->mutex); 414 415 return ret; 416 417 default: 418 return -EINVAL; 419 } 420 } 421 422 static int dln2_update_scan_mode(struct iio_dev *indio_dev, 423 const unsigned long *scan_mask) 424 { 425 struct dln2_adc *dln2 = iio_priv(indio_dev); 426 int chan_count = indio_dev->num_channels - 1; 427 int ret, i, j; 428 429 mutex_lock(&dln2->mutex); 430 431 for (i = 0; i < chan_count; ++i) { 432 ret = dln2_adc_set_chan_enabled(dln2, i, 433 test_bit(i, scan_mask)); 434 if (ret < 0) { 435 for (j = 0; j < i; ++j) 436 dln2_adc_set_chan_enabled(dln2, j, false); 437 mutex_unlock(&dln2->mutex); 438 dev_err(&dln2->pdev->dev, 439 "Unable to enable ADC channel %d\n", i); 440 return -EBUSY; 441 } 442 } 443 444 dln2_adc_update_demux(dln2); 445 446 mutex_unlock(&dln2->mutex); 447 448 return 0; 449 } 450 451 #define DLN2_ADC_CHAN(lval, idx) { \ 452 lval.type = IIO_VOLTAGE; \ 453 lval.channel = idx; \ 454 lval.indexed = 1; \ 455 lval.info_mask_separate = BIT(IIO_CHAN_INFO_RAW); \ 456 lval.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) | \ 457 BIT(IIO_CHAN_INFO_SAMP_FREQ); \ 458 lval.scan_index = idx; \ 459 lval.scan_type.sign = 'u'; \ 460 lval.scan_type.realbits = DLN2_ADC_DATA_BITS; \ 461 lval.scan_type.storagebits = 16; \ 462 lval.scan_type.endianness = IIO_LE; \ 463 } 464 465 /* Assignment version of IIO_CHAN_SOFT_TIMESTAMP */ 466 #define IIO_CHAN_SOFT_TIMESTAMP_ASSIGN(lval, _si) { \ 467 lval.type = IIO_TIMESTAMP; \ 468 lval.channel = -1; \ 469 lval.scan_index = _si; \ 470 lval.scan_type.sign = 's'; \ 471 lval.scan_type.realbits = 64; \ 472 lval.scan_type.storagebits = 64; \ 473 } 474 475 static const struct iio_info dln2_adc_info = { 476 .read_raw = dln2_adc_read_raw, 477 .write_raw = dln2_adc_write_raw, 478 .update_scan_mode = dln2_update_scan_mode, 479 }; 480 481 static irqreturn_t dln2_adc_trigger_h(int irq, void *p) 482 { 483 struct iio_poll_func *pf = p; 484 struct iio_dev *indio_dev = pf->indio_dev; 485 struct { 486 __le16 values[DLN2_ADC_MAX_CHANNELS]; 487 int64_t timestamp_space; 488 } data; 489 struct dln2_adc_get_all_vals dev_data; 490 struct dln2_adc *dln2 = iio_priv(indio_dev); 491 const struct dln2_adc_demux_table *t; 492 int ret, i; 493 494 mutex_lock(&dln2->mutex); 495 ret = dln2_adc_read_all(dln2, &dev_data); 496 mutex_unlock(&dln2->mutex); 497 if (ret < 0) 498 goto done; 499 500 /* Demux operation */ 501 for (i = 0; i < dln2->demux_count; ++i) { 502 t = &dln2->demux[i]; 503 memcpy((void *)data.values + t->to, 504 (void *)dev_data.values + t->from, t->length); 505 } 506 507 /* Zero padding space between values and timestamp */ 508 if (dln2->ts_pad_length) 509 memset((void *)data.values + dln2->ts_pad_offset, 510 0, dln2->ts_pad_length); 511 512 iio_push_to_buffers_with_timestamp(indio_dev, &data, 513 iio_get_time_ns(indio_dev)); 514 515 done: 516 iio_trigger_notify_done(indio_dev->trig); 517 return IRQ_HANDLED; 518 } 519 520 static int dln2_adc_triggered_buffer_postenable(struct iio_dev *indio_dev) 521 { 522 int ret; 523 struct dln2_adc *dln2 = iio_priv(indio_dev); 524 u16 conflict; 525 unsigned int trigger_chan; 526 527 ret = iio_triggered_buffer_postenable(indio_dev); 528 if (ret) 529 return ret; 530 531 mutex_lock(&dln2->mutex); 532 533 /* Enable ADC */ 534 ret = dln2_adc_set_port_enabled(dln2, true, &conflict); 535 if (ret < 0) { 536 mutex_unlock(&dln2->mutex); 537 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__); 538 if (conflict) { 539 dev_err(&dln2->pdev->dev, 540 "ADC pins conflict with mask %04X\n", 541 (int)conflict); 542 ret = -EBUSY; 543 } 544 iio_triggered_buffer_predisable(indio_dev); 545 return ret; 546 } 547 548 /* Assign trigger channel based on first enabled channel */ 549 trigger_chan = find_first_bit(indio_dev->active_scan_mask, 550 indio_dev->masklength); 551 if (trigger_chan < DLN2_ADC_MAX_CHANNELS) { 552 dln2->trigger_chan = trigger_chan; 553 ret = dln2_adc_set_chan_period(dln2, dln2->trigger_chan, 554 dln2->sample_period); 555 mutex_unlock(&dln2->mutex); 556 if (ret < 0) { 557 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__); 558 iio_triggered_buffer_predisable(indio_dev); 559 return ret; 560 } 561 } else { 562 dln2->trigger_chan = -1; 563 mutex_unlock(&dln2->mutex); 564 } 565 566 return 0; 567 } 568 569 static int dln2_adc_triggered_buffer_predisable(struct iio_dev *indio_dev) 570 { 571 int ret, ret2; 572 struct dln2_adc *dln2 = iio_priv(indio_dev); 573 574 mutex_lock(&dln2->mutex); 575 576 /* Disable trigger channel */ 577 if (dln2->trigger_chan != -1) { 578 dln2_adc_set_chan_period(dln2, dln2->trigger_chan, 0); 579 dln2->trigger_chan = -1; 580 } 581 582 /* Disable ADC */ 583 ret = dln2_adc_set_port_enabled(dln2, false, NULL); 584 585 mutex_unlock(&dln2->mutex); 586 if (ret < 0) 587 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__); 588 589 ret2 = iio_triggered_buffer_predisable(indio_dev); 590 if (ret == 0) 591 ret = ret2; 592 593 return ret; 594 } 595 596 static const struct iio_buffer_setup_ops dln2_adc_buffer_setup_ops = { 597 .postenable = dln2_adc_triggered_buffer_postenable, 598 .predisable = dln2_adc_triggered_buffer_predisable, 599 }; 600 601 static void dln2_adc_event(struct platform_device *pdev, u16 echo, 602 const void *data, int len) 603 { 604 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 605 struct dln2_adc *dln2 = iio_priv(indio_dev); 606 607 /* Called via URB completion handler */ 608 iio_trigger_poll(dln2->trig); 609 } 610 611 static int dln2_adc_probe(struct platform_device *pdev) 612 { 613 struct device *dev = &pdev->dev; 614 struct dln2_adc *dln2; 615 struct dln2_platform_data *pdata = dev_get_platdata(&pdev->dev); 616 struct iio_dev *indio_dev; 617 int i, ret, chans; 618 619 indio_dev = devm_iio_device_alloc(dev, sizeof(*dln2)); 620 if (!indio_dev) { 621 dev_err(dev, "failed allocating iio device\n"); 622 return -ENOMEM; 623 } 624 625 dln2 = iio_priv(indio_dev); 626 dln2->pdev = pdev; 627 dln2->port = pdata->port; 628 dln2->trigger_chan = -1; 629 mutex_init(&dln2->mutex); 630 631 platform_set_drvdata(pdev, indio_dev); 632 633 ret = dln2_adc_set_port_resolution(dln2); 634 if (ret < 0) { 635 dev_err(dev, "failed to set ADC resolution to 10 bits\n"); 636 return ret; 637 } 638 639 chans = dln2_adc_get_chan_count(dln2); 640 if (chans < 0) { 641 dev_err(dev, "failed to get channel count: %d\n", chans); 642 return chans; 643 } 644 if (chans > DLN2_ADC_MAX_CHANNELS) { 645 chans = DLN2_ADC_MAX_CHANNELS; 646 dev_warn(dev, "clamping channels to %d\n", 647 DLN2_ADC_MAX_CHANNELS); 648 } 649 650 for (i = 0; i < chans; ++i) 651 DLN2_ADC_CHAN(dln2->iio_channels[i], i) 652 IIO_CHAN_SOFT_TIMESTAMP_ASSIGN(dln2->iio_channels[i], i); 653 654 indio_dev->name = DLN2_ADC_MOD_NAME; 655 indio_dev->info = &dln2_adc_info; 656 indio_dev->modes = INDIO_DIRECT_MODE; 657 indio_dev->channels = dln2->iio_channels; 658 indio_dev->num_channels = chans + 1; 659 indio_dev->setup_ops = &dln2_adc_buffer_setup_ops; 660 661 dln2->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", 662 indio_dev->name, indio_dev->id); 663 if (!dln2->trig) { 664 dev_err(dev, "failed to allocate trigger\n"); 665 return -ENOMEM; 666 } 667 iio_trigger_set_drvdata(dln2->trig, dln2); 668 devm_iio_trigger_register(dev, dln2->trig); 669 iio_trigger_set_immutable(indio_dev, dln2->trig); 670 671 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL, 672 dln2_adc_trigger_h, 673 &dln2_adc_buffer_setup_ops); 674 if (ret) { 675 dev_err(dev, "failed to allocate triggered buffer: %d\n", ret); 676 return ret; 677 } 678 679 ret = dln2_register_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV, 680 dln2_adc_event); 681 if (ret) { 682 dev_err(dev, "failed to setup DLN2 periodic event: %d\n", ret); 683 return ret; 684 } 685 686 ret = iio_device_register(indio_dev); 687 if (ret) { 688 dev_err(dev, "failed to register iio device: %d\n", ret); 689 goto unregister_event; 690 } 691 692 return ret; 693 694 unregister_event: 695 dln2_unregister_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV); 696 697 return ret; 698 } 699 700 static int dln2_adc_remove(struct platform_device *pdev) 701 { 702 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 703 704 iio_device_unregister(indio_dev); 705 dln2_unregister_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV); 706 return 0; 707 } 708 709 static struct platform_driver dln2_adc_driver = { 710 .driver.name = DLN2_ADC_MOD_NAME, 711 .probe = dln2_adc_probe, 712 .remove = dln2_adc_remove, 713 }; 714 715 module_platform_driver(dln2_adc_driver); 716 717 MODULE_AUTHOR("Jack Andersen <jackoalan@gmail.com"); 718 MODULE_DESCRIPTION("Driver for the Diolan DLN2 ADC interface"); 719 MODULE_LICENSE("GPL v2"); 720 MODULE_ALIAS("platform:dln2-adc"); 721