1 /* 2 * Copyright (C) 2017 Tony Lindgren <tony@atomide.com> 3 * 4 * Rewritten for Linux IIO framework with some code based on 5 * earlier driver found in the Motorola Linux kernel: 6 * 7 * Copyright (C) 2009-2010 Motorola, Inc. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 */ 18 19 #include <linux/delay.h> 20 #include <linux/device.h> 21 #include <linux/err.h> 22 #include <linux/init.h> 23 #include <linux/interrupt.h> 24 #include <linux/kernel.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_platform.h> 28 #include <linux/platform_device.h> 29 #include <linux/regmap.h> 30 31 #include <linux/iio/buffer.h> 32 #include <linux/iio/driver.h> 33 #include <linux/iio/iio.h> 34 #include <linux/iio/kfifo_buf.h> 35 #include <linux/mfd/motorola-cpcap.h> 36 37 /* Register CPCAP_REG_ADCC1 bits */ 38 #define CPCAP_BIT_ADEN_AUTO_CLR BIT(15) /* Currently unused */ 39 #define CPCAP_BIT_CAL_MODE BIT(14) /* Set with BIT_RAND0 */ 40 #define CPCAP_BIT_ADC_CLK_SEL1 BIT(13) /* Currently unused */ 41 #define CPCAP_BIT_ADC_CLK_SEL0 BIT(12) /* Currently unused */ 42 #define CPCAP_BIT_ATOX BIT(11) 43 #define CPCAP_BIT_ATO3 BIT(10) 44 #define CPCAP_BIT_ATO2 BIT(9) 45 #define CPCAP_BIT_ATO1 BIT(8) 46 #define CPCAP_BIT_ATO0 BIT(7) 47 #define CPCAP_BIT_ADA2 BIT(6) 48 #define CPCAP_BIT_ADA1 BIT(5) 49 #define CPCAP_BIT_ADA0 BIT(4) 50 #define CPCAP_BIT_AD_SEL1 BIT(3) /* Set for bank1 */ 51 #define CPCAP_BIT_RAND1 BIT(2) /* Set for channel 16 & 17 */ 52 #define CPCAP_BIT_RAND0 BIT(1) /* Set with CAL_MODE */ 53 #define CPCAP_BIT_ADEN BIT(0) /* Currently unused */ 54 55 /* Register CPCAP_REG_ADCC2 bits */ 56 #define CPCAP_BIT_CAL_FACTOR_ENABLE BIT(15) /* Currently unused */ 57 #define CPCAP_BIT_BATDETB_EN BIT(14) /* Currently unused */ 58 #define CPCAP_BIT_ADTRIG_ONESHOT BIT(13) /* Set for !TIMING_IMM */ 59 #define CPCAP_BIT_ASC BIT(12) /* Set for TIMING_IMM */ 60 #define CPCAP_BIT_ATOX_PS_FACTOR BIT(11) 61 #define CPCAP_BIT_ADC_PS_FACTOR1 BIT(10) 62 #define CPCAP_BIT_ADC_PS_FACTOR0 BIT(9) 63 #define CPCAP_BIT_AD4_SELECT BIT(8) /* Currently unused */ 64 #define CPCAP_BIT_ADC_BUSY BIT(7) /* Currently unused */ 65 #define CPCAP_BIT_THERMBIAS_EN BIT(6) /* Currently unused */ 66 #define CPCAP_BIT_ADTRIG_DIS BIT(5) /* Disable interrupt */ 67 #define CPCAP_BIT_LIADC BIT(4) /* Currently unused */ 68 #define CPCAP_BIT_TS_REFEN BIT(3) /* Currently unused */ 69 #define CPCAP_BIT_TS_M2 BIT(2) /* Currently unused */ 70 #define CPCAP_BIT_TS_M1 BIT(1) /* Currently unused */ 71 #define CPCAP_BIT_TS_M0 BIT(0) /* Currently unused */ 72 73 #define CPCAP_MAX_TEMP_LVL 27 74 #define CPCAP_FOUR_POINT_TWO_ADC 801 75 #define ST_ADC_CAL_CHRGI_HIGH_THRESHOLD 530 76 #define ST_ADC_CAL_CHRGI_LOW_THRESHOLD 494 77 #define ST_ADC_CAL_BATTI_HIGH_THRESHOLD 530 78 #define ST_ADC_CAL_BATTI_LOW_THRESHOLD 494 79 #define ST_ADC_CALIBRATE_DIFF_THRESHOLD 3 80 81 #define CPCAP_ADC_MAX_RETRIES 5 /* Calibration and quirk */ 82 83 /** 84 * struct cpcap_adc_ato - timing settings for cpcap adc 85 * 86 * Unfortunately no cpcap documentation available, please document when 87 * using these. 88 */ 89 struct cpcap_adc_ato { 90 unsigned short ato_in; 91 unsigned short atox_in; 92 unsigned short adc_ps_factor_in; 93 unsigned short atox_ps_factor_in; 94 unsigned short ato_out; 95 unsigned short atox_out; 96 unsigned short adc_ps_factor_out; 97 unsigned short atox_ps_factor_out; 98 }; 99 100 /** 101 * struct cpcap-adc - cpcap adc device driver data 102 * @reg: cpcap regmap 103 * @dev: struct device 104 * @vendor: cpcap vendor 105 * @irq: interrupt 106 * @lock: mutex 107 * @ato: request timings 108 * @wq_data_avail: work queue 109 * @done: work done 110 */ 111 struct cpcap_adc { 112 struct regmap *reg; 113 struct device *dev; 114 u16 vendor; 115 int irq; 116 struct mutex lock; /* ADC register access lock */ 117 const struct cpcap_adc_ato *ato; 118 wait_queue_head_t wq_data_avail; 119 bool done; 120 }; 121 122 /** 123 * enum cpcap_adc_channel - cpcap adc channels 124 */ 125 enum cpcap_adc_channel { 126 /* Bank0 channels */ 127 CPCAP_ADC_AD0_BATTDETB, /* Battery detection */ 128 CPCAP_ADC_BATTP, /* Battery voltage */ 129 CPCAP_ADC_VBUS, /* USB VBUS voltage */ 130 CPCAP_ADC_AD3, /* Battery temperature when charging */ 131 CPCAP_ADC_BPLUS_AD4, /* Another battery or system voltage */ 132 CPCAP_ADC_CHG_ISENSE, /* Calibrated charge current */ 133 CPCAP_ADC_BATTI, /* Calibrated system current */ 134 CPCAP_ADC_USB_ID, /* USB OTG ID, unused on droid 4? */ 135 136 /* Bank1 channels */ 137 CPCAP_ADC_AD8, /* Seems unused */ 138 CPCAP_ADC_AD9, /* Seems unused */ 139 CPCAP_ADC_LICELL, /* Maybe system voltage? Always 3V */ 140 CPCAP_ADC_HV_BATTP, /* Another battery detection? */ 141 CPCAP_ADC_TSX1_AD12, /* Seems unused, for touchscreen? */ 142 CPCAP_ADC_TSX2_AD13, /* Seems unused, for touchscreen? */ 143 CPCAP_ADC_TSY1_AD14, /* Seems unused, for touchscreen? */ 144 CPCAP_ADC_TSY2_AD15, /* Seems unused, for touchscreen? */ 145 146 /* Remuxed channels using bank0 entries */ 147 CPCAP_ADC_BATTP_PI16, /* Alternative mux mode for BATTP */ 148 CPCAP_ADC_BATTI_PI17, /* Alternative mux mode for BATTI */ 149 150 CPCAP_ADC_CHANNEL_NUM, 151 }; 152 153 /** 154 * enum cpcap_adc_timing - cpcap adc timing options 155 * 156 * CPCAP_ADC_TIMING_IMM seems to be immediate with no timings. 157 * Please document when using. 158 */ 159 enum cpcap_adc_timing { 160 CPCAP_ADC_TIMING_IMM, 161 CPCAP_ADC_TIMING_IN, 162 CPCAP_ADC_TIMING_OUT, 163 }; 164 165 /** 166 * struct cpcap_adc_phasing_tbl - cpcap phasing table 167 * @offset: offset in the phasing table 168 * @multiplier: multiplier in the phasing table 169 * @divider: divider in the phasing table 170 * @min: minimum value 171 * @max: maximum value 172 */ 173 struct cpcap_adc_phasing_tbl { 174 short offset; 175 unsigned short multiplier; 176 unsigned short divider; 177 short min; 178 short max; 179 }; 180 181 /** 182 * struct cpcap_adc_conversion_tbl - cpcap conversion table 183 * @conv_type: conversion type 184 * @align_offset: align offset 185 * @conv_offset: conversion offset 186 * @cal_offset: calibration offset 187 * @multiplier: conversion multiplier 188 * @divider: conversion divider 189 */ 190 struct cpcap_adc_conversion_tbl { 191 enum iio_chan_info_enum conv_type; 192 int align_offset; 193 int conv_offset; 194 int cal_offset; 195 int multiplier; 196 int divider; 197 }; 198 199 /** 200 * struct cpcap_adc_request - cpcap adc request 201 * @channel: request channel 202 * @phase_tbl: channel phasing table 203 * @conv_tbl: channel conversion table 204 * @bank_index: channel index within the bank 205 * @timing: timing settings 206 * @result: result 207 */ 208 struct cpcap_adc_request { 209 int channel; 210 const struct cpcap_adc_phasing_tbl *phase_tbl; 211 const struct cpcap_adc_conversion_tbl *conv_tbl; 212 int bank_index; 213 enum cpcap_adc_timing timing; 214 int result; 215 }; 216 217 /* Phasing table for channels. Note that channels 16 & 17 use BATTP and BATTI */ 218 static const struct cpcap_adc_phasing_tbl bank_phasing[] = { 219 /* Bank0 */ 220 [CPCAP_ADC_AD0_BATTDETB] = {0, 0x80, 0x80, 0, 1023}, 221 [CPCAP_ADC_BATTP] = {0, 0x80, 0x80, 0, 1023}, 222 [CPCAP_ADC_VBUS] = {0, 0x80, 0x80, 0, 1023}, 223 [CPCAP_ADC_AD3] = {0, 0x80, 0x80, 0, 1023}, 224 [CPCAP_ADC_BPLUS_AD4] = {0, 0x80, 0x80, 0, 1023}, 225 [CPCAP_ADC_CHG_ISENSE] = {0, 0x80, 0x80, -512, 511}, 226 [CPCAP_ADC_BATTI] = {0, 0x80, 0x80, -512, 511}, 227 [CPCAP_ADC_USB_ID] = {0, 0x80, 0x80, 0, 1023}, 228 229 /* Bank1 */ 230 [CPCAP_ADC_AD8] = {0, 0x80, 0x80, 0, 1023}, 231 [CPCAP_ADC_AD9] = {0, 0x80, 0x80, 0, 1023}, 232 [CPCAP_ADC_LICELL] = {0, 0x80, 0x80, 0, 1023}, 233 [CPCAP_ADC_HV_BATTP] = {0, 0x80, 0x80, 0, 1023}, 234 [CPCAP_ADC_TSX1_AD12] = {0, 0x80, 0x80, 0, 1023}, 235 [CPCAP_ADC_TSX2_AD13] = {0, 0x80, 0x80, 0, 1023}, 236 [CPCAP_ADC_TSY1_AD14] = {0, 0x80, 0x80, 0, 1023}, 237 [CPCAP_ADC_TSY2_AD15] = {0, 0x80, 0x80, 0, 1023}, 238 }; 239 240 /* 241 * Conversion table for channels. Updated during init based on calibration. 242 * Here too channels 16 & 17 use BATTP and BATTI. 243 */ 244 static struct cpcap_adc_conversion_tbl bank_conversion[] = { 245 /* Bank0 */ 246 [CPCAP_ADC_AD0_BATTDETB] = { 247 IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 1, 1, 248 }, 249 [CPCAP_ADC_BATTP] = { 250 IIO_CHAN_INFO_PROCESSED, 0, 2400, 0, 2300, 1023, 251 }, 252 [CPCAP_ADC_VBUS] = { 253 IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 10000, 1023, 254 }, 255 [CPCAP_ADC_AD3] = { 256 IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 1, 1, 257 }, 258 [CPCAP_ADC_BPLUS_AD4] = { 259 IIO_CHAN_INFO_PROCESSED, 0, 2400, 0, 2300, 1023, 260 }, 261 [CPCAP_ADC_CHG_ISENSE] = { 262 IIO_CHAN_INFO_PROCESSED, -512, 2, 0, 5000, 1023, 263 }, 264 [CPCAP_ADC_BATTI] = { 265 IIO_CHAN_INFO_PROCESSED, -512, 2, 0, 5000, 1023, 266 }, 267 [CPCAP_ADC_USB_ID] = { 268 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1, 269 }, 270 271 /* Bank1 */ 272 [CPCAP_ADC_AD8] = { 273 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1, 274 }, 275 [CPCAP_ADC_AD9] = { 276 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1, 277 }, 278 [CPCAP_ADC_LICELL] = { 279 IIO_CHAN_INFO_PROCESSED, 0, 0, 0, 3400, 1023, 280 }, 281 [CPCAP_ADC_HV_BATTP] = { 282 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1, 283 }, 284 [CPCAP_ADC_TSX1_AD12] = { 285 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1, 286 }, 287 [CPCAP_ADC_TSX2_AD13] = { 288 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1, 289 }, 290 [CPCAP_ADC_TSY1_AD14] = { 291 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1, 292 }, 293 [CPCAP_ADC_TSY2_AD15] = { 294 IIO_CHAN_INFO_RAW, 0, 0, 0, 1, 1, 295 }, 296 }; 297 298 /* 299 * Temperature lookup table of register values to milliCelcius. 300 * REVISIT: Check the duplicate 0x3ff entry in a freezer 301 */ 302 static const int temp_map[CPCAP_MAX_TEMP_LVL][2] = { 303 { 0x03ff, -40000 }, 304 { 0x03ff, -35000 }, 305 { 0x03ef, -30000 }, 306 { 0x03b2, -25000 }, 307 { 0x036c, -20000 }, 308 { 0x0320, -15000 }, 309 { 0x02d0, -10000 }, 310 { 0x027f, -5000 }, 311 { 0x022f, 0 }, 312 { 0x01e4, 5000 }, 313 { 0x019f, 10000 }, 314 { 0x0161, 15000 }, 315 { 0x012b, 20000 }, 316 { 0x00fc, 25000 }, 317 { 0x00d4, 30000 }, 318 { 0x00b2, 35000 }, 319 { 0x0095, 40000 }, 320 { 0x007d, 45000 }, 321 { 0x0069, 50000 }, 322 { 0x0059, 55000 }, 323 { 0x004b, 60000 }, 324 { 0x003f, 65000 }, 325 { 0x0036, 70000 }, 326 { 0x002e, 75000 }, 327 { 0x0027, 80000 }, 328 { 0x0022, 85000 }, 329 { 0x001d, 90000 }, 330 }; 331 332 #define CPCAP_CHAN(_type, _index, _address, _datasheet_name) { \ 333 .type = (_type), \ 334 .address = (_address), \ 335 .indexed = 1, \ 336 .channel = (_index), \ 337 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 338 BIT(IIO_CHAN_INFO_PROCESSED), \ 339 .scan_index = (_index), \ 340 .scan_type = { \ 341 .sign = 'u', \ 342 .realbits = 10, \ 343 .storagebits = 16, \ 344 .endianness = IIO_CPU, \ 345 }, \ 346 .datasheet_name = (_datasheet_name), \ 347 } 348 349 /* 350 * The datasheet names are from Motorola mapphone Linux kernel except 351 * for the last two which might be uncalibrated charge voltage and 352 * current. 353 */ 354 static const struct iio_chan_spec cpcap_adc_channels[] = { 355 /* Bank0 */ 356 CPCAP_CHAN(IIO_TEMP, 0, CPCAP_REG_ADCD0, "battdetb"), 357 CPCAP_CHAN(IIO_VOLTAGE, 1, CPCAP_REG_ADCD1, "battp"), 358 CPCAP_CHAN(IIO_VOLTAGE, 2, CPCAP_REG_ADCD2, "vbus"), 359 CPCAP_CHAN(IIO_TEMP, 3, CPCAP_REG_ADCD3, "ad3"), 360 CPCAP_CHAN(IIO_VOLTAGE, 4, CPCAP_REG_ADCD4, "ad4"), 361 CPCAP_CHAN(IIO_CURRENT, 5, CPCAP_REG_ADCD5, "chg_isense"), 362 CPCAP_CHAN(IIO_CURRENT, 6, CPCAP_REG_ADCD6, "batti"), 363 CPCAP_CHAN(IIO_VOLTAGE, 7, CPCAP_REG_ADCD7, "usb_id"), 364 365 /* Bank1 */ 366 CPCAP_CHAN(IIO_CURRENT, 8, CPCAP_REG_ADCD0, "ad8"), 367 CPCAP_CHAN(IIO_VOLTAGE, 9, CPCAP_REG_ADCD1, "ad9"), 368 CPCAP_CHAN(IIO_VOLTAGE, 10, CPCAP_REG_ADCD2, "licell"), 369 CPCAP_CHAN(IIO_VOLTAGE, 11, CPCAP_REG_ADCD3, "hv_battp"), 370 CPCAP_CHAN(IIO_VOLTAGE, 12, CPCAP_REG_ADCD4, "tsx1_ad12"), 371 CPCAP_CHAN(IIO_VOLTAGE, 13, CPCAP_REG_ADCD5, "tsx2_ad13"), 372 CPCAP_CHAN(IIO_VOLTAGE, 14, CPCAP_REG_ADCD6, "tsy1_ad14"), 373 CPCAP_CHAN(IIO_VOLTAGE, 15, CPCAP_REG_ADCD7, "tsy2_ad15"), 374 375 /* There are two registers with multiplexed functionality */ 376 CPCAP_CHAN(IIO_VOLTAGE, 16, CPCAP_REG_ADCD0, "chg_vsense"), 377 CPCAP_CHAN(IIO_CURRENT, 17, CPCAP_REG_ADCD1, "batti2"), 378 }; 379 380 static irqreturn_t cpcap_adc_irq_thread(int irq, void *data) 381 { 382 struct iio_dev *indio_dev = data; 383 struct cpcap_adc *ddata = iio_priv(indio_dev); 384 int error; 385 386 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, 387 CPCAP_BIT_ADTRIG_DIS, 388 CPCAP_BIT_ADTRIG_DIS); 389 if (error) 390 return IRQ_NONE; 391 392 ddata->done = true; 393 wake_up_interruptible(&ddata->wq_data_avail); 394 395 return IRQ_HANDLED; 396 } 397 398 /* ADC calibration functions */ 399 static void cpcap_adc_setup_calibrate(struct cpcap_adc *ddata, 400 enum cpcap_adc_channel chan) 401 { 402 unsigned int value = 0; 403 unsigned long timeout = jiffies + msecs_to_jiffies(3000); 404 int error; 405 406 if ((chan != CPCAP_ADC_CHG_ISENSE) && 407 (chan != CPCAP_ADC_BATTI)) 408 return; 409 410 value |= CPCAP_BIT_CAL_MODE | CPCAP_BIT_RAND0; 411 value |= ((chan << 4) & 412 (CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 | CPCAP_BIT_ADA0)); 413 414 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1, 415 CPCAP_BIT_CAL_MODE | CPCAP_BIT_ATOX | 416 CPCAP_BIT_ATO3 | CPCAP_BIT_ATO2 | 417 CPCAP_BIT_ATO1 | CPCAP_BIT_ATO0 | 418 CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 | 419 CPCAP_BIT_ADA0 | CPCAP_BIT_AD_SEL1 | 420 CPCAP_BIT_RAND1 | CPCAP_BIT_RAND0, 421 value); 422 if (error) 423 return; 424 425 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, 426 CPCAP_BIT_ATOX_PS_FACTOR | 427 CPCAP_BIT_ADC_PS_FACTOR1 | 428 CPCAP_BIT_ADC_PS_FACTOR0, 429 0); 430 if (error) 431 return; 432 433 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, 434 CPCAP_BIT_ADTRIG_DIS, 435 CPCAP_BIT_ADTRIG_DIS); 436 if (error) 437 return; 438 439 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, 440 CPCAP_BIT_ASC, 441 CPCAP_BIT_ASC); 442 if (error) 443 return; 444 445 do { 446 schedule_timeout_uninterruptible(1); 447 error = regmap_read(ddata->reg, CPCAP_REG_ADCC2, &value); 448 if (error) 449 return; 450 } while ((value & CPCAP_BIT_ASC) && time_before(jiffies, timeout)); 451 452 if (value & CPCAP_BIT_ASC) 453 dev_err(ddata->dev, 454 "Timeout waiting for calibration to complete\n"); 455 456 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1, 457 CPCAP_BIT_CAL_MODE, 0); 458 if (error) 459 return; 460 } 461 462 static int cpcap_adc_calibrate_one(struct cpcap_adc *ddata, 463 int channel, 464 u16 calibration_register, 465 int lower_threshold, 466 int upper_threshold) 467 { 468 unsigned int calibration_data[2]; 469 unsigned short cal_data_diff; 470 int i, error; 471 472 for (i = 0; i < CPCAP_ADC_MAX_RETRIES; i++) { 473 calibration_data[0] = 0; 474 calibration_data[1] = 0; 475 cal_data_diff = 0; 476 cpcap_adc_setup_calibrate(ddata, channel); 477 error = regmap_read(ddata->reg, calibration_register, 478 &calibration_data[0]); 479 if (error) 480 return error; 481 cpcap_adc_setup_calibrate(ddata, channel); 482 error = regmap_read(ddata->reg, calibration_register, 483 &calibration_data[1]); 484 if (error) 485 return error; 486 487 if (calibration_data[0] > calibration_data[1]) 488 cal_data_diff = 489 calibration_data[0] - calibration_data[1]; 490 else 491 cal_data_diff = 492 calibration_data[1] - calibration_data[0]; 493 494 if (((calibration_data[1] >= lower_threshold) && 495 (calibration_data[1] <= upper_threshold) && 496 (cal_data_diff <= ST_ADC_CALIBRATE_DIFF_THRESHOLD)) || 497 (ddata->vendor == CPCAP_VENDOR_TI)) { 498 bank_conversion[channel].cal_offset = 499 ((short)calibration_data[1] * -1) + 512; 500 dev_dbg(ddata->dev, "ch%i calibration complete: %i\n", 501 channel, bank_conversion[channel].cal_offset); 502 break; 503 } 504 usleep_range(5000, 10000); 505 } 506 507 return 0; 508 } 509 510 static int cpcap_adc_calibrate(struct cpcap_adc *ddata) 511 { 512 int error; 513 514 error = cpcap_adc_calibrate_one(ddata, CPCAP_ADC_CHG_ISENSE, 515 CPCAP_REG_ADCAL1, 516 ST_ADC_CAL_CHRGI_LOW_THRESHOLD, 517 ST_ADC_CAL_CHRGI_HIGH_THRESHOLD); 518 if (error) 519 return error; 520 521 error = cpcap_adc_calibrate_one(ddata, CPCAP_ADC_BATTI, 522 CPCAP_REG_ADCAL2, 523 ST_ADC_CAL_BATTI_LOW_THRESHOLD, 524 ST_ADC_CAL_BATTI_HIGH_THRESHOLD); 525 if (error) 526 return error; 527 528 return 0; 529 } 530 531 /* ADC setup, read and scale functions */ 532 static void cpcap_adc_setup_bank(struct cpcap_adc *ddata, 533 struct cpcap_adc_request *req) 534 { 535 const struct cpcap_adc_ato *ato = ddata->ato; 536 unsigned short value1 = 0; 537 unsigned short value2 = 0; 538 int error; 539 540 if (!ato) 541 return; 542 543 switch (req->channel) { 544 case CPCAP_ADC_AD8 ... CPCAP_ADC_TSY2_AD15: 545 value1 |= CPCAP_BIT_AD_SEL1; 546 break; 547 case CPCAP_ADC_BATTP_PI16 ... CPCAP_ADC_BATTI_PI17: 548 value1 |= CPCAP_BIT_RAND1; 549 default: 550 break; 551 } 552 553 switch (req->timing) { 554 case CPCAP_ADC_TIMING_IN: 555 value1 |= ato->ato_in; 556 value1 |= ato->atox_in; 557 value2 |= ato->adc_ps_factor_in; 558 value2 |= ato->atox_ps_factor_in; 559 break; 560 case CPCAP_ADC_TIMING_OUT: 561 value1 |= ato->ato_out; 562 value1 |= ato->atox_out; 563 value2 |= ato->adc_ps_factor_out; 564 value2 |= ato->atox_ps_factor_out; 565 break; 566 567 case CPCAP_ADC_TIMING_IMM: 568 default: 569 break; 570 } 571 572 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC1, 573 CPCAP_BIT_CAL_MODE | CPCAP_BIT_ATOX | 574 CPCAP_BIT_ATO3 | CPCAP_BIT_ATO2 | 575 CPCAP_BIT_ATO1 | CPCAP_BIT_ATO0 | 576 CPCAP_BIT_ADA2 | CPCAP_BIT_ADA1 | 577 CPCAP_BIT_ADA0 | CPCAP_BIT_AD_SEL1 | 578 CPCAP_BIT_RAND1 | CPCAP_BIT_RAND0, 579 value1); 580 if (error) 581 return; 582 583 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, 584 CPCAP_BIT_ATOX_PS_FACTOR | 585 CPCAP_BIT_ADC_PS_FACTOR1 | 586 CPCAP_BIT_ADC_PS_FACTOR0, 587 value2); 588 if (error) 589 return; 590 591 if (req->timing == CPCAP_ADC_TIMING_IMM) { 592 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, 593 CPCAP_BIT_ADTRIG_DIS, 594 CPCAP_BIT_ADTRIG_DIS); 595 if (error) 596 return; 597 598 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, 599 CPCAP_BIT_ASC, 600 CPCAP_BIT_ASC); 601 if (error) 602 return; 603 } else { 604 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, 605 CPCAP_BIT_ADTRIG_ONESHOT, 606 CPCAP_BIT_ADTRIG_ONESHOT); 607 if (error) 608 return; 609 610 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, 611 CPCAP_BIT_ADTRIG_DIS, 0); 612 if (error) 613 return; 614 } 615 } 616 617 /* 618 * Occasionally the ADC does not seem to start and there will be no 619 * interrupt. Let's re-init interrupt to prevent the ADC from hanging 620 * for the next request. It is unclear why this happens, but the next 621 * request will usually work after doing this. 622 */ 623 static void cpcap_adc_quirk_reset_lost_irq(struct cpcap_adc *ddata) 624 { 625 int error; 626 627 dev_info(ddata->dev, "lost ADC irq, attempting to reinit\n"); 628 disable_irq(ddata->irq); 629 error = regmap_update_bits(ddata->reg, CPCAP_REG_ADCC2, 630 CPCAP_BIT_ADTRIG_DIS, 631 CPCAP_BIT_ADTRIG_DIS); 632 if (error) 633 dev_warn(ddata->dev, "%s reset failed: %i\n", 634 __func__, error); 635 enable_irq(ddata->irq); 636 } 637 638 static int cpcap_adc_start_bank(struct cpcap_adc *ddata, 639 struct cpcap_adc_request *req) 640 { 641 int i, error; 642 643 req->timing = CPCAP_ADC_TIMING_IMM; 644 ddata->done = false; 645 646 for (i = 0; i < CPCAP_ADC_MAX_RETRIES; i++) { 647 cpcap_adc_setup_bank(ddata, req); 648 error = wait_event_interruptible_timeout(ddata->wq_data_avail, 649 ddata->done, 650 msecs_to_jiffies(50)); 651 if (error > 0) 652 return 0; 653 654 if (error == 0) { 655 cpcap_adc_quirk_reset_lost_irq(ddata); 656 error = -ETIMEDOUT; 657 continue; 658 } 659 660 if (error < 0) 661 return error; 662 } 663 664 return error; 665 } 666 667 static void cpcap_adc_phase(struct cpcap_adc_request *req) 668 { 669 const struct cpcap_adc_conversion_tbl *conv_tbl = req->conv_tbl; 670 const struct cpcap_adc_phasing_tbl *phase_tbl = req->phase_tbl; 671 int index = req->channel; 672 673 /* Remuxed channels 16 and 17 use BATTP and BATTI entries */ 674 switch (req->channel) { 675 case CPCAP_ADC_BATTP: 676 case CPCAP_ADC_BATTP_PI16: 677 index = req->bank_index; 678 req->result -= phase_tbl[index].offset; 679 req->result -= CPCAP_FOUR_POINT_TWO_ADC; 680 req->result *= phase_tbl[index].multiplier; 681 if (phase_tbl[index].divider == 0) 682 return; 683 req->result /= phase_tbl[index].divider; 684 req->result += CPCAP_FOUR_POINT_TWO_ADC; 685 break; 686 case CPCAP_ADC_BATTI_PI17: 687 index = req->bank_index; 688 /* fallthrough */ 689 default: 690 req->result += conv_tbl[index].cal_offset; 691 req->result += conv_tbl[index].align_offset; 692 req->result *= phase_tbl[index].multiplier; 693 if (phase_tbl[index].divider == 0) 694 return; 695 req->result /= phase_tbl[index].divider; 696 req->result += phase_tbl[index].offset; 697 break; 698 } 699 700 if (req->result < phase_tbl[index].min) 701 req->result = phase_tbl[index].min; 702 else if (req->result > phase_tbl[index].max) 703 req->result = phase_tbl[index].max; 704 } 705 706 /* Looks up temperatures in a table and calculates averages if needed */ 707 static int cpcap_adc_table_to_millicelcius(unsigned short value) 708 { 709 int i, result = 0, alpha; 710 711 if (value <= temp_map[CPCAP_MAX_TEMP_LVL - 1][0]) 712 return temp_map[CPCAP_MAX_TEMP_LVL - 1][1]; 713 714 if (value >= temp_map[0][0]) 715 return temp_map[0][1]; 716 717 for (i = 0; i < CPCAP_MAX_TEMP_LVL - 1; i++) { 718 if ((value <= temp_map[i][0]) && 719 (value >= temp_map[i + 1][0])) { 720 if (value == temp_map[i][0]) { 721 result = temp_map[i][1]; 722 } else if (value == temp_map[i + 1][0]) { 723 result = temp_map[i + 1][1]; 724 } else { 725 alpha = ((value - temp_map[i][0]) * 1000) / 726 (temp_map[i + 1][0] - temp_map[i][0]); 727 728 result = temp_map[i][1] + 729 ((alpha * (temp_map[i + 1][1] - 730 temp_map[i][1])) / 1000); 731 } 732 break; 733 } 734 } 735 736 return result; 737 } 738 739 static void cpcap_adc_convert(struct cpcap_adc_request *req) 740 { 741 const struct cpcap_adc_conversion_tbl *conv_tbl = req->conv_tbl; 742 int index = req->channel; 743 744 /* Remuxed channels 16 and 17 use BATTP and BATTI entries */ 745 switch (req->channel) { 746 case CPCAP_ADC_BATTP_PI16: 747 index = CPCAP_ADC_BATTP; 748 break; 749 case CPCAP_ADC_BATTI_PI17: 750 index = CPCAP_ADC_BATTI; 751 break; 752 default: 753 break; 754 } 755 756 /* No conversion for raw channels */ 757 if (conv_tbl[index].conv_type == IIO_CHAN_INFO_RAW) 758 return; 759 760 /* Temperatures use a lookup table instead of conversion table */ 761 if ((req->channel == CPCAP_ADC_AD0_BATTDETB) || 762 (req->channel == CPCAP_ADC_AD3)) { 763 req->result = 764 cpcap_adc_table_to_millicelcius(req->result); 765 766 return; 767 } 768 769 /* All processed channels use a conversion table */ 770 req->result *= conv_tbl[index].multiplier; 771 if (conv_tbl[index].divider == 0) 772 return; 773 req->result /= conv_tbl[index].divider; 774 req->result += conv_tbl[index].conv_offset; 775 } 776 777 /* 778 * REVISIT: Check if timed sampling can use multiple channels at the 779 * same time. If not, replace channel_mask with just channel. 780 */ 781 static int cpcap_adc_read_bank_scaled(struct cpcap_adc *ddata, 782 struct cpcap_adc_request *req) 783 { 784 int calibration_data, error, addr; 785 786 if (ddata->vendor == CPCAP_VENDOR_TI) { 787 error = regmap_read(ddata->reg, CPCAP_REG_ADCAL1, 788 &calibration_data); 789 if (error) 790 return error; 791 bank_conversion[CPCAP_ADC_CHG_ISENSE].cal_offset = 792 ((short)calibration_data * -1) + 512; 793 794 error = regmap_read(ddata->reg, CPCAP_REG_ADCAL2, 795 &calibration_data); 796 if (error) 797 return error; 798 bank_conversion[CPCAP_ADC_BATTI].cal_offset = 799 ((short)calibration_data * -1) + 512; 800 } 801 802 addr = CPCAP_REG_ADCD0 + req->bank_index * 4; 803 804 error = regmap_read(ddata->reg, addr, &req->result); 805 if (error) 806 return error; 807 808 req->result &= 0x3ff; 809 cpcap_adc_phase(req); 810 cpcap_adc_convert(req); 811 812 return 0; 813 } 814 815 static int cpcap_adc_init_request(struct cpcap_adc_request *req, 816 int channel) 817 { 818 req->channel = channel; 819 req->phase_tbl = bank_phasing; 820 req->conv_tbl = bank_conversion; 821 822 switch (channel) { 823 case CPCAP_ADC_AD0_BATTDETB ... CPCAP_ADC_USB_ID: 824 req->bank_index = channel; 825 break; 826 case CPCAP_ADC_AD8 ... CPCAP_ADC_TSY2_AD15: 827 req->bank_index = channel - 8; 828 break; 829 case CPCAP_ADC_BATTP_PI16: 830 req->bank_index = CPCAP_ADC_BATTP; 831 break; 832 case CPCAP_ADC_BATTI_PI17: 833 req->bank_index = CPCAP_ADC_BATTI; 834 break; 835 default: 836 return -EINVAL; 837 } 838 839 return 0; 840 } 841 842 static int cpcap_adc_read(struct iio_dev *indio_dev, 843 struct iio_chan_spec const *chan, 844 int *val, int *val2, long mask) 845 { 846 struct cpcap_adc *ddata = iio_priv(indio_dev); 847 struct cpcap_adc_request req; 848 int error; 849 850 error = cpcap_adc_init_request(&req, chan->channel); 851 if (error) 852 return error; 853 854 switch (mask) { 855 case IIO_CHAN_INFO_RAW: 856 mutex_lock(&ddata->lock); 857 error = cpcap_adc_start_bank(ddata, &req); 858 if (error) 859 goto err_unlock; 860 error = regmap_read(ddata->reg, chan->address, val); 861 if (error) 862 goto err_unlock; 863 mutex_unlock(&ddata->lock); 864 break; 865 case IIO_CHAN_INFO_PROCESSED: 866 mutex_lock(&ddata->lock); 867 error = cpcap_adc_start_bank(ddata, &req); 868 if (error) 869 goto err_unlock; 870 error = cpcap_adc_read_bank_scaled(ddata, &req); 871 if (error) 872 goto err_unlock; 873 mutex_unlock(&ddata->lock); 874 *val = req.result; 875 break; 876 default: 877 return -EINVAL; 878 } 879 880 return IIO_VAL_INT; 881 882 err_unlock: 883 mutex_unlock(&ddata->lock); 884 dev_err(ddata->dev, "error reading ADC: %i\n", error); 885 886 return error; 887 } 888 889 static const struct iio_info cpcap_adc_info = { 890 .read_raw = &cpcap_adc_read, 891 .driver_module = THIS_MODULE, 892 }; 893 894 /* 895 * Configuration for Motorola mapphone series such as droid 4. 896 * Copied from the Motorola mapphone kernel tree. 897 */ 898 static const struct cpcap_adc_ato mapphone_adc = { 899 .ato_in = 0x0480, 900 .atox_in = 0, 901 .adc_ps_factor_in = 0x0200, 902 .atox_ps_factor_in = 0, 903 .ato_out = 0, 904 .atox_out = 0, 905 .adc_ps_factor_out = 0, 906 .atox_ps_factor_out = 0, 907 }; 908 909 static const struct of_device_id cpcap_adc_id_table[] = { 910 { 911 .compatible = "motorola,cpcap-adc", 912 }, 913 { 914 .compatible = "motorola,mapphone-cpcap-adc", 915 .data = &mapphone_adc, 916 }, 917 { /* sentinel */ }, 918 }; 919 MODULE_DEVICE_TABLE(of, cpcap_adc_id_table); 920 921 static int cpcap_adc_probe(struct platform_device *pdev) 922 { 923 const struct of_device_id *match; 924 struct cpcap_adc *ddata; 925 struct iio_dev *indio_dev; 926 int error; 927 928 match = of_match_device(of_match_ptr(cpcap_adc_id_table), 929 &pdev->dev); 930 if (!match) 931 return -EINVAL; 932 933 if (!match->data) { 934 dev_err(&pdev->dev, "no configuration data found\n"); 935 936 return -ENODEV; 937 } 938 939 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*ddata)); 940 if (!indio_dev) { 941 dev_err(&pdev->dev, "failed to allocate iio device\n"); 942 943 return -ENOMEM; 944 } 945 ddata = iio_priv(indio_dev); 946 ddata->ato = match->data; 947 ddata->dev = &pdev->dev; 948 949 mutex_init(&ddata->lock); 950 init_waitqueue_head(&ddata->wq_data_avail); 951 952 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; 953 indio_dev->dev.parent = &pdev->dev; 954 indio_dev->dev.of_node = pdev->dev.of_node; 955 indio_dev->channels = cpcap_adc_channels; 956 indio_dev->num_channels = ARRAY_SIZE(cpcap_adc_channels); 957 indio_dev->name = dev_name(&pdev->dev); 958 indio_dev->info = &cpcap_adc_info; 959 960 ddata->reg = dev_get_regmap(pdev->dev.parent, NULL); 961 if (!ddata->reg) 962 return -ENODEV; 963 964 error = cpcap_get_vendor(ddata->dev, ddata->reg, &ddata->vendor); 965 if (error) 966 return error; 967 968 platform_set_drvdata(pdev, indio_dev); 969 970 ddata->irq = platform_get_irq_byname(pdev, "adcdone"); 971 if (!ddata->irq) 972 return -ENODEV; 973 974 error = devm_request_threaded_irq(&pdev->dev, ddata->irq, NULL, 975 cpcap_adc_irq_thread, 976 IRQF_TRIGGER_NONE, 977 "cpcap-adc", indio_dev); 978 if (error) { 979 dev_err(&pdev->dev, "could not get irq: %i\n", 980 error); 981 982 return error; 983 } 984 985 error = cpcap_adc_calibrate(ddata); 986 if (error) 987 return error; 988 989 dev_info(&pdev->dev, "CPCAP ADC device probed\n"); 990 991 return devm_iio_device_register(&pdev->dev, indio_dev); 992 } 993 994 static struct platform_driver cpcap_adc_driver = { 995 .driver = { 996 .name = "cpcap_adc", 997 .of_match_table = of_match_ptr(cpcap_adc_id_table), 998 }, 999 .probe = cpcap_adc_probe, 1000 }; 1001 1002 module_platform_driver(cpcap_adc_driver); 1003 1004 MODULE_ALIAS("platform:cpcap_adc"); 1005 MODULE_DESCRIPTION("CPCAP ADC driver"); 1006 MODULE_AUTHOR("Tony Lindgren <tony@atomide.com"); 1007 MODULE_LICENSE("GPL v2"); 1008