1 /* 2 * Marvell Berlin2 ADC driver 3 * 4 * Copyright (C) 2015 Marvell Technology Group Ltd. 5 * 6 * Antoine Tenart <antoine.tenart@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2. This program is licensed "as is" without any 10 * warranty of any kind, whether express or implied. 11 */ 12 13 #include <linux/iio/iio.h> 14 #include <linux/iio/driver.h> 15 #include <linux/iio/machine.h> 16 #include <linux/interrupt.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/slab.h> 21 #include <linux/mfd/syscon.h> 22 #include <linux/regmap.h> 23 #include <linux/sched.h> 24 #include <linux/wait.h> 25 26 #define BERLIN2_SM_CTRL 0x14 27 #define BERLIN2_SM_CTRL_SM_SOC_INT BIT(1) 28 #define BERLIN2_SM_CTRL_SOC_SM_INT BIT(2) 29 #define BERLIN2_SM_CTRL_ADC_SEL(x) (BIT(x) << 5) /* 0-15 */ 30 #define BERLIN2_SM_CTRL_ADC_SEL_MASK (0xf << 5) 31 #define BERLIN2_SM_CTRL_ADC_POWER BIT(9) 32 #define BERLIN2_SM_CTRL_ADC_CLKSEL_DIV2 (0x0 << 10) 33 #define BERLIN2_SM_CTRL_ADC_CLKSEL_DIV3 (0x1 << 10) 34 #define BERLIN2_SM_CTRL_ADC_CLKSEL_DIV4 (0x2 << 10) 35 #define BERLIN2_SM_CTRL_ADC_CLKSEL_DIV8 (0x3 << 10) 36 #define BERLIN2_SM_CTRL_ADC_CLKSEL_MASK (0x3 << 10) 37 #define BERLIN2_SM_CTRL_ADC_START BIT(12) 38 #define BERLIN2_SM_CTRL_ADC_RESET BIT(13) 39 #define BERLIN2_SM_CTRL_ADC_BANDGAP_RDY BIT(14) 40 #define BERLIN2_SM_CTRL_ADC_CONT_SINGLE (0x0 << 15) 41 #define BERLIN2_SM_CTRL_ADC_CONT_CONTINUOUS (0x1 << 15) 42 #define BERLIN2_SM_CTRL_ADC_BUFFER_EN BIT(16) 43 #define BERLIN2_SM_CTRL_ADC_VREF_EXT (0x0 << 17) 44 #define BERLIN2_SM_CTRL_ADC_VREF_INT (0x1 << 17) 45 #define BERLIN2_SM_CTRL_ADC_ROTATE BIT(19) 46 #define BERLIN2_SM_CTRL_TSEN_EN BIT(20) 47 #define BERLIN2_SM_CTRL_TSEN_CLK_SEL_125 (0x0 << 21) /* 1.25 MHz */ 48 #define BERLIN2_SM_CTRL_TSEN_CLK_SEL_250 (0x1 << 21) /* 2.5 MHz */ 49 #define BERLIN2_SM_CTRL_TSEN_MODE_0_125 (0x0 << 22) /* 0-125 C */ 50 #define BERLIN2_SM_CTRL_TSEN_MODE_10_50 (0x1 << 22) /* 10-50 C */ 51 #define BERLIN2_SM_CTRL_TSEN_RESET BIT(29) 52 #define BERLIN2_SM_ADC_DATA 0x20 53 #define BERLIN2_SM_ADC_MASK 0x3ff 54 #define BERLIN2_SM_ADC_STATUS 0x1c 55 #define BERLIN2_SM_ADC_STATUS_DATA_RDY(x) BIT(x) /* 0-15 */ 56 #define BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK 0xf 57 #define BERLIN2_SM_ADC_STATUS_INT_EN(x) (BIT(x) << 16) /* 0-15 */ 58 #define BERLIN2_SM_ADC_STATUS_INT_EN_MASK (0xf << 16) 59 #define BERLIN2_SM_TSEN_STATUS 0x24 60 #define BERLIN2_SM_TSEN_STATUS_DATA_RDY BIT(0) 61 #define BERLIN2_SM_TSEN_STATUS_INT_EN BIT(1) 62 #define BERLIN2_SM_TSEN_DATA 0x28 63 #define BERLIN2_SM_TSEN_MASK 0xfff 64 #define BERLIN2_SM_TSEN_CTRL 0x74 65 #define BERLIN2_SM_TSEN_CTRL_START BIT(8) 66 #define BERLIN2_SM_TSEN_CTRL_SETTLING_4 (0x0 << 21) /* 4 us */ 67 #define BERLIN2_SM_TSEN_CTRL_SETTLING_12 (0x1 << 21) /* 12 us */ 68 #define BERLIN2_SM_TSEN_CTRL_SETTLING_MASK (0x1 << 21) 69 #define BERLIN2_SM_TSEN_CTRL_TRIM(x) ((x) << 22) 70 #define BERLIN2_SM_TSEN_CTRL_TRIM_MASK (0xf << 22) 71 72 struct berlin2_adc_priv { 73 struct regmap *regmap; 74 struct mutex lock; 75 wait_queue_head_t wq; 76 bool data_available; 77 int data; 78 }; 79 80 #define BERLIN2_ADC_CHANNEL(n, t) \ 81 { \ 82 .channel = n, \ 83 .datasheet_name = "channel"#n, \ 84 .type = t, \ 85 .indexed = 1, \ 86 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 87 } 88 89 static struct iio_chan_spec berlin2_adc_channels[] = { 90 BERLIN2_ADC_CHANNEL(0, IIO_VOLTAGE), /* external input */ 91 BERLIN2_ADC_CHANNEL(1, IIO_VOLTAGE), /* external input */ 92 BERLIN2_ADC_CHANNEL(2, IIO_VOLTAGE), /* external input */ 93 BERLIN2_ADC_CHANNEL(3, IIO_VOLTAGE), /* external input */ 94 BERLIN2_ADC_CHANNEL(4, IIO_VOLTAGE), /* reserved */ 95 BERLIN2_ADC_CHANNEL(5, IIO_VOLTAGE), /* reserved */ 96 { /* temperature sensor */ 97 .channel = 6, 98 .datasheet_name = "channel6", 99 .type = IIO_TEMP, 100 .indexed = 0, 101 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), 102 }, 103 BERLIN2_ADC_CHANNEL(7, IIO_VOLTAGE), /* reserved */ 104 IIO_CHAN_SOFT_TIMESTAMP(8), /* timestamp */ 105 }; 106 #define BERLIN2_N_CHANNELS ARRAY_SIZE(berlin2_adc_channels) 107 108 static int berlin2_adc_read(struct iio_dev *indio_dev, int channel) 109 { 110 struct berlin2_adc_priv *priv = iio_priv(indio_dev); 111 int data, ret; 112 113 mutex_lock(&priv->lock); 114 115 /* Configure the ADC */ 116 regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL, 117 BERLIN2_SM_CTRL_ADC_RESET | BERLIN2_SM_CTRL_ADC_SEL_MASK 118 | BERLIN2_SM_CTRL_ADC_START, 119 BERLIN2_SM_CTRL_ADC_SEL(channel) | BERLIN2_SM_CTRL_ADC_START); 120 121 ret = wait_event_interruptible_timeout(priv->wq, priv->data_available, 122 msecs_to_jiffies(1000)); 123 124 /* Disable the interrupts */ 125 regmap_update_bits(priv->regmap, BERLIN2_SM_ADC_STATUS, 126 BERLIN2_SM_ADC_STATUS_INT_EN(channel), 0); 127 128 if (ret == 0) 129 ret = -ETIMEDOUT; 130 if (ret < 0) { 131 mutex_unlock(&priv->lock); 132 return ret; 133 } 134 135 regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL, 136 BERLIN2_SM_CTRL_ADC_START, 0); 137 138 data = priv->data; 139 priv->data_available = false; 140 141 mutex_unlock(&priv->lock); 142 143 return data; 144 } 145 146 static int berlin2_adc_tsen_read(struct iio_dev *indio_dev) 147 { 148 struct berlin2_adc_priv *priv = iio_priv(indio_dev); 149 int data, ret; 150 151 mutex_lock(&priv->lock); 152 153 /* Configure the ADC */ 154 regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL, 155 BERLIN2_SM_CTRL_TSEN_RESET | BERLIN2_SM_CTRL_ADC_ROTATE, 156 BERLIN2_SM_CTRL_ADC_ROTATE); 157 158 /* Configure the temperature sensor */ 159 regmap_update_bits(priv->regmap, BERLIN2_SM_TSEN_CTRL, 160 BERLIN2_SM_TSEN_CTRL_TRIM_MASK | BERLIN2_SM_TSEN_CTRL_SETTLING_MASK 161 | BERLIN2_SM_TSEN_CTRL_START, 162 BERLIN2_SM_TSEN_CTRL_TRIM(3) | BERLIN2_SM_TSEN_CTRL_SETTLING_12 163 | BERLIN2_SM_TSEN_CTRL_START); 164 165 ret = wait_event_interruptible_timeout(priv->wq, priv->data_available, 166 msecs_to_jiffies(1000)); 167 168 /* Disable interrupts */ 169 regmap_update_bits(priv->regmap, BERLIN2_SM_TSEN_STATUS, 170 BERLIN2_SM_TSEN_STATUS_INT_EN, 0); 171 172 if (ret == 0) 173 ret = -ETIMEDOUT; 174 if (ret < 0) { 175 mutex_unlock(&priv->lock); 176 return ret; 177 } 178 179 regmap_update_bits(priv->regmap, BERLIN2_SM_TSEN_CTRL, 180 BERLIN2_SM_TSEN_CTRL_START, 0); 181 182 data = priv->data; 183 priv->data_available = false; 184 185 mutex_unlock(&priv->lock); 186 187 return data; 188 } 189 190 static int berlin2_adc_read_raw(struct iio_dev *indio_dev, 191 struct iio_chan_spec const *chan, int *val, int *val2, 192 long mask) 193 { 194 struct berlin2_adc_priv *priv = iio_priv(indio_dev); 195 int temp; 196 197 switch (mask) { 198 case IIO_CHAN_INFO_RAW: 199 if (chan->type != IIO_VOLTAGE) 200 return -EINVAL; 201 202 /* Enable the interrupts */ 203 regmap_write(priv->regmap, BERLIN2_SM_ADC_STATUS, 204 BERLIN2_SM_ADC_STATUS_INT_EN(chan->channel)); 205 206 *val = berlin2_adc_read(indio_dev, chan->channel); 207 if (*val < 0) 208 return *val; 209 210 return IIO_VAL_INT; 211 case IIO_CHAN_INFO_PROCESSED: 212 if (chan->type != IIO_TEMP) 213 return -EINVAL; 214 215 /* Enable interrupts */ 216 regmap_write(priv->regmap, BERLIN2_SM_TSEN_STATUS, 217 BERLIN2_SM_TSEN_STATUS_INT_EN); 218 219 temp = berlin2_adc_tsen_read(indio_dev); 220 if (temp < 0) 221 return temp; 222 223 if (temp > 2047) 224 temp = -(4096 - temp); 225 226 /* Convert to milli Celsius */ 227 *val = ((temp * 100000) / 264 - 270000); 228 return IIO_VAL_INT; 229 default: 230 break; 231 } 232 233 return -EINVAL; 234 } 235 236 static irqreturn_t berlin2_adc_irq(int irq, void *private) 237 { 238 struct berlin2_adc_priv *priv = iio_priv(private); 239 unsigned val; 240 241 regmap_read(priv->regmap, BERLIN2_SM_ADC_STATUS, &val); 242 if (val & BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK) { 243 regmap_read(priv->regmap, BERLIN2_SM_ADC_DATA, &priv->data); 244 priv->data &= BERLIN2_SM_ADC_MASK; 245 246 val &= ~BERLIN2_SM_ADC_STATUS_DATA_RDY_MASK; 247 regmap_write(priv->regmap, BERLIN2_SM_ADC_STATUS, val); 248 249 priv->data_available = true; 250 wake_up_interruptible(&priv->wq); 251 } 252 253 return IRQ_HANDLED; 254 } 255 256 static irqreturn_t berlin2_adc_tsen_irq(int irq, void *private) 257 { 258 struct berlin2_adc_priv *priv = iio_priv(private); 259 unsigned val; 260 261 regmap_read(priv->regmap, BERLIN2_SM_TSEN_STATUS, &val); 262 if (val & BERLIN2_SM_TSEN_STATUS_DATA_RDY) { 263 regmap_read(priv->regmap, BERLIN2_SM_TSEN_DATA, &priv->data); 264 priv->data &= BERLIN2_SM_TSEN_MASK; 265 266 val &= ~BERLIN2_SM_TSEN_STATUS_DATA_RDY; 267 regmap_write(priv->regmap, BERLIN2_SM_TSEN_STATUS, val); 268 269 priv->data_available = true; 270 wake_up_interruptible(&priv->wq); 271 } 272 273 return IRQ_HANDLED; 274 } 275 276 static const struct iio_info berlin2_adc_info = { 277 .driver_module = THIS_MODULE, 278 .read_raw = berlin2_adc_read_raw, 279 }; 280 281 static int berlin2_adc_probe(struct platform_device *pdev) 282 { 283 struct iio_dev *indio_dev; 284 struct berlin2_adc_priv *priv; 285 struct device_node *parent_np = of_get_parent(pdev->dev.of_node); 286 int irq, tsen_irq; 287 int ret; 288 289 indio_dev = devm_iio_device_alloc(&pdev->dev, 290 sizeof(struct berlin2_adc_priv)); 291 if (!indio_dev) 292 return -ENOMEM; 293 294 priv = iio_priv(indio_dev); 295 platform_set_drvdata(pdev, indio_dev); 296 297 priv->regmap = syscon_node_to_regmap(parent_np); 298 of_node_put(parent_np); 299 if (IS_ERR(priv->regmap)) 300 return PTR_ERR(priv->regmap); 301 302 irq = platform_get_irq_byname(pdev, "adc"); 303 if (irq < 0) 304 return -ENODEV; 305 306 tsen_irq = platform_get_irq_byname(pdev, "tsen"); 307 if (tsen_irq < 0) 308 return -ENODEV; 309 310 ret = devm_request_irq(&pdev->dev, irq, berlin2_adc_irq, 0, 311 pdev->dev.driver->name, indio_dev); 312 if (ret) 313 return ret; 314 315 ret = devm_request_irq(&pdev->dev, tsen_irq, berlin2_adc_tsen_irq, 316 0, pdev->dev.driver->name, indio_dev); 317 if (ret) 318 return ret; 319 320 init_waitqueue_head(&priv->wq); 321 mutex_init(&priv->lock); 322 323 indio_dev->dev.parent = &pdev->dev; 324 indio_dev->name = dev_name(&pdev->dev); 325 indio_dev->modes = INDIO_DIRECT_MODE; 326 indio_dev->info = &berlin2_adc_info; 327 328 indio_dev->num_channels = BERLIN2_N_CHANNELS; 329 indio_dev->channels = berlin2_adc_channels; 330 331 /* Power up the ADC */ 332 regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL, 333 BERLIN2_SM_CTRL_ADC_POWER, BERLIN2_SM_CTRL_ADC_POWER); 334 335 ret = iio_device_register(indio_dev); 336 if (ret) { 337 /* Power down the ADC */ 338 regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL, 339 BERLIN2_SM_CTRL_ADC_POWER, 0); 340 return ret; 341 } 342 343 return 0; 344 } 345 346 static int berlin2_adc_remove(struct platform_device *pdev) 347 { 348 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 349 struct berlin2_adc_priv *priv = iio_priv(indio_dev); 350 351 iio_device_unregister(indio_dev); 352 353 /* Power down the ADC */ 354 regmap_update_bits(priv->regmap, BERLIN2_SM_CTRL, 355 BERLIN2_SM_CTRL_ADC_POWER, 0); 356 357 return 0; 358 } 359 360 static const struct of_device_id berlin2_adc_match[] = { 361 { .compatible = "marvell,berlin2-adc", }, 362 { }, 363 }; 364 MODULE_DEVICE_TABLE(of, berlin2_adc_match); 365 366 static struct platform_driver berlin2_adc_driver = { 367 .driver = { 368 .name = "berlin2-adc", 369 .of_match_table = berlin2_adc_match, 370 }, 371 .probe = berlin2_adc_probe, 372 .remove = berlin2_adc_remove, 373 }; 374 module_platform_driver(berlin2_adc_driver); 375 376 MODULE_AUTHOR("Antoine Tenart <antoine.tenart@free-electrons.com>"); 377 MODULE_DESCRIPTION("Marvell Berlin2 ADC driver"); 378 MODULE_LICENSE("GPL v2"); 379