1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for the ADC present in the Atmel AT91 evaluation boards. 4 * 5 * Copyright 2011 Free Electrons 6 */ 7 8 #include <linux/bitmap.h> 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/err.h> 12 #include <linux/io.h> 13 #include <linux/input.h> 14 #include <linux/interrupt.h> 15 #include <linux/jiffies.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_device.h> 20 #include <linux/platform_device.h> 21 #include <linux/sched.h> 22 #include <linux/slab.h> 23 #include <linux/wait.h> 24 25 #include <linux/iio/iio.h> 26 #include <linux/iio/buffer.h> 27 #include <linux/iio/trigger.h> 28 #include <linux/iio/trigger_consumer.h> 29 #include <linux/iio/triggered_buffer.h> 30 #include <linux/pinctrl/consumer.h> 31 32 /* Registers */ 33 #define AT91_ADC_CR 0x00 /* Control Register */ 34 #define AT91_ADC_SWRST (1 << 0) /* Software Reset */ 35 #define AT91_ADC_START (1 << 1) /* Start Conversion */ 36 37 #define AT91_ADC_MR 0x04 /* Mode Register */ 38 #define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */ 39 #define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */ 40 #define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */ 41 #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */ 42 #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */ 43 #define AT91_ADC_TRGSEL_TC0 (0 << 1) 44 #define AT91_ADC_TRGSEL_TC1 (1 << 1) 45 #define AT91_ADC_TRGSEL_TC2 (2 << 1) 46 #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1) 47 #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */ 48 #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */ 49 #define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */ 50 #define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */ 51 #define AT91_ADC_PRESCAL_9G45 (0xff << 8) 52 #define AT91_ADC_PRESCAL_(x) ((x) << 8) 53 #define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */ 54 #define AT91_ADC_STARTUP_9G45 (0x7f << 16) 55 #define AT91_ADC_STARTUP_9X5 (0xf << 16) 56 #define AT91_ADC_STARTUP_(x) ((x) << 16) 57 #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */ 58 #define AT91_ADC_SHTIM_(x) ((x) << 24) 59 #define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */ 60 #define AT91_ADC_PENDBC_(x) ((x) << 28) 61 62 #define AT91_ADC_TSR 0x0C 63 #define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */ 64 #define AT91_ADC_TSR_SHTIM_(x) ((x) << 24) 65 66 #define AT91_ADC_CHER 0x10 /* Channel Enable Register */ 67 #define AT91_ADC_CHDR 0x14 /* Channel Disable Register */ 68 #define AT91_ADC_CHSR 0x18 /* Channel Status Register */ 69 #define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */ 70 71 #define AT91_ADC_SR 0x1C /* Status Register */ 72 #define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */ 73 #define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */ 74 #define AT91_ADC_DRDY (1 << 16) /* Data Ready */ 75 #define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */ 76 #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */ 77 #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */ 78 79 #define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */ 80 #define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */ 81 82 #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */ 83 #define AT91_ADC_LDATA (0x3ff) 84 85 #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */ 86 #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */ 87 #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */ 88 #define AT91RL_ADC_IER_PEN (1 << 20) 89 #define AT91RL_ADC_IER_NOPEN (1 << 21) 90 #define AT91_ADC_IER_PEN (1 << 29) 91 #define AT91_ADC_IER_NOPEN (1 << 30) 92 #define AT91_ADC_IER_XRDY (1 << 20) 93 #define AT91_ADC_IER_YRDY (1 << 21) 94 #define AT91_ADC_IER_PRDY (1 << 22) 95 #define AT91_ADC_ISR_PENS (1 << 31) 96 97 #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */ 98 #define AT91_ADC_DATA (0x3ff) 99 100 #define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */ 101 102 #define AT91_ADC_ACR 0x94 /* Analog Control Register */ 103 #define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */ 104 105 #define AT91_ADC_TSMR 0xB0 106 #define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */ 107 #define AT91_ADC_TSMR_TSMODE_NONE (0 << 0) 108 #define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0) 109 #define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0) 110 #define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0) 111 #define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */ 112 #define AT91_ADC_TSMR_TSAV_(x) ((x) << 4) 113 #define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */ 114 #define AT91_ADC_TSMR_SCTIM_(x) ((x) << 16) 115 #define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */ 116 #define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28) 117 #define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */ 118 #define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */ 119 #define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */ 120 121 #define AT91_ADC_TSXPOSR 0xB4 122 #define AT91_ADC_TSYPOSR 0xB8 123 #define AT91_ADC_TSPRESSR 0xBC 124 125 #define AT91_ADC_TRGR_9260 AT91_ADC_MR 126 #define AT91_ADC_TRGR_9G45 0x08 127 #define AT91_ADC_TRGR_9X5 0xC0 128 129 /* Trigger Register bit field */ 130 #define AT91_ADC_TRGR_TRGPER (0xffff << 16) 131 #define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16) 132 #define AT91_ADC_TRGR_TRGMOD (0x7 << 0) 133 #define AT91_ADC_TRGR_NONE (0 << 0) 134 #define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0) 135 136 #define AT91_ADC_CHAN(st, ch) \ 137 (st->registers->channel_base + (ch * 4)) 138 #define at91_adc_readl(st, reg) \ 139 (readl_relaxed(st->reg_base + reg)) 140 #define at91_adc_writel(st, reg, val) \ 141 (writel_relaxed(val, st->reg_base + reg)) 142 143 #define DRIVER_NAME "at91_adc" 144 #define MAX_POS_BITS 12 145 146 #define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */ 147 #define TOUCH_PEN_DETECT_DEBOUNCE_US 200 148 149 #define MAX_RLPOS_BITS 10 150 #define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */ 151 #define TOUCH_SHTIM 0xa 152 #define TOUCH_SCTIM_US 10 /* 10us for the Touchscreen Switches Closure Time */ 153 154 enum atmel_adc_ts_type { 155 ATMEL_ADC_TOUCHSCREEN_NONE = 0, 156 ATMEL_ADC_TOUCHSCREEN_4WIRE = 4, 157 ATMEL_ADC_TOUCHSCREEN_5WIRE = 5, 158 }; 159 160 /** 161 * struct at91_adc_trigger - description of triggers 162 * @name: name of the trigger advertised to the user 163 * @value: value to set in the ADC's trigger setup register 164 * to enable the trigger 165 * @is_external: Does the trigger rely on an external pin? 166 */ 167 struct at91_adc_trigger { 168 const char *name; 169 u8 value; 170 bool is_external; 171 }; 172 173 /** 174 * struct at91_adc_reg_desc - Various informations relative to registers 175 * @channel_base: Base offset for the channel data registers 176 * @drdy_mask: Mask of the DRDY field in the relevant registers 177 * (Interruptions registers mostly) 178 * @status_register: Offset of the Interrupt Status Register 179 * @trigger_register: Offset of the Trigger setup register 180 * @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register 181 * @mr_startup_mask: Mask of the STARTUP field in the adc MR register 182 */ 183 struct at91_adc_reg_desc { 184 u8 channel_base; 185 u32 drdy_mask; 186 u8 status_register; 187 u8 trigger_register; 188 u32 mr_prescal_mask; 189 u32 mr_startup_mask; 190 }; 191 192 struct at91_adc_caps { 193 bool has_ts; /* Support touch screen */ 194 bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */ 195 /* 196 * Numbers of sampling data will be averaged. Can be 0~3. 197 * Hardware can average (2 ^ ts_filter_average) sample data. 198 */ 199 u8 ts_filter_average; 200 /* Pen Detection input pull-up resistor, can be 0~3 */ 201 u8 ts_pen_detect_sensitivity; 202 203 /* startup time calculate function */ 204 u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz); 205 206 u8 num_channels; 207 struct at91_adc_reg_desc registers; 208 }; 209 210 struct at91_adc_state { 211 struct clk *adc_clk; 212 u16 *buffer; 213 unsigned long channels_mask; 214 struct clk *clk; 215 bool done; 216 int irq; 217 u16 last_value; 218 int chnb; 219 struct mutex lock; 220 u8 num_channels; 221 void __iomem *reg_base; 222 const struct at91_adc_reg_desc *registers; 223 u32 startup_time; 224 u8 sample_hold_time; 225 bool sleep_mode; 226 struct iio_trigger **trig; 227 struct at91_adc_trigger *trigger_list; 228 u32 trigger_number; 229 bool use_external; 230 u32 vref_mv; 231 u32 res; /* resolution used for convertions */ 232 bool low_res; /* the resolution corresponds to the lowest one */ 233 wait_queue_head_t wq_data_avail; 234 const struct at91_adc_caps *caps; 235 236 /* 237 * Following ADC channels are shared by touchscreen: 238 * 239 * CH0 -- Touch screen XP/UL 240 * CH1 -- Touch screen XM/UR 241 * CH2 -- Touch screen YP/LL 242 * CH3 -- Touch screen YM/Sense 243 * CH4 -- Touch screen LR(5-wire only) 244 * 245 * The bitfields below represents the reserved channel in the 246 * touchscreen mode. 247 */ 248 #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0) 249 #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0) 250 enum atmel_adc_ts_type touchscreen_type; 251 struct input_dev *ts_input; 252 253 u16 ts_sample_period_val; 254 u32 ts_pressure_threshold; 255 u16 ts_pendbc; 256 257 bool ts_bufferedmeasure; 258 u32 ts_prev_absx; 259 u32 ts_prev_absy; 260 }; 261 262 static irqreturn_t at91_adc_trigger_handler(int irq, void *p) 263 { 264 struct iio_poll_func *pf = p; 265 struct iio_dev *idev = pf->indio_dev; 266 struct at91_adc_state *st = iio_priv(idev); 267 struct iio_chan_spec const *chan; 268 int i, j = 0; 269 270 for (i = 0; i < idev->masklength; i++) { 271 if (!test_bit(i, idev->active_scan_mask)) 272 continue; 273 chan = idev->channels + i; 274 st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, chan->channel)); 275 j++; 276 } 277 278 iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp); 279 280 iio_trigger_notify_done(idev->trig); 281 282 /* Needed to ACK the DRDY interruption */ 283 at91_adc_readl(st, AT91_ADC_LCDR); 284 285 enable_irq(st->irq); 286 287 return IRQ_HANDLED; 288 } 289 290 /* Handler for classic adc channel eoc trigger */ 291 static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev) 292 { 293 struct at91_adc_state *st = iio_priv(idev); 294 295 if (iio_buffer_enabled(idev)) { 296 disable_irq_nosync(irq); 297 iio_trigger_poll(idev->trig); 298 } else { 299 st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb)); 300 /* Needed to ACK the DRDY interruption */ 301 at91_adc_readl(st, AT91_ADC_LCDR); 302 st->done = true; 303 wake_up_interruptible(&st->wq_data_avail); 304 } 305 } 306 307 static int at91_ts_sample(struct iio_dev *idev) 308 { 309 struct at91_adc_state *st = iio_priv(idev); 310 unsigned int xscale, yscale, reg, z1, z2; 311 unsigned int x, y, pres, xpos, ypos; 312 unsigned int rxp = 1; 313 unsigned int factor = 1000; 314 315 unsigned int xyz_mask_bits = st->res; 316 unsigned int xyz_mask = (1 << xyz_mask_bits) - 1; 317 318 /* calculate position */ 319 /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */ 320 reg = at91_adc_readl(st, AT91_ADC_TSXPOSR); 321 xpos = reg & xyz_mask; 322 x = (xpos << MAX_POS_BITS) - xpos; 323 xscale = (reg >> 16) & xyz_mask; 324 if (xscale == 0) { 325 dev_err(&idev->dev, "Error: xscale == 0!\n"); 326 return -1; 327 } 328 x /= xscale; 329 330 /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */ 331 reg = at91_adc_readl(st, AT91_ADC_TSYPOSR); 332 ypos = reg & xyz_mask; 333 y = (ypos << MAX_POS_BITS) - ypos; 334 yscale = (reg >> 16) & xyz_mask; 335 if (yscale == 0) { 336 dev_err(&idev->dev, "Error: yscale == 0!\n"); 337 return -1; 338 } 339 y /= yscale; 340 341 /* calculate the pressure */ 342 reg = at91_adc_readl(st, AT91_ADC_TSPRESSR); 343 z1 = reg & xyz_mask; 344 z2 = (reg >> 16) & xyz_mask; 345 346 if (z1 != 0) 347 pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor) 348 / factor; 349 else 350 pres = st->ts_pressure_threshold; /* no pen contacted */ 351 352 dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n", 353 xpos, xscale, ypos, yscale, z1, z2, pres); 354 355 if (pres < st->ts_pressure_threshold) { 356 dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n", 357 x, y, pres / factor); 358 input_report_abs(st->ts_input, ABS_X, x); 359 input_report_abs(st->ts_input, ABS_Y, y); 360 input_report_abs(st->ts_input, ABS_PRESSURE, pres); 361 input_report_key(st->ts_input, BTN_TOUCH, 1); 362 input_sync(st->ts_input); 363 } else { 364 dev_dbg(&idev->dev, "pressure too low: not reporting\n"); 365 } 366 367 return 0; 368 } 369 370 static irqreturn_t at91_adc_rl_interrupt(int irq, void *private) 371 { 372 struct iio_dev *idev = private; 373 struct at91_adc_state *st = iio_priv(idev); 374 u32 status = at91_adc_readl(st, st->registers->status_register); 375 unsigned int reg; 376 377 status &= at91_adc_readl(st, AT91_ADC_IMR); 378 if (status & GENMASK(st->num_channels - 1, 0)) 379 handle_adc_eoc_trigger(irq, idev); 380 381 if (status & AT91RL_ADC_IER_PEN) { 382 /* Disabling pen debounce is required to get a NOPEN irq */ 383 reg = at91_adc_readl(st, AT91_ADC_MR); 384 reg &= ~AT91_ADC_PENDBC; 385 at91_adc_writel(st, AT91_ADC_MR, reg); 386 387 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN); 388 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN 389 | AT91_ADC_EOC(3)); 390 /* Set up period trigger for sampling */ 391 at91_adc_writel(st, st->registers->trigger_register, 392 AT91_ADC_TRGR_MOD_PERIOD_TRIG | 393 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val)); 394 } else if (status & AT91RL_ADC_IER_NOPEN) { 395 reg = at91_adc_readl(st, AT91_ADC_MR); 396 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC; 397 at91_adc_writel(st, AT91_ADC_MR, reg); 398 at91_adc_writel(st, st->registers->trigger_register, 399 AT91_ADC_TRGR_NONE); 400 401 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN 402 | AT91_ADC_EOC(3)); 403 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN); 404 st->ts_bufferedmeasure = false; 405 input_report_key(st->ts_input, BTN_TOUCH, 0); 406 input_sync(st->ts_input); 407 } else if (status & AT91_ADC_EOC(3) && st->ts_input) { 408 /* Conversion finished and we've a touchscreen */ 409 if (st->ts_bufferedmeasure) { 410 /* 411 * Last measurement is always discarded, since it can 412 * be erroneous. 413 * Always report previous measurement 414 */ 415 input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx); 416 input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy); 417 input_report_key(st->ts_input, BTN_TOUCH, 1); 418 input_sync(st->ts_input); 419 } else 420 st->ts_bufferedmeasure = true; 421 422 /* Now make new measurement */ 423 st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3)) 424 << MAX_RLPOS_BITS; 425 st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2)); 426 427 st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1)) 428 << MAX_RLPOS_BITS; 429 st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0)); 430 } 431 432 return IRQ_HANDLED; 433 } 434 435 static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private) 436 { 437 struct iio_dev *idev = private; 438 struct at91_adc_state *st = iio_priv(idev); 439 u32 status = at91_adc_readl(st, st->registers->status_register); 440 const uint32_t ts_data_irq_mask = 441 AT91_ADC_IER_XRDY | 442 AT91_ADC_IER_YRDY | 443 AT91_ADC_IER_PRDY; 444 445 if (status & GENMASK(st->num_channels - 1, 0)) 446 handle_adc_eoc_trigger(irq, idev); 447 448 if (status & AT91_ADC_IER_PEN) { 449 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN); 450 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN | 451 ts_data_irq_mask); 452 /* Set up period trigger for sampling */ 453 at91_adc_writel(st, st->registers->trigger_register, 454 AT91_ADC_TRGR_MOD_PERIOD_TRIG | 455 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val)); 456 } else if (status & AT91_ADC_IER_NOPEN) { 457 at91_adc_writel(st, st->registers->trigger_register, 0); 458 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN | 459 ts_data_irq_mask); 460 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN); 461 462 input_report_key(st->ts_input, BTN_TOUCH, 0); 463 input_sync(st->ts_input); 464 } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) { 465 /* Now all touchscreen data is ready */ 466 467 if (status & AT91_ADC_ISR_PENS) { 468 /* validate data by pen contact */ 469 at91_ts_sample(idev); 470 } else { 471 /* triggered by event that is no pen contact, just read 472 * them to clean the interrupt and discard all. 473 */ 474 at91_adc_readl(st, AT91_ADC_TSXPOSR); 475 at91_adc_readl(st, AT91_ADC_TSYPOSR); 476 at91_adc_readl(st, AT91_ADC_TSPRESSR); 477 } 478 } 479 480 return IRQ_HANDLED; 481 } 482 483 static int at91_adc_channel_init(struct iio_dev *idev) 484 { 485 struct at91_adc_state *st = iio_priv(idev); 486 struct iio_chan_spec *chan_array, *timestamp; 487 int bit, idx = 0; 488 unsigned long rsvd_mask = 0; 489 490 /* If touchscreen is enable, then reserve the adc channels */ 491 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE) 492 rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE; 493 else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE) 494 rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE; 495 496 /* set up the channel mask to reserve touchscreen channels */ 497 st->channels_mask &= ~rsvd_mask; 498 499 idev->num_channels = bitmap_weight(&st->channels_mask, 500 st->num_channels) + 1; 501 502 chan_array = devm_kzalloc(&idev->dev, 503 ((idev->num_channels + 1) * 504 sizeof(struct iio_chan_spec)), 505 GFP_KERNEL); 506 507 if (!chan_array) 508 return -ENOMEM; 509 510 for_each_set_bit(bit, &st->channels_mask, st->num_channels) { 511 struct iio_chan_spec *chan = chan_array + idx; 512 513 chan->type = IIO_VOLTAGE; 514 chan->indexed = 1; 515 chan->channel = bit; 516 chan->scan_index = idx; 517 chan->scan_type.sign = 'u'; 518 chan->scan_type.realbits = st->res; 519 chan->scan_type.storagebits = 16; 520 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); 521 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 522 idx++; 523 } 524 timestamp = chan_array + idx; 525 526 timestamp->type = IIO_TIMESTAMP; 527 timestamp->channel = -1; 528 timestamp->scan_index = idx; 529 timestamp->scan_type.sign = 's'; 530 timestamp->scan_type.realbits = 64; 531 timestamp->scan_type.storagebits = 64; 532 533 idev->channels = chan_array; 534 return idev->num_channels; 535 } 536 537 static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev, 538 struct at91_adc_trigger *triggers, 539 const char *trigger_name) 540 { 541 struct at91_adc_state *st = iio_priv(idev); 542 int i; 543 544 for (i = 0; i < st->trigger_number; i++) { 545 char *name = kasprintf(GFP_KERNEL, 546 "%s-dev%d-%s", 547 idev->name, 548 idev->id, 549 triggers[i].name); 550 if (!name) 551 return -ENOMEM; 552 553 if (strcmp(trigger_name, name) == 0) { 554 kfree(name); 555 if (triggers[i].value == 0) 556 return -EINVAL; 557 return triggers[i].value; 558 } 559 560 kfree(name); 561 } 562 563 return -EINVAL; 564 } 565 566 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) 567 { 568 struct iio_dev *idev = iio_trigger_get_drvdata(trig); 569 struct at91_adc_state *st = iio_priv(idev); 570 const struct at91_adc_reg_desc *reg = st->registers; 571 u32 status = at91_adc_readl(st, reg->trigger_register); 572 int value; 573 u8 bit; 574 575 value = at91_adc_get_trigger_value_by_name(idev, 576 st->trigger_list, 577 idev->trig->name); 578 if (value < 0) 579 return value; 580 581 if (state) { 582 st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL); 583 if (st->buffer == NULL) 584 return -ENOMEM; 585 586 at91_adc_writel(st, reg->trigger_register, 587 status | value); 588 589 for_each_set_bit(bit, idev->active_scan_mask, 590 st->num_channels) { 591 struct iio_chan_spec const *chan = idev->channels + bit; 592 at91_adc_writel(st, AT91_ADC_CHER, 593 AT91_ADC_CH(chan->channel)); 594 } 595 596 at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask); 597 598 } else { 599 at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask); 600 601 at91_adc_writel(st, reg->trigger_register, 602 status & ~value); 603 604 for_each_set_bit(bit, idev->active_scan_mask, 605 st->num_channels) { 606 struct iio_chan_spec const *chan = idev->channels + bit; 607 at91_adc_writel(st, AT91_ADC_CHDR, 608 AT91_ADC_CH(chan->channel)); 609 } 610 kfree(st->buffer); 611 } 612 613 return 0; 614 } 615 616 static const struct iio_trigger_ops at91_adc_trigger_ops = { 617 .set_trigger_state = &at91_adc_configure_trigger, 618 }; 619 620 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev, 621 struct at91_adc_trigger *trigger) 622 { 623 struct iio_trigger *trig; 624 int ret; 625 626 trig = iio_trigger_alloc("%s-dev%d-%s", idev->name, 627 idev->id, trigger->name); 628 if (trig == NULL) 629 return NULL; 630 631 trig->dev.parent = idev->dev.parent; 632 iio_trigger_set_drvdata(trig, idev); 633 trig->ops = &at91_adc_trigger_ops; 634 635 ret = iio_trigger_register(trig); 636 if (ret) 637 return NULL; 638 639 return trig; 640 } 641 642 static int at91_adc_trigger_init(struct iio_dev *idev) 643 { 644 struct at91_adc_state *st = iio_priv(idev); 645 int i, ret; 646 647 st->trig = devm_kcalloc(&idev->dev, 648 st->trigger_number, sizeof(*st->trig), 649 GFP_KERNEL); 650 651 if (st->trig == NULL) { 652 ret = -ENOMEM; 653 goto error_ret; 654 } 655 656 for (i = 0; i < st->trigger_number; i++) { 657 if (st->trigger_list[i].is_external && !(st->use_external)) 658 continue; 659 660 st->trig[i] = at91_adc_allocate_trigger(idev, 661 st->trigger_list + i); 662 if (st->trig[i] == NULL) { 663 dev_err(&idev->dev, 664 "Could not allocate trigger %d\n", i); 665 ret = -ENOMEM; 666 goto error_trigger; 667 } 668 } 669 670 return 0; 671 672 error_trigger: 673 for (i--; i >= 0; i--) { 674 iio_trigger_unregister(st->trig[i]); 675 iio_trigger_free(st->trig[i]); 676 } 677 error_ret: 678 return ret; 679 } 680 681 static void at91_adc_trigger_remove(struct iio_dev *idev) 682 { 683 struct at91_adc_state *st = iio_priv(idev); 684 int i; 685 686 for (i = 0; i < st->trigger_number; i++) { 687 iio_trigger_unregister(st->trig[i]); 688 iio_trigger_free(st->trig[i]); 689 } 690 } 691 692 static int at91_adc_buffer_init(struct iio_dev *idev) 693 { 694 return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time, 695 &at91_adc_trigger_handler, NULL); 696 } 697 698 static void at91_adc_buffer_remove(struct iio_dev *idev) 699 { 700 iio_triggered_buffer_cleanup(idev); 701 } 702 703 static int at91_adc_read_raw(struct iio_dev *idev, 704 struct iio_chan_spec const *chan, 705 int *val, int *val2, long mask) 706 { 707 struct at91_adc_state *st = iio_priv(idev); 708 int ret; 709 710 switch (mask) { 711 case IIO_CHAN_INFO_RAW: 712 mutex_lock(&st->lock); 713 714 st->chnb = chan->channel; 715 at91_adc_writel(st, AT91_ADC_CHER, 716 AT91_ADC_CH(chan->channel)); 717 at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel)); 718 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START); 719 720 ret = wait_event_interruptible_timeout(st->wq_data_avail, 721 st->done, 722 msecs_to_jiffies(1000)); 723 724 /* Disable interrupts, regardless if adc conversion was 725 * successful or not 726 */ 727 at91_adc_writel(st, AT91_ADC_CHDR, 728 AT91_ADC_CH(chan->channel)); 729 at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel)); 730 731 if (ret > 0) { 732 /* a valid conversion took place */ 733 *val = st->last_value; 734 st->last_value = 0; 735 st->done = false; 736 ret = IIO_VAL_INT; 737 } else if (ret == 0) { 738 /* conversion timeout */ 739 dev_err(&idev->dev, "ADC Channel %d timeout.\n", 740 chan->channel); 741 ret = -ETIMEDOUT; 742 } 743 744 mutex_unlock(&st->lock); 745 return ret; 746 747 case IIO_CHAN_INFO_SCALE: 748 *val = st->vref_mv; 749 *val2 = chan->scan_type.realbits; 750 return IIO_VAL_FRACTIONAL_LOG2; 751 default: 752 break; 753 } 754 return -EINVAL; 755 } 756 757 static int at91_adc_of_get_resolution(struct iio_dev *idev, 758 struct platform_device *pdev) 759 { 760 struct at91_adc_state *st = iio_priv(idev); 761 struct device_node *np = pdev->dev.of_node; 762 int count, i, ret = 0; 763 char *res_name, *s; 764 u32 *resolutions; 765 766 count = of_property_count_strings(np, "atmel,adc-res-names"); 767 if (count < 2) { 768 dev_err(&idev->dev, "You must specified at least two resolution names for " 769 "adc-res-names property in the DT\n"); 770 return count; 771 } 772 773 resolutions = kmalloc_array(count, sizeof(*resolutions), GFP_KERNEL); 774 if (!resolutions) 775 return -ENOMEM; 776 777 if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) { 778 dev_err(&idev->dev, "Missing adc-res property in the DT.\n"); 779 ret = -ENODEV; 780 goto ret; 781 } 782 783 if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name)) 784 res_name = "highres"; 785 786 for (i = 0; i < count; i++) { 787 if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s)) 788 continue; 789 790 if (strcmp(res_name, s)) 791 continue; 792 793 st->res = resolutions[i]; 794 if (!strcmp(res_name, "lowres")) 795 st->low_res = true; 796 else 797 st->low_res = false; 798 799 dev_info(&idev->dev, "Resolution used: %u bits\n", st->res); 800 goto ret; 801 } 802 803 dev_err(&idev->dev, "There is no resolution for %s\n", res_name); 804 805 ret: 806 kfree(resolutions); 807 return ret; 808 } 809 810 static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz) 811 { 812 /* 813 * Number of ticks needed to cover the startup time of the ADC 814 * as defined in the electrical characteristics of the board, 815 * divided by 8. The formula thus is : 816 * Startup Time = (ticks + 1) * 8 / ADC Clock 817 */ 818 return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8; 819 } 820 821 static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz) 822 { 823 /* 824 * For sama5d3x and at91sam9x5, the formula changes to: 825 * Startup Time = <lookup_table_value> / ADC Clock 826 */ 827 static const int startup_lookup[] = { 828 0, 8, 16, 24, 829 64, 80, 96, 112, 830 512, 576, 640, 704, 831 768, 832, 896, 960 832 }; 833 int i, size = ARRAY_SIZE(startup_lookup); 834 unsigned int ticks; 835 836 ticks = startup_time * adc_clk_khz / 1000; 837 for (i = 0; i < size; i++) 838 if (ticks < startup_lookup[i]) 839 break; 840 841 ticks = i; 842 if (ticks == size) 843 /* Reach the end of lookup table */ 844 ticks = size - 1; 845 846 return ticks; 847 } 848 849 static int at91_adc_probe_dt_ts(struct device_node *node, 850 struct at91_adc_state *st, struct device *dev) 851 { 852 int ret; 853 u32 prop; 854 855 ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop); 856 if (ret) { 857 dev_info(dev, "ADC Touch screen is disabled.\n"); 858 return 0; 859 } 860 861 switch (prop) { 862 case 4: 863 case 5: 864 st->touchscreen_type = prop; 865 break; 866 default: 867 dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop); 868 return -EINVAL; 869 } 870 871 if (!st->caps->has_tsmr) 872 return 0; 873 prop = 0; 874 of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop); 875 st->ts_pressure_threshold = prop; 876 if (st->ts_pressure_threshold) { 877 return 0; 878 } else { 879 dev_err(dev, "Invalid pressure threshold for the touchscreen\n"); 880 return -EINVAL; 881 } 882 } 883 884 static int at91_adc_probe_dt(struct iio_dev *idev, 885 struct platform_device *pdev) 886 { 887 struct at91_adc_state *st = iio_priv(idev); 888 struct device_node *node = pdev->dev.of_node; 889 struct device_node *trig_node; 890 int i = 0, ret; 891 u32 prop; 892 893 st->caps = of_device_get_match_data(&pdev->dev); 894 895 st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers"); 896 897 if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) { 898 dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n"); 899 ret = -EINVAL; 900 goto error_ret; 901 } 902 st->channels_mask = prop; 903 904 st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode"); 905 906 if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) { 907 dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n"); 908 ret = -EINVAL; 909 goto error_ret; 910 } 911 st->startup_time = prop; 912 913 prop = 0; 914 of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop); 915 st->sample_hold_time = prop; 916 917 if (of_property_read_u32(node, "atmel,adc-vref", &prop)) { 918 dev_err(&idev->dev, "Missing adc-vref property in the DT.\n"); 919 ret = -EINVAL; 920 goto error_ret; 921 } 922 st->vref_mv = prop; 923 924 ret = at91_adc_of_get_resolution(idev, pdev); 925 if (ret) 926 goto error_ret; 927 928 st->registers = &st->caps->registers; 929 st->num_channels = st->caps->num_channels; 930 st->trigger_number = of_get_child_count(node); 931 st->trigger_list = devm_kcalloc(&idev->dev, 932 st->trigger_number, 933 sizeof(struct at91_adc_trigger), 934 GFP_KERNEL); 935 if (!st->trigger_list) { 936 dev_err(&idev->dev, "Could not allocate trigger list memory.\n"); 937 ret = -ENOMEM; 938 goto error_ret; 939 } 940 941 for_each_child_of_node(node, trig_node) { 942 struct at91_adc_trigger *trig = st->trigger_list + i; 943 const char *name; 944 945 if (of_property_read_string(trig_node, "trigger-name", &name)) { 946 dev_err(&idev->dev, "Missing trigger-name property in the DT.\n"); 947 ret = -EINVAL; 948 goto error_ret; 949 } 950 trig->name = name; 951 952 if (of_property_read_u32(trig_node, "trigger-value", &prop)) { 953 dev_err(&idev->dev, "Missing trigger-value property in the DT.\n"); 954 ret = -EINVAL; 955 goto error_ret; 956 } 957 trig->value = prop; 958 trig->is_external = of_property_read_bool(trig_node, "trigger-external"); 959 i++; 960 } 961 962 /* Check if touchscreen is supported. */ 963 if (st->caps->has_ts) 964 return at91_adc_probe_dt_ts(node, st, &idev->dev); 965 else 966 dev_info(&idev->dev, "not support touchscreen in the adc compatible string.\n"); 967 968 return 0; 969 970 error_ret: 971 return ret; 972 } 973 974 static const struct iio_info at91_adc_info = { 975 .read_raw = &at91_adc_read_raw, 976 }; 977 978 /* Touchscreen related functions */ 979 static int atmel_ts_open(struct input_dev *dev) 980 { 981 struct at91_adc_state *st = input_get_drvdata(dev); 982 983 if (st->caps->has_tsmr) 984 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN); 985 else 986 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN); 987 return 0; 988 } 989 990 static void atmel_ts_close(struct input_dev *dev) 991 { 992 struct at91_adc_state *st = input_get_drvdata(dev); 993 994 if (st->caps->has_tsmr) 995 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN); 996 else 997 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN); 998 } 999 1000 static int at91_ts_hw_init(struct iio_dev *idev, u32 adc_clk_khz) 1001 { 1002 struct at91_adc_state *st = iio_priv(idev); 1003 u32 reg = 0; 1004 u32 tssctim = 0; 1005 int i = 0; 1006 1007 /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid 1008 * pen detect noise. 1009 * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock 1010 */ 1011 st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz / 1012 1000, 1); 1013 1014 while (st->ts_pendbc >> ++i) 1015 ; /* Empty! Find the shift offset */ 1016 if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1)))) 1017 st->ts_pendbc = i; 1018 else 1019 st->ts_pendbc = i - 1; 1020 1021 if (!st->caps->has_tsmr) { 1022 reg = at91_adc_readl(st, AT91_ADC_MR); 1023 reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET; 1024 1025 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC; 1026 at91_adc_writel(st, AT91_ADC_MR, reg); 1027 1028 reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM; 1029 at91_adc_writel(st, AT91_ADC_TSR, reg); 1030 1031 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL * 1032 adc_clk_khz / 1000) - 1, 1); 1033 1034 return 0; 1035 } 1036 1037 /* Touchscreen Switches Closure time needed for allowing the value to 1038 * stabilize. 1039 * Switch Closure Time = (TSSCTIM * 4) ADCClock periods 1040 */ 1041 tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4); 1042 dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n", 1043 adc_clk_khz, tssctim); 1044 1045 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE) 1046 reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS; 1047 else 1048 reg = AT91_ADC_TSMR_TSMODE_5WIRE; 1049 1050 reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM; 1051 reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average) 1052 & AT91_ADC_TSMR_TSAV; 1053 reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC; 1054 reg |= AT91_ADC_TSMR_NOTSDMA; 1055 reg |= AT91_ADC_TSMR_PENDET_ENA; 1056 reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */ 1057 1058 at91_adc_writel(st, AT91_ADC_TSMR, reg); 1059 1060 /* Change adc internal resistor value for better pen detection, 1061 * default value is 100 kOhm. 1062 * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm 1063 * option only available on ES2 and higher 1064 */ 1065 at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity 1066 & AT91_ADC_ACR_PENDETSENS); 1067 1068 /* Sample Period Time = (TRGPER + 1) / ADCClock */ 1069 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US * 1070 adc_clk_khz / 1000) - 1, 1); 1071 1072 return 0; 1073 } 1074 1075 static int at91_ts_register(struct iio_dev *idev, 1076 struct platform_device *pdev) 1077 { 1078 struct at91_adc_state *st = iio_priv(idev); 1079 struct input_dev *input; 1080 int ret; 1081 1082 input = input_allocate_device(); 1083 if (!input) { 1084 dev_err(&idev->dev, "Failed to allocate TS device!\n"); 1085 return -ENOMEM; 1086 } 1087 1088 input->name = DRIVER_NAME; 1089 input->id.bustype = BUS_HOST; 1090 input->dev.parent = &pdev->dev; 1091 input->open = atmel_ts_open; 1092 input->close = atmel_ts_close; 1093 1094 __set_bit(EV_ABS, input->evbit); 1095 __set_bit(EV_KEY, input->evbit); 1096 __set_bit(BTN_TOUCH, input->keybit); 1097 if (st->caps->has_tsmr) { 1098 input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1, 1099 0, 0); 1100 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1, 1101 0, 0); 1102 input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0); 1103 } else { 1104 if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) { 1105 dev_err(&pdev->dev, 1106 "This touchscreen controller only support 4 wires\n"); 1107 ret = -EINVAL; 1108 goto err; 1109 } 1110 1111 input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1, 1112 0, 0); 1113 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1, 1114 0, 0); 1115 } 1116 1117 st->ts_input = input; 1118 input_set_drvdata(input, st); 1119 1120 ret = input_register_device(input); 1121 if (ret) 1122 goto err; 1123 1124 return ret; 1125 1126 err: 1127 input_free_device(st->ts_input); 1128 return ret; 1129 } 1130 1131 static void at91_ts_unregister(struct at91_adc_state *st) 1132 { 1133 input_unregister_device(st->ts_input); 1134 } 1135 1136 static int at91_adc_probe(struct platform_device *pdev) 1137 { 1138 unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim; 1139 int ret; 1140 struct iio_dev *idev; 1141 struct at91_adc_state *st; 1142 u32 reg; 1143 1144 idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state)); 1145 if (!idev) 1146 return -ENOMEM; 1147 1148 st = iio_priv(idev); 1149 1150 ret = at91_adc_probe_dt(idev, pdev); 1151 if (ret) 1152 return ret; 1153 1154 platform_set_drvdata(pdev, idev); 1155 1156 idev->name = dev_name(&pdev->dev); 1157 idev->modes = INDIO_DIRECT_MODE; 1158 idev->info = &at91_adc_info; 1159 1160 st->irq = platform_get_irq(pdev, 0); 1161 if (st->irq < 0) 1162 return -ENODEV; 1163 1164 st->reg_base = devm_platform_ioremap_resource(pdev, 0); 1165 if (IS_ERR(st->reg_base)) 1166 return PTR_ERR(st->reg_base); 1167 1168 1169 /* 1170 * Disable all IRQs before setting up the handler 1171 */ 1172 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST); 1173 at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF); 1174 1175 if (st->caps->has_tsmr) 1176 ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0, 1177 pdev->dev.driver->name, idev); 1178 else 1179 ret = request_irq(st->irq, at91_adc_rl_interrupt, 0, 1180 pdev->dev.driver->name, idev); 1181 if (ret) { 1182 dev_err(&pdev->dev, "Failed to allocate IRQ.\n"); 1183 return ret; 1184 } 1185 1186 st->clk = devm_clk_get(&pdev->dev, "adc_clk"); 1187 if (IS_ERR(st->clk)) { 1188 dev_err(&pdev->dev, "Failed to get the clock.\n"); 1189 ret = PTR_ERR(st->clk); 1190 goto error_free_irq; 1191 } 1192 1193 ret = clk_prepare_enable(st->clk); 1194 if (ret) { 1195 dev_err(&pdev->dev, 1196 "Could not prepare or enable the clock.\n"); 1197 goto error_free_irq; 1198 } 1199 1200 st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk"); 1201 if (IS_ERR(st->adc_clk)) { 1202 dev_err(&pdev->dev, "Failed to get the ADC clock.\n"); 1203 ret = PTR_ERR(st->adc_clk); 1204 goto error_disable_clk; 1205 } 1206 1207 ret = clk_prepare_enable(st->adc_clk); 1208 if (ret) { 1209 dev_err(&pdev->dev, 1210 "Could not prepare or enable the ADC clock.\n"); 1211 goto error_disable_clk; 1212 } 1213 1214 /* 1215 * Prescaler rate computation using the formula from the Atmel's 1216 * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being 1217 * specified by the electrical characteristics of the board. 1218 */ 1219 mstrclk = clk_get_rate(st->clk); 1220 adc_clk = clk_get_rate(st->adc_clk); 1221 adc_clk_khz = adc_clk / 1000; 1222 1223 dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n", 1224 mstrclk, adc_clk); 1225 1226 prsc = (mstrclk / (2 * adc_clk)) - 1; 1227 1228 if (!st->startup_time) { 1229 dev_err(&pdev->dev, "No startup time available.\n"); 1230 ret = -EINVAL; 1231 goto error_disable_adc_clk; 1232 } 1233 ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz); 1234 1235 /* 1236 * a minimal Sample and Hold Time is necessary for the ADC to guarantee 1237 * the best converted final value between two channels selection 1238 * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock 1239 */ 1240 if (st->sample_hold_time > 0) 1241 shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000) 1242 - 1, 1); 1243 else 1244 shtim = 0; 1245 1246 reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask; 1247 reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask; 1248 if (st->low_res) 1249 reg |= AT91_ADC_LOWRES; 1250 if (st->sleep_mode) 1251 reg |= AT91_ADC_SLEEP; 1252 reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM; 1253 at91_adc_writel(st, AT91_ADC_MR, reg); 1254 1255 /* Setup the ADC channels available on the board */ 1256 ret = at91_adc_channel_init(idev); 1257 if (ret < 0) { 1258 dev_err(&pdev->dev, "Couldn't initialize the channels.\n"); 1259 goto error_disable_adc_clk; 1260 } 1261 1262 init_waitqueue_head(&st->wq_data_avail); 1263 mutex_init(&st->lock); 1264 1265 /* 1266 * Since touch screen will set trigger register as period trigger. So 1267 * when touch screen is enabled, then we have to disable hardware 1268 * trigger for classic adc. 1269 */ 1270 if (!st->touchscreen_type) { 1271 ret = at91_adc_buffer_init(idev); 1272 if (ret < 0) { 1273 dev_err(&pdev->dev, "Couldn't initialize the buffer.\n"); 1274 goto error_disable_adc_clk; 1275 } 1276 1277 ret = at91_adc_trigger_init(idev); 1278 if (ret < 0) { 1279 dev_err(&pdev->dev, "Couldn't setup the triggers.\n"); 1280 at91_adc_buffer_remove(idev); 1281 goto error_disable_adc_clk; 1282 } 1283 } else { 1284 ret = at91_ts_register(idev, pdev); 1285 if (ret) 1286 goto error_disable_adc_clk; 1287 1288 at91_ts_hw_init(idev, adc_clk_khz); 1289 } 1290 1291 ret = iio_device_register(idev); 1292 if (ret < 0) { 1293 dev_err(&pdev->dev, "Couldn't register the device.\n"); 1294 goto error_iio_device_register; 1295 } 1296 1297 return 0; 1298 1299 error_iio_device_register: 1300 if (!st->touchscreen_type) { 1301 at91_adc_trigger_remove(idev); 1302 at91_adc_buffer_remove(idev); 1303 } else { 1304 at91_ts_unregister(st); 1305 } 1306 error_disable_adc_clk: 1307 clk_disable_unprepare(st->adc_clk); 1308 error_disable_clk: 1309 clk_disable_unprepare(st->clk); 1310 error_free_irq: 1311 free_irq(st->irq, idev); 1312 return ret; 1313 } 1314 1315 static int at91_adc_remove(struct platform_device *pdev) 1316 { 1317 struct iio_dev *idev = platform_get_drvdata(pdev); 1318 struct at91_adc_state *st = iio_priv(idev); 1319 1320 iio_device_unregister(idev); 1321 if (!st->touchscreen_type) { 1322 at91_adc_trigger_remove(idev); 1323 at91_adc_buffer_remove(idev); 1324 } else { 1325 at91_ts_unregister(st); 1326 } 1327 clk_disable_unprepare(st->adc_clk); 1328 clk_disable_unprepare(st->clk); 1329 free_irq(st->irq, idev); 1330 1331 return 0; 1332 } 1333 1334 #ifdef CONFIG_PM_SLEEP 1335 static int at91_adc_suspend(struct device *dev) 1336 { 1337 struct iio_dev *idev = dev_get_drvdata(dev); 1338 struct at91_adc_state *st = iio_priv(idev); 1339 1340 pinctrl_pm_select_sleep_state(dev); 1341 clk_disable_unprepare(st->clk); 1342 1343 return 0; 1344 } 1345 1346 static int at91_adc_resume(struct device *dev) 1347 { 1348 struct iio_dev *idev = dev_get_drvdata(dev); 1349 struct at91_adc_state *st = iio_priv(idev); 1350 1351 clk_prepare_enable(st->clk); 1352 pinctrl_pm_select_default_state(dev); 1353 1354 return 0; 1355 } 1356 #endif 1357 1358 static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume); 1359 1360 static struct at91_adc_caps at91sam9260_caps = { 1361 .calc_startup_ticks = calc_startup_ticks_9260, 1362 .num_channels = 4, 1363 .registers = { 1364 .channel_base = AT91_ADC_CHR(0), 1365 .drdy_mask = AT91_ADC_DRDY, 1366 .status_register = AT91_ADC_SR, 1367 .trigger_register = AT91_ADC_TRGR_9260, 1368 .mr_prescal_mask = AT91_ADC_PRESCAL_9260, 1369 .mr_startup_mask = AT91_ADC_STARTUP_9260, 1370 }, 1371 }; 1372 1373 static struct at91_adc_caps at91sam9rl_caps = { 1374 .has_ts = true, 1375 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */ 1376 .num_channels = 6, 1377 .registers = { 1378 .channel_base = AT91_ADC_CHR(0), 1379 .drdy_mask = AT91_ADC_DRDY, 1380 .status_register = AT91_ADC_SR, 1381 .trigger_register = AT91_ADC_TRGR_9G45, 1382 .mr_prescal_mask = AT91_ADC_PRESCAL_9260, 1383 .mr_startup_mask = AT91_ADC_STARTUP_9G45, 1384 }, 1385 }; 1386 1387 static struct at91_adc_caps at91sam9g45_caps = { 1388 .has_ts = true, 1389 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */ 1390 .num_channels = 8, 1391 .registers = { 1392 .channel_base = AT91_ADC_CHR(0), 1393 .drdy_mask = AT91_ADC_DRDY, 1394 .status_register = AT91_ADC_SR, 1395 .trigger_register = AT91_ADC_TRGR_9G45, 1396 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45, 1397 .mr_startup_mask = AT91_ADC_STARTUP_9G45, 1398 }, 1399 }; 1400 1401 static struct at91_adc_caps at91sam9x5_caps = { 1402 .has_ts = true, 1403 .has_tsmr = true, 1404 .ts_filter_average = 3, 1405 .ts_pen_detect_sensitivity = 2, 1406 .calc_startup_ticks = calc_startup_ticks_9x5, 1407 .num_channels = 12, 1408 .registers = { 1409 .channel_base = AT91_ADC_CDR0_9X5, 1410 .drdy_mask = AT91_ADC_SR_DRDY_9X5, 1411 .status_register = AT91_ADC_SR_9X5, 1412 .trigger_register = AT91_ADC_TRGR_9X5, 1413 /* prescal mask is same as 9G45 */ 1414 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45, 1415 .mr_startup_mask = AT91_ADC_STARTUP_9X5, 1416 }, 1417 }; 1418 1419 static const struct of_device_id at91_adc_dt_ids[] = { 1420 { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps }, 1421 { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps }, 1422 { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps }, 1423 { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps }, 1424 {}, 1425 }; 1426 MODULE_DEVICE_TABLE(of, at91_adc_dt_ids); 1427 1428 static const struct platform_device_id at91_adc_ids[] = { 1429 { 1430 .name = "at91sam9260-adc", 1431 .driver_data = (unsigned long)&at91sam9260_caps, 1432 }, { 1433 .name = "at91sam9rl-adc", 1434 .driver_data = (unsigned long)&at91sam9rl_caps, 1435 }, { 1436 .name = "at91sam9g45-adc", 1437 .driver_data = (unsigned long)&at91sam9g45_caps, 1438 }, { 1439 .name = "at91sam9x5-adc", 1440 .driver_data = (unsigned long)&at91sam9x5_caps, 1441 }, { 1442 /* terminator */ 1443 } 1444 }; 1445 MODULE_DEVICE_TABLE(platform, at91_adc_ids); 1446 1447 static struct platform_driver at91_adc_driver = { 1448 .probe = at91_adc_probe, 1449 .remove = at91_adc_remove, 1450 .id_table = at91_adc_ids, 1451 .driver = { 1452 .name = DRIVER_NAME, 1453 .of_match_table = at91_adc_dt_ids, 1454 .pm = &at91_adc_pm_ops, 1455 }, 1456 }; 1457 1458 module_platform_driver(at91_adc_driver); 1459 1460 MODULE_LICENSE("GPL"); 1461 MODULE_DESCRIPTION("Atmel AT91 ADC Driver"); 1462 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1463