xref: /openbmc/linux/drivers/iio/adc/at91_adc.c (revision f21e49be)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Driver for the ADC present in the Atmel AT91 evaluation boards.
4  *
5  * Copyright 2011 Free Electrons
6  */
7 
8 #include <linux/bitmap.h>
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/err.h>
12 #include <linux/io.h>
13 #include <linux/input.h>
14 #include <linux/interrupt.h>
15 #include <linux/jiffies.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/sched.h>
22 #include <linux/slab.h>
23 #include <linux/wait.h>
24 
25 #include <linux/iio/iio.h>
26 #include <linux/iio/buffer.h>
27 #include <linux/iio/trigger.h>
28 #include <linux/iio/trigger_consumer.h>
29 #include <linux/iio/triggered_buffer.h>
30 #include <linux/pinctrl/consumer.h>
31 
32 /* Registers */
33 #define AT91_ADC_CR		0x00		/* Control Register */
34 #define		AT91_ADC_SWRST		(1 << 0)	/* Software Reset */
35 #define		AT91_ADC_START		(1 << 1)	/* Start Conversion */
36 
37 #define AT91_ADC_MR		0x04		/* Mode Register */
38 #define		AT91_ADC_TSAMOD		(3 << 0)	/* ADC mode */
39 #define		AT91_ADC_TSAMOD_ADC_ONLY_MODE		(0 << 0)	/* ADC Mode */
40 #define		AT91_ADC_TSAMOD_TS_ONLY_MODE		(1 << 0)	/* Touch Screen Only Mode */
41 #define		AT91_ADC_TRGEN		(1 << 0)	/* Trigger Enable */
42 #define		AT91_ADC_TRGSEL		(7 << 1)	/* Trigger Selection */
43 #define			AT91_ADC_TRGSEL_TC0		(0 << 1)
44 #define			AT91_ADC_TRGSEL_TC1		(1 << 1)
45 #define			AT91_ADC_TRGSEL_TC2		(2 << 1)
46 #define			AT91_ADC_TRGSEL_EXTERNAL	(6 << 1)
47 #define		AT91_ADC_LOWRES		(1 << 4)	/* Low Resolution */
48 #define		AT91_ADC_SLEEP		(1 << 5)	/* Sleep Mode */
49 #define		AT91_ADC_PENDET		(1 << 6)	/* Pen contact detection enable */
50 #define		AT91_ADC_PRESCAL_9260	(0x3f << 8)	/* Prescalar Rate Selection */
51 #define		AT91_ADC_PRESCAL_9G45	(0xff << 8)
52 #define			AT91_ADC_PRESCAL_(x)	((x) << 8)
53 #define		AT91_ADC_STARTUP_9260	(0x1f << 16)	/* Startup Up Time */
54 #define		AT91_ADC_STARTUP_9G45	(0x7f << 16)
55 #define		AT91_ADC_STARTUP_9X5	(0xf << 16)
56 #define			AT91_ADC_STARTUP_(x)	((x) << 16)
57 #define		AT91_ADC_SHTIM		(0xf  << 24)	/* Sample & Hold Time */
58 #define			AT91_ADC_SHTIM_(x)	((x) << 24)
59 #define		AT91_ADC_PENDBC		(0x0f << 28)	/* Pen Debounce time */
60 #define			AT91_ADC_PENDBC_(x)	((x) << 28)
61 
62 #define AT91_ADC_TSR		0x0C
63 #define		AT91_ADC_TSR_SHTIM	(0xf  << 24)	/* Sample & Hold Time */
64 #define			AT91_ADC_TSR_SHTIM_(x)	((x) << 24)
65 
66 #define AT91_ADC_CHER		0x10		/* Channel Enable Register */
67 #define AT91_ADC_CHDR		0x14		/* Channel Disable Register */
68 #define AT91_ADC_CHSR		0x18		/* Channel Status Register */
69 #define		AT91_ADC_CH(n)		(1 << (n))	/* Channel Number */
70 
71 #define AT91_ADC_SR		0x1C		/* Status Register */
72 #define		AT91_ADC_EOC(n)		(1 << (n))	/* End of Conversion on Channel N */
73 #define		AT91_ADC_OVRE(n)	(1 << ((n) + 8))/* Overrun Error on Channel N */
74 #define		AT91_ADC_DRDY		(1 << 16)	/* Data Ready */
75 #define		AT91_ADC_GOVRE		(1 << 17)	/* General Overrun Error */
76 #define		AT91_ADC_ENDRX		(1 << 18)	/* End of RX Buffer */
77 #define		AT91_ADC_RXFUFF		(1 << 19)	/* RX Buffer Full */
78 
79 #define AT91_ADC_SR_9X5		0x30		/* Status Register for 9x5 */
80 #define		AT91_ADC_SR_DRDY_9X5	(1 << 24)	/* Data Ready */
81 
82 #define AT91_ADC_LCDR		0x20		/* Last Converted Data Register */
83 #define		AT91_ADC_LDATA		(0x3ff)
84 
85 #define AT91_ADC_IER		0x24		/* Interrupt Enable Register */
86 #define AT91_ADC_IDR		0x28		/* Interrupt Disable Register */
87 #define AT91_ADC_IMR		0x2C		/* Interrupt Mask Register */
88 #define		AT91RL_ADC_IER_PEN	(1 << 20)
89 #define		AT91RL_ADC_IER_NOPEN	(1 << 21)
90 #define		AT91_ADC_IER_PEN	(1 << 29)
91 #define		AT91_ADC_IER_NOPEN	(1 << 30)
92 #define		AT91_ADC_IER_XRDY	(1 << 20)
93 #define		AT91_ADC_IER_YRDY	(1 << 21)
94 #define		AT91_ADC_IER_PRDY	(1 << 22)
95 #define		AT91_ADC_ISR_PENS	(1 << 31)
96 
97 #define AT91_ADC_CHR(n)		(0x30 + ((n) * 4))	/* Channel Data Register N */
98 #define		AT91_ADC_DATA		(0x3ff)
99 
100 #define AT91_ADC_CDR0_9X5	(0x50)			/* Channel Data Register 0 for 9X5 */
101 
102 #define AT91_ADC_ACR		0x94	/* Analog Control Register */
103 #define		AT91_ADC_ACR_PENDETSENS	(0x3 << 0)	/* pull-up resistor */
104 
105 #define AT91_ADC_TSMR		0xB0
106 #define		AT91_ADC_TSMR_TSMODE	(3 << 0)	/* Touch Screen Mode */
107 #define			AT91_ADC_TSMR_TSMODE_NONE		(0 << 0)
108 #define			AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS	(1 << 0)
109 #define			AT91_ADC_TSMR_TSMODE_4WIRE_PRESS	(2 << 0)
110 #define			AT91_ADC_TSMR_TSMODE_5WIRE		(3 << 0)
111 #define		AT91_ADC_TSMR_TSAV	(3 << 4)	/* Averages samples */
112 #define			AT91_ADC_TSMR_TSAV_(x)		((x) << 4)
113 #define		AT91_ADC_TSMR_SCTIM	(0x0f << 16)	/* Switch closure time */
114 #define			AT91_ADC_TSMR_SCTIM_(x)		((x) << 16)
115 #define		AT91_ADC_TSMR_PENDBC	(0x0f << 28)	/* Pen Debounce time */
116 #define			AT91_ADC_TSMR_PENDBC_(x)	((x) << 28)
117 #define		AT91_ADC_TSMR_NOTSDMA	(1 << 22)	/* No Touchscreen DMA */
118 #define		AT91_ADC_TSMR_PENDET_DIS	(0 << 24)	/* Pen contact detection disable */
119 #define		AT91_ADC_TSMR_PENDET_ENA	(1 << 24)	/* Pen contact detection enable */
120 
121 #define AT91_ADC_TSXPOSR	0xB4
122 #define AT91_ADC_TSYPOSR	0xB8
123 #define AT91_ADC_TSPRESSR	0xBC
124 
125 #define AT91_ADC_TRGR_9260	AT91_ADC_MR
126 #define AT91_ADC_TRGR_9G45	0x08
127 #define AT91_ADC_TRGR_9X5	0xC0
128 
129 /* Trigger Register bit field */
130 #define		AT91_ADC_TRGR_TRGPER	(0xffff << 16)
131 #define			AT91_ADC_TRGR_TRGPER_(x)	((x) << 16)
132 #define		AT91_ADC_TRGR_TRGMOD	(0x7 << 0)
133 #define			AT91_ADC_TRGR_NONE		(0 << 0)
134 #define			AT91_ADC_TRGR_MOD_PERIOD_TRIG	(5 << 0)
135 
136 #define AT91_ADC_CHAN(st, ch) \
137 	(st->registers->channel_base + (ch * 4))
138 #define at91_adc_readl(st, reg) \
139 	(readl_relaxed(st->reg_base + reg))
140 #define at91_adc_writel(st, reg, val) \
141 	(writel_relaxed(val, st->reg_base + reg))
142 
143 #define DRIVER_NAME		"at91_adc"
144 #define MAX_POS_BITS		12
145 
146 #define TOUCH_SAMPLE_PERIOD_US		2000	/* 2ms */
147 #define TOUCH_PEN_DETECT_DEBOUNCE_US	200
148 
149 #define MAX_RLPOS_BITS         10
150 #define TOUCH_SAMPLE_PERIOD_US_RL      10000   /* 10ms, the SoC can't keep up with 2ms */
151 #define TOUCH_SHTIM                    0xa
152 #define TOUCH_SCTIM_US		10		/* 10us for the Touchscreen Switches Closure Time */
153 
154 enum atmel_adc_ts_type {
155 	ATMEL_ADC_TOUCHSCREEN_NONE = 0,
156 	ATMEL_ADC_TOUCHSCREEN_4WIRE = 4,
157 	ATMEL_ADC_TOUCHSCREEN_5WIRE = 5,
158 };
159 
160 /**
161  * struct at91_adc_trigger - description of triggers
162  * @name:		name of the trigger advertised to the user
163  * @value:		value to set in the ADC's trigger setup register
164  *			to enable the trigger
165  * @is_external:	Does the trigger rely on an external pin?
166  */
167 struct at91_adc_trigger {
168 	const char	*name;
169 	u8		value;
170 	bool		is_external;
171 };
172 
173 /**
174  * struct at91_adc_reg_desc - Various informations relative to registers
175  * @channel_base:	Base offset for the channel data registers
176  * @drdy_mask:		Mask of the DRDY field in the relevant registers
177  *			(Interruptions registers mostly)
178  * @status_register:	Offset of the Interrupt Status Register
179  * @trigger_register:	Offset of the Trigger setup register
180  * @mr_prescal_mask:	Mask of the PRESCAL field in the adc MR register
181  * @mr_startup_mask:	Mask of the STARTUP field in the adc MR register
182  */
183 struct at91_adc_reg_desc {
184 	u8	channel_base;
185 	u32	drdy_mask;
186 	u8	status_register;
187 	u8	trigger_register;
188 	u32	mr_prescal_mask;
189 	u32	mr_startup_mask;
190 };
191 
192 struct at91_adc_caps {
193 	bool	has_ts;		/* Support touch screen */
194 	bool	has_tsmr;	/* only at91sam9x5, sama5d3 have TSMR reg */
195 	/*
196 	 * Numbers of sampling data will be averaged. Can be 0~3.
197 	 * Hardware can average (2 ^ ts_filter_average) sample data.
198 	 */
199 	u8	ts_filter_average;
200 	/* Pen Detection input pull-up resistor, can be 0~3 */
201 	u8	ts_pen_detect_sensitivity;
202 
203 	/* startup time calculate function */
204 	u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz);
205 
206 	u8	num_channels;
207 
208 	u8	low_res_bits;
209 	u8	high_res_bits;
210 	u32	trigger_number;
211 	const struct at91_adc_trigger *triggers;
212 	struct at91_adc_reg_desc registers;
213 };
214 
215 struct at91_adc_state {
216 	struct clk		*adc_clk;
217 	u16			*buffer;
218 	unsigned long		channels_mask;
219 	struct clk		*clk;
220 	bool			done;
221 	int			irq;
222 	u16			last_value;
223 	int			chnb;
224 	struct mutex		lock;
225 	u8			num_channels;
226 	void __iomem		*reg_base;
227 	const struct at91_adc_reg_desc *registers;
228 	u32			startup_time;
229 	u8			sample_hold_time;
230 	bool			sleep_mode;
231 	struct iio_trigger	**trig;
232 	bool			use_external;
233 	u32			vref_mv;
234 	u32			res;		/* resolution used for convertions */
235 	wait_queue_head_t	wq_data_avail;
236 	const struct at91_adc_caps	*caps;
237 
238 	/*
239 	 * Following ADC channels are shared by touchscreen:
240 	 *
241 	 * CH0 -- Touch screen XP/UL
242 	 * CH1 -- Touch screen XM/UR
243 	 * CH2 -- Touch screen YP/LL
244 	 * CH3 -- Touch screen YM/Sense
245 	 * CH4 -- Touch screen LR(5-wire only)
246 	 *
247 	 * The bitfields below represents the reserved channel in the
248 	 * touchscreen mode.
249 	 */
250 #define CHAN_MASK_TOUCHSCREEN_4WIRE	(0xf << 0)
251 #define CHAN_MASK_TOUCHSCREEN_5WIRE	(0x1f << 0)
252 	enum atmel_adc_ts_type	touchscreen_type;
253 	struct input_dev	*ts_input;
254 
255 	u16			ts_sample_period_val;
256 	u32			ts_pressure_threshold;
257 	u16			ts_pendbc;
258 
259 	bool			ts_bufferedmeasure;
260 	u32			ts_prev_absx;
261 	u32			ts_prev_absy;
262 };
263 
264 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
265 {
266 	struct iio_poll_func *pf = p;
267 	struct iio_dev *idev = pf->indio_dev;
268 	struct at91_adc_state *st = iio_priv(idev);
269 	struct iio_chan_spec const *chan;
270 	int i, j = 0;
271 
272 	for (i = 0; i < idev->masklength; i++) {
273 		if (!test_bit(i, idev->active_scan_mask))
274 			continue;
275 		chan = idev->channels + i;
276 		st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, chan->channel));
277 		j++;
278 	}
279 
280 	iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp);
281 
282 	iio_trigger_notify_done(idev->trig);
283 
284 	/* Needed to ACK the DRDY interruption */
285 	at91_adc_readl(st, AT91_ADC_LCDR);
286 
287 	enable_irq(st->irq);
288 
289 	return IRQ_HANDLED;
290 }
291 
292 /* Handler for classic adc channel eoc trigger */
293 static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev)
294 {
295 	struct at91_adc_state *st = iio_priv(idev);
296 
297 	if (iio_buffer_enabled(idev)) {
298 		disable_irq_nosync(irq);
299 		iio_trigger_poll(idev->trig);
300 	} else {
301 		st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb));
302 		/* Needed to ACK the DRDY interruption */
303 		at91_adc_readl(st, AT91_ADC_LCDR);
304 		st->done = true;
305 		wake_up_interruptible(&st->wq_data_avail);
306 	}
307 }
308 
309 static int at91_ts_sample(struct iio_dev *idev)
310 {
311 	struct at91_adc_state *st = iio_priv(idev);
312 	unsigned int xscale, yscale, reg, z1, z2;
313 	unsigned int x, y, pres, xpos, ypos;
314 	unsigned int rxp = 1;
315 	unsigned int factor = 1000;
316 
317 	unsigned int xyz_mask_bits = st->res;
318 	unsigned int xyz_mask = (1 << xyz_mask_bits) - 1;
319 
320 	/* calculate position */
321 	/* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */
322 	reg = at91_adc_readl(st, AT91_ADC_TSXPOSR);
323 	xpos = reg & xyz_mask;
324 	x = (xpos << MAX_POS_BITS) - xpos;
325 	xscale = (reg >> 16) & xyz_mask;
326 	if (xscale == 0) {
327 		dev_err(&idev->dev, "Error: xscale == 0!\n");
328 		return -1;
329 	}
330 	x /= xscale;
331 
332 	/* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */
333 	reg = at91_adc_readl(st, AT91_ADC_TSYPOSR);
334 	ypos = reg & xyz_mask;
335 	y = (ypos << MAX_POS_BITS) - ypos;
336 	yscale = (reg >> 16) & xyz_mask;
337 	if (yscale == 0) {
338 		dev_err(&idev->dev, "Error: yscale == 0!\n");
339 		return -1;
340 	}
341 	y /= yscale;
342 
343 	/* calculate the pressure */
344 	reg = at91_adc_readl(st, AT91_ADC_TSPRESSR);
345 	z1 = reg & xyz_mask;
346 	z2 = (reg >> 16) & xyz_mask;
347 
348 	if (z1 != 0)
349 		pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor)
350 			/ factor;
351 	else
352 		pres = st->ts_pressure_threshold;	/* no pen contacted */
353 
354 	dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n",
355 				xpos, xscale, ypos, yscale, z1, z2, pres);
356 
357 	if (pres < st->ts_pressure_threshold) {
358 		dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n",
359 					x, y, pres / factor);
360 		input_report_abs(st->ts_input, ABS_X, x);
361 		input_report_abs(st->ts_input, ABS_Y, y);
362 		input_report_abs(st->ts_input, ABS_PRESSURE, pres);
363 		input_report_key(st->ts_input, BTN_TOUCH, 1);
364 		input_sync(st->ts_input);
365 	} else {
366 		dev_dbg(&idev->dev, "pressure too low: not reporting\n");
367 	}
368 
369 	return 0;
370 }
371 
372 static irqreturn_t at91_adc_rl_interrupt(int irq, void *private)
373 {
374 	struct iio_dev *idev = private;
375 	struct at91_adc_state *st = iio_priv(idev);
376 	u32 status = at91_adc_readl(st, st->registers->status_register);
377 	unsigned int reg;
378 
379 	status &= at91_adc_readl(st, AT91_ADC_IMR);
380 	if (status & GENMASK(st->num_channels - 1, 0))
381 		handle_adc_eoc_trigger(irq, idev);
382 
383 	if (status & AT91RL_ADC_IER_PEN) {
384 		/* Disabling pen debounce is required to get a NOPEN irq */
385 		reg = at91_adc_readl(st, AT91_ADC_MR);
386 		reg &= ~AT91_ADC_PENDBC;
387 		at91_adc_writel(st, AT91_ADC_MR, reg);
388 
389 		at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
390 		at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN
391 				| AT91_ADC_EOC(3));
392 		/* Set up period trigger for sampling */
393 		at91_adc_writel(st, st->registers->trigger_register,
394 			AT91_ADC_TRGR_MOD_PERIOD_TRIG |
395 			AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
396 	} else if (status & AT91RL_ADC_IER_NOPEN) {
397 		reg = at91_adc_readl(st, AT91_ADC_MR);
398 		reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
399 		at91_adc_writel(st, AT91_ADC_MR, reg);
400 		at91_adc_writel(st, st->registers->trigger_register,
401 			AT91_ADC_TRGR_NONE);
402 
403 		at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN
404 				| AT91_ADC_EOC(3));
405 		at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
406 		st->ts_bufferedmeasure = false;
407 		input_report_key(st->ts_input, BTN_TOUCH, 0);
408 		input_sync(st->ts_input);
409 	} else if (status & AT91_ADC_EOC(3) && st->ts_input) {
410 		/* Conversion finished and we've a touchscreen */
411 		if (st->ts_bufferedmeasure) {
412 			/*
413 			 * Last measurement is always discarded, since it can
414 			 * be erroneous.
415 			 * Always report previous measurement
416 			 */
417 			input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx);
418 			input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy);
419 			input_report_key(st->ts_input, BTN_TOUCH, 1);
420 			input_sync(st->ts_input);
421 		} else
422 			st->ts_bufferedmeasure = true;
423 
424 		/* Now make new measurement */
425 		st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3))
426 				   << MAX_RLPOS_BITS;
427 		st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2));
428 
429 		st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1))
430 				   << MAX_RLPOS_BITS;
431 		st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0));
432 	}
433 
434 	return IRQ_HANDLED;
435 }
436 
437 static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private)
438 {
439 	struct iio_dev *idev = private;
440 	struct at91_adc_state *st = iio_priv(idev);
441 	u32 status = at91_adc_readl(st, st->registers->status_register);
442 	const uint32_t ts_data_irq_mask =
443 		AT91_ADC_IER_XRDY |
444 		AT91_ADC_IER_YRDY |
445 		AT91_ADC_IER_PRDY;
446 
447 	if (status & GENMASK(st->num_channels - 1, 0))
448 		handle_adc_eoc_trigger(irq, idev);
449 
450 	if (status & AT91_ADC_IER_PEN) {
451 		at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
452 		at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN |
453 			ts_data_irq_mask);
454 		/* Set up period trigger for sampling */
455 		at91_adc_writel(st, st->registers->trigger_register,
456 			AT91_ADC_TRGR_MOD_PERIOD_TRIG |
457 			AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
458 	} else if (status & AT91_ADC_IER_NOPEN) {
459 		at91_adc_writel(st, st->registers->trigger_register, 0);
460 		at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN |
461 			ts_data_irq_mask);
462 		at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
463 
464 		input_report_key(st->ts_input, BTN_TOUCH, 0);
465 		input_sync(st->ts_input);
466 	} else if ((status & ts_data_irq_mask) == ts_data_irq_mask) {
467 		/* Now all touchscreen data is ready */
468 
469 		if (status & AT91_ADC_ISR_PENS) {
470 			/* validate data by pen contact */
471 			at91_ts_sample(idev);
472 		} else {
473 			/* triggered by event that is no pen contact, just read
474 			 * them to clean the interrupt and discard all.
475 			 */
476 			at91_adc_readl(st, AT91_ADC_TSXPOSR);
477 			at91_adc_readl(st, AT91_ADC_TSYPOSR);
478 			at91_adc_readl(st, AT91_ADC_TSPRESSR);
479 		}
480 	}
481 
482 	return IRQ_HANDLED;
483 }
484 
485 static int at91_adc_channel_init(struct iio_dev *idev)
486 {
487 	struct at91_adc_state *st = iio_priv(idev);
488 	struct iio_chan_spec *chan_array, *timestamp;
489 	int bit, idx = 0;
490 	unsigned long rsvd_mask = 0;
491 
492 	/* If touchscreen is enable, then reserve the adc channels */
493 	if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
494 		rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE;
495 	else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE)
496 		rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE;
497 
498 	/* set up the channel mask to reserve touchscreen channels */
499 	st->channels_mask &= ~rsvd_mask;
500 
501 	idev->num_channels = bitmap_weight(&st->channels_mask,
502 					   st->num_channels) + 1;
503 
504 	chan_array = devm_kzalloc(&idev->dev,
505 				  ((idev->num_channels + 1) *
506 					sizeof(struct iio_chan_spec)),
507 				  GFP_KERNEL);
508 
509 	if (!chan_array)
510 		return -ENOMEM;
511 
512 	for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
513 		struct iio_chan_spec *chan = chan_array + idx;
514 
515 		chan->type = IIO_VOLTAGE;
516 		chan->indexed = 1;
517 		chan->channel = bit;
518 		chan->scan_index = idx;
519 		chan->scan_type.sign = 'u';
520 		chan->scan_type.realbits = st->res;
521 		chan->scan_type.storagebits = 16;
522 		chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
523 		chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
524 		idx++;
525 	}
526 	timestamp = chan_array + idx;
527 
528 	timestamp->type = IIO_TIMESTAMP;
529 	timestamp->channel = -1;
530 	timestamp->scan_index = idx;
531 	timestamp->scan_type.sign = 's';
532 	timestamp->scan_type.realbits = 64;
533 	timestamp->scan_type.storagebits = 64;
534 
535 	idev->channels = chan_array;
536 	return idev->num_channels;
537 }
538 
539 static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
540 					     const struct at91_adc_trigger *triggers,
541 					     const char *trigger_name)
542 {
543 	struct at91_adc_state *st = iio_priv(idev);
544 	int i;
545 
546 	for (i = 0; i < st->caps->trigger_number; i++) {
547 		char *name = kasprintf(GFP_KERNEL,
548 				"%s-dev%d-%s",
549 				idev->name,
550 				iio_device_id(idev),
551 				triggers[i].name);
552 		if (!name)
553 			return -ENOMEM;
554 
555 		if (strcmp(trigger_name, name) == 0) {
556 			kfree(name);
557 			if (triggers[i].value == 0)
558 				return -EINVAL;
559 			return triggers[i].value;
560 		}
561 
562 		kfree(name);
563 	}
564 
565 	return -EINVAL;
566 }
567 
568 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
569 {
570 	struct iio_dev *idev = iio_trigger_get_drvdata(trig);
571 	struct at91_adc_state *st = iio_priv(idev);
572 	const struct at91_adc_reg_desc *reg = st->registers;
573 	u32 status = at91_adc_readl(st, reg->trigger_register);
574 	int value;
575 	u8 bit;
576 
577 	value = at91_adc_get_trigger_value_by_name(idev,
578 						   st->caps->triggers,
579 						   idev->trig->name);
580 	if (value < 0)
581 		return value;
582 
583 	if (state) {
584 		st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
585 		if (st->buffer == NULL)
586 			return -ENOMEM;
587 
588 		at91_adc_writel(st, reg->trigger_register,
589 				status | value);
590 
591 		for_each_set_bit(bit, idev->active_scan_mask,
592 				 st->num_channels) {
593 			struct iio_chan_spec const *chan = idev->channels + bit;
594 			at91_adc_writel(st, AT91_ADC_CHER,
595 					AT91_ADC_CH(chan->channel));
596 		}
597 
598 		at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
599 
600 	} else {
601 		at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
602 
603 		at91_adc_writel(st, reg->trigger_register,
604 				status & ~value);
605 
606 		for_each_set_bit(bit, idev->active_scan_mask,
607 				 st->num_channels) {
608 			struct iio_chan_spec const *chan = idev->channels + bit;
609 			at91_adc_writel(st, AT91_ADC_CHDR,
610 					AT91_ADC_CH(chan->channel));
611 		}
612 		kfree(st->buffer);
613 	}
614 
615 	return 0;
616 }
617 
618 static const struct iio_trigger_ops at91_adc_trigger_ops = {
619 	.set_trigger_state = &at91_adc_configure_trigger,
620 };
621 
622 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
623 						     const struct at91_adc_trigger *trigger)
624 {
625 	struct iio_trigger *trig;
626 	int ret;
627 
628 	trig = iio_trigger_alloc(idev->dev.parent, "%s-dev%d-%s", idev->name,
629 				 iio_device_id(idev), trigger->name);
630 	if (trig == NULL)
631 		return NULL;
632 
633 	iio_trigger_set_drvdata(trig, idev);
634 	trig->ops = &at91_adc_trigger_ops;
635 
636 	ret = iio_trigger_register(trig);
637 	if (ret)
638 		return NULL;
639 
640 	return trig;
641 }
642 
643 static int at91_adc_trigger_init(struct iio_dev *idev)
644 {
645 	struct at91_adc_state *st = iio_priv(idev);
646 	int i, ret;
647 
648 	st->trig = devm_kcalloc(&idev->dev,
649 				st->caps->trigger_number, sizeof(*st->trig),
650 				GFP_KERNEL);
651 
652 	if (st->trig == NULL) {
653 		ret = -ENOMEM;
654 		goto error_ret;
655 	}
656 
657 	for (i = 0; i < st->caps->trigger_number; i++) {
658 		if (st->caps->triggers[i].is_external && !(st->use_external))
659 			continue;
660 
661 		st->trig[i] = at91_adc_allocate_trigger(idev,
662 							st->caps->triggers + i);
663 		if (st->trig[i] == NULL) {
664 			dev_err(&idev->dev,
665 				"Could not allocate trigger %d\n", i);
666 			ret = -ENOMEM;
667 			goto error_trigger;
668 		}
669 	}
670 
671 	return 0;
672 
673 error_trigger:
674 	for (i--; i >= 0; i--) {
675 		iio_trigger_unregister(st->trig[i]);
676 		iio_trigger_free(st->trig[i]);
677 	}
678 error_ret:
679 	return ret;
680 }
681 
682 static void at91_adc_trigger_remove(struct iio_dev *idev)
683 {
684 	struct at91_adc_state *st = iio_priv(idev);
685 	int i;
686 
687 	for (i = 0; i < st->caps->trigger_number; i++) {
688 		iio_trigger_unregister(st->trig[i]);
689 		iio_trigger_free(st->trig[i]);
690 	}
691 }
692 
693 static int at91_adc_buffer_init(struct iio_dev *idev)
694 {
695 	return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
696 		&at91_adc_trigger_handler, NULL);
697 }
698 
699 static void at91_adc_buffer_remove(struct iio_dev *idev)
700 {
701 	iio_triggered_buffer_cleanup(idev);
702 }
703 
704 static int at91_adc_read_raw(struct iio_dev *idev,
705 			     struct iio_chan_spec const *chan,
706 			     int *val, int *val2, long mask)
707 {
708 	struct at91_adc_state *st = iio_priv(idev);
709 	int ret;
710 
711 	switch (mask) {
712 	case IIO_CHAN_INFO_RAW:
713 		mutex_lock(&st->lock);
714 
715 		st->chnb = chan->channel;
716 		at91_adc_writel(st, AT91_ADC_CHER,
717 				AT91_ADC_CH(chan->channel));
718 		at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel));
719 		at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
720 
721 		ret = wait_event_interruptible_timeout(st->wq_data_avail,
722 						       st->done,
723 						       msecs_to_jiffies(1000));
724 
725 		/* Disable interrupts, regardless if adc conversion was
726 		 * successful or not
727 		 */
728 		at91_adc_writel(st, AT91_ADC_CHDR,
729 				AT91_ADC_CH(chan->channel));
730 		at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel));
731 
732 		if (ret > 0) {
733 			/* a valid conversion took place */
734 			*val = st->last_value;
735 			st->last_value = 0;
736 			st->done = false;
737 			ret = IIO_VAL_INT;
738 		} else if (ret == 0) {
739 			/* conversion timeout */
740 			dev_err(&idev->dev, "ADC Channel %d timeout.\n",
741 				chan->channel);
742 			ret = -ETIMEDOUT;
743 		}
744 
745 		mutex_unlock(&st->lock);
746 		return ret;
747 
748 	case IIO_CHAN_INFO_SCALE:
749 		*val = st->vref_mv;
750 		*val2 = chan->scan_type.realbits;
751 		return IIO_VAL_FRACTIONAL_LOG2;
752 	default:
753 		break;
754 	}
755 	return -EINVAL;
756 }
757 
758 
759 static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz)
760 {
761 	/*
762 	 * Number of ticks needed to cover the startup time of the ADC
763 	 * as defined in the electrical characteristics of the board,
764 	 * divided by 8. The formula thus is :
765 	 *   Startup Time = (ticks + 1) * 8 / ADC Clock
766 	 */
767 	return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8;
768 }
769 
770 static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz)
771 {
772 	/*
773 	 * For sama5d3x and at91sam9x5, the formula changes to:
774 	 * Startup Time = <lookup_table_value> / ADC Clock
775 	 */
776 	static const int startup_lookup[] = {
777 		0,   8,   16,  24,
778 		64,  80,  96,  112,
779 		512, 576, 640, 704,
780 		768, 832, 896, 960
781 		};
782 	int i, size = ARRAY_SIZE(startup_lookup);
783 	unsigned int ticks;
784 
785 	ticks = startup_time * adc_clk_khz / 1000;
786 	for (i = 0; i < size; i++)
787 		if (ticks < startup_lookup[i])
788 			break;
789 
790 	ticks = i;
791 	if (ticks == size)
792 		/* Reach the end of lookup table */
793 		ticks = size - 1;
794 
795 	return ticks;
796 }
797 
798 static int at91_adc_probe_dt_ts(struct device_node *node,
799 	struct at91_adc_state *st, struct device *dev)
800 {
801 	int ret;
802 	u32 prop;
803 
804 	ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop);
805 	if (ret) {
806 		dev_info(dev, "ADC Touch screen is disabled.\n");
807 		return 0;
808 	}
809 
810 	switch (prop) {
811 	case 4:
812 	case 5:
813 		st->touchscreen_type = prop;
814 		break;
815 	default:
816 		dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop);
817 		return -EINVAL;
818 	}
819 
820 	if (!st->caps->has_tsmr)
821 		return 0;
822 	prop = 0;
823 	of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop);
824 	st->ts_pressure_threshold = prop;
825 	if (st->ts_pressure_threshold) {
826 		return 0;
827 	} else {
828 		dev_err(dev, "Invalid pressure threshold for the touchscreen\n");
829 		return -EINVAL;
830 	}
831 }
832 
833 static const struct iio_info at91_adc_info = {
834 	.read_raw = &at91_adc_read_raw,
835 };
836 
837 /* Touchscreen related functions */
838 static int atmel_ts_open(struct input_dev *dev)
839 {
840 	struct at91_adc_state *st = input_get_drvdata(dev);
841 
842 	if (st->caps->has_tsmr)
843 		at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
844 	else
845 		at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
846 	return 0;
847 }
848 
849 static void atmel_ts_close(struct input_dev *dev)
850 {
851 	struct at91_adc_state *st = input_get_drvdata(dev);
852 
853 	if (st->caps->has_tsmr)
854 		at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
855 	else
856 		at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
857 }
858 
859 static int at91_ts_hw_init(struct iio_dev *idev, u32 adc_clk_khz)
860 {
861 	struct at91_adc_state *st = iio_priv(idev);
862 	u32 reg = 0;
863 	u32 tssctim = 0;
864 	int i = 0;
865 
866 	/* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid
867 	 * pen detect noise.
868 	 * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock
869 	 */
870 	st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz /
871 				 1000, 1);
872 
873 	while (st->ts_pendbc >> ++i)
874 		;	/* Empty! Find the shift offset */
875 	if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1))))
876 		st->ts_pendbc = i;
877 	else
878 		st->ts_pendbc = i - 1;
879 
880 	if (!st->caps->has_tsmr) {
881 		reg = at91_adc_readl(st, AT91_ADC_MR);
882 		reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET;
883 
884 		reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
885 		at91_adc_writel(st, AT91_ADC_MR, reg);
886 
887 		reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM;
888 		at91_adc_writel(st, AT91_ADC_TSR, reg);
889 
890 		st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL *
891 						    adc_clk_khz / 1000) - 1, 1);
892 
893 		return 0;
894 	}
895 
896 	/* Touchscreen Switches Closure time needed for allowing the value to
897 	 * stabilize.
898 	 * Switch Closure Time = (TSSCTIM * 4) ADCClock periods
899 	 */
900 	tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4);
901 	dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n",
902 		adc_clk_khz, tssctim);
903 
904 	if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
905 		reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS;
906 	else
907 		reg = AT91_ADC_TSMR_TSMODE_5WIRE;
908 
909 	reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM;
910 	reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average)
911 	       & AT91_ADC_TSMR_TSAV;
912 	reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC;
913 	reg |= AT91_ADC_TSMR_NOTSDMA;
914 	reg |= AT91_ADC_TSMR_PENDET_ENA;
915 	reg |= 0x03 << 8;	/* TSFREQ, needs to be bigger than TSAV */
916 
917 	at91_adc_writel(st, AT91_ADC_TSMR, reg);
918 
919 	/* Change adc internal resistor value for better pen detection,
920 	 * default value is 100 kOhm.
921 	 * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm
922 	 * option only available on ES2 and higher
923 	 */
924 	at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity
925 			& AT91_ADC_ACR_PENDETSENS);
926 
927 	/* Sample Period Time = (TRGPER + 1) / ADCClock */
928 	st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US *
929 			adc_clk_khz / 1000) - 1, 1);
930 
931 	return 0;
932 }
933 
934 static int at91_ts_register(struct iio_dev *idev,
935 		struct platform_device *pdev)
936 {
937 	struct at91_adc_state *st = iio_priv(idev);
938 	struct input_dev *input;
939 	int ret;
940 
941 	input = input_allocate_device();
942 	if (!input) {
943 		dev_err(&idev->dev, "Failed to allocate TS device!\n");
944 		return -ENOMEM;
945 	}
946 
947 	input->name = DRIVER_NAME;
948 	input->id.bustype = BUS_HOST;
949 	input->dev.parent = &pdev->dev;
950 	input->open = atmel_ts_open;
951 	input->close = atmel_ts_close;
952 
953 	__set_bit(EV_ABS, input->evbit);
954 	__set_bit(EV_KEY, input->evbit);
955 	__set_bit(BTN_TOUCH, input->keybit);
956 	if (st->caps->has_tsmr) {
957 		input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1,
958 				     0, 0);
959 		input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1,
960 				     0, 0);
961 		input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0);
962 	} else {
963 		if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) {
964 			dev_err(&pdev->dev,
965 				"This touchscreen controller only support 4 wires\n");
966 			ret = -EINVAL;
967 			goto err;
968 		}
969 
970 		input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1,
971 				     0, 0);
972 		input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1,
973 				     0, 0);
974 	}
975 
976 	st->ts_input = input;
977 	input_set_drvdata(input, st);
978 
979 	ret = input_register_device(input);
980 	if (ret)
981 		goto err;
982 
983 	return ret;
984 
985 err:
986 	input_free_device(st->ts_input);
987 	return ret;
988 }
989 
990 static void at91_ts_unregister(struct at91_adc_state *st)
991 {
992 	input_unregister_device(st->ts_input);
993 }
994 
995 static int at91_adc_probe(struct platform_device *pdev)
996 {
997 	unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
998 	struct device_node *node = pdev->dev.of_node;
999 	int ret;
1000 	struct iio_dev *idev;
1001 	struct at91_adc_state *st;
1002 	u32 reg, prop;
1003 	char *s;
1004 
1005 	idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state));
1006 	if (!idev)
1007 		return -ENOMEM;
1008 
1009 	st = iio_priv(idev);
1010 
1011 	st->caps = of_device_get_match_data(&pdev->dev);
1012 
1013 	st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
1014 
1015 	if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
1016 		dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
1017 		return -EINVAL;
1018 	}
1019 	st->channels_mask = prop;
1020 
1021 	st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode");
1022 
1023 	if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
1024 		dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
1025 		return -EINVAL;
1026 	}
1027 	st->startup_time = prop;
1028 
1029 	prop = 0;
1030 	of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop);
1031 	st->sample_hold_time = prop;
1032 
1033 	if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
1034 		dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
1035 		return -EINVAL;
1036 	}
1037 	st->vref_mv = prop;
1038 
1039 	st->res = st->caps->high_res_bits;
1040 	if (st->caps->low_res_bits &&
1041 	    !of_property_read_string(node, "atmel,adc-use-res", (const char **)&s)
1042 	    && !strcmp(s, "lowres"))
1043 		st->res = st->caps->low_res_bits;
1044 
1045 	dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
1046 
1047 	st->registers = &st->caps->registers;
1048 	st->num_channels = st->caps->num_channels;
1049 
1050 	/* Check if touchscreen is supported. */
1051 	if (st->caps->has_ts) {
1052 		ret = at91_adc_probe_dt_ts(node, st, &idev->dev);
1053 		if (ret)
1054 			return ret;
1055 	}
1056 
1057 	platform_set_drvdata(pdev, idev);
1058 
1059 	idev->name = dev_name(&pdev->dev);
1060 	idev->modes = INDIO_DIRECT_MODE;
1061 	idev->info = &at91_adc_info;
1062 
1063 	st->irq = platform_get_irq(pdev, 0);
1064 	if (st->irq < 0)
1065 		return -ENODEV;
1066 
1067 	st->reg_base = devm_platform_ioremap_resource(pdev, 0);
1068 	if (IS_ERR(st->reg_base))
1069 		return PTR_ERR(st->reg_base);
1070 
1071 
1072 	/*
1073 	 * Disable all IRQs before setting up the handler
1074 	 */
1075 	at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
1076 	at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
1077 
1078 	if (st->caps->has_tsmr)
1079 		ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0,
1080 				  pdev->dev.driver->name, idev);
1081 	else
1082 		ret = request_irq(st->irq, at91_adc_rl_interrupt, 0,
1083 				  pdev->dev.driver->name, idev);
1084 	if (ret) {
1085 		dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
1086 		return ret;
1087 	}
1088 
1089 	st->clk = devm_clk_get(&pdev->dev, "adc_clk");
1090 	if (IS_ERR(st->clk)) {
1091 		dev_err(&pdev->dev, "Failed to get the clock.\n");
1092 		ret = PTR_ERR(st->clk);
1093 		goto error_free_irq;
1094 	}
1095 
1096 	ret = clk_prepare_enable(st->clk);
1097 	if (ret) {
1098 		dev_err(&pdev->dev,
1099 			"Could not prepare or enable the clock.\n");
1100 		goto error_free_irq;
1101 	}
1102 
1103 	st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
1104 	if (IS_ERR(st->adc_clk)) {
1105 		dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
1106 		ret = PTR_ERR(st->adc_clk);
1107 		goto error_disable_clk;
1108 	}
1109 
1110 	ret = clk_prepare_enable(st->adc_clk);
1111 	if (ret) {
1112 		dev_err(&pdev->dev,
1113 			"Could not prepare or enable the ADC clock.\n");
1114 		goto error_disable_clk;
1115 	}
1116 
1117 	/*
1118 	 * Prescaler rate computation using the formula from the Atmel's
1119 	 * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
1120 	 * specified by the electrical characteristics of the board.
1121 	 */
1122 	mstrclk = clk_get_rate(st->clk);
1123 	adc_clk = clk_get_rate(st->adc_clk);
1124 	adc_clk_khz = adc_clk / 1000;
1125 
1126 	dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n",
1127 		mstrclk, adc_clk);
1128 
1129 	prsc = (mstrclk / (2 * adc_clk)) - 1;
1130 
1131 	if (!st->startup_time) {
1132 		dev_err(&pdev->dev, "No startup time available.\n");
1133 		ret = -EINVAL;
1134 		goto error_disable_adc_clk;
1135 	}
1136 	ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz);
1137 
1138 	/*
1139 	 * a minimal Sample and Hold Time is necessary for the ADC to guarantee
1140 	 * the best converted final value between two channels selection
1141 	 * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
1142 	 */
1143 	if (st->sample_hold_time > 0)
1144 		shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000)
1145 				 - 1, 1);
1146 	else
1147 		shtim = 0;
1148 
1149 	reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
1150 	reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
1151 	if (st->res == st->caps->low_res_bits)
1152 		reg |= AT91_ADC_LOWRES;
1153 	if (st->sleep_mode)
1154 		reg |= AT91_ADC_SLEEP;
1155 	reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM;
1156 	at91_adc_writel(st, AT91_ADC_MR, reg);
1157 
1158 	/* Setup the ADC channels available on the board */
1159 	ret = at91_adc_channel_init(idev);
1160 	if (ret < 0) {
1161 		dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
1162 		goto error_disable_adc_clk;
1163 	}
1164 
1165 	init_waitqueue_head(&st->wq_data_avail);
1166 	mutex_init(&st->lock);
1167 
1168 	/*
1169 	 * Since touch screen will set trigger register as period trigger. So
1170 	 * when touch screen is enabled, then we have to disable hardware
1171 	 * trigger for classic adc.
1172 	 */
1173 	if (!st->touchscreen_type) {
1174 		ret = at91_adc_buffer_init(idev);
1175 		if (ret < 0) {
1176 			dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
1177 			goto error_disable_adc_clk;
1178 		}
1179 
1180 		ret = at91_adc_trigger_init(idev);
1181 		if (ret < 0) {
1182 			dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
1183 			at91_adc_buffer_remove(idev);
1184 			goto error_disable_adc_clk;
1185 		}
1186 	} else {
1187 		ret = at91_ts_register(idev, pdev);
1188 		if (ret)
1189 			goto error_disable_adc_clk;
1190 
1191 		at91_ts_hw_init(idev, adc_clk_khz);
1192 	}
1193 
1194 	ret = iio_device_register(idev);
1195 	if (ret < 0) {
1196 		dev_err(&pdev->dev, "Couldn't register the device.\n");
1197 		goto error_iio_device_register;
1198 	}
1199 
1200 	return 0;
1201 
1202 error_iio_device_register:
1203 	if (!st->touchscreen_type) {
1204 		at91_adc_trigger_remove(idev);
1205 		at91_adc_buffer_remove(idev);
1206 	} else {
1207 		at91_ts_unregister(st);
1208 	}
1209 error_disable_adc_clk:
1210 	clk_disable_unprepare(st->adc_clk);
1211 error_disable_clk:
1212 	clk_disable_unprepare(st->clk);
1213 error_free_irq:
1214 	free_irq(st->irq, idev);
1215 	return ret;
1216 }
1217 
1218 static int at91_adc_remove(struct platform_device *pdev)
1219 {
1220 	struct iio_dev *idev = platform_get_drvdata(pdev);
1221 	struct at91_adc_state *st = iio_priv(idev);
1222 
1223 	iio_device_unregister(idev);
1224 	if (!st->touchscreen_type) {
1225 		at91_adc_trigger_remove(idev);
1226 		at91_adc_buffer_remove(idev);
1227 	} else {
1228 		at91_ts_unregister(st);
1229 	}
1230 	clk_disable_unprepare(st->adc_clk);
1231 	clk_disable_unprepare(st->clk);
1232 	free_irq(st->irq, idev);
1233 
1234 	return 0;
1235 }
1236 
1237 #ifdef CONFIG_PM_SLEEP
1238 static int at91_adc_suspend(struct device *dev)
1239 {
1240 	struct iio_dev *idev = dev_get_drvdata(dev);
1241 	struct at91_adc_state *st = iio_priv(idev);
1242 
1243 	pinctrl_pm_select_sleep_state(dev);
1244 	clk_disable_unprepare(st->clk);
1245 
1246 	return 0;
1247 }
1248 
1249 static int at91_adc_resume(struct device *dev)
1250 {
1251 	struct iio_dev *idev = dev_get_drvdata(dev);
1252 	struct at91_adc_state *st = iio_priv(idev);
1253 
1254 	clk_prepare_enable(st->clk);
1255 	pinctrl_pm_select_default_state(dev);
1256 
1257 	return 0;
1258 }
1259 #endif
1260 
1261 static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume);
1262 
1263 static const struct at91_adc_trigger at91sam9260_triggers[] = {
1264 	{ .name = "timer-counter-0", .value = 0x1 },
1265 	{ .name = "timer-counter-1", .value = 0x3 },
1266 	{ .name = "timer-counter-2", .value = 0x5 },
1267 	{ .name = "external", .value = 0xd, .is_external = true },
1268 };
1269 
1270 static struct at91_adc_caps at91sam9260_caps = {
1271 	.calc_startup_ticks = calc_startup_ticks_9260,
1272 	.num_channels = 4,
1273 	.low_res_bits = 8,
1274 	.high_res_bits = 10,
1275 	.registers = {
1276 		.channel_base = AT91_ADC_CHR(0),
1277 		.drdy_mask = AT91_ADC_DRDY,
1278 		.status_register = AT91_ADC_SR,
1279 		.trigger_register = AT91_ADC_TRGR_9260,
1280 		.mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1281 		.mr_startup_mask = AT91_ADC_STARTUP_9260,
1282 	},
1283 	.triggers = at91sam9260_triggers,
1284 	.trigger_number = ARRAY_SIZE(at91sam9260_triggers),
1285 };
1286 
1287 static const struct at91_adc_trigger at91sam9x5_triggers[] = {
1288 	{ .name = "external-rising", .value = 0x1, .is_external = true },
1289 	{ .name = "external-falling", .value = 0x2, .is_external = true },
1290 	{ .name = "external-any", .value = 0x3, .is_external = true },
1291 	{ .name = "continuous", .value = 0x6 },
1292 };
1293 
1294 static struct at91_adc_caps at91sam9rl_caps = {
1295 	.has_ts = true,
1296 	.calc_startup_ticks = calc_startup_ticks_9260,	/* same as 9260 */
1297 	.num_channels = 6,
1298 	.low_res_bits = 8,
1299 	.high_res_bits = 10,
1300 	.registers = {
1301 		.channel_base = AT91_ADC_CHR(0),
1302 		.drdy_mask = AT91_ADC_DRDY,
1303 		.status_register = AT91_ADC_SR,
1304 		.trigger_register = AT91_ADC_TRGR_9G45,
1305 		.mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1306 		.mr_startup_mask = AT91_ADC_STARTUP_9G45,
1307 	},
1308 	.triggers = at91sam9x5_triggers,
1309 	.trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
1310 };
1311 
1312 static struct at91_adc_caps at91sam9g45_caps = {
1313 	.has_ts = true,
1314 	.calc_startup_ticks = calc_startup_ticks_9260,	/* same as 9260 */
1315 	.num_channels = 8,
1316 	.low_res_bits = 8,
1317 	.high_res_bits = 10,
1318 	.registers = {
1319 		.channel_base = AT91_ADC_CHR(0),
1320 		.drdy_mask = AT91_ADC_DRDY,
1321 		.status_register = AT91_ADC_SR,
1322 		.trigger_register = AT91_ADC_TRGR_9G45,
1323 		.mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1324 		.mr_startup_mask = AT91_ADC_STARTUP_9G45,
1325 	},
1326 	.triggers = at91sam9x5_triggers,
1327 	.trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
1328 };
1329 
1330 static struct at91_adc_caps at91sam9x5_caps = {
1331 	.has_ts = true,
1332 	.has_tsmr = true,
1333 	.ts_filter_average = 3,
1334 	.ts_pen_detect_sensitivity = 2,
1335 	.calc_startup_ticks = calc_startup_ticks_9x5,
1336 	.num_channels = 12,
1337 	.low_res_bits = 8,
1338 	.high_res_bits = 10,
1339 	.registers = {
1340 		.channel_base = AT91_ADC_CDR0_9X5,
1341 		.drdy_mask = AT91_ADC_SR_DRDY_9X5,
1342 		.status_register = AT91_ADC_SR_9X5,
1343 		.trigger_register = AT91_ADC_TRGR_9X5,
1344 		/* prescal mask is same as 9G45 */
1345 		.mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1346 		.mr_startup_mask = AT91_ADC_STARTUP_9X5,
1347 	},
1348 	.triggers = at91sam9x5_triggers,
1349 	.trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
1350 };
1351 
1352 static struct at91_adc_caps sama5d3_caps = {
1353 	.has_ts = true,
1354 	.has_tsmr = true,
1355 	.ts_filter_average = 3,
1356 	.ts_pen_detect_sensitivity = 2,
1357 	.calc_startup_ticks = calc_startup_ticks_9x5,
1358 	.num_channels = 12,
1359 	.low_res_bits = 0,
1360 	.high_res_bits = 12,
1361 	.registers = {
1362 		.channel_base = AT91_ADC_CDR0_9X5,
1363 		.drdy_mask = AT91_ADC_SR_DRDY_9X5,
1364 		.status_register = AT91_ADC_SR_9X5,
1365 		.trigger_register = AT91_ADC_TRGR_9X5,
1366 		.mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1367 		.mr_startup_mask = AT91_ADC_STARTUP_9X5,
1368 	},
1369 	.triggers = at91sam9x5_triggers,
1370 	.trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
1371 };
1372 
1373 static const struct of_device_id at91_adc_dt_ids[] = {
1374 	{ .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps },
1375 	{ .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps },
1376 	{ .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps },
1377 	{ .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps },
1378 	{ .compatible = "atmel,sama5d3-adc", .data = &sama5d3_caps },
1379 	{},
1380 };
1381 MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
1382 
1383 static struct platform_driver at91_adc_driver = {
1384 	.probe = at91_adc_probe,
1385 	.remove = at91_adc_remove,
1386 	.driver = {
1387 		   .name = DRIVER_NAME,
1388 		   .of_match_table = at91_adc_dt_ids,
1389 		   .pm = &at91_adc_pm_ops,
1390 	},
1391 };
1392 
1393 module_platform_driver(at91_adc_driver);
1394 
1395 MODULE_LICENSE("GPL");
1396 MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
1397 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1398