xref: /openbmc/linux/drivers/iio/adc/at91_adc.c (revision 4da722ca)
1 /*
2  * Driver for the ADC present in the Atmel AT91 evaluation boards.
3  *
4  * Copyright 2011 Free Electrons
5  *
6  * Licensed under the GPLv2 or later.
7  */
8 
9 #include <linux/bitmap.h>
10 #include <linux/bitops.h>
11 #include <linux/clk.h>
12 #include <linux/err.h>
13 #include <linux/io.h>
14 #include <linux/input.h>
15 #include <linux/interrupt.h>
16 #include <linux/jiffies.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/of.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/sched.h>
23 #include <linux/slab.h>
24 #include <linux/wait.h>
25 
26 #include <linux/platform_data/at91_adc.h>
27 
28 #include <linux/iio/iio.h>
29 #include <linux/iio/buffer.h>
30 #include <linux/iio/trigger.h>
31 #include <linux/iio/trigger_consumer.h>
32 #include <linux/iio/triggered_buffer.h>
33 #include <linux/pinctrl/consumer.h>
34 
35 /* Registers */
36 #define AT91_ADC_CR		0x00		/* Control Register */
37 #define		AT91_ADC_SWRST		(1 << 0)	/* Software Reset */
38 #define		AT91_ADC_START		(1 << 1)	/* Start Conversion */
39 
40 #define AT91_ADC_MR		0x04		/* Mode Register */
41 #define		AT91_ADC_TSAMOD		(3 << 0)	/* ADC mode */
42 #define		AT91_ADC_TSAMOD_ADC_ONLY_MODE		(0 << 0)	/* ADC Mode */
43 #define		AT91_ADC_TSAMOD_TS_ONLY_MODE		(1 << 0)	/* Touch Screen Only Mode */
44 #define		AT91_ADC_TRGEN		(1 << 0)	/* Trigger Enable */
45 #define		AT91_ADC_TRGSEL		(7 << 1)	/* Trigger Selection */
46 #define			AT91_ADC_TRGSEL_TC0		(0 << 1)
47 #define			AT91_ADC_TRGSEL_TC1		(1 << 1)
48 #define			AT91_ADC_TRGSEL_TC2		(2 << 1)
49 #define			AT91_ADC_TRGSEL_EXTERNAL	(6 << 1)
50 #define		AT91_ADC_LOWRES		(1 << 4)	/* Low Resolution */
51 #define		AT91_ADC_SLEEP		(1 << 5)	/* Sleep Mode */
52 #define		AT91_ADC_PENDET		(1 << 6)	/* Pen contact detection enable */
53 #define		AT91_ADC_PRESCAL_9260	(0x3f << 8)	/* Prescalar Rate Selection */
54 #define		AT91_ADC_PRESCAL_9G45	(0xff << 8)
55 #define			AT91_ADC_PRESCAL_(x)	((x) << 8)
56 #define		AT91_ADC_STARTUP_9260	(0x1f << 16)	/* Startup Up Time */
57 #define		AT91_ADC_STARTUP_9G45	(0x7f << 16)
58 #define		AT91_ADC_STARTUP_9X5	(0xf << 16)
59 #define			AT91_ADC_STARTUP_(x)	((x) << 16)
60 #define		AT91_ADC_SHTIM		(0xf  << 24)	/* Sample & Hold Time */
61 #define			AT91_ADC_SHTIM_(x)	((x) << 24)
62 #define		AT91_ADC_PENDBC		(0x0f << 28)	/* Pen Debounce time */
63 #define			AT91_ADC_PENDBC_(x)	((x) << 28)
64 
65 #define AT91_ADC_TSR		0x0C
66 #define		AT91_ADC_TSR_SHTIM	(0xf  << 24)	/* Sample & Hold Time */
67 #define			AT91_ADC_TSR_SHTIM_(x)	((x) << 24)
68 
69 #define AT91_ADC_CHER		0x10		/* Channel Enable Register */
70 #define AT91_ADC_CHDR		0x14		/* Channel Disable Register */
71 #define AT91_ADC_CHSR		0x18		/* Channel Status Register */
72 #define		AT91_ADC_CH(n)		(1 << (n))	/* Channel Number */
73 
74 #define AT91_ADC_SR		0x1C		/* Status Register */
75 #define		AT91_ADC_EOC(n)		(1 << (n))	/* End of Conversion on Channel N */
76 #define		AT91_ADC_OVRE(n)	(1 << ((n) + 8))/* Overrun Error on Channel N */
77 #define		AT91_ADC_DRDY		(1 << 16)	/* Data Ready */
78 #define		AT91_ADC_GOVRE		(1 << 17)	/* General Overrun Error */
79 #define		AT91_ADC_ENDRX		(1 << 18)	/* End of RX Buffer */
80 #define		AT91_ADC_RXFUFF		(1 << 19)	/* RX Buffer Full */
81 
82 #define AT91_ADC_SR_9X5		0x30		/* Status Register for 9x5 */
83 #define		AT91_ADC_SR_DRDY_9X5	(1 << 24)	/* Data Ready */
84 
85 #define AT91_ADC_LCDR		0x20		/* Last Converted Data Register */
86 #define		AT91_ADC_LDATA		(0x3ff)
87 
88 #define AT91_ADC_IER		0x24		/* Interrupt Enable Register */
89 #define AT91_ADC_IDR		0x28		/* Interrupt Disable Register */
90 #define AT91_ADC_IMR		0x2C		/* Interrupt Mask Register */
91 #define		AT91RL_ADC_IER_PEN	(1 << 20)
92 #define		AT91RL_ADC_IER_NOPEN	(1 << 21)
93 #define		AT91_ADC_IER_PEN	(1 << 29)
94 #define		AT91_ADC_IER_NOPEN	(1 << 30)
95 #define		AT91_ADC_IER_XRDY	(1 << 20)
96 #define		AT91_ADC_IER_YRDY	(1 << 21)
97 #define		AT91_ADC_IER_PRDY	(1 << 22)
98 #define		AT91_ADC_ISR_PENS	(1 << 31)
99 
100 #define AT91_ADC_CHR(n)		(0x30 + ((n) * 4))	/* Channel Data Register N */
101 #define		AT91_ADC_DATA		(0x3ff)
102 
103 #define AT91_ADC_CDR0_9X5	(0x50)			/* Channel Data Register 0 for 9X5 */
104 
105 #define AT91_ADC_ACR		0x94	/* Analog Control Register */
106 #define		AT91_ADC_ACR_PENDETSENS	(0x3 << 0)	/* pull-up resistor */
107 
108 #define AT91_ADC_TSMR		0xB0
109 #define		AT91_ADC_TSMR_TSMODE	(3 << 0)	/* Touch Screen Mode */
110 #define			AT91_ADC_TSMR_TSMODE_NONE		(0 << 0)
111 #define			AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS	(1 << 0)
112 #define			AT91_ADC_TSMR_TSMODE_4WIRE_PRESS	(2 << 0)
113 #define			AT91_ADC_TSMR_TSMODE_5WIRE		(3 << 0)
114 #define		AT91_ADC_TSMR_TSAV	(3 << 4)	/* Averages samples */
115 #define			AT91_ADC_TSMR_TSAV_(x)		((x) << 4)
116 #define		AT91_ADC_TSMR_SCTIM	(0x0f << 16)	/* Switch closure time */
117 #define			AT91_ADC_TSMR_SCTIM_(x)		((x) << 16)
118 #define		AT91_ADC_TSMR_PENDBC	(0x0f << 28)	/* Pen Debounce time */
119 #define			AT91_ADC_TSMR_PENDBC_(x)	((x) << 28)
120 #define		AT91_ADC_TSMR_NOTSDMA	(1 << 22)	/* No Touchscreen DMA */
121 #define		AT91_ADC_TSMR_PENDET_DIS	(0 << 24)	/* Pen contact detection disable */
122 #define		AT91_ADC_TSMR_PENDET_ENA	(1 << 24)	/* Pen contact detection enable */
123 
124 #define AT91_ADC_TSXPOSR	0xB4
125 #define AT91_ADC_TSYPOSR	0xB8
126 #define AT91_ADC_TSPRESSR	0xBC
127 
128 #define AT91_ADC_TRGR_9260	AT91_ADC_MR
129 #define AT91_ADC_TRGR_9G45	0x08
130 #define AT91_ADC_TRGR_9X5	0xC0
131 
132 /* Trigger Register bit field */
133 #define		AT91_ADC_TRGR_TRGPER	(0xffff << 16)
134 #define			AT91_ADC_TRGR_TRGPER_(x)	((x) << 16)
135 #define		AT91_ADC_TRGR_TRGMOD	(0x7 << 0)
136 #define			AT91_ADC_TRGR_NONE		(0 << 0)
137 #define			AT91_ADC_TRGR_MOD_PERIOD_TRIG	(5 << 0)
138 
139 #define AT91_ADC_CHAN(st, ch) \
140 	(st->registers->channel_base + (ch * 4))
141 #define at91_adc_readl(st, reg) \
142 	(readl_relaxed(st->reg_base + reg))
143 #define at91_adc_writel(st, reg, val) \
144 	(writel_relaxed(val, st->reg_base + reg))
145 
146 #define DRIVER_NAME		"at91_adc"
147 #define MAX_POS_BITS		12
148 
149 #define TOUCH_SAMPLE_PERIOD_US		2000	/* 2ms */
150 #define TOUCH_PEN_DETECT_DEBOUNCE_US	200
151 
152 #define MAX_RLPOS_BITS         10
153 #define TOUCH_SAMPLE_PERIOD_US_RL      10000   /* 10ms, the SoC can't keep up with 2ms */
154 #define TOUCH_SHTIM                    0xa
155 #define TOUCH_SCTIM_US		10		/* 10us for the Touchscreen Switches Closure Time */
156 
157 /**
158  * struct at91_adc_reg_desc - Various informations relative to registers
159  * @channel_base:	Base offset for the channel data registers
160  * @drdy_mask:		Mask of the DRDY field in the relevant registers
161 			(Interruptions registers mostly)
162  * @status_register:	Offset of the Interrupt Status Register
163  * @trigger_register:	Offset of the Trigger setup register
164  * @mr_prescal_mask:	Mask of the PRESCAL field in the adc MR register
165  * @mr_startup_mask:	Mask of the STARTUP field in the adc MR register
166  */
167 struct at91_adc_reg_desc {
168 	u8	channel_base;
169 	u32	drdy_mask;
170 	u8	status_register;
171 	u8	trigger_register;
172 	u32	mr_prescal_mask;
173 	u32	mr_startup_mask;
174 };
175 
176 struct at91_adc_caps {
177 	bool	has_ts;		/* Support touch screen */
178 	bool	has_tsmr;	/* only at91sam9x5, sama5d3 have TSMR reg */
179 	/*
180 	 * Numbers of sampling data will be averaged. Can be 0~3.
181 	 * Hardware can average (2 ^ ts_filter_average) sample data.
182 	 */
183 	u8	ts_filter_average;
184 	/* Pen Detection input pull-up resistor, can be 0~3 */
185 	u8	ts_pen_detect_sensitivity;
186 
187 	/* startup time calculate function */
188 	u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz);
189 
190 	u8	num_channels;
191 	struct at91_adc_reg_desc registers;
192 };
193 
194 struct at91_adc_state {
195 	struct clk		*adc_clk;
196 	u16			*buffer;
197 	unsigned long		channels_mask;
198 	struct clk		*clk;
199 	bool			done;
200 	int			irq;
201 	u16			last_value;
202 	int			chnb;
203 	struct mutex		lock;
204 	u8			num_channels;
205 	void __iomem		*reg_base;
206 	struct at91_adc_reg_desc *registers;
207 	u32			startup_time;
208 	u8			sample_hold_time;
209 	bool			sleep_mode;
210 	struct iio_trigger	**trig;
211 	struct at91_adc_trigger	*trigger_list;
212 	u32			trigger_number;
213 	bool			use_external;
214 	u32			vref_mv;
215 	u32			res;		/* resolution used for convertions */
216 	bool			low_res;	/* the resolution corresponds to the lowest one */
217 	wait_queue_head_t	wq_data_avail;
218 	struct at91_adc_caps	*caps;
219 
220 	/*
221 	 * Following ADC channels are shared by touchscreen:
222 	 *
223 	 * CH0 -- Touch screen XP/UL
224 	 * CH1 -- Touch screen XM/UR
225 	 * CH2 -- Touch screen YP/LL
226 	 * CH3 -- Touch screen YM/Sense
227 	 * CH4 -- Touch screen LR(5-wire only)
228 	 *
229 	 * The bitfields below represents the reserved channel in the
230 	 * touchscreen mode.
231 	 */
232 #define CHAN_MASK_TOUCHSCREEN_4WIRE	(0xf << 0)
233 #define CHAN_MASK_TOUCHSCREEN_5WIRE	(0x1f << 0)
234 	enum atmel_adc_ts_type	touchscreen_type;
235 	struct input_dev	*ts_input;
236 
237 	u16			ts_sample_period_val;
238 	u32			ts_pressure_threshold;
239 	u16			ts_pendbc;
240 
241 	bool			ts_bufferedmeasure;
242 	u32			ts_prev_absx;
243 	u32			ts_prev_absy;
244 };
245 
246 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
247 {
248 	struct iio_poll_func *pf = p;
249 	struct iio_dev *idev = pf->indio_dev;
250 	struct at91_adc_state *st = iio_priv(idev);
251 	int i, j = 0;
252 
253 	for (i = 0; i < idev->masklength; i++) {
254 		if (!test_bit(i, idev->active_scan_mask))
255 			continue;
256 		st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, i));
257 		j++;
258 	}
259 
260 	iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp);
261 
262 	iio_trigger_notify_done(idev->trig);
263 
264 	/* Needed to ACK the DRDY interruption */
265 	at91_adc_readl(st, AT91_ADC_LCDR);
266 
267 	enable_irq(st->irq);
268 
269 	return IRQ_HANDLED;
270 }
271 
272 /* Handler for classic adc channel eoc trigger */
273 static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev)
274 {
275 	struct at91_adc_state *st = iio_priv(idev);
276 
277 	if (iio_buffer_enabled(idev)) {
278 		disable_irq_nosync(irq);
279 		iio_trigger_poll(idev->trig);
280 	} else {
281 		st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb));
282 		st->done = true;
283 		wake_up_interruptible(&st->wq_data_avail);
284 	}
285 }
286 
287 static int at91_ts_sample(struct at91_adc_state *st)
288 {
289 	unsigned int xscale, yscale, reg, z1, z2;
290 	unsigned int x, y, pres, xpos, ypos;
291 	unsigned int rxp = 1;
292 	unsigned int factor = 1000;
293 	struct iio_dev *idev = iio_priv_to_dev(st);
294 
295 	unsigned int xyz_mask_bits = st->res;
296 	unsigned int xyz_mask = (1 << xyz_mask_bits) - 1;
297 
298 	/* calculate position */
299 	/* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */
300 	reg = at91_adc_readl(st, AT91_ADC_TSXPOSR);
301 	xpos = reg & xyz_mask;
302 	x = (xpos << MAX_POS_BITS) - xpos;
303 	xscale = (reg >> 16) & xyz_mask;
304 	if (xscale == 0) {
305 		dev_err(&idev->dev, "Error: xscale == 0!\n");
306 		return -1;
307 	}
308 	x /= xscale;
309 
310 	/* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */
311 	reg = at91_adc_readl(st, AT91_ADC_TSYPOSR);
312 	ypos = reg & xyz_mask;
313 	y = (ypos << MAX_POS_BITS) - ypos;
314 	yscale = (reg >> 16) & xyz_mask;
315 	if (yscale == 0) {
316 		dev_err(&idev->dev, "Error: yscale == 0!\n");
317 		return -1;
318 	}
319 	y /= yscale;
320 
321 	/* calculate the pressure */
322 	reg = at91_adc_readl(st, AT91_ADC_TSPRESSR);
323 	z1 = reg & xyz_mask;
324 	z2 = (reg >> 16) & xyz_mask;
325 
326 	if (z1 != 0)
327 		pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor)
328 			/ factor;
329 	else
330 		pres = st->ts_pressure_threshold;	/* no pen contacted */
331 
332 	dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n",
333 				xpos, xscale, ypos, yscale, z1, z2, pres);
334 
335 	if (pres < st->ts_pressure_threshold) {
336 		dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n",
337 					x, y, pres / factor);
338 		input_report_abs(st->ts_input, ABS_X, x);
339 		input_report_abs(st->ts_input, ABS_Y, y);
340 		input_report_abs(st->ts_input, ABS_PRESSURE, pres);
341 		input_report_key(st->ts_input, BTN_TOUCH, 1);
342 		input_sync(st->ts_input);
343 	} else {
344 		dev_dbg(&idev->dev, "pressure too low: not reporting\n");
345 	}
346 
347 	return 0;
348 }
349 
350 static irqreturn_t at91_adc_rl_interrupt(int irq, void *private)
351 {
352 	struct iio_dev *idev = private;
353 	struct at91_adc_state *st = iio_priv(idev);
354 	u32 status = at91_adc_readl(st, st->registers->status_register);
355 	unsigned int reg;
356 
357 	status &= at91_adc_readl(st, AT91_ADC_IMR);
358 	if (status & GENMASK(st->num_channels - 1, 0))
359 		handle_adc_eoc_trigger(irq, idev);
360 
361 	if (status & AT91RL_ADC_IER_PEN) {
362 		/* Disabling pen debounce is required to get a NOPEN irq */
363 		reg = at91_adc_readl(st, AT91_ADC_MR);
364 		reg &= ~AT91_ADC_PENDBC;
365 		at91_adc_writel(st, AT91_ADC_MR, reg);
366 
367 		at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
368 		at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN
369 				| AT91_ADC_EOC(3));
370 		/* Set up period trigger for sampling */
371 		at91_adc_writel(st, st->registers->trigger_register,
372 			AT91_ADC_TRGR_MOD_PERIOD_TRIG |
373 			AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
374 	} else if (status & AT91RL_ADC_IER_NOPEN) {
375 		reg = at91_adc_readl(st, AT91_ADC_MR);
376 		reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
377 		at91_adc_writel(st, AT91_ADC_MR, reg);
378 		at91_adc_writel(st, st->registers->trigger_register,
379 			AT91_ADC_TRGR_NONE);
380 
381 		at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN
382 				| AT91_ADC_EOC(3));
383 		at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
384 		st->ts_bufferedmeasure = false;
385 		input_report_key(st->ts_input, BTN_TOUCH, 0);
386 		input_sync(st->ts_input);
387 	} else if (status & AT91_ADC_EOC(3) && st->ts_input) {
388 		/* Conversion finished and we've a touchscreen */
389 		if (st->ts_bufferedmeasure) {
390 			/*
391 			 * Last measurement is always discarded, since it can
392 			 * be erroneous.
393 			 * Always report previous measurement
394 			 */
395 			input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx);
396 			input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy);
397 			input_report_key(st->ts_input, BTN_TOUCH, 1);
398 			input_sync(st->ts_input);
399 		} else
400 			st->ts_bufferedmeasure = true;
401 
402 		/* Now make new measurement */
403 		st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3))
404 				   << MAX_RLPOS_BITS;
405 		st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2));
406 
407 		st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1))
408 				   << MAX_RLPOS_BITS;
409 		st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0));
410 	}
411 
412 	return IRQ_HANDLED;
413 }
414 
415 static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private)
416 {
417 	struct iio_dev *idev = private;
418 	struct at91_adc_state *st = iio_priv(idev);
419 	u32 status = at91_adc_readl(st, st->registers->status_register);
420 	const uint32_t ts_data_irq_mask =
421 		AT91_ADC_IER_XRDY |
422 		AT91_ADC_IER_YRDY |
423 		AT91_ADC_IER_PRDY;
424 
425 	if (status & GENMASK(st->num_channels - 1, 0))
426 		handle_adc_eoc_trigger(irq, idev);
427 
428 	if (status & AT91_ADC_IER_PEN) {
429 		at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
430 		at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN |
431 			ts_data_irq_mask);
432 		/* Set up period trigger for sampling */
433 		at91_adc_writel(st, st->registers->trigger_register,
434 			AT91_ADC_TRGR_MOD_PERIOD_TRIG |
435 			AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
436 	} else if (status & AT91_ADC_IER_NOPEN) {
437 		at91_adc_writel(st, st->registers->trigger_register, 0);
438 		at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN |
439 			ts_data_irq_mask);
440 		at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
441 
442 		input_report_key(st->ts_input, BTN_TOUCH, 0);
443 		input_sync(st->ts_input);
444 	} else if ((status & ts_data_irq_mask) == ts_data_irq_mask) {
445 		/* Now all touchscreen data is ready */
446 
447 		if (status & AT91_ADC_ISR_PENS) {
448 			/* validate data by pen contact */
449 			at91_ts_sample(st);
450 		} else {
451 			/* triggered by event that is no pen contact, just read
452 			 * them to clean the interrupt and discard all.
453 			 */
454 			at91_adc_readl(st, AT91_ADC_TSXPOSR);
455 			at91_adc_readl(st, AT91_ADC_TSYPOSR);
456 			at91_adc_readl(st, AT91_ADC_TSPRESSR);
457 		}
458 	}
459 
460 	return IRQ_HANDLED;
461 }
462 
463 static int at91_adc_channel_init(struct iio_dev *idev)
464 {
465 	struct at91_adc_state *st = iio_priv(idev);
466 	struct iio_chan_spec *chan_array, *timestamp;
467 	int bit, idx = 0;
468 	unsigned long rsvd_mask = 0;
469 
470 	/* If touchscreen is enable, then reserve the adc channels */
471 	if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
472 		rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE;
473 	else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE)
474 		rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE;
475 
476 	/* set up the channel mask to reserve touchscreen channels */
477 	st->channels_mask &= ~rsvd_mask;
478 
479 	idev->num_channels = bitmap_weight(&st->channels_mask,
480 					   st->num_channels) + 1;
481 
482 	chan_array = devm_kzalloc(&idev->dev,
483 				  ((idev->num_channels + 1) *
484 					sizeof(struct iio_chan_spec)),
485 				  GFP_KERNEL);
486 
487 	if (!chan_array)
488 		return -ENOMEM;
489 
490 	for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
491 		struct iio_chan_spec *chan = chan_array + idx;
492 
493 		chan->type = IIO_VOLTAGE;
494 		chan->indexed = 1;
495 		chan->channel = bit;
496 		chan->scan_index = idx;
497 		chan->scan_type.sign = 'u';
498 		chan->scan_type.realbits = st->res;
499 		chan->scan_type.storagebits = 16;
500 		chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
501 		chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
502 		idx++;
503 	}
504 	timestamp = chan_array + idx;
505 
506 	timestamp->type = IIO_TIMESTAMP;
507 	timestamp->channel = -1;
508 	timestamp->scan_index = idx;
509 	timestamp->scan_type.sign = 's';
510 	timestamp->scan_type.realbits = 64;
511 	timestamp->scan_type.storagebits = 64;
512 
513 	idev->channels = chan_array;
514 	return idev->num_channels;
515 }
516 
517 static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
518 					     struct at91_adc_trigger *triggers,
519 					     const char *trigger_name)
520 {
521 	struct at91_adc_state *st = iio_priv(idev);
522 	int i;
523 
524 	for (i = 0; i < st->trigger_number; i++) {
525 		char *name = kasprintf(GFP_KERNEL,
526 				"%s-dev%d-%s",
527 				idev->name,
528 				idev->id,
529 				triggers[i].name);
530 		if (!name)
531 			return -ENOMEM;
532 
533 		if (strcmp(trigger_name, name) == 0) {
534 			kfree(name);
535 			if (triggers[i].value == 0)
536 				return -EINVAL;
537 			return triggers[i].value;
538 		}
539 
540 		kfree(name);
541 	}
542 
543 	return -EINVAL;
544 }
545 
546 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
547 {
548 	struct iio_dev *idev = iio_trigger_get_drvdata(trig);
549 	struct at91_adc_state *st = iio_priv(idev);
550 	struct at91_adc_reg_desc *reg = st->registers;
551 	u32 status = at91_adc_readl(st, reg->trigger_register);
552 	int value;
553 	u8 bit;
554 
555 	value = at91_adc_get_trigger_value_by_name(idev,
556 						   st->trigger_list,
557 						   idev->trig->name);
558 	if (value < 0)
559 		return value;
560 
561 	if (state) {
562 		st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
563 		if (st->buffer == NULL)
564 			return -ENOMEM;
565 
566 		at91_adc_writel(st, reg->trigger_register,
567 				status | value);
568 
569 		for_each_set_bit(bit, idev->active_scan_mask,
570 				 st->num_channels) {
571 			struct iio_chan_spec const *chan = idev->channels + bit;
572 			at91_adc_writel(st, AT91_ADC_CHER,
573 					AT91_ADC_CH(chan->channel));
574 		}
575 
576 		at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
577 
578 	} else {
579 		at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
580 
581 		at91_adc_writel(st, reg->trigger_register,
582 				status & ~value);
583 
584 		for_each_set_bit(bit, idev->active_scan_mask,
585 				 st->num_channels) {
586 			struct iio_chan_spec const *chan = idev->channels + bit;
587 			at91_adc_writel(st, AT91_ADC_CHDR,
588 					AT91_ADC_CH(chan->channel));
589 		}
590 		kfree(st->buffer);
591 	}
592 
593 	return 0;
594 }
595 
596 static const struct iio_trigger_ops at91_adc_trigger_ops = {
597 	.owner = THIS_MODULE,
598 	.set_trigger_state = &at91_adc_configure_trigger,
599 };
600 
601 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
602 						     struct at91_adc_trigger *trigger)
603 {
604 	struct iio_trigger *trig;
605 	int ret;
606 
607 	trig = iio_trigger_alloc("%s-dev%d-%s", idev->name,
608 				 idev->id, trigger->name);
609 	if (trig == NULL)
610 		return NULL;
611 
612 	trig->dev.parent = idev->dev.parent;
613 	iio_trigger_set_drvdata(trig, idev);
614 	trig->ops = &at91_adc_trigger_ops;
615 
616 	ret = iio_trigger_register(trig);
617 	if (ret)
618 		return NULL;
619 
620 	return trig;
621 }
622 
623 static int at91_adc_trigger_init(struct iio_dev *idev)
624 {
625 	struct at91_adc_state *st = iio_priv(idev);
626 	int i, ret;
627 
628 	st->trig = devm_kzalloc(&idev->dev,
629 				st->trigger_number * sizeof(*st->trig),
630 				GFP_KERNEL);
631 
632 	if (st->trig == NULL) {
633 		ret = -ENOMEM;
634 		goto error_ret;
635 	}
636 
637 	for (i = 0; i < st->trigger_number; i++) {
638 		if (st->trigger_list[i].is_external && !(st->use_external))
639 			continue;
640 
641 		st->trig[i] = at91_adc_allocate_trigger(idev,
642 							st->trigger_list + i);
643 		if (st->trig[i] == NULL) {
644 			dev_err(&idev->dev,
645 				"Could not allocate trigger %d\n", i);
646 			ret = -ENOMEM;
647 			goto error_trigger;
648 		}
649 	}
650 
651 	return 0;
652 
653 error_trigger:
654 	for (i--; i >= 0; i--) {
655 		iio_trigger_unregister(st->trig[i]);
656 		iio_trigger_free(st->trig[i]);
657 	}
658 error_ret:
659 	return ret;
660 }
661 
662 static void at91_adc_trigger_remove(struct iio_dev *idev)
663 {
664 	struct at91_adc_state *st = iio_priv(idev);
665 	int i;
666 
667 	for (i = 0; i < st->trigger_number; i++) {
668 		iio_trigger_unregister(st->trig[i]);
669 		iio_trigger_free(st->trig[i]);
670 	}
671 }
672 
673 static int at91_adc_buffer_init(struct iio_dev *idev)
674 {
675 	return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
676 		&at91_adc_trigger_handler, NULL);
677 }
678 
679 static void at91_adc_buffer_remove(struct iio_dev *idev)
680 {
681 	iio_triggered_buffer_cleanup(idev);
682 }
683 
684 static int at91_adc_read_raw(struct iio_dev *idev,
685 			     struct iio_chan_spec const *chan,
686 			     int *val, int *val2, long mask)
687 {
688 	struct at91_adc_state *st = iio_priv(idev);
689 	int ret;
690 
691 	switch (mask) {
692 	case IIO_CHAN_INFO_RAW:
693 		mutex_lock(&st->lock);
694 
695 		st->chnb = chan->channel;
696 		at91_adc_writel(st, AT91_ADC_CHER,
697 				AT91_ADC_CH(chan->channel));
698 		at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel));
699 		at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
700 
701 		ret = wait_event_interruptible_timeout(st->wq_data_avail,
702 						       st->done,
703 						       msecs_to_jiffies(1000));
704 		if (ret == 0)
705 			ret = -ETIMEDOUT;
706 		if (ret < 0) {
707 			mutex_unlock(&st->lock);
708 			return ret;
709 		}
710 
711 		*val = st->last_value;
712 
713 		at91_adc_writel(st, AT91_ADC_CHDR,
714 				AT91_ADC_CH(chan->channel));
715 		at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel));
716 
717 		st->last_value = 0;
718 		st->done = false;
719 		mutex_unlock(&st->lock);
720 		return IIO_VAL_INT;
721 
722 	case IIO_CHAN_INFO_SCALE:
723 		*val = st->vref_mv;
724 		*val2 = chan->scan_type.realbits;
725 		return IIO_VAL_FRACTIONAL_LOG2;
726 	default:
727 		break;
728 	}
729 	return -EINVAL;
730 }
731 
732 static int at91_adc_of_get_resolution(struct at91_adc_state *st,
733 				      struct platform_device *pdev)
734 {
735 	struct iio_dev *idev = iio_priv_to_dev(st);
736 	struct device_node *np = pdev->dev.of_node;
737 	int count, i, ret = 0;
738 	char *res_name, *s;
739 	u32 *resolutions;
740 
741 	count = of_property_count_strings(np, "atmel,adc-res-names");
742 	if (count < 2) {
743 		dev_err(&idev->dev, "You must specified at least two resolution names for "
744 				    "adc-res-names property in the DT\n");
745 		return count;
746 	}
747 
748 	resolutions = kmalloc_array(count, sizeof(*resolutions), GFP_KERNEL);
749 	if (!resolutions)
750 		return -ENOMEM;
751 
752 	if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) {
753 		dev_err(&idev->dev, "Missing adc-res property in the DT.\n");
754 		ret = -ENODEV;
755 		goto ret;
756 	}
757 
758 	if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name))
759 		res_name = "highres";
760 
761 	for (i = 0; i < count; i++) {
762 		if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s))
763 			continue;
764 
765 		if (strcmp(res_name, s))
766 			continue;
767 
768 		st->res = resolutions[i];
769 		if (!strcmp(res_name, "lowres"))
770 			st->low_res = true;
771 		else
772 			st->low_res = false;
773 
774 		dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
775 		goto ret;
776 	}
777 
778 	dev_err(&idev->dev, "There is no resolution for %s\n", res_name);
779 
780 ret:
781 	kfree(resolutions);
782 	return ret;
783 }
784 
785 static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz)
786 {
787 	/*
788 	 * Number of ticks needed to cover the startup time of the ADC
789 	 * as defined in the electrical characteristics of the board,
790 	 * divided by 8. The formula thus is :
791 	 *   Startup Time = (ticks + 1) * 8 / ADC Clock
792 	 */
793 	return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8;
794 }
795 
796 static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz)
797 {
798 	/*
799 	 * For sama5d3x and at91sam9x5, the formula changes to:
800 	 * Startup Time = <lookup_table_value> / ADC Clock
801 	 */
802 	const int startup_lookup[] = {
803 		0,   8,   16,  24,
804 		64,  80,  96,  112,
805 		512, 576, 640, 704,
806 		768, 832, 896, 960
807 		};
808 	int i, size = ARRAY_SIZE(startup_lookup);
809 	unsigned int ticks;
810 
811 	ticks = startup_time * adc_clk_khz / 1000;
812 	for (i = 0; i < size; i++)
813 		if (ticks < startup_lookup[i])
814 			break;
815 
816 	ticks = i;
817 	if (ticks == size)
818 		/* Reach the end of lookup table */
819 		ticks = size - 1;
820 
821 	return ticks;
822 }
823 
824 static const struct of_device_id at91_adc_dt_ids[];
825 
826 static int at91_adc_probe_dt_ts(struct device_node *node,
827 	struct at91_adc_state *st, struct device *dev)
828 {
829 	int ret;
830 	u32 prop;
831 
832 	ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop);
833 	if (ret) {
834 		dev_info(dev, "ADC Touch screen is disabled.\n");
835 		return 0;
836 	}
837 
838 	switch (prop) {
839 	case 4:
840 	case 5:
841 		st->touchscreen_type = prop;
842 		break;
843 	default:
844 		dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop);
845 		return -EINVAL;
846 	}
847 
848 	if (!st->caps->has_tsmr)
849 		return 0;
850 	prop = 0;
851 	of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop);
852 	st->ts_pressure_threshold = prop;
853 	if (st->ts_pressure_threshold) {
854 		return 0;
855 	} else {
856 		dev_err(dev, "Invalid pressure threshold for the touchscreen\n");
857 		return -EINVAL;
858 	}
859 }
860 
861 static int at91_adc_probe_dt(struct at91_adc_state *st,
862 			     struct platform_device *pdev)
863 {
864 	struct iio_dev *idev = iio_priv_to_dev(st);
865 	struct device_node *node = pdev->dev.of_node;
866 	struct device_node *trig_node;
867 	int i = 0, ret;
868 	u32 prop;
869 
870 	if (!node)
871 		return -EINVAL;
872 
873 	st->caps = (struct at91_adc_caps *)
874 		of_match_device(at91_adc_dt_ids, &pdev->dev)->data;
875 
876 	st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
877 
878 	if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
879 		dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
880 		ret = -EINVAL;
881 		goto error_ret;
882 	}
883 	st->channels_mask = prop;
884 
885 	st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode");
886 
887 	if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
888 		dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
889 		ret = -EINVAL;
890 		goto error_ret;
891 	}
892 	st->startup_time = prop;
893 
894 	prop = 0;
895 	of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop);
896 	st->sample_hold_time = prop;
897 
898 	if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
899 		dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
900 		ret = -EINVAL;
901 		goto error_ret;
902 	}
903 	st->vref_mv = prop;
904 
905 	ret = at91_adc_of_get_resolution(st, pdev);
906 	if (ret)
907 		goto error_ret;
908 
909 	st->registers = &st->caps->registers;
910 	st->num_channels = st->caps->num_channels;
911 	st->trigger_number = of_get_child_count(node);
912 	st->trigger_list = devm_kzalloc(&idev->dev, st->trigger_number *
913 					sizeof(struct at91_adc_trigger),
914 					GFP_KERNEL);
915 	if (!st->trigger_list) {
916 		dev_err(&idev->dev, "Could not allocate trigger list memory.\n");
917 		ret = -ENOMEM;
918 		goto error_ret;
919 	}
920 
921 	for_each_child_of_node(node, trig_node) {
922 		struct at91_adc_trigger *trig = st->trigger_list + i;
923 		const char *name;
924 
925 		if (of_property_read_string(trig_node, "trigger-name", &name)) {
926 			dev_err(&idev->dev, "Missing trigger-name property in the DT.\n");
927 			ret = -EINVAL;
928 			goto error_ret;
929 		}
930 		trig->name = name;
931 
932 		if (of_property_read_u32(trig_node, "trigger-value", &prop)) {
933 			dev_err(&idev->dev, "Missing trigger-value property in the DT.\n");
934 			ret = -EINVAL;
935 			goto error_ret;
936 		}
937 		trig->value = prop;
938 		trig->is_external = of_property_read_bool(trig_node, "trigger-external");
939 		i++;
940 	}
941 
942 	/* Check if touchscreen is supported. */
943 	if (st->caps->has_ts)
944 		return at91_adc_probe_dt_ts(node, st, &idev->dev);
945 	else
946 		dev_info(&idev->dev, "not support touchscreen in the adc compatible string.\n");
947 
948 	return 0;
949 
950 error_ret:
951 	return ret;
952 }
953 
954 static int at91_adc_probe_pdata(struct at91_adc_state *st,
955 				struct platform_device *pdev)
956 {
957 	struct at91_adc_data *pdata = pdev->dev.platform_data;
958 
959 	if (!pdata)
960 		return -EINVAL;
961 
962 	st->caps = (struct at91_adc_caps *)
963 			platform_get_device_id(pdev)->driver_data;
964 
965 	st->use_external = pdata->use_external_triggers;
966 	st->vref_mv = pdata->vref;
967 	st->channels_mask = pdata->channels_used;
968 	st->num_channels = st->caps->num_channels;
969 	st->startup_time = pdata->startup_time;
970 	st->trigger_number = pdata->trigger_number;
971 	st->trigger_list = pdata->trigger_list;
972 	st->registers = &st->caps->registers;
973 	st->touchscreen_type = pdata->touchscreen_type;
974 
975 	return 0;
976 }
977 
978 static const struct iio_info at91_adc_info = {
979 	.driver_module = THIS_MODULE,
980 	.read_raw = &at91_adc_read_raw,
981 };
982 
983 /* Touchscreen related functions */
984 static int atmel_ts_open(struct input_dev *dev)
985 {
986 	struct at91_adc_state *st = input_get_drvdata(dev);
987 
988 	if (st->caps->has_tsmr)
989 		at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
990 	else
991 		at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
992 	return 0;
993 }
994 
995 static void atmel_ts_close(struct input_dev *dev)
996 {
997 	struct at91_adc_state *st = input_get_drvdata(dev);
998 
999 	if (st->caps->has_tsmr)
1000 		at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
1001 	else
1002 		at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
1003 }
1004 
1005 static int at91_ts_hw_init(struct at91_adc_state *st, u32 adc_clk_khz)
1006 {
1007 	struct iio_dev *idev = iio_priv_to_dev(st);
1008 	u32 reg = 0;
1009 	u32 tssctim = 0;
1010 	int i = 0;
1011 
1012 	/* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid
1013 	 * pen detect noise.
1014 	 * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock
1015 	 */
1016 	st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz /
1017 				 1000, 1);
1018 
1019 	while (st->ts_pendbc >> ++i)
1020 		;	/* Empty! Find the shift offset */
1021 	if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1))))
1022 		st->ts_pendbc = i;
1023 	else
1024 		st->ts_pendbc = i - 1;
1025 
1026 	if (!st->caps->has_tsmr) {
1027 		reg = at91_adc_readl(st, AT91_ADC_MR);
1028 		reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET;
1029 
1030 		reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
1031 		at91_adc_writel(st, AT91_ADC_MR, reg);
1032 
1033 		reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM;
1034 		at91_adc_writel(st, AT91_ADC_TSR, reg);
1035 
1036 		st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL *
1037 						    adc_clk_khz / 1000) - 1, 1);
1038 
1039 		return 0;
1040 	}
1041 
1042 	/* Touchscreen Switches Closure time needed for allowing the value to
1043 	 * stabilize.
1044 	 * Switch Closure Time = (TSSCTIM * 4) ADCClock periods
1045 	 */
1046 	tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4);
1047 	dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n",
1048 		adc_clk_khz, tssctim);
1049 
1050 	if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
1051 		reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS;
1052 	else
1053 		reg = AT91_ADC_TSMR_TSMODE_5WIRE;
1054 
1055 	reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM;
1056 	reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average)
1057 	       & AT91_ADC_TSMR_TSAV;
1058 	reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC;
1059 	reg |= AT91_ADC_TSMR_NOTSDMA;
1060 	reg |= AT91_ADC_TSMR_PENDET_ENA;
1061 	reg |= 0x03 << 8;	/* TSFREQ, needs to be bigger than TSAV */
1062 
1063 	at91_adc_writel(st, AT91_ADC_TSMR, reg);
1064 
1065 	/* Change adc internal resistor value for better pen detection,
1066 	 * default value is 100 kOhm.
1067 	 * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm
1068 	 * option only available on ES2 and higher
1069 	 */
1070 	at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity
1071 			& AT91_ADC_ACR_PENDETSENS);
1072 
1073 	/* Sample Period Time = (TRGPER + 1) / ADCClock */
1074 	st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US *
1075 			adc_clk_khz / 1000) - 1, 1);
1076 
1077 	return 0;
1078 }
1079 
1080 static int at91_ts_register(struct at91_adc_state *st,
1081 		struct platform_device *pdev)
1082 {
1083 	struct input_dev *input;
1084 	struct iio_dev *idev = iio_priv_to_dev(st);
1085 	int ret;
1086 
1087 	input = input_allocate_device();
1088 	if (!input) {
1089 		dev_err(&idev->dev, "Failed to allocate TS device!\n");
1090 		return -ENOMEM;
1091 	}
1092 
1093 	input->name = DRIVER_NAME;
1094 	input->id.bustype = BUS_HOST;
1095 	input->dev.parent = &pdev->dev;
1096 	input->open = atmel_ts_open;
1097 	input->close = atmel_ts_close;
1098 
1099 	__set_bit(EV_ABS, input->evbit);
1100 	__set_bit(EV_KEY, input->evbit);
1101 	__set_bit(BTN_TOUCH, input->keybit);
1102 	if (st->caps->has_tsmr) {
1103 		input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1,
1104 				     0, 0);
1105 		input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1,
1106 				     0, 0);
1107 		input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0);
1108 	} else {
1109 		if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) {
1110 			dev_err(&pdev->dev,
1111 				"This touchscreen controller only support 4 wires\n");
1112 			ret = -EINVAL;
1113 			goto err;
1114 		}
1115 
1116 		input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1,
1117 				     0, 0);
1118 		input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1,
1119 				     0, 0);
1120 	}
1121 
1122 	st->ts_input = input;
1123 	input_set_drvdata(input, st);
1124 
1125 	ret = input_register_device(input);
1126 	if (ret)
1127 		goto err;
1128 
1129 	return ret;
1130 
1131 err:
1132 	input_free_device(st->ts_input);
1133 	return ret;
1134 }
1135 
1136 static void at91_ts_unregister(struct at91_adc_state *st)
1137 {
1138 	input_unregister_device(st->ts_input);
1139 }
1140 
1141 static int at91_adc_probe(struct platform_device *pdev)
1142 {
1143 	unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
1144 	int ret;
1145 	struct iio_dev *idev;
1146 	struct at91_adc_state *st;
1147 	struct resource *res;
1148 	u32 reg;
1149 
1150 	idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state));
1151 	if (!idev)
1152 		return -ENOMEM;
1153 
1154 	st = iio_priv(idev);
1155 
1156 	if (pdev->dev.of_node)
1157 		ret = at91_adc_probe_dt(st, pdev);
1158 	else
1159 		ret = at91_adc_probe_pdata(st, pdev);
1160 
1161 	if (ret) {
1162 		dev_err(&pdev->dev, "No platform data available.\n");
1163 		return -EINVAL;
1164 	}
1165 
1166 	platform_set_drvdata(pdev, idev);
1167 
1168 	idev->dev.parent = &pdev->dev;
1169 	idev->name = dev_name(&pdev->dev);
1170 	idev->modes = INDIO_DIRECT_MODE;
1171 	idev->info = &at91_adc_info;
1172 
1173 	st->irq = platform_get_irq(pdev, 0);
1174 	if (st->irq < 0) {
1175 		dev_err(&pdev->dev, "No IRQ ID is designated\n");
1176 		return -ENODEV;
1177 	}
1178 
1179 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1180 
1181 	st->reg_base = devm_ioremap_resource(&pdev->dev, res);
1182 	if (IS_ERR(st->reg_base)) {
1183 		return PTR_ERR(st->reg_base);
1184 	}
1185 
1186 	/*
1187 	 * Disable all IRQs before setting up the handler
1188 	 */
1189 	at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
1190 	at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
1191 
1192 	if (st->caps->has_tsmr)
1193 		ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0,
1194 				  pdev->dev.driver->name, idev);
1195 	else
1196 		ret = request_irq(st->irq, at91_adc_rl_interrupt, 0,
1197 				  pdev->dev.driver->name, idev);
1198 	if (ret) {
1199 		dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
1200 		return ret;
1201 	}
1202 
1203 	st->clk = devm_clk_get(&pdev->dev, "adc_clk");
1204 	if (IS_ERR(st->clk)) {
1205 		dev_err(&pdev->dev, "Failed to get the clock.\n");
1206 		ret = PTR_ERR(st->clk);
1207 		goto error_free_irq;
1208 	}
1209 
1210 	ret = clk_prepare_enable(st->clk);
1211 	if (ret) {
1212 		dev_err(&pdev->dev,
1213 			"Could not prepare or enable the clock.\n");
1214 		goto error_free_irq;
1215 	}
1216 
1217 	st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
1218 	if (IS_ERR(st->adc_clk)) {
1219 		dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
1220 		ret = PTR_ERR(st->adc_clk);
1221 		goto error_disable_clk;
1222 	}
1223 
1224 	ret = clk_prepare_enable(st->adc_clk);
1225 	if (ret) {
1226 		dev_err(&pdev->dev,
1227 			"Could not prepare or enable the ADC clock.\n");
1228 		goto error_disable_clk;
1229 	}
1230 
1231 	/*
1232 	 * Prescaler rate computation using the formula from the Atmel's
1233 	 * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
1234 	 * specified by the electrical characteristics of the board.
1235 	 */
1236 	mstrclk = clk_get_rate(st->clk);
1237 	adc_clk = clk_get_rate(st->adc_clk);
1238 	adc_clk_khz = adc_clk / 1000;
1239 
1240 	dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n",
1241 		mstrclk, adc_clk);
1242 
1243 	prsc = (mstrclk / (2 * adc_clk)) - 1;
1244 
1245 	if (!st->startup_time) {
1246 		dev_err(&pdev->dev, "No startup time available.\n");
1247 		ret = -EINVAL;
1248 		goto error_disable_adc_clk;
1249 	}
1250 	ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz);
1251 
1252 	/*
1253 	 * a minimal Sample and Hold Time is necessary for the ADC to guarantee
1254 	 * the best converted final value between two channels selection
1255 	 * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
1256 	 */
1257 	if (st->sample_hold_time > 0)
1258 		shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000)
1259 				 - 1, 1);
1260 	else
1261 		shtim = 0;
1262 
1263 	reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
1264 	reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
1265 	if (st->low_res)
1266 		reg |= AT91_ADC_LOWRES;
1267 	if (st->sleep_mode)
1268 		reg |= AT91_ADC_SLEEP;
1269 	reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM;
1270 	at91_adc_writel(st, AT91_ADC_MR, reg);
1271 
1272 	/* Setup the ADC channels available on the board */
1273 	ret = at91_adc_channel_init(idev);
1274 	if (ret < 0) {
1275 		dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
1276 		goto error_disable_adc_clk;
1277 	}
1278 
1279 	init_waitqueue_head(&st->wq_data_avail);
1280 	mutex_init(&st->lock);
1281 
1282 	/*
1283 	 * Since touch screen will set trigger register as period trigger. So
1284 	 * when touch screen is enabled, then we have to disable hardware
1285 	 * trigger for classic adc.
1286 	 */
1287 	if (!st->touchscreen_type) {
1288 		ret = at91_adc_buffer_init(idev);
1289 		if (ret < 0) {
1290 			dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
1291 			goto error_disable_adc_clk;
1292 		}
1293 
1294 		ret = at91_adc_trigger_init(idev);
1295 		if (ret < 0) {
1296 			dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
1297 			at91_adc_buffer_remove(idev);
1298 			goto error_disable_adc_clk;
1299 		}
1300 	} else {
1301 		ret = at91_ts_register(st, pdev);
1302 		if (ret)
1303 			goto error_disable_adc_clk;
1304 
1305 		at91_ts_hw_init(st, adc_clk_khz);
1306 	}
1307 
1308 	ret = iio_device_register(idev);
1309 	if (ret < 0) {
1310 		dev_err(&pdev->dev, "Couldn't register the device.\n");
1311 		goto error_iio_device_register;
1312 	}
1313 
1314 	return 0;
1315 
1316 error_iio_device_register:
1317 	if (!st->touchscreen_type) {
1318 		at91_adc_trigger_remove(idev);
1319 		at91_adc_buffer_remove(idev);
1320 	} else {
1321 		at91_ts_unregister(st);
1322 	}
1323 error_disable_adc_clk:
1324 	clk_disable_unprepare(st->adc_clk);
1325 error_disable_clk:
1326 	clk_disable_unprepare(st->clk);
1327 error_free_irq:
1328 	free_irq(st->irq, idev);
1329 	return ret;
1330 }
1331 
1332 static int at91_adc_remove(struct platform_device *pdev)
1333 {
1334 	struct iio_dev *idev = platform_get_drvdata(pdev);
1335 	struct at91_adc_state *st = iio_priv(idev);
1336 
1337 	iio_device_unregister(idev);
1338 	if (!st->touchscreen_type) {
1339 		at91_adc_trigger_remove(idev);
1340 		at91_adc_buffer_remove(idev);
1341 	} else {
1342 		at91_ts_unregister(st);
1343 	}
1344 	clk_disable_unprepare(st->adc_clk);
1345 	clk_disable_unprepare(st->clk);
1346 	free_irq(st->irq, idev);
1347 
1348 	return 0;
1349 }
1350 
1351 #ifdef CONFIG_PM_SLEEP
1352 static int at91_adc_suspend(struct device *dev)
1353 {
1354 	struct iio_dev *idev = platform_get_drvdata(to_platform_device(dev));
1355 	struct at91_adc_state *st = iio_priv(idev);
1356 
1357 	pinctrl_pm_select_sleep_state(dev);
1358 	clk_disable_unprepare(st->clk);
1359 
1360 	return 0;
1361 }
1362 
1363 static int at91_adc_resume(struct device *dev)
1364 {
1365 	struct iio_dev *idev = platform_get_drvdata(to_platform_device(dev));
1366 	struct at91_adc_state *st = iio_priv(idev);
1367 
1368 	clk_prepare_enable(st->clk);
1369 	pinctrl_pm_select_default_state(dev);
1370 
1371 	return 0;
1372 }
1373 #endif
1374 
1375 static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume);
1376 
1377 static struct at91_adc_caps at91sam9260_caps = {
1378 	.calc_startup_ticks = calc_startup_ticks_9260,
1379 	.num_channels = 4,
1380 	.registers = {
1381 		.channel_base = AT91_ADC_CHR(0),
1382 		.drdy_mask = AT91_ADC_DRDY,
1383 		.status_register = AT91_ADC_SR,
1384 		.trigger_register = AT91_ADC_TRGR_9260,
1385 		.mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1386 		.mr_startup_mask = AT91_ADC_STARTUP_9260,
1387 	},
1388 };
1389 
1390 static struct at91_adc_caps at91sam9rl_caps = {
1391 	.has_ts = true,
1392 	.calc_startup_ticks = calc_startup_ticks_9260,	/* same as 9260 */
1393 	.num_channels = 6,
1394 	.registers = {
1395 		.channel_base = AT91_ADC_CHR(0),
1396 		.drdy_mask = AT91_ADC_DRDY,
1397 		.status_register = AT91_ADC_SR,
1398 		.trigger_register = AT91_ADC_TRGR_9G45,
1399 		.mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1400 		.mr_startup_mask = AT91_ADC_STARTUP_9G45,
1401 	},
1402 };
1403 
1404 static struct at91_adc_caps at91sam9g45_caps = {
1405 	.has_ts = true,
1406 	.calc_startup_ticks = calc_startup_ticks_9260,	/* same as 9260 */
1407 	.num_channels = 8,
1408 	.registers = {
1409 		.channel_base = AT91_ADC_CHR(0),
1410 		.drdy_mask = AT91_ADC_DRDY,
1411 		.status_register = AT91_ADC_SR,
1412 		.trigger_register = AT91_ADC_TRGR_9G45,
1413 		.mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1414 		.mr_startup_mask = AT91_ADC_STARTUP_9G45,
1415 	},
1416 };
1417 
1418 static struct at91_adc_caps at91sam9x5_caps = {
1419 	.has_ts = true,
1420 	.has_tsmr = true,
1421 	.ts_filter_average = 3,
1422 	.ts_pen_detect_sensitivity = 2,
1423 	.calc_startup_ticks = calc_startup_ticks_9x5,
1424 	.num_channels = 12,
1425 	.registers = {
1426 		.channel_base = AT91_ADC_CDR0_9X5,
1427 		.drdy_mask = AT91_ADC_SR_DRDY_9X5,
1428 		.status_register = AT91_ADC_SR_9X5,
1429 		.trigger_register = AT91_ADC_TRGR_9X5,
1430 		/* prescal mask is same as 9G45 */
1431 		.mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1432 		.mr_startup_mask = AT91_ADC_STARTUP_9X5,
1433 	},
1434 };
1435 
1436 static const struct of_device_id at91_adc_dt_ids[] = {
1437 	{ .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps },
1438 	{ .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps },
1439 	{ .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps },
1440 	{ .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps },
1441 	{},
1442 };
1443 MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
1444 
1445 static const struct platform_device_id at91_adc_ids[] = {
1446 	{
1447 		.name = "at91sam9260-adc",
1448 		.driver_data = (unsigned long)&at91sam9260_caps,
1449 	}, {
1450 		.name = "at91sam9rl-adc",
1451 		.driver_data = (unsigned long)&at91sam9rl_caps,
1452 	}, {
1453 		.name = "at91sam9g45-adc",
1454 		.driver_data = (unsigned long)&at91sam9g45_caps,
1455 	}, {
1456 		.name = "at91sam9x5-adc",
1457 		.driver_data = (unsigned long)&at91sam9x5_caps,
1458 	}, {
1459 		/* terminator */
1460 	}
1461 };
1462 MODULE_DEVICE_TABLE(platform, at91_adc_ids);
1463 
1464 static struct platform_driver at91_adc_driver = {
1465 	.probe = at91_adc_probe,
1466 	.remove = at91_adc_remove,
1467 	.id_table = at91_adc_ids,
1468 	.driver = {
1469 		   .name = DRIVER_NAME,
1470 		   .of_match_table = of_match_ptr(at91_adc_dt_ids),
1471 		   .pm = &at91_adc_pm_ops,
1472 	},
1473 };
1474 
1475 module_platform_driver(at91_adc_driver);
1476 
1477 MODULE_LICENSE("GPL");
1478 MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
1479 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1480