10e589d5fSMaxime Ripard /* 20e589d5fSMaxime Ripard * Driver for the ADC present in the Atmel AT91 evaluation boards. 30e589d5fSMaxime Ripard * 40e589d5fSMaxime Ripard * Copyright 2011 Free Electrons 50e589d5fSMaxime Ripard * 60e589d5fSMaxime Ripard * Licensed under the GPLv2 or later. 70e589d5fSMaxime Ripard */ 80e589d5fSMaxime Ripard 90e589d5fSMaxime Ripard #include <linux/bitmap.h> 100e589d5fSMaxime Ripard #include <linux/bitops.h> 110e589d5fSMaxime Ripard #include <linux/clk.h> 120e589d5fSMaxime Ripard #include <linux/err.h> 130e589d5fSMaxime Ripard #include <linux/io.h> 14c8b11de0SJosh Wu #include <linux/input.h> 150e589d5fSMaxime Ripard #include <linux/interrupt.h> 160e589d5fSMaxime Ripard #include <linux/jiffies.h> 170e589d5fSMaxime Ripard #include <linux/kernel.h> 180e589d5fSMaxime Ripard #include <linux/module.h> 19e364185fSMaxime Ripard #include <linux/of.h> 20e364185fSMaxime Ripard #include <linux/of_device.h> 210e589d5fSMaxime Ripard #include <linux/platform_device.h> 220e589d5fSMaxime Ripard #include <linux/sched.h> 230e589d5fSMaxime Ripard #include <linux/slab.h> 240e589d5fSMaxime Ripard #include <linux/wait.h> 250e589d5fSMaxime Ripard 260e589d5fSMaxime Ripard #include <linux/platform_data/at91_adc.h> 270e589d5fSMaxime Ripard 280e589d5fSMaxime Ripard #include <linux/iio/iio.h> 290e589d5fSMaxime Ripard #include <linux/iio/buffer.h> 300e589d5fSMaxime Ripard #include <linux/iio/trigger.h> 310e589d5fSMaxime Ripard #include <linux/iio/trigger_consumer.h> 3290032e4eSLars-Peter Clausen #include <linux/iio/triggered_buffer.h> 330e589d5fSMaxime Ripard 34bee20c4bSAlexandre Belloni /* Registers */ 35bee20c4bSAlexandre Belloni #define AT91_ADC_CR 0x00 /* Control Register */ 36bee20c4bSAlexandre Belloni #define AT91_ADC_SWRST (1 << 0) /* Software Reset */ 37bee20c4bSAlexandre Belloni #define AT91_ADC_START (1 << 1) /* Start Conversion */ 38bee20c4bSAlexandre Belloni 39bee20c4bSAlexandre Belloni #define AT91_ADC_MR 0x04 /* Mode Register */ 40bee20c4bSAlexandre Belloni #define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */ 41bee20c4bSAlexandre Belloni #define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */ 42bee20c4bSAlexandre Belloni #define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */ 43bee20c4bSAlexandre Belloni #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */ 44bee20c4bSAlexandre Belloni #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */ 45bee20c4bSAlexandre Belloni #define AT91_ADC_TRGSEL_TC0 (0 << 1) 46bee20c4bSAlexandre Belloni #define AT91_ADC_TRGSEL_TC1 (1 << 1) 47bee20c4bSAlexandre Belloni #define AT91_ADC_TRGSEL_TC2 (2 << 1) 48bee20c4bSAlexandre Belloni #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1) 49bee20c4bSAlexandre Belloni #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */ 50bee20c4bSAlexandre Belloni #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */ 51bee20c4bSAlexandre Belloni #define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */ 52bee20c4bSAlexandre Belloni #define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */ 53bee20c4bSAlexandre Belloni #define AT91_ADC_PRESCAL_9G45 (0xff << 8) 54bee20c4bSAlexandre Belloni #define AT91_ADC_PRESCAL_(x) ((x) << 8) 55bee20c4bSAlexandre Belloni #define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */ 56bee20c4bSAlexandre Belloni #define AT91_ADC_STARTUP_9G45 (0x7f << 16) 57bee20c4bSAlexandre Belloni #define AT91_ADC_STARTUP_9X5 (0xf << 16) 58bee20c4bSAlexandre Belloni #define AT91_ADC_STARTUP_(x) ((x) << 16) 59bee20c4bSAlexandre Belloni #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */ 60bee20c4bSAlexandre Belloni #define AT91_ADC_SHTIM_(x) ((x) << 24) 61bee20c4bSAlexandre Belloni #define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */ 62bee20c4bSAlexandre Belloni #define AT91_ADC_PENDBC_(x) ((x) << 28) 63bee20c4bSAlexandre Belloni 64bee20c4bSAlexandre Belloni #define AT91_ADC_TSR 0x0C 65bee20c4bSAlexandre Belloni #define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */ 66bee20c4bSAlexandre Belloni #define AT91_ADC_TSR_SHTIM_(x) ((x) << 24) 67bee20c4bSAlexandre Belloni 68bee20c4bSAlexandre Belloni #define AT91_ADC_CHER 0x10 /* Channel Enable Register */ 69bee20c4bSAlexandre Belloni #define AT91_ADC_CHDR 0x14 /* Channel Disable Register */ 70bee20c4bSAlexandre Belloni #define AT91_ADC_CHSR 0x18 /* Channel Status Register */ 71bee20c4bSAlexandre Belloni #define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */ 72bee20c4bSAlexandre Belloni 73bee20c4bSAlexandre Belloni #define AT91_ADC_SR 0x1C /* Status Register */ 74bee20c4bSAlexandre Belloni #define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */ 75bee20c4bSAlexandre Belloni #define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */ 76bee20c4bSAlexandre Belloni #define AT91_ADC_DRDY (1 << 16) /* Data Ready */ 77bee20c4bSAlexandre Belloni #define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */ 78bee20c4bSAlexandre Belloni #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */ 79bee20c4bSAlexandre Belloni #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */ 80bee20c4bSAlexandre Belloni 81bee20c4bSAlexandre Belloni #define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */ 82bee20c4bSAlexandre Belloni #define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */ 83bee20c4bSAlexandre Belloni 84bee20c4bSAlexandre Belloni #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */ 85bee20c4bSAlexandre Belloni #define AT91_ADC_LDATA (0x3ff) 86bee20c4bSAlexandre Belloni 87bee20c4bSAlexandre Belloni #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */ 88bee20c4bSAlexandre Belloni #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */ 89bee20c4bSAlexandre Belloni #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */ 90bee20c4bSAlexandre Belloni #define AT91RL_ADC_IER_PEN (1 << 20) 91bee20c4bSAlexandre Belloni #define AT91RL_ADC_IER_NOPEN (1 << 21) 92bee20c4bSAlexandre Belloni #define AT91_ADC_IER_PEN (1 << 29) 93bee20c4bSAlexandre Belloni #define AT91_ADC_IER_NOPEN (1 << 30) 94bee20c4bSAlexandre Belloni #define AT91_ADC_IER_XRDY (1 << 20) 95bee20c4bSAlexandre Belloni #define AT91_ADC_IER_YRDY (1 << 21) 96bee20c4bSAlexandre Belloni #define AT91_ADC_IER_PRDY (1 << 22) 97bee20c4bSAlexandre Belloni #define AT91_ADC_ISR_PENS (1 << 31) 98bee20c4bSAlexandre Belloni 99bee20c4bSAlexandre Belloni #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */ 100bee20c4bSAlexandre Belloni #define AT91_ADC_DATA (0x3ff) 101bee20c4bSAlexandre Belloni 102bee20c4bSAlexandre Belloni #define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */ 103bee20c4bSAlexandre Belloni 104bee20c4bSAlexandre Belloni #define AT91_ADC_ACR 0x94 /* Analog Control Register */ 105bee20c4bSAlexandre Belloni #define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */ 106bee20c4bSAlexandre Belloni 107bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR 0xB0 108bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */ 109bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_TSMODE_NONE (0 << 0) 110bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0) 111bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0) 112bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0) 113bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */ 114bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_TSAV_(x) ((x) << 4) 115bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */ 116bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */ 117bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28) 118bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */ 119bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */ 120bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */ 121bee20c4bSAlexandre Belloni 122bee20c4bSAlexandre Belloni #define AT91_ADC_TSXPOSR 0xB4 123bee20c4bSAlexandre Belloni #define AT91_ADC_TSYPOSR 0xB8 124bee20c4bSAlexandre Belloni #define AT91_ADC_TSPRESSR 0xBC 125bee20c4bSAlexandre Belloni 126bee20c4bSAlexandre Belloni #define AT91_ADC_TRGR_9260 AT91_ADC_MR 127bee20c4bSAlexandre Belloni #define AT91_ADC_TRGR_9G45 0x08 128bee20c4bSAlexandre Belloni #define AT91_ADC_TRGR_9X5 0xC0 129bee20c4bSAlexandre Belloni 130bee20c4bSAlexandre Belloni /* Trigger Register bit field */ 131bee20c4bSAlexandre Belloni #define AT91_ADC_TRGR_TRGPER (0xffff << 16) 132bee20c4bSAlexandre Belloni #define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16) 133bee20c4bSAlexandre Belloni #define AT91_ADC_TRGR_TRGMOD (0x7 << 0) 134bee20c4bSAlexandre Belloni #define AT91_ADC_TRGR_NONE (0 << 0) 135bee20c4bSAlexandre Belloni #define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0) 1360e589d5fSMaxime Ripard 1370e589d5fSMaxime Ripard #define AT91_ADC_CHAN(st, ch) \ 1380e589d5fSMaxime Ripard (st->registers->channel_base + (ch * 4)) 1390e589d5fSMaxime Ripard #define at91_adc_readl(st, reg) \ 1400e589d5fSMaxime Ripard (readl_relaxed(st->reg_base + reg)) 1410e589d5fSMaxime Ripard #define at91_adc_writel(st, reg, val) \ 1420e589d5fSMaxime Ripard (writel_relaxed(val, st->reg_base + reg)) 1430e589d5fSMaxime Ripard 144c8b11de0SJosh Wu #define DRIVER_NAME "at91_adc" 145c8b11de0SJosh Wu #define MAX_POS_BITS 12 146c8b11de0SJosh Wu 147c8b11de0SJosh Wu #define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */ 148c8b11de0SJosh Wu #define TOUCH_PEN_DETECT_DEBOUNCE_US 200 149c8b11de0SJosh Wu 15084882b06SAlexandre Belloni #define MAX_RLPOS_BITS 10 15184882b06SAlexandre Belloni #define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */ 15284882b06SAlexandre Belloni #define TOUCH_SHTIM 0xa 15384882b06SAlexandre Belloni 1542de0c019SAlexandre Belloni /** 1552de0c019SAlexandre Belloni * struct at91_adc_reg_desc - Various informations relative to registers 1562de0c019SAlexandre Belloni * @channel_base: Base offset for the channel data registers 1572de0c019SAlexandre Belloni * @drdy_mask: Mask of the DRDY field in the relevant registers 1582de0c019SAlexandre Belloni (Interruptions registers mostly) 1592de0c019SAlexandre Belloni * @status_register: Offset of the Interrupt Status Register 1602de0c019SAlexandre Belloni * @trigger_register: Offset of the Trigger setup register 1612de0c019SAlexandre Belloni * @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register 1622de0c019SAlexandre Belloni * @mr_startup_mask: Mask of the STARTUP field in the adc MR register 1632de0c019SAlexandre Belloni */ 1642de0c019SAlexandre Belloni struct at91_adc_reg_desc { 1652de0c019SAlexandre Belloni u8 channel_base; 1662de0c019SAlexandre Belloni u32 drdy_mask; 1672de0c019SAlexandre Belloni u8 status_register; 1682de0c019SAlexandre Belloni u8 trigger_register; 1692de0c019SAlexandre Belloni u32 mr_prescal_mask; 1702de0c019SAlexandre Belloni u32 mr_startup_mask; 1712de0c019SAlexandre Belloni }; 1722de0c019SAlexandre Belloni 173e1811f97SJosh Wu struct at91_adc_caps { 174c8b11de0SJosh Wu bool has_ts; /* Support touch screen */ 175c8b11de0SJosh Wu bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */ 176c8b11de0SJosh Wu /* 177c8b11de0SJosh Wu * Numbers of sampling data will be averaged. Can be 0~3. 178c8b11de0SJosh Wu * Hardware can average (2 ^ ts_filter_average) sample data. 179c8b11de0SJosh Wu */ 180c8b11de0SJosh Wu u8 ts_filter_average; 181c8b11de0SJosh Wu /* Pen Detection input pull-up resistor, can be 0~3 */ 182c8b11de0SJosh Wu u8 ts_pen_detect_sensitivity; 183c8b11de0SJosh Wu 184c4601666SJosh Wu /* startup time calculate function */ 1852ab5f39bSJan Leupold u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz); 186c4601666SJosh Wu 1872b6d598bSJosh Wu u8 num_channels; 188e1811f97SJosh Wu struct at91_adc_reg_desc registers; 189e1811f97SJosh Wu }; 190e1811f97SJosh Wu 1910e589d5fSMaxime Ripard struct at91_adc_state { 1920e589d5fSMaxime Ripard struct clk *adc_clk; 1930e589d5fSMaxime Ripard u16 *buffer; 1940e589d5fSMaxime Ripard unsigned long channels_mask; 1950e589d5fSMaxime Ripard struct clk *clk; 1960e589d5fSMaxime Ripard bool done; 1970e589d5fSMaxime Ripard int irq; 1980e589d5fSMaxime Ripard u16 last_value; 199d4f51956SLudovic Desroches int chnb; 2000e589d5fSMaxime Ripard struct mutex lock; 2010e589d5fSMaxime Ripard u8 num_channels; 2020e589d5fSMaxime Ripard void __iomem *reg_base; 2030e589d5fSMaxime Ripard struct at91_adc_reg_desc *registers; 2042ab5f39bSJan Leupold u32 startup_time; 205beca9e76SJean-Christophe PLAGNIOL-VILLARD u8 sample_hold_time; 206e748783cSJean-Christophe PLAGNIOL-VILLARD bool sleep_mode; 2070e589d5fSMaxime Ripard struct iio_trigger **trig; 2080e589d5fSMaxime Ripard struct at91_adc_trigger *trigger_list; 2090e589d5fSMaxime Ripard u32 trigger_number; 2100e589d5fSMaxime Ripard bool use_external; 2110e589d5fSMaxime Ripard u32 vref_mv; 21247be16b6SLudovic Desroches u32 res; /* resolution used for convertions */ 21347be16b6SLudovic Desroches bool low_res; /* the resolution corresponds to the lowest one */ 2140e589d5fSMaxime Ripard wait_queue_head_t wq_data_avail; 215e1811f97SJosh Wu struct at91_adc_caps *caps; 216c8b11de0SJosh Wu 217c8b11de0SJosh Wu /* 218c8b11de0SJosh Wu * Following ADC channels are shared by touchscreen: 219c8b11de0SJosh Wu * 220c8b11de0SJosh Wu * CH0 -- Touch screen XP/UL 221c8b11de0SJosh Wu * CH1 -- Touch screen XM/UR 222c8b11de0SJosh Wu * CH2 -- Touch screen YP/LL 223c8b11de0SJosh Wu * CH3 -- Touch screen YM/Sense 224c8b11de0SJosh Wu * CH4 -- Touch screen LR(5-wire only) 225c8b11de0SJosh Wu * 226c8b11de0SJosh Wu * The bitfields below represents the reserved channel in the 227c8b11de0SJosh Wu * touchscreen mode. 228c8b11de0SJosh Wu */ 229c8b11de0SJosh Wu #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0) 230c8b11de0SJosh Wu #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0) 231c8b11de0SJosh Wu enum atmel_adc_ts_type touchscreen_type; 232c8b11de0SJosh Wu struct input_dev *ts_input; 233c8b11de0SJosh Wu 234c8b11de0SJosh Wu u16 ts_sample_period_val; 235c8b11de0SJosh Wu u32 ts_pressure_threshold; 23684882b06SAlexandre Belloni u16 ts_pendbc; 23784882b06SAlexandre Belloni 23884882b06SAlexandre Belloni bool ts_bufferedmeasure; 23984882b06SAlexandre Belloni u32 ts_prev_absx; 24084882b06SAlexandre Belloni u32 ts_prev_absy; 2410e589d5fSMaxime Ripard }; 2420e589d5fSMaxime Ripard 2430e589d5fSMaxime Ripard static irqreturn_t at91_adc_trigger_handler(int irq, void *p) 2440e589d5fSMaxime Ripard { 2450e589d5fSMaxime Ripard struct iio_poll_func *pf = p; 2460e589d5fSMaxime Ripard struct iio_dev *idev = pf->indio_dev; 2470e589d5fSMaxime Ripard struct at91_adc_state *st = iio_priv(idev); 2480e589d5fSMaxime Ripard int i, j = 0; 2490e589d5fSMaxime Ripard 2500e589d5fSMaxime Ripard for (i = 0; i < idev->masklength; i++) { 2510e589d5fSMaxime Ripard if (!test_bit(i, idev->active_scan_mask)) 2520e589d5fSMaxime Ripard continue; 2530e589d5fSMaxime Ripard st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, i)); 2540e589d5fSMaxime Ripard j++; 2550e589d5fSMaxime Ripard } 2560e589d5fSMaxime Ripard 257e79cece0SLars-Peter Clausen iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp); 2580e589d5fSMaxime Ripard 2590e589d5fSMaxime Ripard iio_trigger_notify_done(idev->trig); 2600e589d5fSMaxime Ripard 2610e589d5fSMaxime Ripard /* Needed to ACK the DRDY interruption */ 2620e589d5fSMaxime Ripard at91_adc_readl(st, AT91_ADC_LCDR); 2630e589d5fSMaxime Ripard 2640e589d5fSMaxime Ripard enable_irq(st->irq); 2650e589d5fSMaxime Ripard 2660e589d5fSMaxime Ripard return IRQ_HANDLED; 2670e589d5fSMaxime Ripard } 2680e589d5fSMaxime Ripard 269c8b11de0SJosh Wu /* Handler for classic adc channel eoc trigger */ 2703068ab20SJosh Wu static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev) 2710e589d5fSMaxime Ripard { 2720e589d5fSMaxime Ripard struct at91_adc_state *st = iio_priv(idev); 2730e589d5fSMaxime Ripard 2740e589d5fSMaxime Ripard if (iio_buffer_enabled(idev)) { 2750e589d5fSMaxime Ripard disable_irq_nosync(irq); 276398fd22bSPeter Meerwald iio_trigger_poll(idev->trig); 2770e589d5fSMaxime Ripard } else { 278d4f51956SLudovic Desroches st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb)); 2790e589d5fSMaxime Ripard st->done = true; 2800e589d5fSMaxime Ripard wake_up_interruptible(&st->wq_data_avail); 2810e589d5fSMaxime Ripard } 282c8b11de0SJosh Wu } 283c8b11de0SJosh Wu 284c8b11de0SJosh Wu static int at91_ts_sample(struct at91_adc_state *st) 285c8b11de0SJosh Wu { 286c8b11de0SJosh Wu unsigned int xscale, yscale, reg, z1, z2; 287c8b11de0SJosh Wu unsigned int x, y, pres, xpos, ypos; 288c8b11de0SJosh Wu unsigned int rxp = 1; 289c8b11de0SJosh Wu unsigned int factor = 1000; 290c8b11de0SJosh Wu struct iio_dev *idev = iio_priv_to_dev(st); 291c8b11de0SJosh Wu 292c8b11de0SJosh Wu unsigned int xyz_mask_bits = st->res; 293c8b11de0SJosh Wu unsigned int xyz_mask = (1 << xyz_mask_bits) - 1; 294c8b11de0SJosh Wu 295c8b11de0SJosh Wu /* calculate position */ 296c8b11de0SJosh Wu /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */ 297c8b11de0SJosh Wu reg = at91_adc_readl(st, AT91_ADC_TSXPOSR); 298c8b11de0SJosh Wu xpos = reg & xyz_mask; 299c8b11de0SJosh Wu x = (xpos << MAX_POS_BITS) - xpos; 300c8b11de0SJosh Wu xscale = (reg >> 16) & xyz_mask; 301c8b11de0SJosh Wu if (xscale == 0) { 302c8b11de0SJosh Wu dev_err(&idev->dev, "Error: xscale == 0!\n"); 303c8b11de0SJosh Wu return -1; 304c8b11de0SJosh Wu } 305c8b11de0SJosh Wu x /= xscale; 306c8b11de0SJosh Wu 307c8b11de0SJosh Wu /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */ 308c8b11de0SJosh Wu reg = at91_adc_readl(st, AT91_ADC_TSYPOSR); 309c8b11de0SJosh Wu ypos = reg & xyz_mask; 310c8b11de0SJosh Wu y = (ypos << MAX_POS_BITS) - ypos; 311c8b11de0SJosh Wu yscale = (reg >> 16) & xyz_mask; 312c8b11de0SJosh Wu if (yscale == 0) { 313c8b11de0SJosh Wu dev_err(&idev->dev, "Error: yscale == 0!\n"); 314c8b11de0SJosh Wu return -1; 315c8b11de0SJosh Wu } 316c8b11de0SJosh Wu y /= yscale; 317c8b11de0SJosh Wu 318c8b11de0SJosh Wu /* calculate the pressure */ 319c8b11de0SJosh Wu reg = at91_adc_readl(st, AT91_ADC_TSPRESSR); 320c8b11de0SJosh Wu z1 = reg & xyz_mask; 321c8b11de0SJosh Wu z2 = (reg >> 16) & xyz_mask; 322c8b11de0SJosh Wu 323c8b11de0SJosh Wu if (z1 != 0) 324c8b11de0SJosh Wu pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor) 325c8b11de0SJosh Wu / factor; 326c8b11de0SJosh Wu else 327c8b11de0SJosh Wu pres = st->ts_pressure_threshold; /* no pen contacted */ 328c8b11de0SJosh Wu 329c8b11de0SJosh Wu dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n", 330c8b11de0SJosh Wu xpos, xscale, ypos, yscale, z1, z2, pres); 331c8b11de0SJosh Wu 332c8b11de0SJosh Wu if (pres < st->ts_pressure_threshold) { 333c8b11de0SJosh Wu dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n", 334c8b11de0SJosh Wu x, y, pres / factor); 335c8b11de0SJosh Wu input_report_abs(st->ts_input, ABS_X, x); 336c8b11de0SJosh Wu input_report_abs(st->ts_input, ABS_Y, y); 337c8b11de0SJosh Wu input_report_abs(st->ts_input, ABS_PRESSURE, pres); 338c8b11de0SJosh Wu input_report_key(st->ts_input, BTN_TOUCH, 1); 339c8b11de0SJosh Wu input_sync(st->ts_input); 340c8b11de0SJosh Wu } else { 341c8b11de0SJosh Wu dev_dbg(&idev->dev, "pressure too low: not reporting\n"); 342c8b11de0SJosh Wu } 343c8b11de0SJosh Wu 344c8b11de0SJosh Wu return 0; 345c8b11de0SJosh Wu } 346c8b11de0SJosh Wu 34784882b06SAlexandre Belloni static irqreturn_t at91_adc_rl_interrupt(int irq, void *private) 34884882b06SAlexandre Belloni { 34984882b06SAlexandre Belloni struct iio_dev *idev = private; 35084882b06SAlexandre Belloni struct at91_adc_state *st = iio_priv(idev); 35184882b06SAlexandre Belloni u32 status = at91_adc_readl(st, st->registers->status_register); 35284882b06SAlexandre Belloni unsigned int reg; 35384882b06SAlexandre Belloni 35484882b06SAlexandre Belloni status &= at91_adc_readl(st, AT91_ADC_IMR); 355d4f51956SLudovic Desroches if (status & GENMASK(st->num_channels - 1, 0)) 35684882b06SAlexandre Belloni handle_adc_eoc_trigger(irq, idev); 35784882b06SAlexandre Belloni 35884882b06SAlexandre Belloni if (status & AT91RL_ADC_IER_PEN) { 35984882b06SAlexandre Belloni /* Disabling pen debounce is required to get a NOPEN irq */ 36084882b06SAlexandre Belloni reg = at91_adc_readl(st, AT91_ADC_MR); 36184882b06SAlexandre Belloni reg &= ~AT91_ADC_PENDBC; 36284882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_MR, reg); 36384882b06SAlexandre Belloni 36484882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN); 36584882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN 36684882b06SAlexandre Belloni | AT91_ADC_EOC(3)); 36784882b06SAlexandre Belloni /* Set up period trigger for sampling */ 36884882b06SAlexandre Belloni at91_adc_writel(st, st->registers->trigger_register, 36984882b06SAlexandre Belloni AT91_ADC_TRGR_MOD_PERIOD_TRIG | 37084882b06SAlexandre Belloni AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val)); 37184882b06SAlexandre Belloni } else if (status & AT91RL_ADC_IER_NOPEN) { 37284882b06SAlexandre Belloni reg = at91_adc_readl(st, AT91_ADC_MR); 37384882b06SAlexandre Belloni reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC; 37484882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_MR, reg); 37584882b06SAlexandre Belloni at91_adc_writel(st, st->registers->trigger_register, 37684882b06SAlexandre Belloni AT91_ADC_TRGR_NONE); 37784882b06SAlexandre Belloni 37884882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN 37984882b06SAlexandre Belloni | AT91_ADC_EOC(3)); 38084882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN); 38184882b06SAlexandre Belloni st->ts_bufferedmeasure = false; 38284882b06SAlexandre Belloni input_report_key(st->ts_input, BTN_TOUCH, 0); 38384882b06SAlexandre Belloni input_sync(st->ts_input); 38484882b06SAlexandre Belloni } else if (status & AT91_ADC_EOC(3)) { 38584882b06SAlexandre Belloni /* Conversion finished */ 38684882b06SAlexandre Belloni if (st->ts_bufferedmeasure) { 38784882b06SAlexandre Belloni /* 38884882b06SAlexandre Belloni * Last measurement is always discarded, since it can 38984882b06SAlexandre Belloni * be erroneous. 39084882b06SAlexandre Belloni * Always report previous measurement 39184882b06SAlexandre Belloni */ 39284882b06SAlexandre Belloni input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx); 39384882b06SAlexandre Belloni input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy); 39484882b06SAlexandre Belloni input_report_key(st->ts_input, BTN_TOUCH, 1); 39584882b06SAlexandre Belloni input_sync(st->ts_input); 39684882b06SAlexandre Belloni } else 39784882b06SAlexandre Belloni st->ts_bufferedmeasure = true; 39884882b06SAlexandre Belloni 39984882b06SAlexandre Belloni /* Now make new measurement */ 40084882b06SAlexandre Belloni st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3)) 40184882b06SAlexandre Belloni << MAX_RLPOS_BITS; 40284882b06SAlexandre Belloni st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2)); 40384882b06SAlexandre Belloni 40484882b06SAlexandre Belloni st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1)) 40584882b06SAlexandre Belloni << MAX_RLPOS_BITS; 40684882b06SAlexandre Belloni st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0)); 40784882b06SAlexandre Belloni } 40884882b06SAlexandre Belloni 40984882b06SAlexandre Belloni return IRQ_HANDLED; 41084882b06SAlexandre Belloni } 41184882b06SAlexandre Belloni 41284882b06SAlexandre Belloni static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private) 413c8b11de0SJosh Wu { 414c8b11de0SJosh Wu struct iio_dev *idev = private; 415c8b11de0SJosh Wu struct at91_adc_state *st = iio_priv(idev); 416c8b11de0SJosh Wu u32 status = at91_adc_readl(st, st->registers->status_register); 417c8b11de0SJosh Wu const uint32_t ts_data_irq_mask = 418c8b11de0SJosh Wu AT91_ADC_IER_XRDY | 419c8b11de0SJosh Wu AT91_ADC_IER_YRDY | 420c8b11de0SJosh Wu AT91_ADC_IER_PRDY; 421c8b11de0SJosh Wu 422d4f51956SLudovic Desroches if (status & GENMASK(st->num_channels - 1, 0)) 423c8b11de0SJosh Wu handle_adc_eoc_trigger(irq, idev); 424c8b11de0SJosh Wu 425c8b11de0SJosh Wu if (status & AT91_ADC_IER_PEN) { 426c8b11de0SJosh Wu at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN); 427c8b11de0SJosh Wu at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN | 428c8b11de0SJosh Wu ts_data_irq_mask); 429c8b11de0SJosh Wu /* Set up period trigger for sampling */ 430c8b11de0SJosh Wu at91_adc_writel(st, st->registers->trigger_register, 431c8b11de0SJosh Wu AT91_ADC_TRGR_MOD_PERIOD_TRIG | 432c8b11de0SJosh Wu AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val)); 433c8b11de0SJosh Wu } else if (status & AT91_ADC_IER_NOPEN) { 434c8b11de0SJosh Wu at91_adc_writel(st, st->registers->trigger_register, 0); 435c8b11de0SJosh Wu at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN | 436c8b11de0SJosh Wu ts_data_irq_mask); 437c8b11de0SJosh Wu at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN); 438c8b11de0SJosh Wu 439c8b11de0SJosh Wu input_report_key(st->ts_input, BTN_TOUCH, 0); 440c8b11de0SJosh Wu input_sync(st->ts_input); 441c8b11de0SJosh Wu } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) { 442c8b11de0SJosh Wu /* Now all touchscreen data is ready */ 443c8b11de0SJosh Wu 444c8b11de0SJosh Wu if (status & AT91_ADC_ISR_PENS) { 445c8b11de0SJosh Wu /* validate data by pen contact */ 446c8b11de0SJosh Wu at91_ts_sample(st); 447c8b11de0SJosh Wu } else { 448c8b11de0SJosh Wu /* triggered by event that is no pen contact, just read 449c8b11de0SJosh Wu * them to clean the interrupt and discard all. 450c8b11de0SJosh Wu */ 451c8b11de0SJosh Wu at91_adc_readl(st, AT91_ADC_TSXPOSR); 452c8b11de0SJosh Wu at91_adc_readl(st, AT91_ADC_TSYPOSR); 453c8b11de0SJosh Wu at91_adc_readl(st, AT91_ADC_TSPRESSR); 454c8b11de0SJosh Wu } 455c8b11de0SJosh Wu } 4560e589d5fSMaxime Ripard 4570e589d5fSMaxime Ripard return IRQ_HANDLED; 4580e589d5fSMaxime Ripard } 4590e589d5fSMaxime Ripard 4600e589d5fSMaxime Ripard static int at91_adc_channel_init(struct iio_dev *idev) 4610e589d5fSMaxime Ripard { 4620e589d5fSMaxime Ripard struct at91_adc_state *st = iio_priv(idev); 4630e589d5fSMaxime Ripard struct iio_chan_spec *chan_array, *timestamp; 4640e589d5fSMaxime Ripard int bit, idx = 0; 465c8b11de0SJosh Wu unsigned long rsvd_mask = 0; 466c8b11de0SJosh Wu 467c8b11de0SJosh Wu /* If touchscreen is enable, then reserve the adc channels */ 468c8b11de0SJosh Wu if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE) 469c8b11de0SJosh Wu rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE; 470c8b11de0SJosh Wu else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE) 471c8b11de0SJosh Wu rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE; 472c8b11de0SJosh Wu 473c8b11de0SJosh Wu /* set up the channel mask to reserve touchscreen channels */ 474c8b11de0SJosh Wu st->channels_mask &= ~rsvd_mask; 4750e589d5fSMaxime Ripard 4760e589d5fSMaxime Ripard idev->num_channels = bitmap_weight(&st->channels_mask, 4770e589d5fSMaxime Ripard st->num_channels) + 1; 4780e589d5fSMaxime Ripard 4796b3aa313SAxel Lin chan_array = devm_kzalloc(&idev->dev, 4806b3aa313SAxel Lin ((idev->num_channels + 1) * 4816b3aa313SAxel Lin sizeof(struct iio_chan_spec)), 4826b3aa313SAxel Lin GFP_KERNEL); 4830e589d5fSMaxime Ripard 4840e589d5fSMaxime Ripard if (!chan_array) 4850e589d5fSMaxime Ripard return -ENOMEM; 4860e589d5fSMaxime Ripard 4870e589d5fSMaxime Ripard for_each_set_bit(bit, &st->channels_mask, st->num_channels) { 4880e589d5fSMaxime Ripard struct iio_chan_spec *chan = chan_array + idx; 4890e589d5fSMaxime Ripard 4900e589d5fSMaxime Ripard chan->type = IIO_VOLTAGE; 4910e589d5fSMaxime Ripard chan->indexed = 1; 4920e589d5fSMaxime Ripard chan->channel = bit; 4930e589d5fSMaxime Ripard chan->scan_index = idx; 4940e589d5fSMaxime Ripard chan->scan_type.sign = 'u'; 49547be16b6SLudovic Desroches chan->scan_type.realbits = st->res; 4960e589d5fSMaxime Ripard chan->scan_type.storagebits = 16; 49701bdab66SJonathan Cameron chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE); 49801bdab66SJonathan Cameron chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); 4990e589d5fSMaxime Ripard idx++; 5000e589d5fSMaxime Ripard } 5010e589d5fSMaxime Ripard timestamp = chan_array + idx; 5020e589d5fSMaxime Ripard 5030e589d5fSMaxime Ripard timestamp->type = IIO_TIMESTAMP; 5040e589d5fSMaxime Ripard timestamp->channel = -1; 5050e589d5fSMaxime Ripard timestamp->scan_index = idx; 5060e589d5fSMaxime Ripard timestamp->scan_type.sign = 's'; 5070e589d5fSMaxime Ripard timestamp->scan_type.realbits = 64; 5080e589d5fSMaxime Ripard timestamp->scan_type.storagebits = 64; 5090e589d5fSMaxime Ripard 5100e589d5fSMaxime Ripard idev->channels = chan_array; 5110e589d5fSMaxime Ripard return idev->num_channels; 5120e589d5fSMaxime Ripard } 5130e589d5fSMaxime Ripard 5144f3bcd87SDan Carpenter static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev, 5150e589d5fSMaxime Ripard struct at91_adc_trigger *triggers, 5160e589d5fSMaxime Ripard const char *trigger_name) 5170e589d5fSMaxime Ripard { 5180e589d5fSMaxime Ripard struct at91_adc_state *st = iio_priv(idev); 5190e589d5fSMaxime Ripard int i; 5200e589d5fSMaxime Ripard 5210e589d5fSMaxime Ripard for (i = 0; i < st->trigger_number; i++) { 5220e589d5fSMaxime Ripard char *name = kasprintf(GFP_KERNEL, 5230e589d5fSMaxime Ripard "%s-dev%d-%s", 5240e589d5fSMaxime Ripard idev->name, 5250e589d5fSMaxime Ripard idev->id, 5260e589d5fSMaxime Ripard triggers[i].name); 5270e589d5fSMaxime Ripard if (!name) 5280e589d5fSMaxime Ripard return -ENOMEM; 5290e589d5fSMaxime Ripard 5300e589d5fSMaxime Ripard if (strcmp(trigger_name, name) == 0) { 5310e589d5fSMaxime Ripard kfree(name); 5324f3bcd87SDan Carpenter if (triggers[i].value == 0) 5334f3bcd87SDan Carpenter return -EINVAL; 5344f3bcd87SDan Carpenter return triggers[i].value; 5350e589d5fSMaxime Ripard } 5360e589d5fSMaxime Ripard 5370e589d5fSMaxime Ripard kfree(name); 5380e589d5fSMaxime Ripard } 5390e589d5fSMaxime Ripard 5404f3bcd87SDan Carpenter return -EINVAL; 5410e589d5fSMaxime Ripard } 5420e589d5fSMaxime Ripard 5430e589d5fSMaxime Ripard static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) 5440e589d5fSMaxime Ripard { 5451e9663c6SLars-Peter Clausen struct iio_dev *idev = iio_trigger_get_drvdata(trig); 5460e589d5fSMaxime Ripard struct at91_adc_state *st = iio_priv(idev); 5470e589d5fSMaxime Ripard struct at91_adc_reg_desc *reg = st->registers; 5480e589d5fSMaxime Ripard u32 status = at91_adc_readl(st, reg->trigger_register); 5494f3bcd87SDan Carpenter int value; 5500e589d5fSMaxime Ripard u8 bit; 5510e589d5fSMaxime Ripard 5520e589d5fSMaxime Ripard value = at91_adc_get_trigger_value_by_name(idev, 5530e589d5fSMaxime Ripard st->trigger_list, 5540e589d5fSMaxime Ripard idev->trig->name); 5554f3bcd87SDan Carpenter if (value < 0) 5564f3bcd87SDan Carpenter return value; 5570e589d5fSMaxime Ripard 5580e589d5fSMaxime Ripard if (state) { 5590e589d5fSMaxime Ripard st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL); 5600e589d5fSMaxime Ripard if (st->buffer == NULL) 5610e589d5fSMaxime Ripard return -ENOMEM; 5620e589d5fSMaxime Ripard 5630e589d5fSMaxime Ripard at91_adc_writel(st, reg->trigger_register, 5640e589d5fSMaxime Ripard status | value); 5650e589d5fSMaxime Ripard 56670dddeeeSOctavian Purdila for_each_set_bit(bit, idev->active_scan_mask, 5670e589d5fSMaxime Ripard st->num_channels) { 5680e589d5fSMaxime Ripard struct iio_chan_spec const *chan = idev->channels + bit; 5690e589d5fSMaxime Ripard at91_adc_writel(st, AT91_ADC_CHER, 5700e589d5fSMaxime Ripard AT91_ADC_CH(chan->channel)); 5710e589d5fSMaxime Ripard } 5720e589d5fSMaxime Ripard 5730e589d5fSMaxime Ripard at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask); 5740e589d5fSMaxime Ripard 5750e589d5fSMaxime Ripard } else { 5760e589d5fSMaxime Ripard at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask); 5770e589d5fSMaxime Ripard 5780e589d5fSMaxime Ripard at91_adc_writel(st, reg->trigger_register, 5790e589d5fSMaxime Ripard status & ~value); 5800e589d5fSMaxime Ripard 58170dddeeeSOctavian Purdila for_each_set_bit(bit, idev->active_scan_mask, 5820e589d5fSMaxime Ripard st->num_channels) { 5830e589d5fSMaxime Ripard struct iio_chan_spec const *chan = idev->channels + bit; 5840e589d5fSMaxime Ripard at91_adc_writel(st, AT91_ADC_CHDR, 5850e589d5fSMaxime Ripard AT91_ADC_CH(chan->channel)); 5860e589d5fSMaxime Ripard } 5870e589d5fSMaxime Ripard kfree(st->buffer); 5880e589d5fSMaxime Ripard } 5890e589d5fSMaxime Ripard 5900e589d5fSMaxime Ripard return 0; 5910e589d5fSMaxime Ripard } 5920e589d5fSMaxime Ripard 5930e589d5fSMaxime Ripard static const struct iio_trigger_ops at91_adc_trigger_ops = { 5940e589d5fSMaxime Ripard .owner = THIS_MODULE, 5950e589d5fSMaxime Ripard .set_trigger_state = &at91_adc_configure_trigger, 5960e589d5fSMaxime Ripard }; 5970e589d5fSMaxime Ripard 5980e589d5fSMaxime Ripard static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev, 5990e589d5fSMaxime Ripard struct at91_adc_trigger *trigger) 6000e589d5fSMaxime Ripard { 6010e589d5fSMaxime Ripard struct iio_trigger *trig; 6020e589d5fSMaxime Ripard int ret; 6030e589d5fSMaxime Ripard 6040e589d5fSMaxime Ripard trig = iio_trigger_alloc("%s-dev%d-%s", idev->name, 6050e589d5fSMaxime Ripard idev->id, trigger->name); 6060e589d5fSMaxime Ripard if (trig == NULL) 6070e589d5fSMaxime Ripard return NULL; 6080e589d5fSMaxime Ripard 6090e589d5fSMaxime Ripard trig->dev.parent = idev->dev.parent; 6101e9663c6SLars-Peter Clausen iio_trigger_set_drvdata(trig, idev); 6110e589d5fSMaxime Ripard trig->ops = &at91_adc_trigger_ops; 6120e589d5fSMaxime Ripard 6130e589d5fSMaxime Ripard ret = iio_trigger_register(trig); 6140e589d5fSMaxime Ripard if (ret) 6150e589d5fSMaxime Ripard return NULL; 6160e589d5fSMaxime Ripard 6170e589d5fSMaxime Ripard return trig; 6180e589d5fSMaxime Ripard } 6190e589d5fSMaxime Ripard 6200e589d5fSMaxime Ripard static int at91_adc_trigger_init(struct iio_dev *idev) 6210e589d5fSMaxime Ripard { 6220e589d5fSMaxime Ripard struct at91_adc_state *st = iio_priv(idev); 6230e589d5fSMaxime Ripard int i, ret; 6240e589d5fSMaxime Ripard 6256b3aa313SAxel Lin st->trig = devm_kzalloc(&idev->dev, 62642877236SThomas Meyer st->trigger_number * sizeof(*st->trig), 6276b3aa313SAxel Lin GFP_KERNEL); 6280e589d5fSMaxime Ripard 6290e589d5fSMaxime Ripard if (st->trig == NULL) { 6300e589d5fSMaxime Ripard ret = -ENOMEM; 6310e589d5fSMaxime Ripard goto error_ret; 6320e589d5fSMaxime Ripard } 6330e589d5fSMaxime Ripard 6340e589d5fSMaxime Ripard for (i = 0; i < st->trigger_number; i++) { 6350e589d5fSMaxime Ripard if (st->trigger_list[i].is_external && !(st->use_external)) 6360e589d5fSMaxime Ripard continue; 6370e589d5fSMaxime Ripard 6380e589d5fSMaxime Ripard st->trig[i] = at91_adc_allocate_trigger(idev, 6390e589d5fSMaxime Ripard st->trigger_list + i); 6400e589d5fSMaxime Ripard if (st->trig[i] == NULL) { 6410e589d5fSMaxime Ripard dev_err(&idev->dev, 6420e589d5fSMaxime Ripard "Could not allocate trigger %d\n", i); 6430e589d5fSMaxime Ripard ret = -ENOMEM; 6440e589d5fSMaxime Ripard goto error_trigger; 6450e589d5fSMaxime Ripard } 6460e589d5fSMaxime Ripard } 6470e589d5fSMaxime Ripard 6480e589d5fSMaxime Ripard return 0; 6490e589d5fSMaxime Ripard 6500e589d5fSMaxime Ripard error_trigger: 6510e589d5fSMaxime Ripard for (i--; i >= 0; i--) { 6520e589d5fSMaxime Ripard iio_trigger_unregister(st->trig[i]); 6530e589d5fSMaxime Ripard iio_trigger_free(st->trig[i]); 6540e589d5fSMaxime Ripard } 6550e589d5fSMaxime Ripard error_ret: 6560e589d5fSMaxime Ripard return ret; 6570e589d5fSMaxime Ripard } 6580e589d5fSMaxime Ripard 6590e589d5fSMaxime Ripard static void at91_adc_trigger_remove(struct iio_dev *idev) 6600e589d5fSMaxime Ripard { 6610e589d5fSMaxime Ripard struct at91_adc_state *st = iio_priv(idev); 6620e589d5fSMaxime Ripard int i; 6630e589d5fSMaxime Ripard 6640e589d5fSMaxime Ripard for (i = 0; i < st->trigger_number; i++) { 6650e589d5fSMaxime Ripard iio_trigger_unregister(st->trig[i]); 6660e589d5fSMaxime Ripard iio_trigger_free(st->trig[i]); 6670e589d5fSMaxime Ripard } 6680e589d5fSMaxime Ripard } 6690e589d5fSMaxime Ripard 6700e589d5fSMaxime Ripard static int at91_adc_buffer_init(struct iio_dev *idev) 6710e589d5fSMaxime Ripard { 67290032e4eSLars-Peter Clausen return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time, 67390032e4eSLars-Peter Clausen &at91_adc_trigger_handler, NULL); 6740e589d5fSMaxime Ripard } 6750e589d5fSMaxime Ripard 6760e589d5fSMaxime Ripard static void at91_adc_buffer_remove(struct iio_dev *idev) 6770e589d5fSMaxime Ripard { 67890032e4eSLars-Peter Clausen iio_triggered_buffer_cleanup(idev); 6790e589d5fSMaxime Ripard } 6800e589d5fSMaxime Ripard 6810e589d5fSMaxime Ripard static int at91_adc_read_raw(struct iio_dev *idev, 6820e589d5fSMaxime Ripard struct iio_chan_spec const *chan, 6830e589d5fSMaxime Ripard int *val, int *val2, long mask) 6840e589d5fSMaxime Ripard { 6850e589d5fSMaxime Ripard struct at91_adc_state *st = iio_priv(idev); 6860e589d5fSMaxime Ripard int ret; 6870e589d5fSMaxime Ripard 6880e589d5fSMaxime Ripard switch (mask) { 6890e589d5fSMaxime Ripard case IIO_CHAN_INFO_RAW: 6900e589d5fSMaxime Ripard mutex_lock(&st->lock); 6910e589d5fSMaxime Ripard 692d4f51956SLudovic Desroches st->chnb = chan->channel; 6930e589d5fSMaxime Ripard at91_adc_writel(st, AT91_ADC_CHER, 6940e589d5fSMaxime Ripard AT91_ADC_CH(chan->channel)); 695d4f51956SLudovic Desroches at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel)); 6960e589d5fSMaxime Ripard at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START); 6970e589d5fSMaxime Ripard 6980e589d5fSMaxime Ripard ret = wait_event_interruptible_timeout(st->wq_data_avail, 6990e589d5fSMaxime Ripard st->done, 7000e589d5fSMaxime Ripard msecs_to_jiffies(1000)); 7010e589d5fSMaxime Ripard if (ret == 0) 70290e6dc7cSLars-Peter Clausen ret = -ETIMEDOUT; 70390e6dc7cSLars-Peter Clausen if (ret < 0) { 70490e6dc7cSLars-Peter Clausen mutex_unlock(&st->lock); 7050e589d5fSMaxime Ripard return ret; 70690e6dc7cSLars-Peter Clausen } 7070e589d5fSMaxime Ripard 7080e589d5fSMaxime Ripard *val = st->last_value; 7090e589d5fSMaxime Ripard 7100e589d5fSMaxime Ripard at91_adc_writel(st, AT91_ADC_CHDR, 7110e589d5fSMaxime Ripard AT91_ADC_CH(chan->channel)); 712d4f51956SLudovic Desroches at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel)); 7130e589d5fSMaxime Ripard 7140e589d5fSMaxime Ripard st->last_value = 0; 7150e589d5fSMaxime Ripard st->done = false; 7160e589d5fSMaxime Ripard mutex_unlock(&st->lock); 7170e589d5fSMaxime Ripard return IIO_VAL_INT; 7180e589d5fSMaxime Ripard 7190e589d5fSMaxime Ripard case IIO_CHAN_INFO_SCALE: 720c45e561eSLars-Peter Clausen *val = st->vref_mv; 721c45e561eSLars-Peter Clausen *val2 = chan->scan_type.realbits; 722c45e561eSLars-Peter Clausen return IIO_VAL_FRACTIONAL_LOG2; 7230e589d5fSMaxime Ripard default: 7240e589d5fSMaxime Ripard break; 7250e589d5fSMaxime Ripard } 7260e589d5fSMaxime Ripard return -EINVAL; 7270e589d5fSMaxime Ripard } 7280e589d5fSMaxime Ripard 72947be16b6SLudovic Desroches static int at91_adc_of_get_resolution(struct at91_adc_state *st, 73047be16b6SLudovic Desroches struct platform_device *pdev) 73147be16b6SLudovic Desroches { 73247be16b6SLudovic Desroches struct iio_dev *idev = iio_priv_to_dev(st); 73347be16b6SLudovic Desroches struct device_node *np = pdev->dev.of_node; 73447be16b6SLudovic Desroches int count, i, ret = 0; 73547be16b6SLudovic Desroches char *res_name, *s; 73647be16b6SLudovic Desroches u32 *resolutions; 73747be16b6SLudovic Desroches 73847be16b6SLudovic Desroches count = of_property_count_strings(np, "atmel,adc-res-names"); 73947be16b6SLudovic Desroches if (count < 2) { 74047be16b6SLudovic Desroches dev_err(&idev->dev, "You must specified at least two resolution names for " 74147be16b6SLudovic Desroches "adc-res-names property in the DT\n"); 74247be16b6SLudovic Desroches return count; 74347be16b6SLudovic Desroches } 74447be16b6SLudovic Desroches 7453fba9b5fSNizam Haider resolutions = kmalloc_array(count, sizeof(*resolutions), GFP_KERNEL); 74647be16b6SLudovic Desroches if (!resolutions) 74747be16b6SLudovic Desroches return -ENOMEM; 74847be16b6SLudovic Desroches 74947be16b6SLudovic Desroches if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) { 75047be16b6SLudovic Desroches dev_err(&idev->dev, "Missing adc-res property in the DT.\n"); 75147be16b6SLudovic Desroches ret = -ENODEV; 75247be16b6SLudovic Desroches goto ret; 75347be16b6SLudovic Desroches } 75447be16b6SLudovic Desroches 75547be16b6SLudovic Desroches if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name)) 75647be16b6SLudovic Desroches res_name = "highres"; 75747be16b6SLudovic Desroches 75847be16b6SLudovic Desroches for (i = 0; i < count; i++) { 75947be16b6SLudovic Desroches if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s)) 76047be16b6SLudovic Desroches continue; 76147be16b6SLudovic Desroches 76247be16b6SLudovic Desroches if (strcmp(res_name, s)) 76347be16b6SLudovic Desroches continue; 76447be16b6SLudovic Desroches 76547be16b6SLudovic Desroches st->res = resolutions[i]; 76647be16b6SLudovic Desroches if (!strcmp(res_name, "lowres")) 76747be16b6SLudovic Desroches st->low_res = true; 76847be16b6SLudovic Desroches else 76947be16b6SLudovic Desroches st->low_res = false; 77047be16b6SLudovic Desroches 77147be16b6SLudovic Desroches dev_info(&idev->dev, "Resolution used: %u bits\n", st->res); 77247be16b6SLudovic Desroches goto ret; 77347be16b6SLudovic Desroches } 77447be16b6SLudovic Desroches 77547be16b6SLudovic Desroches dev_err(&idev->dev, "There is no resolution for %s\n", res_name); 77647be16b6SLudovic Desroches 77747be16b6SLudovic Desroches ret: 77847be16b6SLudovic Desroches kfree(resolutions); 77947be16b6SLudovic Desroches return ret; 78047be16b6SLudovic Desroches } 78147be16b6SLudovic Desroches 7822ab5f39bSJan Leupold static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz) 783c4601666SJosh Wu { 784c4601666SJosh Wu /* 785c4601666SJosh Wu * Number of ticks needed to cover the startup time of the ADC 786c4601666SJosh Wu * as defined in the electrical characteristics of the board, 787c4601666SJosh Wu * divided by 8. The formula thus is : 788c4601666SJosh Wu * Startup Time = (ticks + 1) * 8 / ADC Clock 789c4601666SJosh Wu */ 790c4601666SJosh Wu return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8; 791c4601666SJosh Wu } 792c4601666SJosh Wu 7932ab5f39bSJan Leupold static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz) 794c4601666SJosh Wu { 795c4601666SJosh Wu /* 796c4601666SJosh Wu * For sama5d3x and at91sam9x5, the formula changes to: 797c4601666SJosh Wu * Startup Time = <lookup_table_value> / ADC Clock 798c4601666SJosh Wu */ 799c4601666SJosh Wu const int startup_lookup[] = { 800c4601666SJosh Wu 0 , 8 , 16 , 24 , 801c4601666SJosh Wu 64 , 80 , 96 , 112, 802c4601666SJosh Wu 512, 576, 640, 704, 803c4601666SJosh Wu 768, 832, 896, 960 804c4601666SJosh Wu }; 805c4601666SJosh Wu int i, size = ARRAY_SIZE(startup_lookup); 806c4601666SJosh Wu unsigned int ticks; 807c4601666SJosh Wu 808c4601666SJosh Wu ticks = startup_time * adc_clk_khz / 1000; 809c4601666SJosh Wu for (i = 0; i < size; i++) 810c4601666SJosh Wu if (ticks < startup_lookup[i]) 811c4601666SJosh Wu break; 812c4601666SJosh Wu 813c4601666SJosh Wu ticks = i; 814c4601666SJosh Wu if (ticks == size) 815c4601666SJosh Wu /* Reach the end of lookup table */ 816c4601666SJosh Wu ticks = size - 1; 817c4601666SJosh Wu 818c4601666SJosh Wu return ticks; 819c4601666SJosh Wu } 820c4601666SJosh Wu 821e1811f97SJosh Wu static const struct of_device_id at91_adc_dt_ids[]; 822e1811f97SJosh Wu 823c8b11de0SJosh Wu static int at91_adc_probe_dt_ts(struct device_node *node, 824c8b11de0SJosh Wu struct at91_adc_state *st, struct device *dev) 825c8b11de0SJosh Wu { 826c8b11de0SJosh Wu int ret; 827c8b11de0SJosh Wu u32 prop; 828c8b11de0SJosh Wu 829c8b11de0SJosh Wu ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop); 830c8b11de0SJosh Wu if (ret) { 831c8b11de0SJosh Wu dev_info(dev, "ADC Touch screen is disabled.\n"); 832c8b11de0SJosh Wu return 0; 833c8b11de0SJosh Wu } 834c8b11de0SJosh Wu 835c8b11de0SJosh Wu switch (prop) { 836c8b11de0SJosh Wu case 4: 837c8b11de0SJosh Wu case 5: 838c8b11de0SJosh Wu st->touchscreen_type = prop; 839c8b11de0SJosh Wu break; 840c8b11de0SJosh Wu default: 841c8b11de0SJosh Wu dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop); 842c8b11de0SJosh Wu return -EINVAL; 843c8b11de0SJosh Wu } 844c8b11de0SJosh Wu 84584882b06SAlexandre Belloni if (!st->caps->has_tsmr) 84684882b06SAlexandre Belloni return 0; 847c8b11de0SJosh Wu prop = 0; 848c8b11de0SJosh Wu of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop); 849c8b11de0SJosh Wu st->ts_pressure_threshold = prop; 850c8b11de0SJosh Wu if (st->ts_pressure_threshold) { 851c8b11de0SJosh Wu return 0; 852c8b11de0SJosh Wu } else { 853c8b11de0SJosh Wu dev_err(dev, "Invalid pressure threshold for the touchscreen\n"); 854c8b11de0SJosh Wu return -EINVAL; 855c8b11de0SJosh Wu } 856c8b11de0SJosh Wu } 857c8b11de0SJosh Wu 858e364185fSMaxime Ripard static int at91_adc_probe_dt(struct at91_adc_state *st, 859e364185fSMaxime Ripard struct platform_device *pdev) 860e364185fSMaxime Ripard { 861e364185fSMaxime Ripard struct iio_dev *idev = iio_priv_to_dev(st); 862e364185fSMaxime Ripard struct device_node *node = pdev->dev.of_node; 863e364185fSMaxime Ripard struct device_node *trig_node; 864e364185fSMaxime Ripard int i = 0, ret; 865e364185fSMaxime Ripard u32 prop; 866e364185fSMaxime Ripard 867e364185fSMaxime Ripard if (!node) 868e364185fSMaxime Ripard return -EINVAL; 869e364185fSMaxime Ripard 870e1811f97SJosh Wu st->caps = (struct at91_adc_caps *) 871e1811f97SJosh Wu of_match_device(at91_adc_dt_ids, &pdev->dev)->data; 872e1811f97SJosh Wu 873e364185fSMaxime Ripard st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers"); 874e364185fSMaxime Ripard 875e364185fSMaxime Ripard if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) { 876e364185fSMaxime Ripard dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n"); 877e364185fSMaxime Ripard ret = -EINVAL; 878e364185fSMaxime Ripard goto error_ret; 879e364185fSMaxime Ripard } 880e364185fSMaxime Ripard st->channels_mask = prop; 881e364185fSMaxime Ripard 882e748783cSJean-Christophe PLAGNIOL-VILLARD st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode"); 883e748783cSJean-Christophe PLAGNIOL-VILLARD 884e364185fSMaxime Ripard if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) { 885e364185fSMaxime Ripard dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n"); 886e364185fSMaxime Ripard ret = -EINVAL; 887e364185fSMaxime Ripard goto error_ret; 888e364185fSMaxime Ripard } 889e364185fSMaxime Ripard st->startup_time = prop; 890e364185fSMaxime Ripard 891beca9e76SJean-Christophe PLAGNIOL-VILLARD prop = 0; 892beca9e76SJean-Christophe PLAGNIOL-VILLARD of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop); 893beca9e76SJean-Christophe PLAGNIOL-VILLARD st->sample_hold_time = prop; 894e364185fSMaxime Ripard 895e364185fSMaxime Ripard if (of_property_read_u32(node, "atmel,adc-vref", &prop)) { 896e364185fSMaxime Ripard dev_err(&idev->dev, "Missing adc-vref property in the DT.\n"); 897e364185fSMaxime Ripard ret = -EINVAL; 898e364185fSMaxime Ripard goto error_ret; 899e364185fSMaxime Ripard } 900e364185fSMaxime Ripard st->vref_mv = prop; 901e364185fSMaxime Ripard 90247be16b6SLudovic Desroches ret = at91_adc_of_get_resolution(st, pdev); 90347be16b6SLudovic Desroches if (ret) 90447be16b6SLudovic Desroches goto error_ret; 90547be16b6SLudovic Desroches 906e1811f97SJosh Wu st->registers = &st->caps->registers; 9072b6d598bSJosh Wu st->num_channels = st->caps->num_channels; 908e364185fSMaxime Ripard st->trigger_number = of_get_child_count(node); 9096b3aa313SAxel Lin st->trigger_list = devm_kzalloc(&idev->dev, st->trigger_number * 9106b3aa313SAxel Lin sizeof(struct at91_adc_trigger), 9116b3aa313SAxel Lin GFP_KERNEL); 912e364185fSMaxime Ripard if (!st->trigger_list) { 913e364185fSMaxime Ripard dev_err(&idev->dev, "Could not allocate trigger list memory.\n"); 914e364185fSMaxime Ripard ret = -ENOMEM; 915e364185fSMaxime Ripard goto error_ret; 916e364185fSMaxime Ripard } 917e364185fSMaxime Ripard 918e364185fSMaxime Ripard for_each_child_of_node(node, trig_node) { 919e364185fSMaxime Ripard struct at91_adc_trigger *trig = st->trigger_list + i; 920e364185fSMaxime Ripard const char *name; 921e364185fSMaxime Ripard 922e364185fSMaxime Ripard if (of_property_read_string(trig_node, "trigger-name", &name)) { 923e364185fSMaxime Ripard dev_err(&idev->dev, "Missing trigger-name property in the DT.\n"); 924e364185fSMaxime Ripard ret = -EINVAL; 925e364185fSMaxime Ripard goto error_ret; 926e364185fSMaxime Ripard } 927e364185fSMaxime Ripard trig->name = name; 928e364185fSMaxime Ripard 929e364185fSMaxime Ripard if (of_property_read_u32(trig_node, "trigger-value", &prop)) { 930e364185fSMaxime Ripard dev_err(&idev->dev, "Missing trigger-value property in the DT.\n"); 931e364185fSMaxime Ripard ret = -EINVAL; 932e364185fSMaxime Ripard goto error_ret; 933e364185fSMaxime Ripard } 934e364185fSMaxime Ripard trig->value = prop; 935e364185fSMaxime Ripard trig->is_external = of_property_read_bool(trig_node, "trigger-external"); 936e364185fSMaxime Ripard i++; 937e364185fSMaxime Ripard } 938e364185fSMaxime Ripard 939c8b11de0SJosh Wu /* Check if touchscreen is supported. */ 940c8b11de0SJosh Wu if (st->caps->has_ts) 941c8b11de0SJosh Wu return at91_adc_probe_dt_ts(node, st, &idev->dev); 942c8b11de0SJosh Wu else 943c8b11de0SJosh Wu dev_info(&idev->dev, "not support touchscreen in the adc compatible string.\n"); 944c8b11de0SJosh Wu 945e364185fSMaxime Ripard return 0; 946e364185fSMaxime Ripard 947e364185fSMaxime Ripard error_ret: 948e364185fSMaxime Ripard return ret; 949e364185fSMaxime Ripard } 950e364185fSMaxime Ripard 9510e589d5fSMaxime Ripard static int at91_adc_probe_pdata(struct at91_adc_state *st, 9520e589d5fSMaxime Ripard struct platform_device *pdev) 9530e589d5fSMaxime Ripard { 9540e589d5fSMaxime Ripard struct at91_adc_data *pdata = pdev->dev.platform_data; 9550e589d5fSMaxime Ripard 9560e589d5fSMaxime Ripard if (!pdata) 9570e589d5fSMaxime Ripard return -EINVAL; 9580e589d5fSMaxime Ripard 959467a44b0SAlexandre Belloni st->caps = (struct at91_adc_caps *) 960467a44b0SAlexandre Belloni platform_get_device_id(pdev)->driver_data; 961467a44b0SAlexandre Belloni 9620e589d5fSMaxime Ripard st->use_external = pdata->use_external_triggers; 9630e589d5fSMaxime Ripard st->vref_mv = pdata->vref; 9640e589d5fSMaxime Ripard st->channels_mask = pdata->channels_used; 965467a44b0SAlexandre Belloni st->num_channels = st->caps->num_channels; 9660e589d5fSMaxime Ripard st->startup_time = pdata->startup_time; 9670e589d5fSMaxime Ripard st->trigger_number = pdata->trigger_number; 9680e589d5fSMaxime Ripard st->trigger_list = pdata->trigger_list; 969467a44b0SAlexandre Belloni st->registers = &st->caps->registers; 97084882b06SAlexandre Belloni st->touchscreen_type = pdata->touchscreen_type; 9710e589d5fSMaxime Ripard 9720e589d5fSMaxime Ripard return 0; 9730e589d5fSMaxime Ripard } 9740e589d5fSMaxime Ripard 9750e589d5fSMaxime Ripard static const struct iio_info at91_adc_info = { 9760e589d5fSMaxime Ripard .driver_module = THIS_MODULE, 9770e589d5fSMaxime Ripard .read_raw = &at91_adc_read_raw, 9780e589d5fSMaxime Ripard }; 9790e589d5fSMaxime Ripard 980c8b11de0SJosh Wu /* Touchscreen related functions */ 981c8b11de0SJosh Wu static int atmel_ts_open(struct input_dev *dev) 982c8b11de0SJosh Wu { 983c8b11de0SJosh Wu struct at91_adc_state *st = input_get_drvdata(dev); 984c8b11de0SJosh Wu 98584882b06SAlexandre Belloni if (st->caps->has_tsmr) 986c8b11de0SJosh Wu at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN); 98784882b06SAlexandre Belloni else 98884882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN); 989c8b11de0SJosh Wu return 0; 990c8b11de0SJosh Wu } 991c8b11de0SJosh Wu 992c8b11de0SJosh Wu static void atmel_ts_close(struct input_dev *dev) 993c8b11de0SJosh Wu { 994c8b11de0SJosh Wu struct at91_adc_state *st = input_get_drvdata(dev); 995c8b11de0SJosh Wu 99684882b06SAlexandre Belloni if (st->caps->has_tsmr) 997c8b11de0SJosh Wu at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN); 99884882b06SAlexandre Belloni else 99984882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN); 1000c8b11de0SJosh Wu } 1001c8b11de0SJosh Wu 1002c8b11de0SJosh Wu static int at91_ts_hw_init(struct at91_adc_state *st, u32 adc_clk_khz) 1003c8b11de0SJosh Wu { 100484882b06SAlexandre Belloni u32 reg = 0; 1005c8b11de0SJosh Wu int i = 0; 1006c8b11de0SJosh Wu 100784882b06SAlexandre Belloni /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid 100884882b06SAlexandre Belloni * pen detect noise. 100984882b06SAlexandre Belloni * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock 101084882b06SAlexandre Belloni */ 101184882b06SAlexandre Belloni st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz / 101284882b06SAlexandre Belloni 1000, 1); 101384882b06SAlexandre Belloni 101484882b06SAlexandre Belloni while (st->ts_pendbc >> ++i) 101584882b06SAlexandre Belloni ; /* Empty! Find the shift offset */ 101684882b06SAlexandre Belloni if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1)))) 101784882b06SAlexandre Belloni st->ts_pendbc = i; 101884882b06SAlexandre Belloni else 101984882b06SAlexandre Belloni st->ts_pendbc = i - 1; 102084882b06SAlexandre Belloni 102184882b06SAlexandre Belloni if (!st->caps->has_tsmr) { 102284882b06SAlexandre Belloni reg = at91_adc_readl(st, AT91_ADC_MR); 102384882b06SAlexandre Belloni reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET; 102484882b06SAlexandre Belloni 102584882b06SAlexandre Belloni reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC; 102684882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_MR, reg); 102784882b06SAlexandre Belloni 102884882b06SAlexandre Belloni reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM; 102984882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_TSR, reg); 103084882b06SAlexandre Belloni 103184882b06SAlexandre Belloni st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL * 103284882b06SAlexandre Belloni adc_clk_khz / 1000) - 1, 1); 103384882b06SAlexandre Belloni 103484882b06SAlexandre Belloni return 0; 103584882b06SAlexandre Belloni } 103684882b06SAlexandre Belloni 1037c8b11de0SJosh Wu if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE) 1038c8b11de0SJosh Wu reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS; 1039c8b11de0SJosh Wu else 1040c8b11de0SJosh Wu reg = AT91_ADC_TSMR_TSMODE_5WIRE; 1041c8b11de0SJosh Wu 1042c8b11de0SJosh Wu reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average) 1043c8b11de0SJosh Wu & AT91_ADC_TSMR_TSAV; 104484882b06SAlexandre Belloni reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC; 1045c8b11de0SJosh Wu reg |= AT91_ADC_TSMR_NOTSDMA; 1046c8b11de0SJosh Wu reg |= AT91_ADC_TSMR_PENDET_ENA; 104784882b06SAlexandre Belloni reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */ 1048c8b11de0SJosh Wu 1049c8b11de0SJosh Wu at91_adc_writel(st, AT91_ADC_TSMR, reg); 1050c8b11de0SJosh Wu 1051c8b11de0SJosh Wu /* Change adc internal resistor value for better pen detection, 1052c8b11de0SJosh Wu * default value is 100 kOhm. 1053c8b11de0SJosh Wu * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm 1054c8b11de0SJosh Wu * option only available on ES2 and higher 1055c8b11de0SJosh Wu */ 1056c8b11de0SJosh Wu at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity 1057c8b11de0SJosh Wu & AT91_ADC_ACR_PENDETSENS); 1058c8b11de0SJosh Wu 105984882b06SAlexandre Belloni /* Sample Period Time = (TRGPER + 1) / ADCClock */ 1060c8b11de0SJosh Wu st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US * 1061c8b11de0SJosh Wu adc_clk_khz / 1000) - 1, 1); 1062c8b11de0SJosh Wu 1063c8b11de0SJosh Wu return 0; 1064c8b11de0SJosh Wu } 1065c8b11de0SJosh Wu 1066c8b11de0SJosh Wu static int at91_ts_register(struct at91_adc_state *st, 1067c8b11de0SJosh Wu struct platform_device *pdev) 1068c8b11de0SJosh Wu { 1069c8b11de0SJosh Wu struct input_dev *input; 1070c8b11de0SJosh Wu struct iio_dev *idev = iio_priv_to_dev(st); 1071c8b11de0SJosh Wu int ret; 1072c8b11de0SJosh Wu 1073c8b11de0SJosh Wu input = input_allocate_device(); 1074c8b11de0SJosh Wu if (!input) { 1075c8b11de0SJosh Wu dev_err(&idev->dev, "Failed to allocate TS device!\n"); 1076c8b11de0SJosh Wu return -ENOMEM; 1077c8b11de0SJosh Wu } 1078c8b11de0SJosh Wu 1079c8b11de0SJosh Wu input->name = DRIVER_NAME; 1080c8b11de0SJosh Wu input->id.bustype = BUS_HOST; 1081c8b11de0SJosh Wu input->dev.parent = &pdev->dev; 1082c8b11de0SJosh Wu input->open = atmel_ts_open; 1083c8b11de0SJosh Wu input->close = atmel_ts_close; 1084c8b11de0SJosh Wu 1085c8b11de0SJosh Wu __set_bit(EV_ABS, input->evbit); 1086c8b11de0SJosh Wu __set_bit(EV_KEY, input->evbit); 1087c8b11de0SJosh Wu __set_bit(BTN_TOUCH, input->keybit); 108884882b06SAlexandre Belloni if (st->caps->has_tsmr) { 108984882b06SAlexandre Belloni input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1, 109084882b06SAlexandre Belloni 0, 0); 109184882b06SAlexandre Belloni input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1, 109284882b06SAlexandre Belloni 0, 0); 1093c8b11de0SJosh Wu input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0); 109484882b06SAlexandre Belloni } else { 109584882b06SAlexandre Belloni if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) { 109684882b06SAlexandre Belloni dev_err(&pdev->dev, 109784882b06SAlexandre Belloni "This touchscreen controller only support 4 wires\n"); 109884882b06SAlexandre Belloni ret = -EINVAL; 109984882b06SAlexandre Belloni goto err; 110084882b06SAlexandre Belloni } 110184882b06SAlexandre Belloni 110284882b06SAlexandre Belloni input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1, 110384882b06SAlexandre Belloni 0, 0); 110484882b06SAlexandre Belloni input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1, 110584882b06SAlexandre Belloni 0, 0); 110684882b06SAlexandre Belloni } 1107c8b11de0SJosh Wu 1108c8b11de0SJosh Wu st->ts_input = input; 1109c8b11de0SJosh Wu input_set_drvdata(input, st); 1110c8b11de0SJosh Wu 1111c8b11de0SJosh Wu ret = input_register_device(input); 1112c8b11de0SJosh Wu if (ret) 111384882b06SAlexandre Belloni goto err; 1114c8b11de0SJosh Wu 1115c8b11de0SJosh Wu return ret; 111684882b06SAlexandre Belloni 111784882b06SAlexandre Belloni err: 111884882b06SAlexandre Belloni input_free_device(st->ts_input); 111984882b06SAlexandre Belloni return ret; 1120c8b11de0SJosh Wu } 1121c8b11de0SJosh Wu 1122c8b11de0SJosh Wu static void at91_ts_unregister(struct at91_adc_state *st) 1123c8b11de0SJosh Wu { 1124c8b11de0SJosh Wu input_unregister_device(st->ts_input); 1125c8b11de0SJosh Wu } 1126c8b11de0SJosh Wu 1127fc52692cSGreg Kroah-Hartman static int at91_adc_probe(struct platform_device *pdev) 11280e589d5fSMaxime Ripard { 1129db10e201SJosh Wu unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim; 11300e589d5fSMaxime Ripard int ret; 11310e589d5fSMaxime Ripard struct iio_dev *idev; 11320e589d5fSMaxime Ripard struct at91_adc_state *st; 11330e589d5fSMaxime Ripard struct resource *res; 1134e748783cSJean-Christophe PLAGNIOL-VILLARD u32 reg; 11350e589d5fSMaxime Ripard 1136f8837532SSachin Kamat idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state)); 1137f8837532SSachin Kamat if (!idev) 1138f8837532SSachin Kamat return -ENOMEM; 11390e589d5fSMaxime Ripard 11400e589d5fSMaxime Ripard st = iio_priv(idev); 11410e589d5fSMaxime Ripard 1142e364185fSMaxime Ripard if (pdev->dev.of_node) 1143e364185fSMaxime Ripard ret = at91_adc_probe_dt(st, pdev); 1144e364185fSMaxime Ripard else 11450e589d5fSMaxime Ripard ret = at91_adc_probe_pdata(st, pdev); 1146e364185fSMaxime Ripard 11470e589d5fSMaxime Ripard if (ret) { 11480e589d5fSMaxime Ripard dev_err(&pdev->dev, "No platform data available.\n"); 1149f8837532SSachin Kamat return -EINVAL; 11500e589d5fSMaxime Ripard } 11510e589d5fSMaxime Ripard 11520e589d5fSMaxime Ripard platform_set_drvdata(pdev, idev); 11530e589d5fSMaxime Ripard 11540e589d5fSMaxime Ripard idev->dev.parent = &pdev->dev; 11550e589d5fSMaxime Ripard idev->name = dev_name(&pdev->dev); 11560e589d5fSMaxime Ripard idev->modes = INDIO_DIRECT_MODE; 11570e589d5fSMaxime Ripard idev->info = &at91_adc_info; 11580e589d5fSMaxime Ripard 11590e589d5fSMaxime Ripard st->irq = platform_get_irq(pdev, 0); 11600e589d5fSMaxime Ripard if (st->irq < 0) { 11610e589d5fSMaxime Ripard dev_err(&pdev->dev, "No IRQ ID is designated\n"); 1162f8837532SSachin Kamat return -ENODEV; 11630e589d5fSMaxime Ripard } 11640e589d5fSMaxime Ripard 1165390d75c1SJulia Lawall res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 11660e589d5fSMaxime Ripard 11675fd98466SThierry Reding st->reg_base = devm_ioremap_resource(&pdev->dev, res); 11685fd98466SThierry Reding if (IS_ERR(st->reg_base)) { 1169f8837532SSachin Kamat return PTR_ERR(st->reg_base); 11700e589d5fSMaxime Ripard } 11710e589d5fSMaxime Ripard 11720e589d5fSMaxime Ripard /* 11730e589d5fSMaxime Ripard * Disable all IRQs before setting up the handler 11740e589d5fSMaxime Ripard */ 11750e589d5fSMaxime Ripard at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST); 11760e589d5fSMaxime Ripard at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF); 117784882b06SAlexandre Belloni 117884882b06SAlexandre Belloni if (st->caps->has_tsmr) 117984882b06SAlexandre Belloni ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0, 118084882b06SAlexandre Belloni pdev->dev.driver->name, idev); 118184882b06SAlexandre Belloni else 118284882b06SAlexandre Belloni ret = request_irq(st->irq, at91_adc_rl_interrupt, 0, 118384882b06SAlexandre Belloni pdev->dev.driver->name, idev); 11840e589d5fSMaxime Ripard if (ret) { 11850e589d5fSMaxime Ripard dev_err(&pdev->dev, "Failed to allocate IRQ.\n"); 1186f8837532SSachin Kamat return ret; 11870e589d5fSMaxime Ripard } 11880e589d5fSMaxime Ripard 1189390d75c1SJulia Lawall st->clk = devm_clk_get(&pdev->dev, "adc_clk"); 11900e589d5fSMaxime Ripard if (IS_ERR(st->clk)) { 11910e589d5fSMaxime Ripard dev_err(&pdev->dev, "Failed to get the clock.\n"); 11920e589d5fSMaxime Ripard ret = PTR_ERR(st->clk); 11930e589d5fSMaxime Ripard goto error_free_irq; 11940e589d5fSMaxime Ripard } 11950e589d5fSMaxime Ripard 119600062a9cSJulia Lawall ret = clk_prepare_enable(st->clk); 11970e589d5fSMaxime Ripard if (ret) { 119800062a9cSJulia Lawall dev_err(&pdev->dev, 119900062a9cSJulia Lawall "Could not prepare or enable the clock.\n"); 1200390d75c1SJulia Lawall goto error_free_irq; 12010e589d5fSMaxime Ripard } 12020e589d5fSMaxime Ripard 1203390d75c1SJulia Lawall st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk"); 12040e589d5fSMaxime Ripard if (IS_ERR(st->adc_clk)) { 12050e589d5fSMaxime Ripard dev_err(&pdev->dev, "Failed to get the ADC clock.\n"); 1206f755bbbfSJulia Lawall ret = PTR_ERR(st->adc_clk); 12070e589d5fSMaxime Ripard goto error_disable_clk; 12080e589d5fSMaxime Ripard } 12090e589d5fSMaxime Ripard 121000062a9cSJulia Lawall ret = clk_prepare_enable(st->adc_clk); 12110e589d5fSMaxime Ripard if (ret) { 121200062a9cSJulia Lawall dev_err(&pdev->dev, 121300062a9cSJulia Lawall "Could not prepare or enable the ADC clock.\n"); 1214390d75c1SJulia Lawall goto error_disable_clk; 12150e589d5fSMaxime Ripard } 12160e589d5fSMaxime Ripard 12170e589d5fSMaxime Ripard /* 12180e589d5fSMaxime Ripard * Prescaler rate computation using the formula from the Atmel's 12190e589d5fSMaxime Ripard * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being 12200e589d5fSMaxime Ripard * specified by the electrical characteristics of the board. 12210e589d5fSMaxime Ripard */ 12220e589d5fSMaxime Ripard mstrclk = clk_get_rate(st->clk); 12230e589d5fSMaxime Ripard adc_clk = clk_get_rate(st->adc_clk); 1224db10e201SJosh Wu adc_clk_khz = adc_clk / 1000; 1225c8b11de0SJosh Wu 1226c8b11de0SJosh Wu dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n", 1227c8b11de0SJosh Wu mstrclk, adc_clk); 1228c8b11de0SJosh Wu 12290e589d5fSMaxime Ripard prsc = (mstrclk / (2 * adc_clk)) - 1; 12300e589d5fSMaxime Ripard 12310e589d5fSMaxime Ripard if (!st->startup_time) { 12320e589d5fSMaxime Ripard dev_err(&pdev->dev, "No startup time available.\n"); 12330e589d5fSMaxime Ripard ret = -EINVAL; 12340e589d5fSMaxime Ripard goto error_disable_adc_clk; 12350e589d5fSMaxime Ripard } 1236c4601666SJosh Wu ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz); 12370e589d5fSMaxime Ripard 12380e589d5fSMaxime Ripard /* 1239beca9e76SJean-Christophe PLAGNIOL-VILLARD * a minimal Sample and Hold Time is necessary for the ADC to guarantee 1240beca9e76SJean-Christophe PLAGNIOL-VILLARD * the best converted final value between two channels selection 1241beca9e76SJean-Christophe PLAGNIOL-VILLARD * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock 1242beca9e76SJean-Christophe PLAGNIOL-VILLARD */ 12438f32b6baSAlexandre Belloni if (st->sample_hold_time > 0) 12448f32b6baSAlexandre Belloni shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000) 12458f32b6baSAlexandre Belloni - 1, 1); 12468f32b6baSAlexandre Belloni else 12478f32b6baSAlexandre Belloni shtim = 0; 1248beca9e76SJean-Christophe PLAGNIOL-VILLARD 12499120c0beSJosh Wu reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask; 12509120c0beSJosh Wu reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask; 125147be16b6SLudovic Desroches if (st->low_res) 1252e748783cSJean-Christophe PLAGNIOL-VILLARD reg |= AT91_ADC_LOWRES; 1253e748783cSJean-Christophe PLAGNIOL-VILLARD if (st->sleep_mode) 1254e748783cSJean-Christophe PLAGNIOL-VILLARD reg |= AT91_ADC_SLEEP; 1255beca9e76SJean-Christophe PLAGNIOL-VILLARD reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM; 1256e748783cSJean-Christophe PLAGNIOL-VILLARD at91_adc_writel(st, AT91_ADC_MR, reg); 12570e589d5fSMaxime Ripard 12580e589d5fSMaxime Ripard /* Setup the ADC channels available on the board */ 12590e589d5fSMaxime Ripard ret = at91_adc_channel_init(idev); 12600e589d5fSMaxime Ripard if (ret < 0) { 12610e589d5fSMaxime Ripard dev_err(&pdev->dev, "Couldn't initialize the channels.\n"); 12620e589d5fSMaxime Ripard goto error_disable_adc_clk; 12630e589d5fSMaxime Ripard } 12640e589d5fSMaxime Ripard 12650e589d5fSMaxime Ripard init_waitqueue_head(&st->wq_data_avail); 12660e589d5fSMaxime Ripard mutex_init(&st->lock); 12670e589d5fSMaxime Ripard 1268c8b11de0SJosh Wu /* 1269c8b11de0SJosh Wu * Since touch screen will set trigger register as period trigger. So 1270c8b11de0SJosh Wu * when touch screen is enabled, then we have to disable hardware 1271c8b11de0SJosh Wu * trigger for classic adc. 1272c8b11de0SJosh Wu */ 1273c8b11de0SJosh Wu if (!st->touchscreen_type) { 12740e589d5fSMaxime Ripard ret = at91_adc_buffer_init(idev); 12750e589d5fSMaxime Ripard if (ret < 0) { 12760e589d5fSMaxime Ripard dev_err(&pdev->dev, "Couldn't initialize the buffer.\n"); 12770e589d5fSMaxime Ripard goto error_disable_adc_clk; 12780e589d5fSMaxime Ripard } 12790e589d5fSMaxime Ripard 12800e589d5fSMaxime Ripard ret = at91_adc_trigger_init(idev); 12810e589d5fSMaxime Ripard if (ret < 0) { 12820e589d5fSMaxime Ripard dev_err(&pdev->dev, "Couldn't setup the triggers.\n"); 1283c8b11de0SJosh Wu at91_adc_buffer_remove(idev); 1284c8b11de0SJosh Wu goto error_disable_adc_clk; 1285c8b11de0SJosh Wu } 1286c8b11de0SJosh Wu } else { 1287c8b11de0SJosh Wu ret = at91_ts_register(st, pdev); 1288c8b11de0SJosh Wu if (ret) 1289c8b11de0SJosh Wu goto error_disable_adc_clk; 1290c8b11de0SJosh Wu 1291c8b11de0SJosh Wu at91_ts_hw_init(st, adc_clk_khz); 12920e589d5fSMaxime Ripard } 12930e589d5fSMaxime Ripard 12940e589d5fSMaxime Ripard ret = iio_device_register(idev); 12950e589d5fSMaxime Ripard if (ret < 0) { 12960e589d5fSMaxime Ripard dev_err(&pdev->dev, "Couldn't register the device.\n"); 1297c8b11de0SJosh Wu goto error_iio_device_register; 12980e589d5fSMaxime Ripard } 12990e589d5fSMaxime Ripard 13000e589d5fSMaxime Ripard return 0; 13010e589d5fSMaxime Ripard 1302c8b11de0SJosh Wu error_iio_device_register: 1303c8b11de0SJosh Wu if (!st->touchscreen_type) { 13040e589d5fSMaxime Ripard at91_adc_trigger_remove(idev); 13050e589d5fSMaxime Ripard at91_adc_buffer_remove(idev); 1306c8b11de0SJosh Wu } else { 1307c8b11de0SJosh Wu at91_ts_unregister(st); 1308c8b11de0SJosh Wu } 13090e589d5fSMaxime Ripard error_disable_adc_clk: 131000062a9cSJulia Lawall clk_disable_unprepare(st->adc_clk); 13110e589d5fSMaxime Ripard error_disable_clk: 131200062a9cSJulia Lawall clk_disable_unprepare(st->clk); 13130e589d5fSMaxime Ripard error_free_irq: 13140e589d5fSMaxime Ripard free_irq(st->irq, idev); 13150e589d5fSMaxime Ripard return ret; 13160e589d5fSMaxime Ripard } 13170e589d5fSMaxime Ripard 1318fc52692cSGreg Kroah-Hartman static int at91_adc_remove(struct platform_device *pdev) 13190e589d5fSMaxime Ripard { 13200e589d5fSMaxime Ripard struct iio_dev *idev = platform_get_drvdata(pdev); 13210e589d5fSMaxime Ripard struct at91_adc_state *st = iio_priv(idev); 13220e589d5fSMaxime Ripard 13230e589d5fSMaxime Ripard iio_device_unregister(idev); 1324c8b11de0SJosh Wu if (!st->touchscreen_type) { 13250e589d5fSMaxime Ripard at91_adc_trigger_remove(idev); 13260e589d5fSMaxime Ripard at91_adc_buffer_remove(idev); 1327c8b11de0SJosh Wu } else { 1328c8b11de0SJosh Wu at91_ts_unregister(st); 1329c8b11de0SJosh Wu } 13300e589d5fSMaxime Ripard clk_disable_unprepare(st->adc_clk); 133100062a9cSJulia Lawall clk_disable_unprepare(st->clk); 13320e589d5fSMaxime Ripard free_irq(st->irq, idev); 13330e589d5fSMaxime Ripard 13340e589d5fSMaxime Ripard return 0; 13350e589d5fSMaxime Ripard } 13360e589d5fSMaxime Ripard 1337e1811f97SJosh Wu static struct at91_adc_caps at91sam9260_caps = { 1338c4601666SJosh Wu .calc_startup_ticks = calc_startup_ticks_9260, 13392b6d598bSJosh Wu .num_channels = 4, 1340e1811f97SJosh Wu .registers = { 1341e1811f97SJosh Wu .channel_base = AT91_ADC_CHR(0), 1342e1811f97SJosh Wu .drdy_mask = AT91_ADC_DRDY, 1343e1811f97SJosh Wu .status_register = AT91_ADC_SR, 1344e1811f97SJosh Wu .trigger_register = AT91_ADC_TRGR_9260, 13459120c0beSJosh Wu .mr_prescal_mask = AT91_ADC_PRESCAL_9260, 13469120c0beSJosh Wu .mr_startup_mask = AT91_ADC_STARTUP_9260, 1347e1811f97SJosh Wu }, 1348e1811f97SJosh Wu }; 1349e1811f97SJosh Wu 135065b1fdbaSAlexandre Belloni static struct at91_adc_caps at91sam9rl_caps = { 135165b1fdbaSAlexandre Belloni .has_ts = true, 135265b1fdbaSAlexandre Belloni .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */ 135365b1fdbaSAlexandre Belloni .num_channels = 6, 135465b1fdbaSAlexandre Belloni .registers = { 135565b1fdbaSAlexandre Belloni .channel_base = AT91_ADC_CHR(0), 135665b1fdbaSAlexandre Belloni .drdy_mask = AT91_ADC_DRDY, 135765b1fdbaSAlexandre Belloni .status_register = AT91_ADC_SR, 135865b1fdbaSAlexandre Belloni .trigger_register = AT91_ADC_TRGR_9G45, 135965b1fdbaSAlexandre Belloni .mr_prescal_mask = AT91_ADC_PRESCAL_9260, 136065b1fdbaSAlexandre Belloni .mr_startup_mask = AT91_ADC_STARTUP_9G45, 136165b1fdbaSAlexandre Belloni }, 136265b1fdbaSAlexandre Belloni }; 136365b1fdbaSAlexandre Belloni 1364e1811f97SJosh Wu static struct at91_adc_caps at91sam9g45_caps = { 1365c8b11de0SJosh Wu .has_ts = true, 1366c4601666SJosh Wu .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */ 13672b6d598bSJosh Wu .num_channels = 8, 1368e1811f97SJosh Wu .registers = { 1369e1811f97SJosh Wu .channel_base = AT91_ADC_CHR(0), 1370e1811f97SJosh Wu .drdy_mask = AT91_ADC_DRDY, 1371e1811f97SJosh Wu .status_register = AT91_ADC_SR, 1372e1811f97SJosh Wu .trigger_register = AT91_ADC_TRGR_9G45, 13739120c0beSJosh Wu .mr_prescal_mask = AT91_ADC_PRESCAL_9G45, 13749120c0beSJosh Wu .mr_startup_mask = AT91_ADC_STARTUP_9G45, 1375e1811f97SJosh Wu }, 1376e1811f97SJosh Wu }; 1377e1811f97SJosh Wu 1378e1811f97SJosh Wu static struct at91_adc_caps at91sam9x5_caps = { 1379c8b11de0SJosh Wu .has_ts = true, 1380c8b11de0SJosh Wu .has_tsmr = true, 1381c8b11de0SJosh Wu .ts_filter_average = 3, 1382c8b11de0SJosh Wu .ts_pen_detect_sensitivity = 2, 1383c4601666SJosh Wu .calc_startup_ticks = calc_startup_ticks_9x5, 13842b6d598bSJosh Wu .num_channels = 12, 1385e1811f97SJosh Wu .registers = { 1386e1811f97SJosh Wu .channel_base = AT91_ADC_CDR0_9X5, 1387e1811f97SJosh Wu .drdy_mask = AT91_ADC_SR_DRDY_9X5, 1388e1811f97SJosh Wu .status_register = AT91_ADC_SR_9X5, 1389e1811f97SJosh Wu .trigger_register = AT91_ADC_TRGR_9X5, 13909120c0beSJosh Wu /* prescal mask is same as 9G45 */ 13919120c0beSJosh Wu .mr_prescal_mask = AT91_ADC_PRESCAL_9G45, 13929120c0beSJosh Wu .mr_startup_mask = AT91_ADC_STARTUP_9X5, 1393e1811f97SJosh Wu }, 1394e1811f97SJosh Wu }; 1395e1811f97SJosh Wu 1396e364185fSMaxime Ripard static const struct of_device_id at91_adc_dt_ids[] = { 1397e1811f97SJosh Wu { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps }, 139865b1fdbaSAlexandre Belloni { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps }, 1399e1811f97SJosh Wu { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps }, 1400e1811f97SJosh Wu { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps }, 1401e364185fSMaxime Ripard {}, 1402e364185fSMaxime Ripard }; 1403e364185fSMaxime Ripard MODULE_DEVICE_TABLE(of, at91_adc_dt_ids); 1404467a44b0SAlexandre Belloni 1405467a44b0SAlexandre Belloni static const struct platform_device_id at91_adc_ids[] = { 1406467a44b0SAlexandre Belloni { 1407467a44b0SAlexandre Belloni .name = "at91sam9260-adc", 1408467a44b0SAlexandre Belloni .driver_data = (unsigned long)&at91sam9260_caps, 1409467a44b0SAlexandre Belloni }, { 141065b1fdbaSAlexandre Belloni .name = "at91sam9rl-adc", 141165b1fdbaSAlexandre Belloni .driver_data = (unsigned long)&at91sam9rl_caps, 141265b1fdbaSAlexandre Belloni }, { 1413467a44b0SAlexandre Belloni .name = "at91sam9g45-adc", 1414467a44b0SAlexandre Belloni .driver_data = (unsigned long)&at91sam9g45_caps, 1415467a44b0SAlexandre Belloni }, { 1416467a44b0SAlexandre Belloni .name = "at91sam9x5-adc", 1417467a44b0SAlexandre Belloni .driver_data = (unsigned long)&at91sam9x5_caps, 1418467a44b0SAlexandre Belloni }, { 1419467a44b0SAlexandre Belloni /* terminator */ 1420467a44b0SAlexandre Belloni } 1421467a44b0SAlexandre Belloni }; 1422467a44b0SAlexandre Belloni MODULE_DEVICE_TABLE(platform, at91_adc_ids); 1423e364185fSMaxime Ripard 14240e589d5fSMaxime Ripard static struct platform_driver at91_adc_driver = { 14250e589d5fSMaxime Ripard .probe = at91_adc_probe, 1426fc52692cSGreg Kroah-Hartman .remove = at91_adc_remove, 1427467a44b0SAlexandre Belloni .id_table = at91_adc_ids, 14280e589d5fSMaxime Ripard .driver = { 1429c8b11de0SJosh Wu .name = DRIVER_NAME, 1430e364185fSMaxime Ripard .of_match_table = of_match_ptr(at91_adc_dt_ids), 14310e589d5fSMaxime Ripard }, 14320e589d5fSMaxime Ripard }; 14330e589d5fSMaxime Ripard 14340e589d5fSMaxime Ripard module_platform_driver(at91_adc_driver); 14350e589d5fSMaxime Ripard 14360e589d5fSMaxime Ripard MODULE_LICENSE("GPL"); 14370e589d5fSMaxime Ripard MODULE_DESCRIPTION("Atmel AT91 ADC Driver"); 14380e589d5fSMaxime Ripard MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1439