1c51cb3f5SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later
20e589d5fSMaxime Ripard /*
30e589d5fSMaxime Ripard * Driver for the ADC present in the Atmel AT91 evaluation boards.
40e589d5fSMaxime Ripard *
50e589d5fSMaxime Ripard * Copyright 2011 Free Electrons
60e589d5fSMaxime Ripard */
70e589d5fSMaxime Ripard
80e589d5fSMaxime Ripard #include <linux/bitmap.h>
90e589d5fSMaxime Ripard #include <linux/bitops.h>
100e589d5fSMaxime Ripard #include <linux/clk.h>
110e589d5fSMaxime Ripard #include <linux/err.h>
120e589d5fSMaxime Ripard #include <linux/io.h>
13c8b11de0SJosh Wu #include <linux/input.h>
140e589d5fSMaxime Ripard #include <linux/interrupt.h>
150e589d5fSMaxime Ripard #include <linux/jiffies.h>
160e589d5fSMaxime Ripard #include <linux/kernel.h>
170e589d5fSMaxime Ripard #include <linux/module.h>
18e364185fSMaxime Ripard #include <linux/of.h>
190e589d5fSMaxime Ripard #include <linux/platform_device.h>
200e589d5fSMaxime Ripard #include <linux/sched.h>
210e589d5fSMaxime Ripard #include <linux/slab.h>
220e589d5fSMaxime Ripard #include <linux/wait.h>
230e589d5fSMaxime Ripard
240e589d5fSMaxime Ripard #include <linux/iio/iio.h>
250e589d5fSMaxime Ripard #include <linux/iio/buffer.h>
260e589d5fSMaxime Ripard #include <linux/iio/trigger.h>
270e589d5fSMaxime Ripard #include <linux/iio/trigger_consumer.h>
2890032e4eSLars-Peter Clausen #include <linux/iio/triggered_buffer.h>
29bc3ae982SWenyou Yang #include <linux/pinctrl/consumer.h>
300e589d5fSMaxime Ripard
31bee20c4bSAlexandre Belloni /* Registers */
32bee20c4bSAlexandre Belloni #define AT91_ADC_CR 0x00 /* Control Register */
33bee20c4bSAlexandre Belloni #define AT91_ADC_SWRST (1 << 0) /* Software Reset */
34bee20c4bSAlexandre Belloni #define AT91_ADC_START (1 << 1) /* Start Conversion */
35bee20c4bSAlexandre Belloni
36bee20c4bSAlexandre Belloni #define AT91_ADC_MR 0x04 /* Mode Register */
37bee20c4bSAlexandre Belloni #define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */
38bee20c4bSAlexandre Belloni #define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */
39bee20c4bSAlexandre Belloni #define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */
40bee20c4bSAlexandre Belloni #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
41bee20c4bSAlexandre Belloni #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
42bee20c4bSAlexandre Belloni #define AT91_ADC_TRGSEL_TC0 (0 << 1)
43bee20c4bSAlexandre Belloni #define AT91_ADC_TRGSEL_TC1 (1 << 1)
44bee20c4bSAlexandre Belloni #define AT91_ADC_TRGSEL_TC2 (2 << 1)
45bee20c4bSAlexandre Belloni #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
46bee20c4bSAlexandre Belloni #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
47bee20c4bSAlexandre Belloni #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */
48bee20c4bSAlexandre Belloni #define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */
49bee20c4bSAlexandre Belloni #define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */
50bee20c4bSAlexandre Belloni #define AT91_ADC_PRESCAL_9G45 (0xff << 8)
51bee20c4bSAlexandre Belloni #define AT91_ADC_PRESCAL_(x) ((x) << 8)
52bee20c4bSAlexandre Belloni #define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */
53bee20c4bSAlexandre Belloni #define AT91_ADC_STARTUP_9G45 (0x7f << 16)
54bee20c4bSAlexandre Belloni #define AT91_ADC_STARTUP_9X5 (0xf << 16)
55bee20c4bSAlexandre Belloni #define AT91_ADC_STARTUP_(x) ((x) << 16)
56bee20c4bSAlexandre Belloni #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */
57bee20c4bSAlexandre Belloni #define AT91_ADC_SHTIM_(x) ((x) << 24)
58bee20c4bSAlexandre Belloni #define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */
59bee20c4bSAlexandre Belloni #define AT91_ADC_PENDBC_(x) ((x) << 28)
60bee20c4bSAlexandre Belloni
61bee20c4bSAlexandre Belloni #define AT91_ADC_TSR 0x0C
62bee20c4bSAlexandre Belloni #define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */
63bee20c4bSAlexandre Belloni #define AT91_ADC_TSR_SHTIM_(x) ((x) << 24)
64bee20c4bSAlexandre Belloni
65bee20c4bSAlexandre Belloni #define AT91_ADC_CHER 0x10 /* Channel Enable Register */
66bee20c4bSAlexandre Belloni #define AT91_ADC_CHDR 0x14 /* Channel Disable Register */
67bee20c4bSAlexandre Belloni #define AT91_ADC_CHSR 0x18 /* Channel Status Register */
68bee20c4bSAlexandre Belloni #define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */
69bee20c4bSAlexandre Belloni
70bee20c4bSAlexandre Belloni #define AT91_ADC_SR 0x1C /* Status Register */
71bee20c4bSAlexandre Belloni #define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */
72bee20c4bSAlexandre Belloni #define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */
73bee20c4bSAlexandre Belloni #define AT91_ADC_DRDY (1 << 16) /* Data Ready */
74bee20c4bSAlexandre Belloni #define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */
75bee20c4bSAlexandre Belloni #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */
76bee20c4bSAlexandre Belloni #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */
77bee20c4bSAlexandre Belloni
78bee20c4bSAlexandre Belloni #define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */
79bee20c4bSAlexandre Belloni #define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */
80bee20c4bSAlexandre Belloni
81bee20c4bSAlexandre Belloni #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */
82bee20c4bSAlexandre Belloni #define AT91_ADC_LDATA (0x3ff)
83bee20c4bSAlexandre Belloni
84bee20c4bSAlexandre Belloni #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */
85bee20c4bSAlexandre Belloni #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
86bee20c4bSAlexandre Belloni #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
87bee20c4bSAlexandre Belloni #define AT91RL_ADC_IER_PEN (1 << 20)
88bee20c4bSAlexandre Belloni #define AT91RL_ADC_IER_NOPEN (1 << 21)
89bee20c4bSAlexandre Belloni #define AT91_ADC_IER_PEN (1 << 29)
90bee20c4bSAlexandre Belloni #define AT91_ADC_IER_NOPEN (1 << 30)
91bee20c4bSAlexandre Belloni #define AT91_ADC_IER_XRDY (1 << 20)
92bee20c4bSAlexandre Belloni #define AT91_ADC_IER_YRDY (1 << 21)
93bee20c4bSAlexandre Belloni #define AT91_ADC_IER_PRDY (1 << 22)
94bee20c4bSAlexandre Belloni #define AT91_ADC_ISR_PENS (1 << 31)
95bee20c4bSAlexandre Belloni
96bee20c4bSAlexandre Belloni #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */
97bee20c4bSAlexandre Belloni #define AT91_ADC_DATA (0x3ff)
98bee20c4bSAlexandre Belloni
99bee20c4bSAlexandre Belloni #define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */
100bee20c4bSAlexandre Belloni
101bee20c4bSAlexandre Belloni #define AT91_ADC_ACR 0x94 /* Analog Control Register */
102bee20c4bSAlexandre Belloni #define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */
103bee20c4bSAlexandre Belloni
104bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR 0xB0
105bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */
106bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_TSMODE_NONE (0 << 0)
107bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0)
108bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0)
109bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0)
110bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */
111bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_TSAV_(x) ((x) << 4)
112bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */
113ede63aafSNicolas Ferre #define AT91_ADC_TSMR_SCTIM_(x) ((x) << 16)
114bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */
115bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28)
116bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */
117bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */
118bee20c4bSAlexandre Belloni #define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */
119bee20c4bSAlexandre Belloni
120bee20c4bSAlexandre Belloni #define AT91_ADC_TSXPOSR 0xB4
121bee20c4bSAlexandre Belloni #define AT91_ADC_TSYPOSR 0xB8
122bee20c4bSAlexandre Belloni #define AT91_ADC_TSPRESSR 0xBC
123bee20c4bSAlexandre Belloni
124bee20c4bSAlexandre Belloni #define AT91_ADC_TRGR_9260 AT91_ADC_MR
125bee20c4bSAlexandre Belloni #define AT91_ADC_TRGR_9G45 0x08
126bee20c4bSAlexandre Belloni #define AT91_ADC_TRGR_9X5 0xC0
127bee20c4bSAlexandre Belloni
128bee20c4bSAlexandre Belloni /* Trigger Register bit field */
129bee20c4bSAlexandre Belloni #define AT91_ADC_TRGR_TRGPER (0xffff << 16)
130bee20c4bSAlexandre Belloni #define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16)
131bee20c4bSAlexandre Belloni #define AT91_ADC_TRGR_TRGMOD (0x7 << 0)
132bee20c4bSAlexandre Belloni #define AT91_ADC_TRGR_NONE (0 << 0)
133bee20c4bSAlexandre Belloni #define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0)
1340e589d5fSMaxime Ripard
1350e589d5fSMaxime Ripard #define AT91_ADC_CHAN(st, ch) \
1360e589d5fSMaxime Ripard (st->registers->channel_base + (ch * 4))
1370e589d5fSMaxime Ripard #define at91_adc_readl(st, reg) \
1380e589d5fSMaxime Ripard (readl_relaxed(st->reg_base + reg))
1390e589d5fSMaxime Ripard #define at91_adc_writel(st, reg, val) \
1400e589d5fSMaxime Ripard (writel_relaxed(val, st->reg_base + reg))
1410e589d5fSMaxime Ripard
142c8b11de0SJosh Wu #define DRIVER_NAME "at91_adc"
143c8b11de0SJosh Wu #define MAX_POS_BITS 12
144c8b11de0SJosh Wu
145c8b11de0SJosh Wu #define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
146c8b11de0SJosh Wu #define TOUCH_PEN_DETECT_DEBOUNCE_US 200
147c8b11de0SJosh Wu
14884882b06SAlexandre Belloni #define MAX_RLPOS_BITS 10
14984882b06SAlexandre Belloni #define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */
15084882b06SAlexandre Belloni #define TOUCH_SHTIM 0xa
151ede63aafSNicolas Ferre #define TOUCH_SCTIM_US 10 /* 10us for the Touchscreen Switches Closure Time */
15284882b06SAlexandre Belloni
153ead1c9f3SAlexandru Ardelean enum atmel_adc_ts_type {
154ead1c9f3SAlexandru Ardelean ATMEL_ADC_TOUCHSCREEN_NONE = 0,
155ead1c9f3SAlexandru Ardelean ATMEL_ADC_TOUCHSCREEN_4WIRE = 4,
156ead1c9f3SAlexandru Ardelean ATMEL_ADC_TOUCHSCREEN_5WIRE = 5,
157ead1c9f3SAlexandru Ardelean };
158ead1c9f3SAlexandru Ardelean
159ead1c9f3SAlexandru Ardelean /**
160ead1c9f3SAlexandru Ardelean * struct at91_adc_trigger - description of triggers
161ead1c9f3SAlexandru Ardelean * @name: name of the trigger advertised to the user
162ead1c9f3SAlexandru Ardelean * @value: value to set in the ADC's trigger setup register
163ead1c9f3SAlexandru Ardelean * to enable the trigger
164ead1c9f3SAlexandru Ardelean * @is_external: Does the trigger rely on an external pin?
165ead1c9f3SAlexandru Ardelean */
166ead1c9f3SAlexandru Ardelean struct at91_adc_trigger {
167ead1c9f3SAlexandru Ardelean const char *name;
168ead1c9f3SAlexandru Ardelean u8 value;
169ead1c9f3SAlexandru Ardelean bool is_external;
170ead1c9f3SAlexandru Ardelean };
171ead1c9f3SAlexandru Ardelean
1722de0c019SAlexandre Belloni /**
1732de0c019SAlexandre Belloni * struct at91_adc_reg_desc - Various informations relative to registers
1742de0c019SAlexandre Belloni * @channel_base: Base offset for the channel data registers
1752de0c019SAlexandre Belloni * @drdy_mask: Mask of the DRDY field in the relevant registers
1764ab559a6SLee Jones * (Interruptions registers mostly)
1772de0c019SAlexandre Belloni * @status_register: Offset of the Interrupt Status Register
1782de0c019SAlexandre Belloni * @trigger_register: Offset of the Trigger setup register
1792de0c019SAlexandre Belloni * @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register
1802de0c019SAlexandre Belloni * @mr_startup_mask: Mask of the STARTUP field in the adc MR register
1812de0c019SAlexandre Belloni */
1822de0c019SAlexandre Belloni struct at91_adc_reg_desc {
1832de0c019SAlexandre Belloni u8 channel_base;
1842de0c019SAlexandre Belloni u32 drdy_mask;
1852de0c019SAlexandre Belloni u8 status_register;
1862de0c019SAlexandre Belloni u8 trigger_register;
1872de0c019SAlexandre Belloni u32 mr_prescal_mask;
1882de0c019SAlexandre Belloni u32 mr_startup_mask;
1892de0c019SAlexandre Belloni };
1902de0c019SAlexandre Belloni
191e1811f97SJosh Wu struct at91_adc_caps {
192c8b11de0SJosh Wu bool has_ts; /* Support touch screen */
193c8b11de0SJosh Wu bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */
194c8b11de0SJosh Wu /*
195c8b11de0SJosh Wu * Numbers of sampling data will be averaged. Can be 0~3.
196c8b11de0SJosh Wu * Hardware can average (2 ^ ts_filter_average) sample data.
197c8b11de0SJosh Wu */
198c8b11de0SJosh Wu u8 ts_filter_average;
199c8b11de0SJosh Wu /* Pen Detection input pull-up resistor, can be 0~3 */
200c8b11de0SJosh Wu u8 ts_pen_detect_sensitivity;
201c8b11de0SJosh Wu
202c4601666SJosh Wu /* startup time calculate function */
2032ab5f39bSJan Leupold u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz);
204c4601666SJosh Wu
2052b6d598bSJosh Wu u8 num_channels;
2065eb39ef8SAlexandre Belloni
2075eb39ef8SAlexandre Belloni u8 low_res_bits;
2085eb39ef8SAlexandre Belloni u8 high_res_bits;
20909d4726bSAlexandre Belloni u32 trigger_number;
21009d4726bSAlexandre Belloni const struct at91_adc_trigger *triggers;
211e1811f97SJosh Wu struct at91_adc_reg_desc registers;
212e1811f97SJosh Wu };
213e1811f97SJosh Wu
2140e589d5fSMaxime Ripard struct at91_adc_state {
2150e589d5fSMaxime Ripard struct clk *adc_clk;
2160e589d5fSMaxime Ripard u16 *buffer;
2170e589d5fSMaxime Ripard unsigned long channels_mask;
2180e589d5fSMaxime Ripard struct clk *clk;
2190e589d5fSMaxime Ripard bool done;
2200e589d5fSMaxime Ripard int irq;
2210e589d5fSMaxime Ripard u16 last_value;
222d4f51956SLudovic Desroches int chnb;
2230e589d5fSMaxime Ripard struct mutex lock;
2240e589d5fSMaxime Ripard u8 num_channels;
2250e589d5fSMaxime Ripard void __iomem *reg_base;
2263e4ef8e8SAlexandru Ardelean const struct at91_adc_reg_desc *registers;
2272ab5f39bSJan Leupold u32 startup_time;
228beca9e76SJean-Christophe PLAGNIOL-VILLARD u8 sample_hold_time;
229e748783cSJean-Christophe PLAGNIOL-VILLARD bool sleep_mode;
2300e589d5fSMaxime Ripard struct iio_trigger **trig;
2310e589d5fSMaxime Ripard bool use_external;
2320e589d5fSMaxime Ripard u32 vref_mv;
23347be16b6SLudovic Desroches u32 res; /* resolution used for convertions */
2340e589d5fSMaxime Ripard wait_queue_head_t wq_data_avail;
2353e4ef8e8SAlexandru Ardelean const struct at91_adc_caps *caps;
236c8b11de0SJosh Wu
237c8b11de0SJosh Wu /*
238c8b11de0SJosh Wu * Following ADC channels are shared by touchscreen:
239c8b11de0SJosh Wu *
240c8b11de0SJosh Wu * CH0 -- Touch screen XP/UL
241c8b11de0SJosh Wu * CH1 -- Touch screen XM/UR
242c8b11de0SJosh Wu * CH2 -- Touch screen YP/LL
243c8b11de0SJosh Wu * CH3 -- Touch screen YM/Sense
244c8b11de0SJosh Wu * CH4 -- Touch screen LR(5-wire only)
245c8b11de0SJosh Wu *
246c8b11de0SJosh Wu * The bitfields below represents the reserved channel in the
247c8b11de0SJosh Wu * touchscreen mode.
248c8b11de0SJosh Wu */
249c8b11de0SJosh Wu #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0)
250c8b11de0SJosh Wu #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0)
251c8b11de0SJosh Wu enum atmel_adc_ts_type touchscreen_type;
252c8b11de0SJosh Wu struct input_dev *ts_input;
253c8b11de0SJosh Wu
254c8b11de0SJosh Wu u16 ts_sample_period_val;
255c8b11de0SJosh Wu u32 ts_pressure_threshold;
25684882b06SAlexandre Belloni u16 ts_pendbc;
25784882b06SAlexandre Belloni
25884882b06SAlexandre Belloni bool ts_bufferedmeasure;
25984882b06SAlexandre Belloni u32 ts_prev_absx;
26084882b06SAlexandre Belloni u32 ts_prev_absy;
2610e589d5fSMaxime Ripard };
2620e589d5fSMaxime Ripard
at91_adc_trigger_handler(int irq,void * p)2630e589d5fSMaxime Ripard static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
2640e589d5fSMaxime Ripard {
2650e589d5fSMaxime Ripard struct iio_poll_func *pf = p;
2660e589d5fSMaxime Ripard struct iio_dev *idev = pf->indio_dev;
2670e589d5fSMaxime Ripard struct at91_adc_state *st = iio_priv(idev);
268aea835f2SEugen Hristev struct iio_chan_spec const *chan;
2690e589d5fSMaxime Ripard int i, j = 0;
2700e589d5fSMaxime Ripard
2710e589d5fSMaxime Ripard for (i = 0; i < idev->masklength; i++) {
2720e589d5fSMaxime Ripard if (!test_bit(i, idev->active_scan_mask))
2730e589d5fSMaxime Ripard continue;
274aea835f2SEugen Hristev chan = idev->channels + i;
275aea835f2SEugen Hristev st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, chan->channel));
2760e589d5fSMaxime Ripard j++;
2770e589d5fSMaxime Ripard }
2780e589d5fSMaxime Ripard
279e79cece0SLars-Peter Clausen iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp);
2800e589d5fSMaxime Ripard
2810e589d5fSMaxime Ripard iio_trigger_notify_done(idev->trig);
2820e589d5fSMaxime Ripard
2830e589d5fSMaxime Ripard /* Needed to ACK the DRDY interruption */
2840e589d5fSMaxime Ripard at91_adc_readl(st, AT91_ADC_LCDR);
2850e589d5fSMaxime Ripard
2860e589d5fSMaxime Ripard enable_irq(st->irq);
2870e589d5fSMaxime Ripard
2880e589d5fSMaxime Ripard return IRQ_HANDLED;
2890e589d5fSMaxime Ripard }
2900e589d5fSMaxime Ripard
291c8b11de0SJosh Wu /* Handler for classic adc channel eoc trigger */
handle_adc_eoc_trigger(int irq,struct iio_dev * idev)2923068ab20SJosh Wu static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev)
2930e589d5fSMaxime Ripard {
2940e589d5fSMaxime Ripard struct at91_adc_state *st = iio_priv(idev);
2950e589d5fSMaxime Ripard
2960e589d5fSMaxime Ripard if (iio_buffer_enabled(idev)) {
2970e589d5fSMaxime Ripard disable_irq_nosync(irq);
298398fd22bSPeter Meerwald iio_trigger_poll(idev->trig);
2990e589d5fSMaxime Ripard } else {
300d4f51956SLudovic Desroches st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb));
301bc1b4532SEugen Hristev /* Needed to ACK the DRDY interruption */
302bc1b4532SEugen Hristev at91_adc_readl(st, AT91_ADC_LCDR);
3030e589d5fSMaxime Ripard st->done = true;
3040e589d5fSMaxime Ripard wake_up_interruptible(&st->wq_data_avail);
3050e589d5fSMaxime Ripard }
306c8b11de0SJosh Wu }
307c8b11de0SJosh Wu
at91_ts_sample(struct iio_dev * idev)308044d406aSAlexandru Ardelean static int at91_ts_sample(struct iio_dev *idev)
309c8b11de0SJosh Wu {
310044d406aSAlexandru Ardelean struct at91_adc_state *st = iio_priv(idev);
311c8b11de0SJosh Wu unsigned int xscale, yscale, reg, z1, z2;
312c8b11de0SJosh Wu unsigned int x, y, pres, xpos, ypos;
313c8b11de0SJosh Wu unsigned int rxp = 1;
314c8b11de0SJosh Wu unsigned int factor = 1000;
315c8b11de0SJosh Wu
316c8b11de0SJosh Wu unsigned int xyz_mask_bits = st->res;
317c8b11de0SJosh Wu unsigned int xyz_mask = (1 << xyz_mask_bits) - 1;
318c8b11de0SJosh Wu
319c8b11de0SJosh Wu /* calculate position */
320c8b11de0SJosh Wu /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */
321c8b11de0SJosh Wu reg = at91_adc_readl(st, AT91_ADC_TSXPOSR);
322c8b11de0SJosh Wu xpos = reg & xyz_mask;
323c8b11de0SJosh Wu x = (xpos << MAX_POS_BITS) - xpos;
324c8b11de0SJosh Wu xscale = (reg >> 16) & xyz_mask;
325c8b11de0SJosh Wu if (xscale == 0) {
326c8b11de0SJosh Wu dev_err(&idev->dev, "Error: xscale == 0!\n");
327c8b11de0SJosh Wu return -1;
328c8b11de0SJosh Wu }
329c8b11de0SJosh Wu x /= xscale;
330c8b11de0SJosh Wu
331c8b11de0SJosh Wu /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */
332c8b11de0SJosh Wu reg = at91_adc_readl(st, AT91_ADC_TSYPOSR);
333c8b11de0SJosh Wu ypos = reg & xyz_mask;
334c8b11de0SJosh Wu y = (ypos << MAX_POS_BITS) - ypos;
335c8b11de0SJosh Wu yscale = (reg >> 16) & xyz_mask;
336c8b11de0SJosh Wu if (yscale == 0) {
337c8b11de0SJosh Wu dev_err(&idev->dev, "Error: yscale == 0!\n");
338c8b11de0SJosh Wu return -1;
339c8b11de0SJosh Wu }
340c8b11de0SJosh Wu y /= yscale;
341c8b11de0SJosh Wu
342c8b11de0SJosh Wu /* calculate the pressure */
343c8b11de0SJosh Wu reg = at91_adc_readl(st, AT91_ADC_TSPRESSR);
344c8b11de0SJosh Wu z1 = reg & xyz_mask;
345c8b11de0SJosh Wu z2 = (reg >> 16) & xyz_mask;
346c8b11de0SJosh Wu
347c8b11de0SJosh Wu if (z1 != 0)
348c8b11de0SJosh Wu pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor)
349c8b11de0SJosh Wu / factor;
350c8b11de0SJosh Wu else
351c8b11de0SJosh Wu pres = st->ts_pressure_threshold; /* no pen contacted */
352c8b11de0SJosh Wu
353c8b11de0SJosh Wu dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n",
354c8b11de0SJosh Wu xpos, xscale, ypos, yscale, z1, z2, pres);
355c8b11de0SJosh Wu
356c8b11de0SJosh Wu if (pres < st->ts_pressure_threshold) {
357c8b11de0SJosh Wu dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n",
358c8b11de0SJosh Wu x, y, pres / factor);
359c8b11de0SJosh Wu input_report_abs(st->ts_input, ABS_X, x);
360c8b11de0SJosh Wu input_report_abs(st->ts_input, ABS_Y, y);
361c8b11de0SJosh Wu input_report_abs(st->ts_input, ABS_PRESSURE, pres);
362c8b11de0SJosh Wu input_report_key(st->ts_input, BTN_TOUCH, 1);
363c8b11de0SJosh Wu input_sync(st->ts_input);
364c8b11de0SJosh Wu } else {
365c8b11de0SJosh Wu dev_dbg(&idev->dev, "pressure too low: not reporting\n");
366c8b11de0SJosh Wu }
367c8b11de0SJosh Wu
368c8b11de0SJosh Wu return 0;
369c8b11de0SJosh Wu }
370c8b11de0SJosh Wu
at91_adc_rl_interrupt(int irq,void * private)37184882b06SAlexandre Belloni static irqreturn_t at91_adc_rl_interrupt(int irq, void *private)
37284882b06SAlexandre Belloni {
37384882b06SAlexandre Belloni struct iio_dev *idev = private;
37484882b06SAlexandre Belloni struct at91_adc_state *st = iio_priv(idev);
37584882b06SAlexandre Belloni u32 status = at91_adc_readl(st, st->registers->status_register);
37684882b06SAlexandre Belloni unsigned int reg;
37784882b06SAlexandre Belloni
37884882b06SAlexandre Belloni status &= at91_adc_readl(st, AT91_ADC_IMR);
379d4f51956SLudovic Desroches if (status & GENMASK(st->num_channels - 1, 0))
38084882b06SAlexandre Belloni handle_adc_eoc_trigger(irq, idev);
38184882b06SAlexandre Belloni
38284882b06SAlexandre Belloni if (status & AT91RL_ADC_IER_PEN) {
38384882b06SAlexandre Belloni /* Disabling pen debounce is required to get a NOPEN irq */
38484882b06SAlexandre Belloni reg = at91_adc_readl(st, AT91_ADC_MR);
38584882b06SAlexandre Belloni reg &= ~AT91_ADC_PENDBC;
38684882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_MR, reg);
38784882b06SAlexandre Belloni
38884882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
38984882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN
39084882b06SAlexandre Belloni | AT91_ADC_EOC(3));
39184882b06SAlexandre Belloni /* Set up period trigger for sampling */
39284882b06SAlexandre Belloni at91_adc_writel(st, st->registers->trigger_register,
39384882b06SAlexandre Belloni AT91_ADC_TRGR_MOD_PERIOD_TRIG |
39484882b06SAlexandre Belloni AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
39584882b06SAlexandre Belloni } else if (status & AT91RL_ADC_IER_NOPEN) {
39684882b06SAlexandre Belloni reg = at91_adc_readl(st, AT91_ADC_MR);
39784882b06SAlexandre Belloni reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
39884882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_MR, reg);
39984882b06SAlexandre Belloni at91_adc_writel(st, st->registers->trigger_register,
40084882b06SAlexandre Belloni AT91_ADC_TRGR_NONE);
40184882b06SAlexandre Belloni
40284882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN
40384882b06SAlexandre Belloni | AT91_ADC_EOC(3));
40484882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
40584882b06SAlexandre Belloni st->ts_bufferedmeasure = false;
40684882b06SAlexandre Belloni input_report_key(st->ts_input, BTN_TOUCH, 0);
40784882b06SAlexandre Belloni input_sync(st->ts_input);
408c2ab4474SAnders Darander } else if (status & AT91_ADC_EOC(3) && st->ts_input) {
409c2ab4474SAnders Darander /* Conversion finished and we've a touchscreen */
41084882b06SAlexandre Belloni if (st->ts_bufferedmeasure) {
41184882b06SAlexandre Belloni /*
41284882b06SAlexandre Belloni * Last measurement is always discarded, since it can
41384882b06SAlexandre Belloni * be erroneous.
41484882b06SAlexandre Belloni * Always report previous measurement
41584882b06SAlexandre Belloni */
41684882b06SAlexandre Belloni input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx);
41784882b06SAlexandre Belloni input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy);
41884882b06SAlexandre Belloni input_report_key(st->ts_input, BTN_TOUCH, 1);
41984882b06SAlexandre Belloni input_sync(st->ts_input);
42084882b06SAlexandre Belloni } else
42184882b06SAlexandre Belloni st->ts_bufferedmeasure = true;
42284882b06SAlexandre Belloni
42384882b06SAlexandre Belloni /* Now make new measurement */
42484882b06SAlexandre Belloni st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3))
42584882b06SAlexandre Belloni << MAX_RLPOS_BITS;
42684882b06SAlexandre Belloni st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2));
42784882b06SAlexandre Belloni
42884882b06SAlexandre Belloni st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1))
42984882b06SAlexandre Belloni << MAX_RLPOS_BITS;
43084882b06SAlexandre Belloni st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0));
43184882b06SAlexandre Belloni }
43284882b06SAlexandre Belloni
43384882b06SAlexandre Belloni return IRQ_HANDLED;
43484882b06SAlexandre Belloni }
43584882b06SAlexandre Belloni
at91_adc_9x5_interrupt(int irq,void * private)43684882b06SAlexandre Belloni static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private)
437c8b11de0SJosh Wu {
438c8b11de0SJosh Wu struct iio_dev *idev = private;
439c8b11de0SJosh Wu struct at91_adc_state *st = iio_priv(idev);
440c8b11de0SJosh Wu u32 status = at91_adc_readl(st, st->registers->status_register);
441c8b11de0SJosh Wu const uint32_t ts_data_irq_mask =
442c8b11de0SJosh Wu AT91_ADC_IER_XRDY |
443c8b11de0SJosh Wu AT91_ADC_IER_YRDY |
444c8b11de0SJosh Wu AT91_ADC_IER_PRDY;
445c8b11de0SJosh Wu
446d4f51956SLudovic Desroches if (status & GENMASK(st->num_channels - 1, 0))
447c8b11de0SJosh Wu handle_adc_eoc_trigger(irq, idev);
448c8b11de0SJosh Wu
449c8b11de0SJosh Wu if (status & AT91_ADC_IER_PEN) {
450c8b11de0SJosh Wu at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
451c8b11de0SJosh Wu at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN |
452c8b11de0SJosh Wu ts_data_irq_mask);
453c8b11de0SJosh Wu /* Set up period trigger for sampling */
454c8b11de0SJosh Wu at91_adc_writel(st, st->registers->trigger_register,
455c8b11de0SJosh Wu AT91_ADC_TRGR_MOD_PERIOD_TRIG |
456c8b11de0SJosh Wu AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
457c8b11de0SJosh Wu } else if (status & AT91_ADC_IER_NOPEN) {
458c8b11de0SJosh Wu at91_adc_writel(st, st->registers->trigger_register, 0);
459c8b11de0SJosh Wu at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN |
460c8b11de0SJosh Wu ts_data_irq_mask);
461c8b11de0SJosh Wu at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
462c8b11de0SJosh Wu
463c8b11de0SJosh Wu input_report_key(st->ts_input, BTN_TOUCH, 0);
464c8b11de0SJosh Wu input_sync(st->ts_input);
465c8b11de0SJosh Wu } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) {
466c8b11de0SJosh Wu /* Now all touchscreen data is ready */
467c8b11de0SJosh Wu
468c8b11de0SJosh Wu if (status & AT91_ADC_ISR_PENS) {
469c8b11de0SJosh Wu /* validate data by pen contact */
470044d406aSAlexandru Ardelean at91_ts_sample(idev);
471c8b11de0SJosh Wu } else {
472c8b11de0SJosh Wu /* triggered by event that is no pen contact, just read
473c8b11de0SJosh Wu * them to clean the interrupt and discard all.
474c8b11de0SJosh Wu */
475c8b11de0SJosh Wu at91_adc_readl(st, AT91_ADC_TSXPOSR);
476c8b11de0SJosh Wu at91_adc_readl(st, AT91_ADC_TSYPOSR);
477c8b11de0SJosh Wu at91_adc_readl(st, AT91_ADC_TSPRESSR);
478c8b11de0SJosh Wu }
479c8b11de0SJosh Wu }
4800e589d5fSMaxime Ripard
4810e589d5fSMaxime Ripard return IRQ_HANDLED;
4820e589d5fSMaxime Ripard }
4830e589d5fSMaxime Ripard
at91_adc_channel_init(struct iio_dev * idev)4840e589d5fSMaxime Ripard static int at91_adc_channel_init(struct iio_dev *idev)
4850e589d5fSMaxime Ripard {
4860e589d5fSMaxime Ripard struct at91_adc_state *st = iio_priv(idev);
4870e589d5fSMaxime Ripard struct iio_chan_spec *chan_array, *timestamp;
4880e589d5fSMaxime Ripard int bit, idx = 0;
489c8b11de0SJosh Wu unsigned long rsvd_mask = 0;
490c8b11de0SJosh Wu
491c8b11de0SJosh Wu /* If touchscreen is enable, then reserve the adc channels */
492c8b11de0SJosh Wu if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
493c8b11de0SJosh Wu rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE;
494c8b11de0SJosh Wu else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE)
495c8b11de0SJosh Wu rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE;
496c8b11de0SJosh Wu
497c8b11de0SJosh Wu /* set up the channel mask to reserve touchscreen channels */
498c8b11de0SJosh Wu st->channels_mask &= ~rsvd_mask;
4990e589d5fSMaxime Ripard
5000e589d5fSMaxime Ripard idev->num_channels = bitmap_weight(&st->channels_mask,
5010e589d5fSMaxime Ripard st->num_channels) + 1;
5020e589d5fSMaxime Ripard
5036b3aa313SAxel Lin chan_array = devm_kzalloc(&idev->dev,
5046b3aa313SAxel Lin ((idev->num_channels + 1) *
5056b3aa313SAxel Lin sizeof(struct iio_chan_spec)),
5066b3aa313SAxel Lin GFP_KERNEL);
5070e589d5fSMaxime Ripard
5080e589d5fSMaxime Ripard if (!chan_array)
5090e589d5fSMaxime Ripard return -ENOMEM;
5100e589d5fSMaxime Ripard
5110e589d5fSMaxime Ripard for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
5120e589d5fSMaxime Ripard struct iio_chan_spec *chan = chan_array + idx;
5130e589d5fSMaxime Ripard
5140e589d5fSMaxime Ripard chan->type = IIO_VOLTAGE;
5150e589d5fSMaxime Ripard chan->indexed = 1;
5160e589d5fSMaxime Ripard chan->channel = bit;
5170e589d5fSMaxime Ripard chan->scan_index = idx;
5180e589d5fSMaxime Ripard chan->scan_type.sign = 'u';
51947be16b6SLudovic Desroches chan->scan_type.realbits = st->res;
5200e589d5fSMaxime Ripard chan->scan_type.storagebits = 16;
52101bdab66SJonathan Cameron chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
52201bdab66SJonathan Cameron chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
5230e589d5fSMaxime Ripard idx++;
5240e589d5fSMaxime Ripard }
5250e589d5fSMaxime Ripard timestamp = chan_array + idx;
5260e589d5fSMaxime Ripard
5270e589d5fSMaxime Ripard timestamp->type = IIO_TIMESTAMP;
5280e589d5fSMaxime Ripard timestamp->channel = -1;
5290e589d5fSMaxime Ripard timestamp->scan_index = idx;
5300e589d5fSMaxime Ripard timestamp->scan_type.sign = 's';
5310e589d5fSMaxime Ripard timestamp->scan_type.realbits = 64;
5320e589d5fSMaxime Ripard timestamp->scan_type.storagebits = 64;
5330e589d5fSMaxime Ripard
5340e589d5fSMaxime Ripard idev->channels = chan_array;
5350e589d5fSMaxime Ripard return idev->num_channels;
5360e589d5fSMaxime Ripard }
5370e589d5fSMaxime Ripard
at91_adc_get_trigger_value_by_name(struct iio_dev * idev,const struct at91_adc_trigger * triggers,const char * trigger_name)5384f3bcd87SDan Carpenter static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
53909d4726bSAlexandre Belloni const struct at91_adc_trigger *triggers,
5400e589d5fSMaxime Ripard const char *trigger_name)
5410e589d5fSMaxime Ripard {
5420e589d5fSMaxime Ripard struct at91_adc_state *st = iio_priv(idev);
5430e589d5fSMaxime Ripard int i;
5440e589d5fSMaxime Ripard
54509d4726bSAlexandre Belloni for (i = 0; i < st->caps->trigger_number; i++) {
5460e589d5fSMaxime Ripard char *name = kasprintf(GFP_KERNEL,
5470e589d5fSMaxime Ripard "%s-dev%d-%s",
5480e589d5fSMaxime Ripard idev->name,
54915ea2878SJonathan Cameron iio_device_id(idev),
5500e589d5fSMaxime Ripard triggers[i].name);
5510e589d5fSMaxime Ripard if (!name)
5520e589d5fSMaxime Ripard return -ENOMEM;
5530e589d5fSMaxime Ripard
5540e589d5fSMaxime Ripard if (strcmp(trigger_name, name) == 0) {
5550e589d5fSMaxime Ripard kfree(name);
5564f3bcd87SDan Carpenter if (triggers[i].value == 0)
5574f3bcd87SDan Carpenter return -EINVAL;
5584f3bcd87SDan Carpenter return triggers[i].value;
5590e589d5fSMaxime Ripard }
5600e589d5fSMaxime Ripard
5610e589d5fSMaxime Ripard kfree(name);
5620e589d5fSMaxime Ripard }
5630e589d5fSMaxime Ripard
5644f3bcd87SDan Carpenter return -EINVAL;
5650e589d5fSMaxime Ripard }
5660e589d5fSMaxime Ripard
at91_adc_configure_trigger(struct iio_trigger * trig,bool state)5670e589d5fSMaxime Ripard static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
5680e589d5fSMaxime Ripard {
5691e9663c6SLars-Peter Clausen struct iio_dev *idev = iio_trigger_get_drvdata(trig);
5700e589d5fSMaxime Ripard struct at91_adc_state *st = iio_priv(idev);
5713e4ef8e8SAlexandru Ardelean const struct at91_adc_reg_desc *reg = st->registers;
5720e589d5fSMaxime Ripard u32 status = at91_adc_readl(st, reg->trigger_register);
5734f3bcd87SDan Carpenter int value;
5740e589d5fSMaxime Ripard u8 bit;
5750e589d5fSMaxime Ripard
5760e589d5fSMaxime Ripard value = at91_adc_get_trigger_value_by_name(idev,
57709d4726bSAlexandre Belloni st->caps->triggers,
5780e589d5fSMaxime Ripard idev->trig->name);
5794f3bcd87SDan Carpenter if (value < 0)
5804f3bcd87SDan Carpenter return value;
5810e589d5fSMaxime Ripard
5820e589d5fSMaxime Ripard if (state) {
5830e589d5fSMaxime Ripard st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
5840e589d5fSMaxime Ripard if (st->buffer == NULL)
5850e589d5fSMaxime Ripard return -ENOMEM;
5860e589d5fSMaxime Ripard
5870e589d5fSMaxime Ripard at91_adc_writel(st, reg->trigger_register,
5880e589d5fSMaxime Ripard status | value);
5890e589d5fSMaxime Ripard
59070dddeeeSOctavian Purdila for_each_set_bit(bit, idev->active_scan_mask,
5910e589d5fSMaxime Ripard st->num_channels) {
5920e589d5fSMaxime Ripard struct iio_chan_spec const *chan = idev->channels + bit;
5930e589d5fSMaxime Ripard at91_adc_writel(st, AT91_ADC_CHER,
5940e589d5fSMaxime Ripard AT91_ADC_CH(chan->channel));
5950e589d5fSMaxime Ripard }
5960e589d5fSMaxime Ripard
5970e589d5fSMaxime Ripard at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
5980e589d5fSMaxime Ripard
5990e589d5fSMaxime Ripard } else {
6000e589d5fSMaxime Ripard at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
6010e589d5fSMaxime Ripard
6020e589d5fSMaxime Ripard at91_adc_writel(st, reg->trigger_register,
6030e589d5fSMaxime Ripard status & ~value);
6040e589d5fSMaxime Ripard
60570dddeeeSOctavian Purdila for_each_set_bit(bit, idev->active_scan_mask,
6060e589d5fSMaxime Ripard st->num_channels) {
6070e589d5fSMaxime Ripard struct iio_chan_spec const *chan = idev->channels + bit;
6080e589d5fSMaxime Ripard at91_adc_writel(st, AT91_ADC_CHDR,
6090e589d5fSMaxime Ripard AT91_ADC_CH(chan->channel));
6100e589d5fSMaxime Ripard }
6110e589d5fSMaxime Ripard kfree(st->buffer);
6120e589d5fSMaxime Ripard }
6130e589d5fSMaxime Ripard
6140e589d5fSMaxime Ripard return 0;
6150e589d5fSMaxime Ripard }
6160e589d5fSMaxime Ripard
6170e589d5fSMaxime Ripard static const struct iio_trigger_ops at91_adc_trigger_ops = {
6180e589d5fSMaxime Ripard .set_trigger_state = &at91_adc_configure_trigger,
6190e589d5fSMaxime Ripard };
6200e589d5fSMaxime Ripard
at91_adc_allocate_trigger(struct iio_dev * idev,const struct at91_adc_trigger * trigger)6210e589d5fSMaxime Ripard static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
62209d4726bSAlexandre Belloni const struct at91_adc_trigger *trigger)
6230e589d5fSMaxime Ripard {
6240e589d5fSMaxime Ripard struct iio_trigger *trig;
6250e589d5fSMaxime Ripard int ret;
6260e589d5fSMaxime Ripard
627995071d3SGwendal Grignou trig = iio_trigger_alloc(idev->dev.parent, "%s-dev%d-%s", idev->name,
62815ea2878SJonathan Cameron iio_device_id(idev), trigger->name);
6290e589d5fSMaxime Ripard if (trig == NULL)
6300e589d5fSMaxime Ripard return NULL;
6310e589d5fSMaxime Ripard
6321e9663c6SLars-Peter Clausen iio_trigger_set_drvdata(trig, idev);
6330e589d5fSMaxime Ripard trig->ops = &at91_adc_trigger_ops;
6340e589d5fSMaxime Ripard
6350e589d5fSMaxime Ripard ret = iio_trigger_register(trig);
636*65f20301SYang Yingliang if (ret) {
637*65f20301SYang Yingliang iio_trigger_free(trig);
6380e589d5fSMaxime Ripard return NULL;
639*65f20301SYang Yingliang }
6400e589d5fSMaxime Ripard
6410e589d5fSMaxime Ripard return trig;
6420e589d5fSMaxime Ripard }
6430e589d5fSMaxime Ripard
at91_adc_trigger_init(struct iio_dev * idev)6440e589d5fSMaxime Ripard static int at91_adc_trigger_init(struct iio_dev *idev)
6450e589d5fSMaxime Ripard {
6460e589d5fSMaxime Ripard struct at91_adc_state *st = iio_priv(idev);
6470e589d5fSMaxime Ripard int i, ret;
6480e589d5fSMaxime Ripard
649a86854d0SKees Cook st->trig = devm_kcalloc(&idev->dev,
65009d4726bSAlexandre Belloni st->caps->trigger_number, sizeof(*st->trig),
6516b3aa313SAxel Lin GFP_KERNEL);
6520e589d5fSMaxime Ripard
6530e589d5fSMaxime Ripard if (st->trig == NULL) {
6540e589d5fSMaxime Ripard ret = -ENOMEM;
6550e589d5fSMaxime Ripard goto error_ret;
6560e589d5fSMaxime Ripard }
6570e589d5fSMaxime Ripard
65809d4726bSAlexandre Belloni for (i = 0; i < st->caps->trigger_number; i++) {
65909d4726bSAlexandre Belloni if (st->caps->triggers[i].is_external && !(st->use_external))
6600e589d5fSMaxime Ripard continue;
6610e589d5fSMaxime Ripard
6620e589d5fSMaxime Ripard st->trig[i] = at91_adc_allocate_trigger(idev,
66309d4726bSAlexandre Belloni st->caps->triggers + i);
6640e589d5fSMaxime Ripard if (st->trig[i] == NULL) {
6650e589d5fSMaxime Ripard dev_err(&idev->dev,
6660e589d5fSMaxime Ripard "Could not allocate trigger %d\n", i);
6670e589d5fSMaxime Ripard ret = -ENOMEM;
6680e589d5fSMaxime Ripard goto error_trigger;
6690e589d5fSMaxime Ripard }
6700e589d5fSMaxime Ripard }
6710e589d5fSMaxime Ripard
6720e589d5fSMaxime Ripard return 0;
6730e589d5fSMaxime Ripard
6740e589d5fSMaxime Ripard error_trigger:
6750e589d5fSMaxime Ripard for (i--; i >= 0; i--) {
6760e589d5fSMaxime Ripard iio_trigger_unregister(st->trig[i]);
6770e589d5fSMaxime Ripard iio_trigger_free(st->trig[i]);
6780e589d5fSMaxime Ripard }
6790e589d5fSMaxime Ripard error_ret:
6800e589d5fSMaxime Ripard return ret;
6810e589d5fSMaxime Ripard }
6820e589d5fSMaxime Ripard
at91_adc_trigger_remove(struct iio_dev * idev)6830e589d5fSMaxime Ripard static void at91_adc_trigger_remove(struct iio_dev *idev)
6840e589d5fSMaxime Ripard {
6850e589d5fSMaxime Ripard struct at91_adc_state *st = iio_priv(idev);
6860e589d5fSMaxime Ripard int i;
6870e589d5fSMaxime Ripard
68809d4726bSAlexandre Belloni for (i = 0; i < st->caps->trigger_number; i++) {
6890e589d5fSMaxime Ripard iio_trigger_unregister(st->trig[i]);
6900e589d5fSMaxime Ripard iio_trigger_free(st->trig[i]);
6910e589d5fSMaxime Ripard }
6920e589d5fSMaxime Ripard }
6930e589d5fSMaxime Ripard
at91_adc_buffer_init(struct iio_dev * idev)6940e589d5fSMaxime Ripard static int at91_adc_buffer_init(struct iio_dev *idev)
6950e589d5fSMaxime Ripard {
69690032e4eSLars-Peter Clausen return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
69790032e4eSLars-Peter Clausen &at91_adc_trigger_handler, NULL);
6980e589d5fSMaxime Ripard }
6990e589d5fSMaxime Ripard
at91_adc_buffer_remove(struct iio_dev * idev)7000e589d5fSMaxime Ripard static void at91_adc_buffer_remove(struct iio_dev *idev)
7010e589d5fSMaxime Ripard {
70290032e4eSLars-Peter Clausen iio_triggered_buffer_cleanup(idev);
7030e589d5fSMaxime Ripard }
7040e589d5fSMaxime Ripard
at91_adc_read_raw(struct iio_dev * idev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)7050e589d5fSMaxime Ripard static int at91_adc_read_raw(struct iio_dev *idev,
7060e589d5fSMaxime Ripard struct iio_chan_spec const *chan,
7070e589d5fSMaxime Ripard int *val, int *val2, long mask)
7080e589d5fSMaxime Ripard {
7090e589d5fSMaxime Ripard struct at91_adc_state *st = iio_priv(idev);
7100e589d5fSMaxime Ripard int ret;
7110e589d5fSMaxime Ripard
7120e589d5fSMaxime Ripard switch (mask) {
7130e589d5fSMaxime Ripard case IIO_CHAN_INFO_RAW:
7140e589d5fSMaxime Ripard mutex_lock(&st->lock);
7150e589d5fSMaxime Ripard
716d4f51956SLudovic Desroches st->chnb = chan->channel;
7170e589d5fSMaxime Ripard at91_adc_writel(st, AT91_ADC_CHER,
7180e589d5fSMaxime Ripard AT91_ADC_CH(chan->channel));
719d4f51956SLudovic Desroches at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel));
7200e589d5fSMaxime Ripard at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
7210e589d5fSMaxime Ripard
7220e589d5fSMaxime Ripard ret = wait_event_interruptible_timeout(st->wq_data_avail,
7230e589d5fSMaxime Ripard st->done,
7240e589d5fSMaxime Ripard msecs_to_jiffies(1000));
7250e589d5fSMaxime Ripard
72609c6bdeeSGeorg Ottinger /* Disable interrupts, regardless if adc conversion was
72709c6bdeeSGeorg Ottinger * successful or not
72809c6bdeeSGeorg Ottinger */
7290e589d5fSMaxime Ripard at91_adc_writel(st, AT91_ADC_CHDR,
7300e589d5fSMaxime Ripard AT91_ADC_CH(chan->channel));
731d4f51956SLudovic Desroches at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel));
7320e589d5fSMaxime Ripard
73309c6bdeeSGeorg Ottinger if (ret > 0) {
73409c6bdeeSGeorg Ottinger /* a valid conversion took place */
73509c6bdeeSGeorg Ottinger *val = st->last_value;
7360e589d5fSMaxime Ripard st->last_value = 0;
7370e589d5fSMaxime Ripard st->done = false;
73809c6bdeeSGeorg Ottinger ret = IIO_VAL_INT;
73909c6bdeeSGeorg Ottinger } else if (ret == 0) {
74009c6bdeeSGeorg Ottinger /* conversion timeout */
74109c6bdeeSGeorg Ottinger dev_err(&idev->dev, "ADC Channel %d timeout.\n",
74209c6bdeeSGeorg Ottinger chan->channel);
74309c6bdeeSGeorg Ottinger ret = -ETIMEDOUT;
74409c6bdeeSGeorg Ottinger }
74509c6bdeeSGeorg Ottinger
7460e589d5fSMaxime Ripard mutex_unlock(&st->lock);
74709c6bdeeSGeorg Ottinger return ret;
7480e589d5fSMaxime Ripard
7490e589d5fSMaxime Ripard case IIO_CHAN_INFO_SCALE:
750c45e561eSLars-Peter Clausen *val = st->vref_mv;
751c45e561eSLars-Peter Clausen *val2 = chan->scan_type.realbits;
752c45e561eSLars-Peter Clausen return IIO_VAL_FRACTIONAL_LOG2;
7530e589d5fSMaxime Ripard default:
7540e589d5fSMaxime Ripard break;
7550e589d5fSMaxime Ripard }
7560e589d5fSMaxime Ripard return -EINVAL;
7570e589d5fSMaxime Ripard }
7580e589d5fSMaxime Ripard
75947be16b6SLudovic Desroches
calc_startup_ticks_9260(u32 startup_time,u32 adc_clk_khz)7602ab5f39bSJan Leupold static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz)
761c4601666SJosh Wu {
762c4601666SJosh Wu /*
763c4601666SJosh Wu * Number of ticks needed to cover the startup time of the ADC
764c4601666SJosh Wu * as defined in the electrical characteristics of the board,
765c4601666SJosh Wu * divided by 8. The formula thus is :
766c4601666SJosh Wu * Startup Time = (ticks + 1) * 8 / ADC Clock
767c4601666SJosh Wu */
768c4601666SJosh Wu return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8;
769c4601666SJosh Wu }
770c4601666SJosh Wu
calc_startup_ticks_9x5(u32 startup_time,u32 adc_clk_khz)7712ab5f39bSJan Leupold static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz)
772c4601666SJosh Wu {
773c4601666SJosh Wu /*
774c4601666SJosh Wu * For sama5d3x and at91sam9x5, the formula changes to:
775c4601666SJosh Wu * Startup Time = <lookup_table_value> / ADC Clock
776c4601666SJosh Wu */
7775b4e17c9SColin Ian King static const int startup_lookup[] = {
778c4601666SJosh Wu 0, 8, 16, 24,
779c4601666SJosh Wu 64, 80, 96, 112,
780c4601666SJosh Wu 512, 576, 640, 704,
781c4601666SJosh Wu 768, 832, 896, 960
782c4601666SJosh Wu };
783c4601666SJosh Wu int i, size = ARRAY_SIZE(startup_lookup);
784c4601666SJosh Wu unsigned int ticks;
785c4601666SJosh Wu
786c4601666SJosh Wu ticks = startup_time * adc_clk_khz / 1000;
787c4601666SJosh Wu for (i = 0; i < size; i++)
788c4601666SJosh Wu if (ticks < startup_lookup[i])
789c4601666SJosh Wu break;
790c4601666SJosh Wu
791c4601666SJosh Wu ticks = i;
792c4601666SJosh Wu if (ticks == size)
793c4601666SJosh Wu /* Reach the end of lookup table */
794c4601666SJosh Wu ticks = size - 1;
795c4601666SJosh Wu
796c4601666SJosh Wu return ticks;
797c4601666SJosh Wu }
798c4601666SJosh Wu
at91_adc_probe_dt_ts(struct device_node * node,struct at91_adc_state * st,struct device * dev)799c8b11de0SJosh Wu static int at91_adc_probe_dt_ts(struct device_node *node,
800c8b11de0SJosh Wu struct at91_adc_state *st, struct device *dev)
801c8b11de0SJosh Wu {
802c8b11de0SJosh Wu int ret;
803c8b11de0SJosh Wu u32 prop;
804c8b11de0SJosh Wu
805c8b11de0SJosh Wu ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop);
806c8b11de0SJosh Wu if (ret) {
807c8b11de0SJosh Wu dev_info(dev, "ADC Touch screen is disabled.\n");
808c8b11de0SJosh Wu return 0;
809c8b11de0SJosh Wu }
810c8b11de0SJosh Wu
811c8b11de0SJosh Wu switch (prop) {
812c8b11de0SJosh Wu case 4:
813c8b11de0SJosh Wu case 5:
814c8b11de0SJosh Wu st->touchscreen_type = prop;
815c8b11de0SJosh Wu break;
816c8b11de0SJosh Wu default:
817c8b11de0SJosh Wu dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop);
818c8b11de0SJosh Wu return -EINVAL;
819c8b11de0SJosh Wu }
820c8b11de0SJosh Wu
82184882b06SAlexandre Belloni if (!st->caps->has_tsmr)
82284882b06SAlexandre Belloni return 0;
823c8b11de0SJosh Wu prop = 0;
824c8b11de0SJosh Wu of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop);
825c8b11de0SJosh Wu st->ts_pressure_threshold = prop;
826c8b11de0SJosh Wu if (st->ts_pressure_threshold) {
827c8b11de0SJosh Wu return 0;
828c8b11de0SJosh Wu } else {
829c8b11de0SJosh Wu dev_err(dev, "Invalid pressure threshold for the touchscreen\n");
830c8b11de0SJosh Wu return -EINVAL;
831c8b11de0SJosh Wu }
832c8b11de0SJosh Wu }
833c8b11de0SJosh Wu
8340e589d5fSMaxime Ripard static const struct iio_info at91_adc_info = {
8350e589d5fSMaxime Ripard .read_raw = &at91_adc_read_raw,
8360e589d5fSMaxime Ripard };
8370e589d5fSMaxime Ripard
838c8b11de0SJosh Wu /* Touchscreen related functions */
atmel_ts_open(struct input_dev * dev)839c8b11de0SJosh Wu static int atmel_ts_open(struct input_dev *dev)
840c8b11de0SJosh Wu {
841c8b11de0SJosh Wu struct at91_adc_state *st = input_get_drvdata(dev);
842c8b11de0SJosh Wu
84384882b06SAlexandre Belloni if (st->caps->has_tsmr)
844c8b11de0SJosh Wu at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
84584882b06SAlexandre Belloni else
84684882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
847c8b11de0SJosh Wu return 0;
848c8b11de0SJosh Wu }
849c8b11de0SJosh Wu
atmel_ts_close(struct input_dev * dev)850c8b11de0SJosh Wu static void atmel_ts_close(struct input_dev *dev)
851c8b11de0SJosh Wu {
852c8b11de0SJosh Wu struct at91_adc_state *st = input_get_drvdata(dev);
853c8b11de0SJosh Wu
85484882b06SAlexandre Belloni if (st->caps->has_tsmr)
855c8b11de0SJosh Wu at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
85684882b06SAlexandre Belloni else
85784882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
858c8b11de0SJosh Wu }
859c8b11de0SJosh Wu
at91_ts_hw_init(struct iio_dev * idev,u32 adc_clk_khz)860044d406aSAlexandru Ardelean static int at91_ts_hw_init(struct iio_dev *idev, u32 adc_clk_khz)
861c8b11de0SJosh Wu {
862044d406aSAlexandru Ardelean struct at91_adc_state *st = iio_priv(idev);
86384882b06SAlexandre Belloni u32 reg = 0;
864ede63aafSNicolas Ferre u32 tssctim = 0;
865c8b11de0SJosh Wu int i = 0;
866c8b11de0SJosh Wu
86784882b06SAlexandre Belloni /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid
86884882b06SAlexandre Belloni * pen detect noise.
86984882b06SAlexandre Belloni * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock
87084882b06SAlexandre Belloni */
87184882b06SAlexandre Belloni st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz /
87284882b06SAlexandre Belloni 1000, 1);
87384882b06SAlexandre Belloni
87484882b06SAlexandre Belloni while (st->ts_pendbc >> ++i)
87584882b06SAlexandre Belloni ; /* Empty! Find the shift offset */
87684882b06SAlexandre Belloni if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1))))
87784882b06SAlexandre Belloni st->ts_pendbc = i;
87884882b06SAlexandre Belloni else
87984882b06SAlexandre Belloni st->ts_pendbc = i - 1;
88084882b06SAlexandre Belloni
88184882b06SAlexandre Belloni if (!st->caps->has_tsmr) {
88284882b06SAlexandre Belloni reg = at91_adc_readl(st, AT91_ADC_MR);
88384882b06SAlexandre Belloni reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET;
88484882b06SAlexandre Belloni
88584882b06SAlexandre Belloni reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
88684882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_MR, reg);
88784882b06SAlexandre Belloni
88884882b06SAlexandre Belloni reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM;
88984882b06SAlexandre Belloni at91_adc_writel(st, AT91_ADC_TSR, reg);
89084882b06SAlexandre Belloni
89184882b06SAlexandre Belloni st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL *
89284882b06SAlexandre Belloni adc_clk_khz / 1000) - 1, 1);
89384882b06SAlexandre Belloni
89484882b06SAlexandre Belloni return 0;
89584882b06SAlexandre Belloni }
89684882b06SAlexandre Belloni
897ede63aafSNicolas Ferre /* Touchscreen Switches Closure time needed for allowing the value to
898ede63aafSNicolas Ferre * stabilize.
899ede63aafSNicolas Ferre * Switch Closure Time = (TSSCTIM * 4) ADCClock periods
900ede63aafSNicolas Ferre */
901ede63aafSNicolas Ferre tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4);
902ede63aafSNicolas Ferre dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n",
903ede63aafSNicolas Ferre adc_clk_khz, tssctim);
904ede63aafSNicolas Ferre
905c8b11de0SJosh Wu if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
906c8b11de0SJosh Wu reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS;
907c8b11de0SJosh Wu else
908c8b11de0SJosh Wu reg = AT91_ADC_TSMR_TSMODE_5WIRE;
909c8b11de0SJosh Wu
910ede63aafSNicolas Ferre reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM;
911c8b11de0SJosh Wu reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average)
912c8b11de0SJosh Wu & AT91_ADC_TSMR_TSAV;
91384882b06SAlexandre Belloni reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC;
914c8b11de0SJosh Wu reg |= AT91_ADC_TSMR_NOTSDMA;
915c8b11de0SJosh Wu reg |= AT91_ADC_TSMR_PENDET_ENA;
91684882b06SAlexandre Belloni reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */
917c8b11de0SJosh Wu
918c8b11de0SJosh Wu at91_adc_writel(st, AT91_ADC_TSMR, reg);
919c8b11de0SJosh Wu
920c8b11de0SJosh Wu /* Change adc internal resistor value for better pen detection,
921c8b11de0SJosh Wu * default value is 100 kOhm.
922c8b11de0SJosh Wu * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm
923c8b11de0SJosh Wu * option only available on ES2 and higher
924c8b11de0SJosh Wu */
925c8b11de0SJosh Wu at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity
926c8b11de0SJosh Wu & AT91_ADC_ACR_PENDETSENS);
927c8b11de0SJosh Wu
92884882b06SAlexandre Belloni /* Sample Period Time = (TRGPER + 1) / ADCClock */
929c8b11de0SJosh Wu st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US *
930c8b11de0SJosh Wu adc_clk_khz / 1000) - 1, 1);
931c8b11de0SJosh Wu
932c8b11de0SJosh Wu return 0;
933c8b11de0SJosh Wu }
934c8b11de0SJosh Wu
at91_ts_register(struct iio_dev * idev,struct platform_device * pdev)935044d406aSAlexandru Ardelean static int at91_ts_register(struct iio_dev *idev,
936c8b11de0SJosh Wu struct platform_device *pdev)
937c8b11de0SJosh Wu {
938044d406aSAlexandru Ardelean struct at91_adc_state *st = iio_priv(idev);
939c8b11de0SJosh Wu struct input_dev *input;
940c8b11de0SJosh Wu int ret;
941c8b11de0SJosh Wu
942c8b11de0SJosh Wu input = input_allocate_device();
943c8b11de0SJosh Wu if (!input) {
944c8b11de0SJosh Wu dev_err(&idev->dev, "Failed to allocate TS device!\n");
945c8b11de0SJosh Wu return -ENOMEM;
946c8b11de0SJosh Wu }
947c8b11de0SJosh Wu
948c8b11de0SJosh Wu input->name = DRIVER_NAME;
949c8b11de0SJosh Wu input->id.bustype = BUS_HOST;
950c8b11de0SJosh Wu input->dev.parent = &pdev->dev;
951c8b11de0SJosh Wu input->open = atmel_ts_open;
952c8b11de0SJosh Wu input->close = atmel_ts_close;
953c8b11de0SJosh Wu
954c8b11de0SJosh Wu __set_bit(EV_ABS, input->evbit);
955c8b11de0SJosh Wu __set_bit(EV_KEY, input->evbit);
956c8b11de0SJosh Wu __set_bit(BTN_TOUCH, input->keybit);
95784882b06SAlexandre Belloni if (st->caps->has_tsmr) {
95884882b06SAlexandre Belloni input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1,
95984882b06SAlexandre Belloni 0, 0);
96084882b06SAlexandre Belloni input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1,
96184882b06SAlexandre Belloni 0, 0);
962c8b11de0SJosh Wu input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0);
96384882b06SAlexandre Belloni } else {
96484882b06SAlexandre Belloni if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) {
96584882b06SAlexandre Belloni dev_err(&pdev->dev,
96684882b06SAlexandre Belloni "This touchscreen controller only support 4 wires\n");
96784882b06SAlexandre Belloni ret = -EINVAL;
96884882b06SAlexandre Belloni goto err;
96984882b06SAlexandre Belloni }
97084882b06SAlexandre Belloni
97184882b06SAlexandre Belloni input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1,
97284882b06SAlexandre Belloni 0, 0);
97384882b06SAlexandre Belloni input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1,
97484882b06SAlexandre Belloni 0, 0);
97584882b06SAlexandre Belloni }
976c8b11de0SJosh Wu
977c8b11de0SJosh Wu st->ts_input = input;
978c8b11de0SJosh Wu input_set_drvdata(input, st);
979c8b11de0SJosh Wu
980c8b11de0SJosh Wu ret = input_register_device(input);
981c8b11de0SJosh Wu if (ret)
98284882b06SAlexandre Belloni goto err;
983c8b11de0SJosh Wu
984c8b11de0SJosh Wu return ret;
98584882b06SAlexandre Belloni
98684882b06SAlexandre Belloni err:
98784882b06SAlexandre Belloni input_free_device(st->ts_input);
98884882b06SAlexandre Belloni return ret;
989c8b11de0SJosh Wu }
990c8b11de0SJosh Wu
at91_ts_unregister(struct at91_adc_state * st)991c8b11de0SJosh Wu static void at91_ts_unregister(struct at91_adc_state *st)
992c8b11de0SJosh Wu {
993c8b11de0SJosh Wu input_unregister_device(st->ts_input);
994c8b11de0SJosh Wu }
995c8b11de0SJosh Wu
at91_adc_probe(struct platform_device * pdev)996fc52692cSGreg Kroah-Hartman static int at91_adc_probe(struct platform_device *pdev)
9970e589d5fSMaxime Ripard {
998db10e201SJosh Wu unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
9999054c15cSAlexandre Belloni struct device_node *node = pdev->dev.of_node;
10000e589d5fSMaxime Ripard int ret;
10010e589d5fSMaxime Ripard struct iio_dev *idev;
10020e589d5fSMaxime Ripard struct at91_adc_state *st;
10039054c15cSAlexandre Belloni u32 reg, prop;
10049054c15cSAlexandre Belloni char *s;
10050e589d5fSMaxime Ripard
1006f8837532SSachin Kamat idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state));
1007f8837532SSachin Kamat if (!idev)
1008f8837532SSachin Kamat return -ENOMEM;
10090e589d5fSMaxime Ripard
10100e589d5fSMaxime Ripard st = iio_priv(idev);
10110e589d5fSMaxime Ripard
10129054c15cSAlexandre Belloni st->caps = of_device_get_match_data(&pdev->dev);
10139054c15cSAlexandre Belloni
10149054c15cSAlexandre Belloni st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
10159054c15cSAlexandre Belloni
10169054c15cSAlexandre Belloni if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
10179054c15cSAlexandre Belloni dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
10189054c15cSAlexandre Belloni return -EINVAL;
10199054c15cSAlexandre Belloni }
10209054c15cSAlexandre Belloni st->channels_mask = prop;
10219054c15cSAlexandre Belloni
10229054c15cSAlexandre Belloni st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode");
10239054c15cSAlexandre Belloni
10249054c15cSAlexandre Belloni if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
10259054c15cSAlexandre Belloni dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
10269054c15cSAlexandre Belloni return -EINVAL;
10279054c15cSAlexandre Belloni }
10289054c15cSAlexandre Belloni st->startup_time = prop;
10299054c15cSAlexandre Belloni
10309054c15cSAlexandre Belloni prop = 0;
10319054c15cSAlexandre Belloni of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop);
10329054c15cSAlexandre Belloni st->sample_hold_time = prop;
10339054c15cSAlexandre Belloni
10349054c15cSAlexandre Belloni if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
10359054c15cSAlexandre Belloni dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
10369054c15cSAlexandre Belloni return -EINVAL;
10379054c15cSAlexandre Belloni }
10389054c15cSAlexandre Belloni st->vref_mv = prop;
10399054c15cSAlexandre Belloni
10409054c15cSAlexandre Belloni st->res = st->caps->high_res_bits;
10419054c15cSAlexandre Belloni if (st->caps->low_res_bits &&
10429054c15cSAlexandre Belloni !of_property_read_string(node, "atmel,adc-use-res", (const char **)&s)
10439054c15cSAlexandre Belloni && !strcmp(s, "lowres"))
10449054c15cSAlexandre Belloni st->res = st->caps->low_res_bits;
10459054c15cSAlexandre Belloni
10469054c15cSAlexandre Belloni dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
10479054c15cSAlexandre Belloni
10489054c15cSAlexandre Belloni st->registers = &st->caps->registers;
10499054c15cSAlexandre Belloni st->num_channels = st->caps->num_channels;
10509054c15cSAlexandre Belloni
10519054c15cSAlexandre Belloni /* Check if touchscreen is supported. */
10529054c15cSAlexandre Belloni if (st->caps->has_ts) {
10539054c15cSAlexandre Belloni ret = at91_adc_probe_dt_ts(node, st, &idev->dev);
1054ead1c9f3SAlexandru Ardelean if (ret)
1055ead1c9f3SAlexandru Ardelean return ret;
10569054c15cSAlexandre Belloni }
10570e589d5fSMaxime Ripard
10580e589d5fSMaxime Ripard platform_set_drvdata(pdev, idev);
10590e589d5fSMaxime Ripard
10600e589d5fSMaxime Ripard idev->name = dev_name(&pdev->dev);
10610e589d5fSMaxime Ripard idev->modes = INDIO_DIRECT_MODE;
10620e589d5fSMaxime Ripard idev->info = &at91_adc_info;
10630e589d5fSMaxime Ripard
10640e589d5fSMaxime Ripard st->irq = platform_get_irq(pdev, 0);
10657c279229SStephen Boyd if (st->irq < 0)
1066f8837532SSachin Kamat return -ENODEV;
10670e589d5fSMaxime Ripard
1068af5c2174SAishwarya Ramakrishnan st->reg_base = devm_platform_ioremap_resource(pdev, 0);
1069c34812e4SVenkat Prashanth B U if (IS_ERR(st->reg_base))
1070f8837532SSachin Kamat return PTR_ERR(st->reg_base);
1071c34812e4SVenkat Prashanth B U
10720e589d5fSMaxime Ripard
10730e589d5fSMaxime Ripard /*
10740e589d5fSMaxime Ripard * Disable all IRQs before setting up the handler
10750e589d5fSMaxime Ripard */
10760e589d5fSMaxime Ripard at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
10770e589d5fSMaxime Ripard at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
107884882b06SAlexandre Belloni
107984882b06SAlexandre Belloni if (st->caps->has_tsmr)
108084882b06SAlexandre Belloni ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0,
108184882b06SAlexandre Belloni pdev->dev.driver->name, idev);
108284882b06SAlexandre Belloni else
108384882b06SAlexandre Belloni ret = request_irq(st->irq, at91_adc_rl_interrupt, 0,
108484882b06SAlexandre Belloni pdev->dev.driver->name, idev);
10850e589d5fSMaxime Ripard if (ret) {
10860e589d5fSMaxime Ripard dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
1087f8837532SSachin Kamat return ret;
10880e589d5fSMaxime Ripard }
10890e589d5fSMaxime Ripard
1090390d75c1SJulia Lawall st->clk = devm_clk_get(&pdev->dev, "adc_clk");
10910e589d5fSMaxime Ripard if (IS_ERR(st->clk)) {
10920e589d5fSMaxime Ripard dev_err(&pdev->dev, "Failed to get the clock.\n");
10930e589d5fSMaxime Ripard ret = PTR_ERR(st->clk);
10940e589d5fSMaxime Ripard goto error_free_irq;
10950e589d5fSMaxime Ripard }
10960e589d5fSMaxime Ripard
109700062a9cSJulia Lawall ret = clk_prepare_enable(st->clk);
10980e589d5fSMaxime Ripard if (ret) {
109900062a9cSJulia Lawall dev_err(&pdev->dev,
110000062a9cSJulia Lawall "Could not prepare or enable the clock.\n");
1101390d75c1SJulia Lawall goto error_free_irq;
11020e589d5fSMaxime Ripard }
11030e589d5fSMaxime Ripard
1104390d75c1SJulia Lawall st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
11050e589d5fSMaxime Ripard if (IS_ERR(st->adc_clk)) {
11060e589d5fSMaxime Ripard dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
1107f755bbbfSJulia Lawall ret = PTR_ERR(st->adc_clk);
11080e589d5fSMaxime Ripard goto error_disable_clk;
11090e589d5fSMaxime Ripard }
11100e589d5fSMaxime Ripard
111100062a9cSJulia Lawall ret = clk_prepare_enable(st->adc_clk);
11120e589d5fSMaxime Ripard if (ret) {
111300062a9cSJulia Lawall dev_err(&pdev->dev,
111400062a9cSJulia Lawall "Could not prepare or enable the ADC clock.\n");
1115390d75c1SJulia Lawall goto error_disable_clk;
11160e589d5fSMaxime Ripard }
11170e589d5fSMaxime Ripard
11180e589d5fSMaxime Ripard /*
11190e589d5fSMaxime Ripard * Prescaler rate computation using the formula from the Atmel's
11200e589d5fSMaxime Ripard * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
11210e589d5fSMaxime Ripard * specified by the electrical characteristics of the board.
11220e589d5fSMaxime Ripard */
11230e589d5fSMaxime Ripard mstrclk = clk_get_rate(st->clk);
11240e589d5fSMaxime Ripard adc_clk = clk_get_rate(st->adc_clk);
1125db10e201SJosh Wu adc_clk_khz = adc_clk / 1000;
1126c8b11de0SJosh Wu
1127c8b11de0SJosh Wu dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n",
1128c8b11de0SJosh Wu mstrclk, adc_clk);
1129c8b11de0SJosh Wu
11300e589d5fSMaxime Ripard prsc = (mstrclk / (2 * adc_clk)) - 1;
11310e589d5fSMaxime Ripard
11320e589d5fSMaxime Ripard if (!st->startup_time) {
11330e589d5fSMaxime Ripard dev_err(&pdev->dev, "No startup time available.\n");
11340e589d5fSMaxime Ripard ret = -EINVAL;
11350e589d5fSMaxime Ripard goto error_disable_adc_clk;
11360e589d5fSMaxime Ripard }
1137c4601666SJosh Wu ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz);
11380e589d5fSMaxime Ripard
11390e589d5fSMaxime Ripard /*
1140beca9e76SJean-Christophe PLAGNIOL-VILLARD * a minimal Sample and Hold Time is necessary for the ADC to guarantee
1141beca9e76SJean-Christophe PLAGNIOL-VILLARD * the best converted final value between two channels selection
1142beca9e76SJean-Christophe PLAGNIOL-VILLARD * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
1143beca9e76SJean-Christophe PLAGNIOL-VILLARD */
11448f32b6baSAlexandre Belloni if (st->sample_hold_time > 0)
11458f32b6baSAlexandre Belloni shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000)
11468f32b6baSAlexandre Belloni - 1, 1);
11478f32b6baSAlexandre Belloni else
11488f32b6baSAlexandre Belloni shtim = 0;
1149beca9e76SJean-Christophe PLAGNIOL-VILLARD
11509120c0beSJosh Wu reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
11519120c0beSJosh Wu reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
11525eb39ef8SAlexandre Belloni if (st->res == st->caps->low_res_bits)
1153e748783cSJean-Christophe PLAGNIOL-VILLARD reg |= AT91_ADC_LOWRES;
1154e748783cSJean-Christophe PLAGNIOL-VILLARD if (st->sleep_mode)
1155e748783cSJean-Christophe PLAGNIOL-VILLARD reg |= AT91_ADC_SLEEP;
1156beca9e76SJean-Christophe PLAGNIOL-VILLARD reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM;
1157e748783cSJean-Christophe PLAGNIOL-VILLARD at91_adc_writel(st, AT91_ADC_MR, reg);
11580e589d5fSMaxime Ripard
11590e589d5fSMaxime Ripard /* Setup the ADC channels available on the board */
11600e589d5fSMaxime Ripard ret = at91_adc_channel_init(idev);
11610e589d5fSMaxime Ripard if (ret < 0) {
11620e589d5fSMaxime Ripard dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
11630e589d5fSMaxime Ripard goto error_disable_adc_clk;
11640e589d5fSMaxime Ripard }
11650e589d5fSMaxime Ripard
11660e589d5fSMaxime Ripard init_waitqueue_head(&st->wq_data_avail);
11670e589d5fSMaxime Ripard mutex_init(&st->lock);
11680e589d5fSMaxime Ripard
1169c8b11de0SJosh Wu /*
1170c8b11de0SJosh Wu * Since touch screen will set trigger register as period trigger. So
1171c8b11de0SJosh Wu * when touch screen is enabled, then we have to disable hardware
1172c8b11de0SJosh Wu * trigger for classic adc.
1173c8b11de0SJosh Wu */
1174c8b11de0SJosh Wu if (!st->touchscreen_type) {
11750e589d5fSMaxime Ripard ret = at91_adc_buffer_init(idev);
11760e589d5fSMaxime Ripard if (ret < 0) {
11770e589d5fSMaxime Ripard dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
11780e589d5fSMaxime Ripard goto error_disable_adc_clk;
11790e589d5fSMaxime Ripard }
11800e589d5fSMaxime Ripard
11810e589d5fSMaxime Ripard ret = at91_adc_trigger_init(idev);
11820e589d5fSMaxime Ripard if (ret < 0) {
11830e589d5fSMaxime Ripard dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
1184c8b11de0SJosh Wu at91_adc_buffer_remove(idev);
1185c8b11de0SJosh Wu goto error_disable_adc_clk;
1186c8b11de0SJosh Wu }
1187c8b11de0SJosh Wu } else {
1188044d406aSAlexandru Ardelean ret = at91_ts_register(idev, pdev);
1189c8b11de0SJosh Wu if (ret)
1190c8b11de0SJosh Wu goto error_disable_adc_clk;
1191c8b11de0SJosh Wu
1192044d406aSAlexandru Ardelean at91_ts_hw_init(idev, adc_clk_khz);
11930e589d5fSMaxime Ripard }
11940e589d5fSMaxime Ripard
11950e589d5fSMaxime Ripard ret = iio_device_register(idev);
11960e589d5fSMaxime Ripard if (ret < 0) {
11970e589d5fSMaxime Ripard dev_err(&pdev->dev, "Couldn't register the device.\n");
1198c8b11de0SJosh Wu goto error_iio_device_register;
11990e589d5fSMaxime Ripard }
12000e589d5fSMaxime Ripard
12010e589d5fSMaxime Ripard return 0;
12020e589d5fSMaxime Ripard
1203c8b11de0SJosh Wu error_iio_device_register:
1204c8b11de0SJosh Wu if (!st->touchscreen_type) {
12050e589d5fSMaxime Ripard at91_adc_trigger_remove(idev);
12060e589d5fSMaxime Ripard at91_adc_buffer_remove(idev);
1207c8b11de0SJosh Wu } else {
1208c8b11de0SJosh Wu at91_ts_unregister(st);
1209c8b11de0SJosh Wu }
12100e589d5fSMaxime Ripard error_disable_adc_clk:
121100062a9cSJulia Lawall clk_disable_unprepare(st->adc_clk);
12120e589d5fSMaxime Ripard error_disable_clk:
121300062a9cSJulia Lawall clk_disable_unprepare(st->clk);
12140e589d5fSMaxime Ripard error_free_irq:
12150e589d5fSMaxime Ripard free_irq(st->irq, idev);
12160e589d5fSMaxime Ripard return ret;
12170e589d5fSMaxime Ripard }
12180e589d5fSMaxime Ripard
at91_adc_remove(struct platform_device * pdev)1219fc52692cSGreg Kroah-Hartman static int at91_adc_remove(struct platform_device *pdev)
12200e589d5fSMaxime Ripard {
12210e589d5fSMaxime Ripard struct iio_dev *idev = platform_get_drvdata(pdev);
12220e589d5fSMaxime Ripard struct at91_adc_state *st = iio_priv(idev);
12230e589d5fSMaxime Ripard
12240e589d5fSMaxime Ripard iio_device_unregister(idev);
1225c8b11de0SJosh Wu if (!st->touchscreen_type) {
12260e589d5fSMaxime Ripard at91_adc_trigger_remove(idev);
12270e589d5fSMaxime Ripard at91_adc_buffer_remove(idev);
1228c8b11de0SJosh Wu } else {
1229c8b11de0SJosh Wu at91_ts_unregister(st);
1230c8b11de0SJosh Wu }
12310e589d5fSMaxime Ripard clk_disable_unprepare(st->adc_clk);
123200062a9cSJulia Lawall clk_disable_unprepare(st->clk);
12330e589d5fSMaxime Ripard free_irq(st->irq, idev);
12340e589d5fSMaxime Ripard
12350e589d5fSMaxime Ripard return 0;
12360e589d5fSMaxime Ripard }
12370e589d5fSMaxime Ripard
at91_adc_suspend(struct device * dev)1238bc3ae982SWenyou Yang static int at91_adc_suspend(struct device *dev)
1239bc3ae982SWenyou Yang {
1240e3faedf7SKefeng Wang struct iio_dev *idev = dev_get_drvdata(dev);
1241bc3ae982SWenyou Yang struct at91_adc_state *st = iio_priv(idev);
1242bc3ae982SWenyou Yang
1243bc3ae982SWenyou Yang pinctrl_pm_select_sleep_state(dev);
1244bc3ae982SWenyou Yang clk_disable_unprepare(st->clk);
1245bc3ae982SWenyou Yang
1246bc3ae982SWenyou Yang return 0;
1247bc3ae982SWenyou Yang }
1248bc3ae982SWenyou Yang
at91_adc_resume(struct device * dev)1249bc3ae982SWenyou Yang static int at91_adc_resume(struct device *dev)
1250bc3ae982SWenyou Yang {
1251e3faedf7SKefeng Wang struct iio_dev *idev = dev_get_drvdata(dev);
1252bc3ae982SWenyou Yang struct at91_adc_state *st = iio_priv(idev);
1253bc3ae982SWenyou Yang
1254bc3ae982SWenyou Yang clk_prepare_enable(st->clk);
1255bc3ae982SWenyou Yang pinctrl_pm_select_default_state(dev);
1256bc3ae982SWenyou Yang
1257bc3ae982SWenyou Yang return 0;
1258bc3ae982SWenyou Yang }
1259bc3ae982SWenyou Yang
126019e2ed80SJonathan Cameron static DEFINE_SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend,
126119e2ed80SJonathan Cameron at91_adc_resume);
1262bc3ae982SWenyou Yang
126309d4726bSAlexandre Belloni static const struct at91_adc_trigger at91sam9260_triggers[] = {
126409d4726bSAlexandre Belloni { .name = "timer-counter-0", .value = 0x1 },
126509d4726bSAlexandre Belloni { .name = "timer-counter-1", .value = 0x3 },
126609d4726bSAlexandre Belloni { .name = "timer-counter-2", .value = 0x5 },
126709d4726bSAlexandre Belloni { .name = "external", .value = 0xd, .is_external = true },
126809d4726bSAlexandre Belloni };
126909d4726bSAlexandre Belloni
1270e1811f97SJosh Wu static struct at91_adc_caps at91sam9260_caps = {
1271c4601666SJosh Wu .calc_startup_ticks = calc_startup_ticks_9260,
12722b6d598bSJosh Wu .num_channels = 4,
12735eb39ef8SAlexandre Belloni .low_res_bits = 8,
12745eb39ef8SAlexandre Belloni .high_res_bits = 10,
1275e1811f97SJosh Wu .registers = {
1276e1811f97SJosh Wu .channel_base = AT91_ADC_CHR(0),
1277e1811f97SJosh Wu .drdy_mask = AT91_ADC_DRDY,
1278e1811f97SJosh Wu .status_register = AT91_ADC_SR,
1279e1811f97SJosh Wu .trigger_register = AT91_ADC_TRGR_9260,
12809120c0beSJosh Wu .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
12819120c0beSJosh Wu .mr_startup_mask = AT91_ADC_STARTUP_9260,
1282e1811f97SJosh Wu },
128309d4726bSAlexandre Belloni .triggers = at91sam9260_triggers,
128409d4726bSAlexandre Belloni .trigger_number = ARRAY_SIZE(at91sam9260_triggers),
128509d4726bSAlexandre Belloni };
128609d4726bSAlexandre Belloni
128709d4726bSAlexandre Belloni static const struct at91_adc_trigger at91sam9x5_triggers[] = {
128809d4726bSAlexandre Belloni { .name = "external-rising", .value = 0x1, .is_external = true },
128909d4726bSAlexandre Belloni { .name = "external-falling", .value = 0x2, .is_external = true },
129009d4726bSAlexandre Belloni { .name = "external-any", .value = 0x3, .is_external = true },
129109d4726bSAlexandre Belloni { .name = "continuous", .value = 0x6 },
1292e1811f97SJosh Wu };
1293e1811f97SJosh Wu
129465b1fdbaSAlexandre Belloni static struct at91_adc_caps at91sam9rl_caps = {
129565b1fdbaSAlexandre Belloni .has_ts = true,
129665b1fdbaSAlexandre Belloni .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
129765b1fdbaSAlexandre Belloni .num_channels = 6,
12985eb39ef8SAlexandre Belloni .low_res_bits = 8,
12995eb39ef8SAlexandre Belloni .high_res_bits = 10,
130065b1fdbaSAlexandre Belloni .registers = {
130165b1fdbaSAlexandre Belloni .channel_base = AT91_ADC_CHR(0),
130265b1fdbaSAlexandre Belloni .drdy_mask = AT91_ADC_DRDY,
130365b1fdbaSAlexandre Belloni .status_register = AT91_ADC_SR,
130465b1fdbaSAlexandre Belloni .trigger_register = AT91_ADC_TRGR_9G45,
130565b1fdbaSAlexandre Belloni .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
130665b1fdbaSAlexandre Belloni .mr_startup_mask = AT91_ADC_STARTUP_9G45,
130765b1fdbaSAlexandre Belloni },
130809d4726bSAlexandre Belloni .triggers = at91sam9x5_triggers,
130909d4726bSAlexandre Belloni .trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
131065b1fdbaSAlexandre Belloni };
131165b1fdbaSAlexandre Belloni
1312e1811f97SJosh Wu static struct at91_adc_caps at91sam9g45_caps = {
1313c8b11de0SJosh Wu .has_ts = true,
1314c4601666SJosh Wu .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
13152b6d598bSJosh Wu .num_channels = 8,
13165eb39ef8SAlexandre Belloni .low_res_bits = 8,
13175eb39ef8SAlexandre Belloni .high_res_bits = 10,
1318e1811f97SJosh Wu .registers = {
1319e1811f97SJosh Wu .channel_base = AT91_ADC_CHR(0),
1320e1811f97SJosh Wu .drdy_mask = AT91_ADC_DRDY,
1321e1811f97SJosh Wu .status_register = AT91_ADC_SR,
1322e1811f97SJosh Wu .trigger_register = AT91_ADC_TRGR_9G45,
13239120c0beSJosh Wu .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
13249120c0beSJosh Wu .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1325e1811f97SJosh Wu },
132609d4726bSAlexandre Belloni .triggers = at91sam9x5_triggers,
132709d4726bSAlexandre Belloni .trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
1328e1811f97SJosh Wu };
1329e1811f97SJosh Wu
1330e1811f97SJosh Wu static struct at91_adc_caps at91sam9x5_caps = {
1331c8b11de0SJosh Wu .has_ts = true,
1332c8b11de0SJosh Wu .has_tsmr = true,
1333c8b11de0SJosh Wu .ts_filter_average = 3,
1334c8b11de0SJosh Wu .ts_pen_detect_sensitivity = 2,
1335c4601666SJosh Wu .calc_startup_ticks = calc_startup_ticks_9x5,
13362b6d598bSJosh Wu .num_channels = 12,
13375eb39ef8SAlexandre Belloni .low_res_bits = 8,
13385eb39ef8SAlexandre Belloni .high_res_bits = 10,
1339e1811f97SJosh Wu .registers = {
1340e1811f97SJosh Wu .channel_base = AT91_ADC_CDR0_9X5,
1341e1811f97SJosh Wu .drdy_mask = AT91_ADC_SR_DRDY_9X5,
1342e1811f97SJosh Wu .status_register = AT91_ADC_SR_9X5,
1343e1811f97SJosh Wu .trigger_register = AT91_ADC_TRGR_9X5,
13449120c0beSJosh Wu /* prescal mask is same as 9G45 */
13459120c0beSJosh Wu .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
13469120c0beSJosh Wu .mr_startup_mask = AT91_ADC_STARTUP_9X5,
1347e1811f97SJosh Wu },
134809d4726bSAlexandre Belloni .triggers = at91sam9x5_triggers,
134909d4726bSAlexandre Belloni .trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
1350e1811f97SJosh Wu };
1351e1811f97SJosh Wu
13525eb39ef8SAlexandre Belloni static struct at91_adc_caps sama5d3_caps = {
13535eb39ef8SAlexandre Belloni .has_ts = true,
13545eb39ef8SAlexandre Belloni .has_tsmr = true,
13555eb39ef8SAlexandre Belloni .ts_filter_average = 3,
13565eb39ef8SAlexandre Belloni .ts_pen_detect_sensitivity = 2,
13575eb39ef8SAlexandre Belloni .calc_startup_ticks = calc_startup_ticks_9x5,
13585eb39ef8SAlexandre Belloni .num_channels = 12,
13595eb39ef8SAlexandre Belloni .low_res_bits = 0,
13605eb39ef8SAlexandre Belloni .high_res_bits = 12,
13615eb39ef8SAlexandre Belloni .registers = {
13625eb39ef8SAlexandre Belloni .channel_base = AT91_ADC_CDR0_9X5,
13635eb39ef8SAlexandre Belloni .drdy_mask = AT91_ADC_SR_DRDY_9X5,
13645eb39ef8SAlexandre Belloni .status_register = AT91_ADC_SR_9X5,
13655eb39ef8SAlexandre Belloni .trigger_register = AT91_ADC_TRGR_9X5,
13665eb39ef8SAlexandre Belloni .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
13675eb39ef8SAlexandre Belloni .mr_startup_mask = AT91_ADC_STARTUP_9X5,
13685eb39ef8SAlexandre Belloni },
136909d4726bSAlexandre Belloni .triggers = at91sam9x5_triggers,
137009d4726bSAlexandre Belloni .trigger_number = ARRAY_SIZE(at91sam9x5_triggers),
13715eb39ef8SAlexandre Belloni };
13725eb39ef8SAlexandre Belloni
1373e364185fSMaxime Ripard static const struct of_device_id at91_adc_dt_ids[] = {
1374e1811f97SJosh Wu { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps },
137565b1fdbaSAlexandre Belloni { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps },
1376e1811f97SJosh Wu { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps },
1377e1811f97SJosh Wu { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps },
13785eb39ef8SAlexandre Belloni { .compatible = "atmel,sama5d3-adc", .data = &sama5d3_caps },
1379e364185fSMaxime Ripard {},
1380e364185fSMaxime Ripard };
1381e364185fSMaxime Ripard MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
1382467a44b0SAlexandre Belloni
13830e589d5fSMaxime Ripard static struct platform_driver at91_adc_driver = {
13840e589d5fSMaxime Ripard .probe = at91_adc_probe,
1385fc52692cSGreg Kroah-Hartman .remove = at91_adc_remove,
13860e589d5fSMaxime Ripard .driver = {
1387c8b11de0SJosh Wu .name = DRIVER_NAME,
1388f091d7c5SAlexandru Ardelean .of_match_table = at91_adc_dt_ids,
138919e2ed80SJonathan Cameron .pm = pm_sleep_ptr(&at91_adc_pm_ops),
13900e589d5fSMaxime Ripard },
13910e589d5fSMaxime Ripard };
13920e589d5fSMaxime Ripard
13930e589d5fSMaxime Ripard module_platform_driver(at91_adc_driver);
13940e589d5fSMaxime Ripard
13950e589d5fSMaxime Ripard MODULE_LICENSE("GPL");
13960e589d5fSMaxime Ripard MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
13970e589d5fSMaxime Ripard MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1398