1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Atmel ADC driver for SAMA5D2 devices and compatible. 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dmaengine.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/sched.h> 20 #include <linux/wait.h> 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/buffer.h> 24 #include <linux/iio/trigger.h> 25 #include <linux/iio/trigger_consumer.h> 26 #include <linux/iio/triggered_buffer.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/regulator/consumer.h> 29 30 /* Control Register */ 31 #define AT91_SAMA5D2_CR 0x00 32 /* Software Reset */ 33 #define AT91_SAMA5D2_CR_SWRST BIT(0) 34 /* Start Conversion */ 35 #define AT91_SAMA5D2_CR_START BIT(1) 36 /* Touchscreen Calibration */ 37 #define AT91_SAMA5D2_CR_TSCALIB BIT(2) 38 /* Comparison Restart */ 39 #define AT91_SAMA5D2_CR_CMPRST BIT(4) 40 41 /* Mode Register */ 42 #define AT91_SAMA5D2_MR 0x04 43 /* Trigger Selection */ 44 #define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1) 45 /* ADTRG */ 46 #define AT91_SAMA5D2_MR_TRGSEL_TRIG0 0 47 /* TIOA0 */ 48 #define AT91_SAMA5D2_MR_TRGSEL_TRIG1 1 49 /* TIOA1 */ 50 #define AT91_SAMA5D2_MR_TRGSEL_TRIG2 2 51 /* TIOA2 */ 52 #define AT91_SAMA5D2_MR_TRGSEL_TRIG3 3 53 /* PWM event line 0 */ 54 #define AT91_SAMA5D2_MR_TRGSEL_TRIG4 4 55 /* PWM event line 1 */ 56 #define AT91_SAMA5D2_MR_TRGSEL_TRIG5 5 57 /* TIOA3 */ 58 #define AT91_SAMA5D2_MR_TRGSEL_TRIG6 6 59 /* RTCOUT0 */ 60 #define AT91_SAMA5D2_MR_TRGSEL_TRIG7 7 61 /* Sleep Mode */ 62 #define AT91_SAMA5D2_MR_SLEEP BIT(5) 63 /* Fast Wake Up */ 64 #define AT91_SAMA5D2_MR_FWUP BIT(6) 65 /* Prescaler Rate Selection */ 66 #define AT91_SAMA5D2_MR_PRESCAL(v) ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET) 67 #define AT91_SAMA5D2_MR_PRESCAL_OFFSET 8 68 #define AT91_SAMA5D2_MR_PRESCAL_MAX 0xff 69 #define AT91_SAMA5D2_MR_PRESCAL_MASK GENMASK(15, 8) 70 /* Startup Time */ 71 #define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16) 72 #define AT91_SAMA5D2_MR_STARTUP_MASK GENMASK(19, 16) 73 /* Analog Change */ 74 #define AT91_SAMA5D2_MR_ANACH BIT(23) 75 /* Tracking Time */ 76 #define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24) 77 #define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xff 78 /* Transfer Time */ 79 #define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28) 80 #define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3 81 /* Use Sequence Enable */ 82 #define AT91_SAMA5D2_MR_USEQ BIT(31) 83 84 /* Channel Sequence Register 1 */ 85 #define AT91_SAMA5D2_SEQR1 0x08 86 /* Channel Sequence Register 2 */ 87 #define AT91_SAMA5D2_SEQR2 0x0c 88 /* Channel Enable Register */ 89 #define AT91_SAMA5D2_CHER 0x10 90 /* Channel Disable Register */ 91 #define AT91_SAMA5D2_CHDR 0x14 92 /* Channel Status Register */ 93 #define AT91_SAMA5D2_CHSR 0x18 94 /* Last Converted Data Register */ 95 #define AT91_SAMA5D2_LCDR 0x20 96 /* Interrupt Enable Register */ 97 #define AT91_SAMA5D2_IER 0x24 98 /* Interrupt Enable Register - TS X measurement ready */ 99 #define AT91_SAMA5D2_IER_XRDY BIT(20) 100 /* Interrupt Enable Register - TS Y measurement ready */ 101 #define AT91_SAMA5D2_IER_YRDY BIT(21) 102 /* Interrupt Enable Register - TS pressure measurement ready */ 103 #define AT91_SAMA5D2_IER_PRDY BIT(22) 104 /* Interrupt Enable Register - Data ready */ 105 #define AT91_SAMA5D2_IER_DRDY BIT(24) 106 /* Interrupt Enable Register - general overrun error */ 107 #define AT91_SAMA5D2_IER_GOVRE BIT(25) 108 /* Interrupt Enable Register - Pen detect */ 109 #define AT91_SAMA5D2_IER_PEN BIT(29) 110 /* Interrupt Enable Register - No pen detect */ 111 #define AT91_SAMA5D2_IER_NOPEN BIT(30) 112 /* Interrupt Disable Register */ 113 #define AT91_SAMA5D2_IDR 0x28 114 /* Interrupt Mask Register */ 115 #define AT91_SAMA5D2_IMR 0x2c 116 /* Interrupt Status Register */ 117 #define AT91_SAMA5D2_ISR 0x30 118 /* Interrupt Status Register - Pen touching sense status */ 119 #define AT91_SAMA5D2_ISR_PENS BIT(31) 120 /* Last Channel Trigger Mode Register */ 121 #define AT91_SAMA5D2_LCTMR 0x34 122 /* Last Channel Compare Window Register */ 123 #define AT91_SAMA5D2_LCCWR 0x38 124 /* Overrun Status Register */ 125 #define AT91_SAMA5D2_OVER 0x3c 126 /* Extended Mode Register */ 127 #define AT91_SAMA5D2_EMR 0x40 128 /* Extended Mode Register - Oversampling rate */ 129 #define AT91_SAMA5D2_EMR_OSR(V) ((V) << 16) 130 #define AT91_SAMA5D2_EMR_OSR_MASK GENMASK(17, 16) 131 #define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0 132 #define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1 133 #define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2 134 135 /* Extended Mode Register - Averaging on single trigger event */ 136 #define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20) 137 /* Compare Window Register */ 138 #define AT91_SAMA5D2_CWR 0x44 139 /* Channel Gain Register */ 140 #define AT91_SAMA5D2_CGR 0x48 141 142 /* Channel Offset Register */ 143 #define AT91_SAMA5D2_COR 0x4c 144 #define AT91_SAMA5D2_COR_DIFF_OFFSET 16 145 146 /* Channel Data Register 0 */ 147 #define AT91_SAMA5D2_CDR0 0x50 148 /* Analog Control Register */ 149 #define AT91_SAMA5D2_ACR 0x94 150 /* Analog Control Register - Pen detect sensitivity mask */ 151 #define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0) 152 153 /* Touchscreen Mode Register */ 154 #define AT91_SAMA5D2_TSMR 0xb0 155 /* Touchscreen Mode Register - No touch mode */ 156 #define AT91_SAMA5D2_TSMR_TSMODE_NONE 0 157 /* Touchscreen Mode Register - 4 wire screen, no pressure measurement */ 158 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_NO_PRESS 1 159 /* Touchscreen Mode Register - 4 wire screen, pressure measurement */ 160 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS 2 161 /* Touchscreen Mode Register - 5 wire screen */ 162 #define AT91_SAMA5D2_TSMR_TSMODE_5WIRE 3 163 /* Touchscreen Mode Register - Average samples mask */ 164 #define AT91_SAMA5D2_TSMR_TSAV_MASK GENMASK(5, 4) 165 /* Touchscreen Mode Register - Average samples */ 166 #define AT91_SAMA5D2_TSMR_TSAV(x) ((x) << 4) 167 /* Touchscreen Mode Register - Touch/trigger frequency ratio mask */ 168 #define AT91_SAMA5D2_TSMR_TSFREQ_MASK GENMASK(11, 8) 169 /* Touchscreen Mode Register - Touch/trigger frequency ratio */ 170 #define AT91_SAMA5D2_TSMR_TSFREQ(x) ((x) << 8) 171 /* Touchscreen Mode Register - Pen Debounce Time mask */ 172 #define AT91_SAMA5D2_TSMR_PENDBC_MASK GENMASK(31, 28) 173 /* Touchscreen Mode Register - Pen Debounce Time */ 174 #define AT91_SAMA5D2_TSMR_PENDBC(x) ((x) << 28) 175 /* Touchscreen Mode Register - No DMA for touch measurements */ 176 #define AT91_SAMA5D2_TSMR_NOTSDMA BIT(22) 177 /* Touchscreen Mode Register - Disable pen detection */ 178 #define AT91_SAMA5D2_TSMR_PENDET_DIS (0 << 24) 179 /* Touchscreen Mode Register - Enable pen detection */ 180 #define AT91_SAMA5D2_TSMR_PENDET_ENA BIT(24) 181 182 /* Touchscreen X Position Register */ 183 #define AT91_SAMA5D2_XPOSR 0xb4 184 /* Touchscreen Y Position Register */ 185 #define AT91_SAMA5D2_YPOSR 0xb8 186 /* Touchscreen Pressure Register */ 187 #define AT91_SAMA5D2_PRESSR 0xbc 188 /* Trigger Register */ 189 #define AT91_SAMA5D2_TRGR 0xc0 190 /* Mask for TRGMOD field of TRGR register */ 191 #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0) 192 /* No trigger, only software trigger can start conversions */ 193 #define AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER 0 194 /* Trigger Mode external trigger rising edge */ 195 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE 1 196 /* Trigger Mode external trigger falling edge */ 197 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL 2 198 /* Trigger Mode external trigger any edge */ 199 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY 3 200 /* Trigger Mode internal periodic */ 201 #define AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC 5 202 /* Trigger Mode - trigger period mask */ 203 #define AT91_SAMA5D2_TRGR_TRGPER_MASK GENMASK(31, 16) 204 /* Trigger Mode - trigger period */ 205 #define AT91_SAMA5D2_TRGR_TRGPER(x) ((x) << 16) 206 207 /* Correction Select Register */ 208 #define AT91_SAMA5D2_COSR 0xd0 209 /* Correction Value Register */ 210 #define AT91_SAMA5D2_CVR 0xd4 211 /* Channel Error Correction Register */ 212 #define AT91_SAMA5D2_CECR 0xd8 213 /* Write Protection Mode Register */ 214 #define AT91_SAMA5D2_WPMR 0xe4 215 /* Write Protection Status Register */ 216 #define AT91_SAMA5D2_WPSR 0xe8 217 /* Version Register */ 218 #define AT91_SAMA5D2_VERSION 0xfc 219 220 #define AT91_SAMA5D2_HW_TRIG_CNT 3 221 #define AT91_SAMA5D2_SINGLE_CHAN_CNT 12 222 #define AT91_SAMA5D2_DIFF_CHAN_CNT 6 223 224 #define AT91_SAMA5D2_TIMESTAMP_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \ 225 AT91_SAMA5D2_DIFF_CHAN_CNT + 1) 226 227 #define AT91_SAMA5D2_TOUCH_X_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \ 228 AT91_SAMA5D2_DIFF_CHAN_CNT * 2) 229 #define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX (AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1) 230 #define AT91_SAMA5D2_TOUCH_P_CHAN_IDX (AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1) 231 #define AT91_SAMA5D2_MAX_CHAN_IDX AT91_SAMA5D2_TOUCH_P_CHAN_IDX 232 233 #define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */ 234 #define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US 200 235 236 #define AT91_SAMA5D2_XYZ_MASK GENMASK(11, 0) 237 238 #define AT91_SAMA5D2_MAX_POS_BITS 12 239 240 /* 241 * Maximum number of bytes to hold conversion from all channels 242 * without the timestamp. 243 */ 244 #define AT91_BUFFER_MAX_CONVERSION_BYTES ((AT91_SAMA5D2_SINGLE_CHAN_CNT + \ 245 AT91_SAMA5D2_DIFF_CHAN_CNT) * 2) 246 247 /* This total must also include the timestamp */ 248 #define AT91_BUFFER_MAX_BYTES (AT91_BUFFER_MAX_CONVERSION_BYTES + 8) 249 250 #define AT91_BUFFER_MAX_HWORDS (AT91_BUFFER_MAX_BYTES / 2) 251 252 #define AT91_HWFIFO_MAX_SIZE_STR "128" 253 #define AT91_HWFIFO_MAX_SIZE 128 254 255 /* Possible values for oversampling ratio */ 256 #define AT91_OSR_1SAMPLES 1 257 #define AT91_OSR_4SAMPLES 4 258 #define AT91_OSR_16SAMPLES 16 259 260 #define AT91_SAMA5D2_CHAN_SINGLE(num, addr) \ 261 { \ 262 .type = IIO_VOLTAGE, \ 263 .channel = num, \ 264 .address = addr, \ 265 .scan_index = num, \ 266 .scan_type = { \ 267 .sign = 'u', \ 268 .realbits = 14, \ 269 .storagebits = 16, \ 270 }, \ 271 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 272 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 273 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 274 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 275 .datasheet_name = "CH"#num, \ 276 .indexed = 1, \ 277 } 278 279 #define AT91_SAMA5D2_CHAN_DIFF(num, num2, addr) \ 280 { \ 281 .type = IIO_VOLTAGE, \ 282 .differential = 1, \ 283 .channel = num, \ 284 .channel2 = num2, \ 285 .address = addr, \ 286 .scan_index = num + AT91_SAMA5D2_SINGLE_CHAN_CNT, \ 287 .scan_type = { \ 288 .sign = 's', \ 289 .realbits = 14, \ 290 .storagebits = 16, \ 291 }, \ 292 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 293 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 294 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 295 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 296 .datasheet_name = "CH"#num"-CH"#num2, \ 297 .indexed = 1, \ 298 } 299 300 #define AT91_SAMA5D2_CHAN_TOUCH(num, name, mod) \ 301 { \ 302 .type = IIO_POSITIONRELATIVE, \ 303 .modified = 1, \ 304 .channel = num, \ 305 .channel2 = mod, \ 306 .scan_index = num, \ 307 .scan_type = { \ 308 .sign = 'u', \ 309 .realbits = 12, \ 310 .storagebits = 16, \ 311 }, \ 312 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 313 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 314 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 315 .datasheet_name = name, \ 316 } 317 #define AT91_SAMA5D2_CHAN_PRESSURE(num, name) \ 318 { \ 319 .type = IIO_PRESSURE, \ 320 .channel = num, \ 321 .scan_index = num, \ 322 .scan_type = { \ 323 .sign = 'u', \ 324 .realbits = 12, \ 325 .storagebits = 16, \ 326 }, \ 327 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 328 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 329 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 330 .datasheet_name = name, \ 331 } 332 333 #define at91_adc_readl(st, reg) readl_relaxed(st->base + reg) 334 #define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg) 335 336 struct at91_adc_soc_info { 337 unsigned startup_time; 338 unsigned min_sample_rate; 339 unsigned max_sample_rate; 340 }; 341 342 struct at91_adc_trigger { 343 char *name; 344 unsigned int trgmod_value; 345 unsigned int edge_type; 346 bool hw_trig; 347 }; 348 349 /** 350 * struct at91_adc_dma - at91-sama5d2 dma information struct 351 * @dma_chan: the dma channel acquired 352 * @rx_buf: dma coherent allocated area 353 * @rx_dma_buf: dma handler for the buffer 354 * @phys_addr: physical address of the ADC base register 355 * @buf_idx: index inside the dma buffer where reading was last done 356 * @rx_buf_sz: size of buffer used by DMA operation 357 * @watermark: number of conversions to copy before DMA triggers irq 358 * @dma_ts: hold the start timestamp of dma operation 359 */ 360 struct at91_adc_dma { 361 struct dma_chan *dma_chan; 362 u8 *rx_buf; 363 dma_addr_t rx_dma_buf; 364 phys_addr_t phys_addr; 365 int buf_idx; 366 int rx_buf_sz; 367 int watermark; 368 s64 dma_ts; 369 }; 370 371 /** 372 * struct at91_adc_touch - at91-sama5d2 touchscreen information struct 373 * @sample_period_val: the value for periodic trigger interval 374 * @touching: is the pen touching the screen or not 375 * @x_pos: temporary placeholder for pressure computation 376 * @channels_bitmask: bitmask with the touchscreen channels enabled 377 * @workq: workqueue for buffer data pushing 378 */ 379 struct at91_adc_touch { 380 u16 sample_period_val; 381 bool touching; 382 u16 x_pos; 383 unsigned long channels_bitmask; 384 struct work_struct workq; 385 }; 386 387 struct at91_adc_state { 388 void __iomem *base; 389 int irq; 390 struct clk *per_clk; 391 struct regulator *reg; 392 struct regulator *vref; 393 int vref_uv; 394 unsigned int current_sample_rate; 395 struct iio_trigger *trig; 396 const struct at91_adc_trigger *selected_trig; 397 const struct iio_chan_spec *chan; 398 bool conversion_done; 399 u32 conversion_value; 400 unsigned int oversampling_ratio; 401 struct at91_adc_soc_info soc_info; 402 wait_queue_head_t wq_data_available; 403 struct at91_adc_dma dma_st; 404 struct at91_adc_touch touch_st; 405 struct iio_dev *indio_dev; 406 u16 buffer[AT91_BUFFER_MAX_HWORDS]; 407 /* 408 * lock to prevent concurrent 'single conversion' requests through 409 * sysfs. 410 */ 411 struct mutex lock; 412 }; 413 414 static const struct at91_adc_trigger at91_adc_trigger_list[] = { 415 { 416 .name = "external_rising", 417 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE, 418 .edge_type = IRQ_TYPE_EDGE_RISING, 419 .hw_trig = true, 420 }, 421 { 422 .name = "external_falling", 423 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL, 424 .edge_type = IRQ_TYPE_EDGE_FALLING, 425 .hw_trig = true, 426 }, 427 { 428 .name = "external_any", 429 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY, 430 .edge_type = IRQ_TYPE_EDGE_BOTH, 431 .hw_trig = true, 432 }, 433 { 434 .name = "software", 435 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER, 436 .edge_type = IRQ_TYPE_NONE, 437 .hw_trig = false, 438 }, 439 }; 440 441 static const struct iio_chan_spec at91_adc_channels[] = { 442 AT91_SAMA5D2_CHAN_SINGLE(0, 0x50), 443 AT91_SAMA5D2_CHAN_SINGLE(1, 0x54), 444 AT91_SAMA5D2_CHAN_SINGLE(2, 0x58), 445 AT91_SAMA5D2_CHAN_SINGLE(3, 0x5c), 446 AT91_SAMA5D2_CHAN_SINGLE(4, 0x60), 447 AT91_SAMA5D2_CHAN_SINGLE(5, 0x64), 448 AT91_SAMA5D2_CHAN_SINGLE(6, 0x68), 449 AT91_SAMA5D2_CHAN_SINGLE(7, 0x6c), 450 AT91_SAMA5D2_CHAN_SINGLE(8, 0x70), 451 AT91_SAMA5D2_CHAN_SINGLE(9, 0x74), 452 AT91_SAMA5D2_CHAN_SINGLE(10, 0x78), 453 AT91_SAMA5D2_CHAN_SINGLE(11, 0x7c), 454 AT91_SAMA5D2_CHAN_DIFF(0, 1, 0x50), 455 AT91_SAMA5D2_CHAN_DIFF(2, 3, 0x58), 456 AT91_SAMA5D2_CHAN_DIFF(4, 5, 0x60), 457 AT91_SAMA5D2_CHAN_DIFF(6, 7, 0x68), 458 AT91_SAMA5D2_CHAN_DIFF(8, 9, 0x70), 459 AT91_SAMA5D2_CHAN_DIFF(10, 11, 0x78), 460 IIO_CHAN_SOFT_TIMESTAMP(AT91_SAMA5D2_TIMESTAMP_CHAN_IDX), 461 AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_X_CHAN_IDX, "x", IIO_MOD_X), 462 AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, "y", IIO_MOD_Y), 463 AT91_SAMA5D2_CHAN_PRESSURE(AT91_SAMA5D2_TOUCH_P_CHAN_IDX, "pressure"), 464 }; 465 466 static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) 467 { 468 int i; 469 470 for (i = 0; i < indio_dev->num_channels; i++) { 471 if (indio_dev->channels[i].scan_index == chan) 472 return i; 473 } 474 return -EINVAL; 475 } 476 477 static inline struct iio_chan_spec const * 478 at91_adc_chan_get(struct iio_dev *indio_dev, int chan) 479 { 480 int index = at91_adc_chan_xlate(indio_dev, chan); 481 482 if (index < 0) 483 return NULL; 484 return indio_dev->channels + index; 485 } 486 487 static inline int at91_adc_of_xlate(struct iio_dev *indio_dev, 488 const struct of_phandle_args *iiospec) 489 { 490 return at91_adc_chan_xlate(indio_dev, iiospec->args[0]); 491 } 492 493 static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev) 494 { 495 u32 mask = 0; 496 u8 bit; 497 498 for_each_set_bit(bit, indio_dev->active_scan_mask, 499 indio_dev->num_channels) { 500 struct iio_chan_spec const *chan = 501 at91_adc_chan_get(indio_dev, bit); 502 mask |= BIT(chan->channel); 503 } 504 505 return mask & GENMASK(11, 0); 506 } 507 508 static void at91_adc_config_emr(struct at91_adc_state *st) 509 { 510 /* configure the extended mode register */ 511 unsigned int emr = at91_adc_readl(st, AT91_SAMA5D2_EMR); 512 513 /* select oversampling per single trigger event */ 514 emr |= AT91_SAMA5D2_EMR_ASTE(1); 515 516 /* delete leftover content if it's the case */ 517 emr &= ~AT91_SAMA5D2_EMR_OSR_MASK; 518 519 /* select oversampling ratio from configuration */ 520 switch (st->oversampling_ratio) { 521 case AT91_OSR_1SAMPLES: 522 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES) & 523 AT91_SAMA5D2_EMR_OSR_MASK; 524 break; 525 case AT91_OSR_4SAMPLES: 526 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES) & 527 AT91_SAMA5D2_EMR_OSR_MASK; 528 break; 529 case AT91_OSR_16SAMPLES: 530 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES) & 531 AT91_SAMA5D2_EMR_OSR_MASK; 532 break; 533 } 534 535 at91_adc_writel(st, AT91_SAMA5D2_EMR, emr); 536 } 537 538 static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val) 539 { 540 if (st->oversampling_ratio == AT91_OSR_1SAMPLES) { 541 /* 542 * in this case we only have 12 bits of real data, but channel 543 * is registered as 14 bits, so shift left two bits 544 */ 545 *val <<= 2; 546 } else if (st->oversampling_ratio == AT91_OSR_4SAMPLES) { 547 /* 548 * in this case we have 13 bits of real data, but channel 549 * is registered as 14 bits, so left shift one bit 550 */ 551 *val <<= 1; 552 } 553 554 return IIO_VAL_INT; 555 } 556 557 static void at91_adc_adjust_val_osr_array(struct at91_adc_state *st, void *buf, 558 int len) 559 { 560 int i = 0, val; 561 u16 *buf_u16 = (u16 *) buf; 562 563 /* 564 * We are converting each two bytes (each sample). 565 * First convert the byte based array to u16, and convert each sample 566 * separately. 567 * Each value is two bytes in an array of chars, so to not shift 568 * more than we need, save the value separately. 569 * len is in bytes, so divide by two to get number of samples. 570 */ 571 while (i < len / 2) { 572 val = buf_u16[i]; 573 at91_adc_adjust_val_osr(st, &val); 574 buf_u16[i] = val; 575 i++; 576 } 577 } 578 579 static int at91_adc_configure_touch(struct at91_adc_state *st, bool state) 580 { 581 u32 clk_khz = st->current_sample_rate / 1000; 582 int i = 0; 583 u16 pendbc; 584 u32 tsmr, acr; 585 586 if (!state) { 587 /* disabling touch IRQs and setting mode to no touch enabled */ 588 at91_adc_writel(st, AT91_SAMA5D2_IDR, 589 AT91_SAMA5D2_IER_PEN | AT91_SAMA5D2_IER_NOPEN); 590 at91_adc_writel(st, AT91_SAMA5D2_TSMR, 0); 591 return 0; 592 } 593 /* 594 * debounce time is in microseconds, we need it in milliseconds to 595 * multiply with kilohertz, so, divide by 1000, but after the multiply. 596 * round up to make sure pendbc is at least 1 597 */ 598 pendbc = round_up(AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US * 599 clk_khz / 1000, 1); 600 601 /* get the required exponent */ 602 while (pendbc >> i++) 603 ; 604 605 pendbc = i; 606 607 tsmr = AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS; 608 609 tsmr |= AT91_SAMA5D2_TSMR_TSAV(2) & AT91_SAMA5D2_TSMR_TSAV_MASK; 610 tsmr |= AT91_SAMA5D2_TSMR_PENDBC(pendbc) & 611 AT91_SAMA5D2_TSMR_PENDBC_MASK; 612 tsmr |= AT91_SAMA5D2_TSMR_NOTSDMA; 613 tsmr |= AT91_SAMA5D2_TSMR_PENDET_ENA; 614 tsmr |= AT91_SAMA5D2_TSMR_TSFREQ(2) & AT91_SAMA5D2_TSMR_TSFREQ_MASK; 615 616 at91_adc_writel(st, AT91_SAMA5D2_TSMR, tsmr); 617 618 acr = at91_adc_readl(st, AT91_SAMA5D2_ACR); 619 acr &= ~AT91_SAMA5D2_ACR_PENDETSENS_MASK; 620 acr |= 0x02 & AT91_SAMA5D2_ACR_PENDETSENS_MASK; 621 at91_adc_writel(st, AT91_SAMA5D2_ACR, acr); 622 623 /* Sample Period Time = (TRGPER + 1) / ADCClock */ 624 st->touch_st.sample_period_val = 625 round_up((AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US * 626 clk_khz / 1000) - 1, 1); 627 /* enable pen detect IRQ */ 628 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN); 629 630 return 0; 631 } 632 633 static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg) 634 { 635 u32 val; 636 u32 scale, result, pos; 637 638 /* 639 * to obtain the actual position we must divide by scale 640 * and multiply with max, where 641 * max = 2^AT91_SAMA5D2_MAX_POS_BITS - 1 642 */ 643 /* first half of register is the x or y, second half is the scale */ 644 val = at91_adc_readl(st, reg); 645 if (!val) 646 dev_dbg(&st->indio_dev->dev, "pos is 0\n"); 647 648 pos = val & AT91_SAMA5D2_XYZ_MASK; 649 result = (pos << AT91_SAMA5D2_MAX_POS_BITS) - pos; 650 scale = (val >> 16) & AT91_SAMA5D2_XYZ_MASK; 651 if (scale == 0) { 652 dev_err(&st->indio_dev->dev, "scale is 0\n"); 653 return 0; 654 } 655 result /= scale; 656 657 return result; 658 } 659 660 static u16 at91_adc_touch_x_pos(struct at91_adc_state *st) 661 { 662 st->touch_st.x_pos = at91_adc_touch_pos(st, AT91_SAMA5D2_XPOSR); 663 return st->touch_st.x_pos; 664 } 665 666 static u16 at91_adc_touch_y_pos(struct at91_adc_state *st) 667 { 668 return at91_adc_touch_pos(st, AT91_SAMA5D2_YPOSR); 669 } 670 671 static u16 at91_adc_touch_pressure(struct at91_adc_state *st) 672 { 673 u32 val; 674 u32 z1, z2; 675 u32 pres; 676 u32 rxp = 1; 677 u32 factor = 1000; 678 679 /* calculate the pressure */ 680 val = at91_adc_readl(st, AT91_SAMA5D2_PRESSR); 681 z1 = val & AT91_SAMA5D2_XYZ_MASK; 682 z2 = (val >> 16) & AT91_SAMA5D2_XYZ_MASK; 683 684 if (z1 != 0) 685 pres = rxp * (st->touch_st.x_pos * factor / 1024) * 686 (z2 * factor / z1 - factor) / 687 factor; 688 else 689 pres = 0xFFFF; /* no pen contact */ 690 691 /* 692 * The pressure from device grows down, minimum is 0xFFFF, maximum 0x0. 693 * We compute it this way, but let's return it in the expected way, 694 * growing from 0 to 0xFFFF. 695 */ 696 return 0xFFFF - pres; 697 } 698 699 static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val) 700 { 701 *val = 0; 702 if (!st->touch_st.touching) 703 return -ENODATA; 704 if (chan == AT91_SAMA5D2_TOUCH_X_CHAN_IDX) 705 *val = at91_adc_touch_x_pos(st); 706 else if (chan == AT91_SAMA5D2_TOUCH_Y_CHAN_IDX) 707 *val = at91_adc_touch_y_pos(st); 708 else 709 return -ENODATA; 710 711 return IIO_VAL_INT; 712 } 713 714 static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val) 715 { 716 *val = 0; 717 if (!st->touch_st.touching) 718 return -ENODATA; 719 if (chan == AT91_SAMA5D2_TOUCH_P_CHAN_IDX) 720 *val = at91_adc_touch_pressure(st); 721 else 722 return -ENODATA; 723 724 return IIO_VAL_INT; 725 } 726 727 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) 728 { 729 struct iio_dev *indio = iio_trigger_get_drvdata(trig); 730 struct at91_adc_state *st = iio_priv(indio); 731 u32 status = at91_adc_readl(st, AT91_SAMA5D2_TRGR); 732 733 /* clear TRGMOD */ 734 status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK; 735 736 if (state) 737 status |= st->selected_trig->trgmod_value; 738 739 /* set/unset hw trigger */ 740 at91_adc_writel(st, AT91_SAMA5D2_TRGR, status); 741 742 return 0; 743 } 744 745 static int at91_adc_reenable_trigger(struct iio_trigger *trig) 746 { 747 struct iio_dev *indio = iio_trigger_get_drvdata(trig); 748 struct at91_adc_state *st = iio_priv(indio); 749 750 /* if we are using DMA, we must not reenable irq after each trigger */ 751 if (st->dma_st.dma_chan) 752 return 0; 753 754 enable_irq(st->irq); 755 756 /* Needed to ACK the DRDY interruption */ 757 at91_adc_readl(st, AT91_SAMA5D2_LCDR); 758 759 return 0; 760 } 761 762 static const struct iio_trigger_ops at91_adc_trigger_ops = { 763 .set_trigger_state = &at91_adc_configure_trigger, 764 .try_reenable = &at91_adc_reenable_trigger, 765 .validate_device = iio_trigger_validate_own_device, 766 }; 767 768 static int at91_adc_dma_size_done(struct at91_adc_state *st) 769 { 770 struct dma_tx_state state; 771 enum dma_status status; 772 int i, size; 773 774 status = dmaengine_tx_status(st->dma_st.dma_chan, 775 st->dma_st.dma_chan->cookie, 776 &state); 777 if (status != DMA_IN_PROGRESS) 778 return 0; 779 780 /* Transferred length is size in bytes from end of buffer */ 781 i = st->dma_st.rx_buf_sz - state.residue; 782 783 /* Return available bytes */ 784 if (i >= st->dma_st.buf_idx) 785 size = i - st->dma_st.buf_idx; 786 else 787 size = st->dma_st.rx_buf_sz + i - st->dma_st.buf_idx; 788 return size; 789 } 790 791 static void at91_dma_buffer_done(void *data) 792 { 793 struct iio_dev *indio_dev = data; 794 795 iio_trigger_poll_chained(indio_dev->trig); 796 } 797 798 static int at91_adc_dma_start(struct iio_dev *indio_dev) 799 { 800 struct at91_adc_state *st = iio_priv(indio_dev); 801 struct dma_async_tx_descriptor *desc; 802 dma_cookie_t cookie; 803 int ret; 804 u8 bit; 805 806 if (!st->dma_st.dma_chan) 807 return 0; 808 809 /* we start a new DMA, so set buffer index to start */ 810 st->dma_st.buf_idx = 0; 811 812 /* 813 * compute buffer size w.r.t. watermark and enabled channels. 814 * scan_bytes is aligned so we need an exact size for DMA 815 */ 816 st->dma_st.rx_buf_sz = 0; 817 818 for_each_set_bit(bit, indio_dev->active_scan_mask, 819 indio_dev->num_channels) { 820 struct iio_chan_spec const *chan = 821 at91_adc_chan_get(indio_dev, bit); 822 823 if (!chan) 824 continue; 825 826 st->dma_st.rx_buf_sz += chan->scan_type.storagebits / 8; 827 } 828 st->dma_st.rx_buf_sz *= st->dma_st.watermark; 829 830 /* Prepare a DMA cyclic transaction */ 831 desc = dmaengine_prep_dma_cyclic(st->dma_st.dma_chan, 832 st->dma_st.rx_dma_buf, 833 st->dma_st.rx_buf_sz, 834 st->dma_st.rx_buf_sz / 2, 835 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 836 837 if (!desc) { 838 dev_err(&indio_dev->dev, "cannot prepare DMA cyclic\n"); 839 return -EBUSY; 840 } 841 842 desc->callback = at91_dma_buffer_done; 843 desc->callback_param = indio_dev; 844 845 cookie = dmaengine_submit(desc); 846 ret = dma_submit_error(cookie); 847 if (ret) { 848 dev_err(&indio_dev->dev, "cannot submit DMA cyclic\n"); 849 dmaengine_terminate_async(st->dma_st.dma_chan); 850 return ret; 851 } 852 853 /* enable general overrun error signaling */ 854 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_GOVRE); 855 /* Issue pending DMA requests */ 856 dma_async_issue_pending(st->dma_st.dma_chan); 857 858 /* consider current time as DMA start time for timestamps */ 859 st->dma_st.dma_ts = iio_get_time_ns(indio_dev); 860 861 dev_dbg(&indio_dev->dev, "DMA cyclic started\n"); 862 863 return 0; 864 } 865 866 static bool at91_adc_buffer_check_use_irq(struct iio_dev *indio, 867 struct at91_adc_state *st) 868 { 869 /* if using DMA, we do not use our own IRQ (we use DMA-controller) */ 870 if (st->dma_st.dma_chan) 871 return false; 872 /* if the trigger is not ours, then it has its own IRQ */ 873 if (iio_trigger_validate_own_device(indio->trig, indio)) 874 return false; 875 return true; 876 } 877 878 static bool at91_adc_current_chan_is_touch(struct iio_dev *indio_dev) 879 { 880 struct at91_adc_state *st = iio_priv(indio_dev); 881 882 return !!bitmap_subset(indio_dev->active_scan_mask, 883 &st->touch_st.channels_bitmask, 884 AT91_SAMA5D2_MAX_CHAN_IDX + 1); 885 } 886 887 static int at91_adc_buffer_preenable(struct iio_dev *indio_dev) 888 { 889 int ret; 890 u8 bit; 891 struct at91_adc_state *st = iio_priv(indio_dev); 892 893 /* check if we are enabling triggered buffer or the touchscreen */ 894 if (at91_adc_current_chan_is_touch(indio_dev)) 895 return at91_adc_configure_touch(st, true); 896 897 /* if we are not in triggered mode, we cannot enable the buffer. */ 898 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES)) 899 return -EINVAL; 900 901 /* we continue with the triggered buffer */ 902 ret = at91_adc_dma_start(indio_dev); 903 if (ret) { 904 dev_err(&indio_dev->dev, "buffer postenable failed\n"); 905 return ret; 906 } 907 908 for_each_set_bit(bit, indio_dev->active_scan_mask, 909 indio_dev->num_channels) { 910 struct iio_chan_spec const *chan = 911 at91_adc_chan_get(indio_dev, bit); 912 u32 cor; 913 914 if (!chan) 915 continue; 916 /* these channel types cannot be handled by this trigger */ 917 if (chan->type == IIO_POSITIONRELATIVE || 918 chan->type == IIO_PRESSURE) 919 continue; 920 921 cor = at91_adc_readl(st, AT91_SAMA5D2_COR); 922 923 if (chan->differential) 924 cor |= (BIT(chan->channel) | BIT(chan->channel2)) << 925 AT91_SAMA5D2_COR_DIFF_OFFSET; 926 else 927 cor &= ~(BIT(chan->channel) << 928 AT91_SAMA5D2_COR_DIFF_OFFSET); 929 930 at91_adc_writel(st, AT91_SAMA5D2_COR, cor); 931 932 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel)); 933 } 934 935 if (at91_adc_buffer_check_use_irq(indio_dev, st)) 936 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_DRDY); 937 938 return 0; 939 } 940 941 static int at91_adc_buffer_postdisable(struct iio_dev *indio_dev) 942 { 943 struct at91_adc_state *st = iio_priv(indio_dev); 944 u8 bit; 945 946 /* check if we are disabling triggered buffer or the touchscreen */ 947 if (at91_adc_current_chan_is_touch(indio_dev)) 948 return at91_adc_configure_touch(st, false); 949 950 /* if we are not in triggered mode, nothing to do here */ 951 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES)) 952 return -EINVAL; 953 954 /* 955 * For each enable channel we must disable it in hardware. 956 * In the case of DMA, we must read the last converted value 957 * to clear EOC status and not get a possible interrupt later. 958 * This value is being read by DMA from LCDR anyway, so it's not lost. 959 */ 960 for_each_set_bit(bit, indio_dev->active_scan_mask, 961 indio_dev->num_channels) { 962 struct iio_chan_spec const *chan = 963 at91_adc_chan_get(indio_dev, bit); 964 965 if (!chan) 966 continue; 967 /* these channel types are virtual, no need to do anything */ 968 if (chan->type == IIO_POSITIONRELATIVE || 969 chan->type == IIO_PRESSURE) 970 continue; 971 972 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel)); 973 974 if (st->dma_st.dma_chan) 975 at91_adc_readl(st, chan->address); 976 } 977 978 if (at91_adc_buffer_check_use_irq(indio_dev, st)) 979 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_DRDY); 980 981 /* read overflow register to clear possible overflow status */ 982 at91_adc_readl(st, AT91_SAMA5D2_OVER); 983 984 /* if we are using DMA we must clear registers and end DMA */ 985 if (st->dma_st.dma_chan) 986 dmaengine_terminate_sync(st->dma_st.dma_chan); 987 988 return 0; 989 } 990 991 static const struct iio_buffer_setup_ops at91_buffer_setup_ops = { 992 .preenable = &at91_adc_buffer_preenable, 993 .postdisable = &at91_adc_buffer_postdisable, 994 }; 995 996 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio, 997 char *trigger_name) 998 { 999 struct iio_trigger *trig; 1000 int ret; 1001 1002 trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name, 1003 indio->id, trigger_name); 1004 if (!trig) 1005 return NULL; 1006 1007 trig->dev.parent = indio->dev.parent; 1008 iio_trigger_set_drvdata(trig, indio); 1009 trig->ops = &at91_adc_trigger_ops; 1010 1011 ret = devm_iio_trigger_register(&indio->dev, trig); 1012 if (ret) 1013 return ERR_PTR(ret); 1014 1015 return trig; 1016 } 1017 1018 static int at91_adc_trigger_init(struct iio_dev *indio) 1019 { 1020 struct at91_adc_state *st = iio_priv(indio); 1021 1022 st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name); 1023 if (IS_ERR(st->trig)) { 1024 dev_err(&indio->dev, 1025 "could not allocate trigger\n"); 1026 return PTR_ERR(st->trig); 1027 } 1028 1029 return 0; 1030 } 1031 1032 static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev, 1033 struct iio_poll_func *pf) 1034 { 1035 struct at91_adc_state *st = iio_priv(indio_dev); 1036 int i = 0; 1037 int val; 1038 u8 bit; 1039 u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev); 1040 unsigned int timeout = 50; 1041 1042 /* 1043 * Check if the conversion is ready. If not, wait a little bit, and 1044 * in case of timeout exit with an error. 1045 */ 1046 while ((at91_adc_readl(st, AT91_SAMA5D2_ISR) & mask) != mask && 1047 timeout) { 1048 usleep_range(50, 100); 1049 timeout--; 1050 } 1051 1052 /* Cannot read data, not ready. Continue without reporting data */ 1053 if (!timeout) 1054 return; 1055 1056 for_each_set_bit(bit, indio_dev->active_scan_mask, 1057 indio_dev->num_channels) { 1058 struct iio_chan_spec const *chan = 1059 at91_adc_chan_get(indio_dev, bit); 1060 1061 if (!chan) 1062 continue; 1063 /* 1064 * Our external trigger only supports the voltage channels. 1065 * In case someone requested a different type of channel 1066 * just put zeroes to buffer. 1067 * This should not happen because we check the scan mode 1068 * and scan mask when we enable the buffer, and we don't allow 1069 * the buffer to start with a mixed mask (voltage and something 1070 * else). 1071 * Thus, emit a warning. 1072 */ 1073 if (chan->type == IIO_VOLTAGE) { 1074 val = at91_adc_readl(st, chan->address); 1075 at91_adc_adjust_val_osr(st, &val); 1076 st->buffer[i] = val; 1077 } else { 1078 st->buffer[i] = 0; 1079 WARN(true, "This trigger cannot handle this type of channel"); 1080 } 1081 i++; 1082 } 1083 iio_push_to_buffers_with_timestamp(indio_dev, st->buffer, 1084 pf->timestamp); 1085 } 1086 1087 static void at91_adc_trigger_handler_dma(struct iio_dev *indio_dev) 1088 { 1089 struct at91_adc_state *st = iio_priv(indio_dev); 1090 int transferred_len = at91_adc_dma_size_done(st); 1091 s64 ns = iio_get_time_ns(indio_dev); 1092 s64 interval; 1093 int sample_index = 0, sample_count, sample_size; 1094 1095 u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR); 1096 /* if we reached this point, we cannot sample faster */ 1097 if (status & AT91_SAMA5D2_IER_GOVRE) 1098 pr_info_ratelimited("%s: conversion overrun detected\n", 1099 indio_dev->name); 1100 1101 sample_size = div_s64(st->dma_st.rx_buf_sz, st->dma_st.watermark); 1102 1103 sample_count = div_s64(transferred_len, sample_size); 1104 1105 /* 1106 * interval between samples is total time since last transfer handling 1107 * divided by the number of samples (total size divided by sample size) 1108 */ 1109 interval = div_s64((ns - st->dma_st.dma_ts), sample_count); 1110 1111 while (transferred_len >= sample_size) { 1112 /* 1113 * for all the values in the current sample, 1114 * adjust the values inside the buffer for oversampling 1115 */ 1116 at91_adc_adjust_val_osr_array(st, 1117 &st->dma_st.rx_buf[st->dma_st.buf_idx], 1118 sample_size); 1119 1120 iio_push_to_buffers_with_timestamp(indio_dev, 1121 (st->dma_st.rx_buf + st->dma_st.buf_idx), 1122 (st->dma_st.dma_ts + interval * sample_index)); 1123 /* adjust remaining length */ 1124 transferred_len -= sample_size; 1125 /* adjust buffer index */ 1126 st->dma_st.buf_idx += sample_size; 1127 /* in case of reaching end of buffer, reset index */ 1128 if (st->dma_st.buf_idx >= st->dma_st.rx_buf_sz) 1129 st->dma_st.buf_idx = 0; 1130 sample_index++; 1131 } 1132 /* adjust saved time for next transfer handling */ 1133 st->dma_st.dma_ts = iio_get_time_ns(indio_dev); 1134 } 1135 1136 static irqreturn_t at91_adc_trigger_handler(int irq, void *p) 1137 { 1138 struct iio_poll_func *pf = p; 1139 struct iio_dev *indio_dev = pf->indio_dev; 1140 struct at91_adc_state *st = iio_priv(indio_dev); 1141 1142 /* 1143 * If it's not our trigger, start a conversion now, as we are 1144 * actually polling the trigger now. 1145 */ 1146 if (iio_trigger_validate_own_device(indio_dev->trig, indio_dev)) 1147 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START); 1148 1149 if (st->dma_st.dma_chan) 1150 at91_adc_trigger_handler_dma(indio_dev); 1151 else 1152 at91_adc_trigger_handler_nodma(indio_dev, pf); 1153 1154 iio_trigger_notify_done(indio_dev->trig); 1155 1156 return IRQ_HANDLED; 1157 } 1158 1159 static int at91_adc_buffer_init(struct iio_dev *indio) 1160 { 1161 return devm_iio_triggered_buffer_setup(&indio->dev, indio, 1162 &iio_pollfunc_store_time, 1163 &at91_adc_trigger_handler, &at91_buffer_setup_ops); 1164 } 1165 1166 static unsigned at91_adc_startup_time(unsigned startup_time_min, 1167 unsigned adc_clk_khz) 1168 { 1169 static const unsigned int startup_lookup[] = { 1170 0, 8, 16, 24, 1171 64, 80, 96, 112, 1172 512, 576, 640, 704, 1173 768, 832, 896, 960 1174 }; 1175 unsigned ticks_min, i; 1176 1177 /* 1178 * Since the adc frequency is checked before, there is no reason 1179 * to not meet the startup time constraint. 1180 */ 1181 1182 ticks_min = startup_time_min * adc_clk_khz / 1000; 1183 for (i = 0; i < ARRAY_SIZE(startup_lookup); i++) 1184 if (startup_lookup[i] > ticks_min) 1185 break; 1186 1187 return i; 1188 } 1189 1190 static void at91_adc_setup_samp_freq(struct iio_dev *indio_dev, unsigned freq) 1191 { 1192 struct at91_adc_state *st = iio_priv(indio_dev); 1193 unsigned f_per, prescal, startup, mr; 1194 1195 f_per = clk_get_rate(st->per_clk); 1196 prescal = (f_per / (2 * freq)) - 1; 1197 1198 startup = at91_adc_startup_time(st->soc_info.startup_time, 1199 freq / 1000); 1200 1201 mr = at91_adc_readl(st, AT91_SAMA5D2_MR); 1202 mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK); 1203 mr |= AT91_SAMA5D2_MR_STARTUP(startup); 1204 mr |= AT91_SAMA5D2_MR_PRESCAL(prescal); 1205 at91_adc_writel(st, AT91_SAMA5D2_MR, mr); 1206 1207 dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n", 1208 freq, startup, prescal); 1209 st->current_sample_rate = freq; 1210 } 1211 1212 static inline unsigned at91_adc_get_sample_freq(struct at91_adc_state *st) 1213 { 1214 return st->current_sample_rate; 1215 } 1216 1217 static void at91_adc_touch_data_handler(struct iio_dev *indio_dev) 1218 { 1219 struct at91_adc_state *st = iio_priv(indio_dev); 1220 u8 bit; 1221 u16 val; 1222 int i = 0; 1223 1224 for_each_set_bit(bit, indio_dev->active_scan_mask, 1225 AT91_SAMA5D2_MAX_CHAN_IDX + 1) { 1226 struct iio_chan_spec const *chan = 1227 at91_adc_chan_get(indio_dev, bit); 1228 1229 if (chan->type == IIO_POSITIONRELATIVE) 1230 at91_adc_read_position(st, chan->channel, &val); 1231 else if (chan->type == IIO_PRESSURE) 1232 at91_adc_read_pressure(st, chan->channel, &val); 1233 else 1234 continue; 1235 st->buffer[i] = val; 1236 i++; 1237 } 1238 /* 1239 * Schedule work to push to buffers. 1240 * This is intended to push to the callback buffer that another driver 1241 * registered. We are still in a handler from our IRQ. If we push 1242 * directly, it means the other driver has it's callback called 1243 * from our IRQ context. Which is something we better avoid. 1244 * Let's schedule it after our IRQ is completed. 1245 */ 1246 schedule_work(&st->touch_st.workq); 1247 } 1248 1249 static void at91_adc_pen_detect_interrupt(struct at91_adc_state *st) 1250 { 1251 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_PEN); 1252 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_NOPEN | 1253 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | 1254 AT91_SAMA5D2_IER_PRDY); 1255 at91_adc_writel(st, AT91_SAMA5D2_TRGR, 1256 AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC | 1257 AT91_SAMA5D2_TRGR_TRGPER(st->touch_st.sample_period_val)); 1258 st->touch_st.touching = true; 1259 } 1260 1261 static void at91_adc_no_pen_detect_interrupt(struct iio_dev *indio_dev) 1262 { 1263 struct at91_adc_state *st = iio_priv(indio_dev); 1264 1265 at91_adc_writel(st, AT91_SAMA5D2_TRGR, 1266 AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER); 1267 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_NOPEN | 1268 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | 1269 AT91_SAMA5D2_IER_PRDY); 1270 st->touch_st.touching = false; 1271 1272 at91_adc_touch_data_handler(indio_dev); 1273 1274 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN); 1275 } 1276 1277 static void at91_adc_workq_handler(struct work_struct *workq) 1278 { 1279 struct at91_adc_touch *touch_st = container_of(workq, 1280 struct at91_adc_touch, workq); 1281 struct at91_adc_state *st = container_of(touch_st, 1282 struct at91_adc_state, touch_st); 1283 struct iio_dev *indio_dev = st->indio_dev; 1284 1285 iio_push_to_buffers(indio_dev, st->buffer); 1286 } 1287 1288 static irqreturn_t at91_adc_interrupt(int irq, void *private) 1289 { 1290 struct iio_dev *indio = private; 1291 struct at91_adc_state *st = iio_priv(indio); 1292 u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR); 1293 u32 imr = at91_adc_readl(st, AT91_SAMA5D2_IMR); 1294 u32 rdy_mask = AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | 1295 AT91_SAMA5D2_IER_PRDY; 1296 1297 if (!(status & imr)) 1298 return IRQ_NONE; 1299 if (status & AT91_SAMA5D2_IER_PEN) { 1300 /* pen detected IRQ */ 1301 at91_adc_pen_detect_interrupt(st); 1302 } else if ((status & AT91_SAMA5D2_IER_NOPEN)) { 1303 /* nopen detected IRQ */ 1304 at91_adc_no_pen_detect_interrupt(indio); 1305 } else if ((status & AT91_SAMA5D2_ISR_PENS) && 1306 ((status & rdy_mask) == rdy_mask)) { 1307 /* periodic trigger IRQ - during pen sense */ 1308 at91_adc_touch_data_handler(indio); 1309 } else if (status & AT91_SAMA5D2_ISR_PENS) { 1310 /* 1311 * touching, but the measurements are not ready yet. 1312 * read and ignore. 1313 */ 1314 status = at91_adc_readl(st, AT91_SAMA5D2_XPOSR); 1315 status = at91_adc_readl(st, AT91_SAMA5D2_YPOSR); 1316 status = at91_adc_readl(st, AT91_SAMA5D2_PRESSR); 1317 } else if (iio_buffer_enabled(indio) && 1318 (status & AT91_SAMA5D2_IER_DRDY)) { 1319 /* triggered buffer without DMA */ 1320 disable_irq_nosync(irq); 1321 iio_trigger_poll(indio->trig); 1322 } else if (iio_buffer_enabled(indio) && st->dma_st.dma_chan) { 1323 /* triggered buffer with DMA - should not happen */ 1324 disable_irq_nosync(irq); 1325 WARN(true, "Unexpected irq occurred\n"); 1326 } else if (!iio_buffer_enabled(indio)) { 1327 /* software requested conversion */ 1328 st->conversion_value = at91_adc_readl(st, st->chan->address); 1329 st->conversion_done = true; 1330 wake_up_interruptible(&st->wq_data_available); 1331 } 1332 return IRQ_HANDLED; 1333 } 1334 1335 static int at91_adc_read_info_raw(struct iio_dev *indio_dev, 1336 struct iio_chan_spec const *chan, int *val) 1337 { 1338 struct at91_adc_state *st = iio_priv(indio_dev); 1339 u32 cor = 0; 1340 u16 tmp_val; 1341 int ret; 1342 1343 /* 1344 * Keep in mind that we cannot use software trigger or touchscreen 1345 * if external trigger is enabled 1346 */ 1347 if (chan->type == IIO_POSITIONRELATIVE) { 1348 ret = iio_device_claim_direct_mode(indio_dev); 1349 if (ret) 1350 return ret; 1351 mutex_lock(&st->lock); 1352 1353 ret = at91_adc_read_position(st, chan->channel, 1354 &tmp_val); 1355 *val = tmp_val; 1356 mutex_unlock(&st->lock); 1357 iio_device_release_direct_mode(indio_dev); 1358 1359 return at91_adc_adjust_val_osr(st, val); 1360 } 1361 if (chan->type == IIO_PRESSURE) { 1362 ret = iio_device_claim_direct_mode(indio_dev); 1363 if (ret) 1364 return ret; 1365 mutex_lock(&st->lock); 1366 1367 ret = at91_adc_read_pressure(st, chan->channel, 1368 &tmp_val); 1369 *val = tmp_val; 1370 mutex_unlock(&st->lock); 1371 iio_device_release_direct_mode(indio_dev); 1372 1373 return at91_adc_adjust_val_osr(st, val); 1374 } 1375 1376 /* in this case we have a voltage channel */ 1377 1378 ret = iio_device_claim_direct_mode(indio_dev); 1379 if (ret) 1380 return ret; 1381 mutex_lock(&st->lock); 1382 1383 st->chan = chan; 1384 1385 if (chan->differential) 1386 cor = (BIT(chan->channel) | BIT(chan->channel2)) << 1387 AT91_SAMA5D2_COR_DIFF_OFFSET; 1388 1389 at91_adc_writel(st, AT91_SAMA5D2_COR, cor); 1390 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel)); 1391 at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel)); 1392 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START); 1393 1394 ret = wait_event_interruptible_timeout(st->wq_data_available, 1395 st->conversion_done, 1396 msecs_to_jiffies(1000)); 1397 if (ret == 0) 1398 ret = -ETIMEDOUT; 1399 1400 if (ret > 0) { 1401 *val = st->conversion_value; 1402 ret = at91_adc_adjust_val_osr(st, val); 1403 if (chan->scan_type.sign == 's') 1404 *val = sign_extend32(*val, 11); 1405 st->conversion_done = false; 1406 } 1407 1408 at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel)); 1409 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel)); 1410 1411 /* Needed to ACK the DRDY interruption */ 1412 at91_adc_readl(st, AT91_SAMA5D2_LCDR); 1413 1414 mutex_unlock(&st->lock); 1415 1416 iio_device_release_direct_mode(indio_dev); 1417 return ret; 1418 } 1419 1420 static int at91_adc_read_raw(struct iio_dev *indio_dev, 1421 struct iio_chan_spec const *chan, 1422 int *val, int *val2, long mask) 1423 { 1424 struct at91_adc_state *st = iio_priv(indio_dev); 1425 1426 switch (mask) { 1427 case IIO_CHAN_INFO_RAW: 1428 return at91_adc_read_info_raw(indio_dev, chan, val); 1429 case IIO_CHAN_INFO_SCALE: 1430 *val = st->vref_uv / 1000; 1431 if (chan->differential) 1432 *val *= 2; 1433 *val2 = chan->scan_type.realbits; 1434 return IIO_VAL_FRACTIONAL_LOG2; 1435 1436 case IIO_CHAN_INFO_SAMP_FREQ: 1437 *val = at91_adc_get_sample_freq(st); 1438 return IIO_VAL_INT; 1439 1440 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1441 *val = st->oversampling_ratio; 1442 return IIO_VAL_INT; 1443 1444 default: 1445 return -EINVAL; 1446 } 1447 } 1448 1449 static int at91_adc_write_raw(struct iio_dev *indio_dev, 1450 struct iio_chan_spec const *chan, 1451 int val, int val2, long mask) 1452 { 1453 struct at91_adc_state *st = iio_priv(indio_dev); 1454 1455 switch (mask) { 1456 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1457 if ((val != AT91_OSR_1SAMPLES) && (val != AT91_OSR_4SAMPLES) && 1458 (val != AT91_OSR_16SAMPLES)) 1459 return -EINVAL; 1460 /* if no change, optimize out */ 1461 if (val == st->oversampling_ratio) 1462 return 0; 1463 st->oversampling_ratio = val; 1464 /* update ratio */ 1465 at91_adc_config_emr(st); 1466 return 0; 1467 case IIO_CHAN_INFO_SAMP_FREQ: 1468 if (val < st->soc_info.min_sample_rate || 1469 val > st->soc_info.max_sample_rate) 1470 return -EINVAL; 1471 1472 at91_adc_setup_samp_freq(indio_dev, val); 1473 return 0; 1474 default: 1475 return -EINVAL; 1476 }; 1477 } 1478 1479 static void at91_adc_dma_init(struct platform_device *pdev) 1480 { 1481 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 1482 struct at91_adc_state *st = iio_priv(indio_dev); 1483 struct dma_slave_config config = {0}; 1484 /* 1485 * We make the buffer double the size of the fifo, 1486 * such that DMA uses one half of the buffer (full fifo size) 1487 * and the software uses the other half to read/write. 1488 */ 1489 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE * 1490 AT91_BUFFER_MAX_CONVERSION_BYTES * 2, 1491 PAGE_SIZE); 1492 1493 if (st->dma_st.dma_chan) 1494 return; 1495 1496 st->dma_st.dma_chan = dma_request_chan(&pdev->dev, "rx"); 1497 if (IS_ERR(st->dma_st.dma_chan)) { 1498 dev_info(&pdev->dev, "can't get DMA channel\n"); 1499 st->dma_st.dma_chan = NULL; 1500 goto dma_exit; 1501 } 1502 1503 st->dma_st.rx_buf = dma_alloc_coherent(st->dma_st.dma_chan->device->dev, 1504 pages * PAGE_SIZE, 1505 &st->dma_st.rx_dma_buf, 1506 GFP_KERNEL); 1507 if (!st->dma_st.rx_buf) { 1508 dev_info(&pdev->dev, "can't allocate coherent DMA area\n"); 1509 goto dma_chan_disable; 1510 } 1511 1512 /* Configure DMA channel to read data register */ 1513 config.direction = DMA_DEV_TO_MEM; 1514 config.src_addr = (phys_addr_t)(st->dma_st.phys_addr 1515 + AT91_SAMA5D2_LCDR); 1516 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1517 config.src_maxburst = 1; 1518 config.dst_maxburst = 1; 1519 1520 if (dmaengine_slave_config(st->dma_st.dma_chan, &config)) { 1521 dev_info(&pdev->dev, "can't configure DMA slave\n"); 1522 goto dma_free_area; 1523 } 1524 1525 dev_info(&pdev->dev, "using %s for rx DMA transfers\n", 1526 dma_chan_name(st->dma_st.dma_chan)); 1527 1528 return; 1529 1530 dma_free_area: 1531 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE, 1532 st->dma_st.rx_buf, st->dma_st.rx_dma_buf); 1533 dma_chan_disable: 1534 dma_release_channel(st->dma_st.dma_chan); 1535 st->dma_st.dma_chan = NULL; 1536 dma_exit: 1537 dev_info(&pdev->dev, "continuing without DMA support\n"); 1538 } 1539 1540 static void at91_adc_dma_disable(struct platform_device *pdev) 1541 { 1542 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 1543 struct at91_adc_state *st = iio_priv(indio_dev); 1544 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE * 1545 AT91_BUFFER_MAX_CONVERSION_BYTES * 2, 1546 PAGE_SIZE); 1547 1548 /* if we are not using DMA, just return */ 1549 if (!st->dma_st.dma_chan) 1550 return; 1551 1552 /* wait for all transactions to be terminated first*/ 1553 dmaengine_terminate_sync(st->dma_st.dma_chan); 1554 1555 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE, 1556 st->dma_st.rx_buf, st->dma_st.rx_dma_buf); 1557 dma_release_channel(st->dma_st.dma_chan); 1558 st->dma_st.dma_chan = NULL; 1559 1560 dev_info(&pdev->dev, "continuing without DMA support\n"); 1561 } 1562 1563 static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) 1564 { 1565 struct at91_adc_state *st = iio_priv(indio_dev); 1566 1567 if (val > AT91_HWFIFO_MAX_SIZE) 1568 return -EINVAL; 1569 1570 if (!st->selected_trig->hw_trig) { 1571 dev_dbg(&indio_dev->dev, "we need hw trigger for DMA\n"); 1572 return 0; 1573 } 1574 1575 dev_dbg(&indio_dev->dev, "new watermark is %u\n", val); 1576 st->dma_st.watermark = val; 1577 1578 /* 1579 * The logic here is: if we have watermark 1, it means we do 1580 * each conversion with it's own IRQ, thus we don't need DMA. 1581 * If the watermark is higher, we do DMA to do all the transfers in bulk 1582 */ 1583 1584 if (val == 1) 1585 at91_adc_dma_disable(to_platform_device(&indio_dev->dev)); 1586 else if (val > 1) 1587 at91_adc_dma_init(to_platform_device(&indio_dev->dev)); 1588 1589 return 0; 1590 } 1591 1592 static int at91_adc_update_scan_mode(struct iio_dev *indio_dev, 1593 const unsigned long *scan_mask) 1594 { 1595 struct at91_adc_state *st = iio_priv(indio_dev); 1596 1597 if (bitmap_subset(scan_mask, &st->touch_st.channels_bitmask, 1598 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) 1599 return 0; 1600 /* 1601 * if the new bitmap is a combination of touchscreen and regular 1602 * channels, then we are not fine 1603 */ 1604 if (bitmap_intersects(&st->touch_st.channels_bitmask, scan_mask, 1605 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) 1606 return -EINVAL; 1607 return 0; 1608 } 1609 1610 static void at91_adc_hw_init(struct iio_dev *indio_dev) 1611 { 1612 struct at91_adc_state *st = iio_priv(indio_dev); 1613 1614 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST); 1615 at91_adc_writel(st, AT91_SAMA5D2_IDR, 0xffffffff); 1616 /* 1617 * Transfer field must be set to 2 according to the datasheet and 1618 * allows different analog settings for each channel. 1619 */ 1620 at91_adc_writel(st, AT91_SAMA5D2_MR, 1621 AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH); 1622 1623 at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate); 1624 1625 /* configure extended mode register */ 1626 at91_adc_config_emr(st); 1627 } 1628 1629 static ssize_t at91_adc_get_fifo_state(struct device *dev, 1630 struct device_attribute *attr, char *buf) 1631 { 1632 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1633 struct at91_adc_state *st = iio_priv(indio_dev); 1634 1635 return scnprintf(buf, PAGE_SIZE, "%d\n", !!st->dma_st.dma_chan); 1636 } 1637 1638 static ssize_t at91_adc_get_watermark(struct device *dev, 1639 struct device_attribute *attr, char *buf) 1640 { 1641 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1642 struct at91_adc_state *st = iio_priv(indio_dev); 1643 1644 return scnprintf(buf, PAGE_SIZE, "%d\n", st->dma_st.watermark); 1645 } 1646 1647 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, 1648 at91_adc_get_fifo_state, NULL, 0); 1649 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, 1650 at91_adc_get_watermark, NULL, 0); 1651 1652 static IIO_CONST_ATTR(hwfifo_watermark_min, "2"); 1653 static IIO_CONST_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR); 1654 1655 static IIO_CONST_ATTR(oversampling_ratio_available, 1656 __stringify(AT91_OSR_1SAMPLES) " " 1657 __stringify(AT91_OSR_4SAMPLES) " " 1658 __stringify(AT91_OSR_16SAMPLES)); 1659 1660 static struct attribute *at91_adc_attributes[] = { 1661 &iio_const_attr_oversampling_ratio_available.dev_attr.attr, 1662 NULL, 1663 }; 1664 1665 static const struct attribute_group at91_adc_attribute_group = { 1666 .attrs = at91_adc_attributes, 1667 }; 1668 1669 static const struct attribute *at91_adc_fifo_attributes[] = { 1670 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, 1671 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, 1672 &iio_dev_attr_hwfifo_watermark.dev_attr.attr, 1673 &iio_dev_attr_hwfifo_enabled.dev_attr.attr, 1674 NULL, 1675 }; 1676 1677 static const struct iio_info at91_adc_info = { 1678 .attrs = &at91_adc_attribute_group, 1679 .read_raw = &at91_adc_read_raw, 1680 .write_raw = &at91_adc_write_raw, 1681 .update_scan_mode = &at91_adc_update_scan_mode, 1682 .of_xlate = &at91_adc_of_xlate, 1683 .hwfifo_set_watermark = &at91_adc_set_watermark, 1684 }; 1685 1686 static int at91_adc_probe(struct platform_device *pdev) 1687 { 1688 struct iio_dev *indio_dev; 1689 struct at91_adc_state *st; 1690 struct resource *res; 1691 int ret, i; 1692 u32 edge_type = IRQ_TYPE_NONE; 1693 1694 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); 1695 if (!indio_dev) 1696 return -ENOMEM; 1697 1698 indio_dev->name = dev_name(&pdev->dev); 1699 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; 1700 indio_dev->info = &at91_adc_info; 1701 indio_dev->channels = at91_adc_channels; 1702 indio_dev->num_channels = ARRAY_SIZE(at91_adc_channels); 1703 1704 st = iio_priv(indio_dev); 1705 st->indio_dev = indio_dev; 1706 1707 bitmap_set(&st->touch_st.channels_bitmask, 1708 AT91_SAMA5D2_TOUCH_X_CHAN_IDX, 1); 1709 bitmap_set(&st->touch_st.channels_bitmask, 1710 AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, 1); 1711 bitmap_set(&st->touch_st.channels_bitmask, 1712 AT91_SAMA5D2_TOUCH_P_CHAN_IDX, 1); 1713 1714 st->oversampling_ratio = AT91_OSR_1SAMPLES; 1715 1716 ret = of_property_read_u32(pdev->dev.of_node, 1717 "atmel,min-sample-rate-hz", 1718 &st->soc_info.min_sample_rate); 1719 if (ret) { 1720 dev_err(&pdev->dev, 1721 "invalid or missing value for atmel,min-sample-rate-hz\n"); 1722 return ret; 1723 } 1724 1725 ret = of_property_read_u32(pdev->dev.of_node, 1726 "atmel,max-sample-rate-hz", 1727 &st->soc_info.max_sample_rate); 1728 if (ret) { 1729 dev_err(&pdev->dev, 1730 "invalid or missing value for atmel,max-sample-rate-hz\n"); 1731 return ret; 1732 } 1733 1734 ret = of_property_read_u32(pdev->dev.of_node, "atmel,startup-time-ms", 1735 &st->soc_info.startup_time); 1736 if (ret) { 1737 dev_err(&pdev->dev, 1738 "invalid or missing value for atmel,startup-time-ms\n"); 1739 return ret; 1740 } 1741 1742 ret = of_property_read_u32(pdev->dev.of_node, 1743 "atmel,trigger-edge-type", &edge_type); 1744 if (ret) { 1745 dev_dbg(&pdev->dev, 1746 "atmel,trigger-edge-type not specified, only software trigger available\n"); 1747 } 1748 1749 st->selected_trig = NULL; 1750 1751 /* find the right trigger, or no trigger at all */ 1752 for (i = 0; i < AT91_SAMA5D2_HW_TRIG_CNT + 1; i++) 1753 if (at91_adc_trigger_list[i].edge_type == edge_type) { 1754 st->selected_trig = &at91_adc_trigger_list[i]; 1755 break; 1756 } 1757 1758 if (!st->selected_trig) { 1759 dev_err(&pdev->dev, "invalid external trigger edge value\n"); 1760 return -EINVAL; 1761 } 1762 1763 init_waitqueue_head(&st->wq_data_available); 1764 mutex_init(&st->lock); 1765 INIT_WORK(&st->touch_st.workq, at91_adc_workq_handler); 1766 1767 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1768 if (!res) 1769 return -EINVAL; 1770 1771 /* if we plan to use DMA, we need the physical address of the regs */ 1772 st->dma_st.phys_addr = res->start; 1773 1774 st->base = devm_ioremap_resource(&pdev->dev, res); 1775 if (IS_ERR(st->base)) 1776 return PTR_ERR(st->base); 1777 1778 st->irq = platform_get_irq(pdev, 0); 1779 if (st->irq <= 0) { 1780 if (!st->irq) 1781 st->irq = -ENXIO; 1782 1783 return st->irq; 1784 } 1785 1786 st->per_clk = devm_clk_get(&pdev->dev, "adc_clk"); 1787 if (IS_ERR(st->per_clk)) 1788 return PTR_ERR(st->per_clk); 1789 1790 st->reg = devm_regulator_get(&pdev->dev, "vddana"); 1791 if (IS_ERR(st->reg)) 1792 return PTR_ERR(st->reg); 1793 1794 st->vref = devm_regulator_get(&pdev->dev, "vref"); 1795 if (IS_ERR(st->vref)) 1796 return PTR_ERR(st->vref); 1797 1798 ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0, 1799 pdev->dev.driver->name, indio_dev); 1800 if (ret) 1801 return ret; 1802 1803 ret = regulator_enable(st->reg); 1804 if (ret) 1805 return ret; 1806 1807 ret = regulator_enable(st->vref); 1808 if (ret) 1809 goto reg_disable; 1810 1811 st->vref_uv = regulator_get_voltage(st->vref); 1812 if (st->vref_uv <= 0) { 1813 ret = -EINVAL; 1814 goto vref_disable; 1815 } 1816 1817 at91_adc_hw_init(indio_dev); 1818 1819 ret = clk_prepare_enable(st->per_clk); 1820 if (ret) 1821 goto vref_disable; 1822 1823 platform_set_drvdata(pdev, indio_dev); 1824 1825 ret = at91_adc_buffer_init(indio_dev); 1826 if (ret < 0) { 1827 dev_err(&pdev->dev, "couldn't initialize the buffer.\n"); 1828 goto per_clk_disable_unprepare; 1829 } 1830 1831 if (st->selected_trig->hw_trig) { 1832 ret = at91_adc_trigger_init(indio_dev); 1833 if (ret < 0) { 1834 dev_err(&pdev->dev, "couldn't setup the triggers.\n"); 1835 goto per_clk_disable_unprepare; 1836 } 1837 /* 1838 * Initially the iio buffer has a length of 2 and 1839 * a watermark of 1 1840 */ 1841 st->dma_st.watermark = 1; 1842 1843 iio_buffer_set_attrs(indio_dev->buffer, 1844 at91_adc_fifo_attributes); 1845 } 1846 1847 if (dma_coerce_mask_and_coherent(&indio_dev->dev, DMA_BIT_MASK(32))) 1848 dev_info(&pdev->dev, "cannot set DMA mask to 32-bit\n"); 1849 1850 ret = iio_device_register(indio_dev); 1851 if (ret < 0) 1852 goto dma_disable; 1853 1854 if (st->selected_trig->hw_trig) 1855 dev_info(&pdev->dev, "setting up trigger as %s\n", 1856 st->selected_trig->name); 1857 1858 dev_info(&pdev->dev, "version: %x\n", 1859 readl_relaxed(st->base + AT91_SAMA5D2_VERSION)); 1860 1861 return 0; 1862 1863 dma_disable: 1864 at91_adc_dma_disable(pdev); 1865 per_clk_disable_unprepare: 1866 clk_disable_unprepare(st->per_clk); 1867 vref_disable: 1868 regulator_disable(st->vref); 1869 reg_disable: 1870 regulator_disable(st->reg); 1871 return ret; 1872 } 1873 1874 static int at91_adc_remove(struct platform_device *pdev) 1875 { 1876 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 1877 struct at91_adc_state *st = iio_priv(indio_dev); 1878 1879 iio_device_unregister(indio_dev); 1880 1881 at91_adc_dma_disable(pdev); 1882 1883 clk_disable_unprepare(st->per_clk); 1884 1885 regulator_disable(st->vref); 1886 regulator_disable(st->reg); 1887 1888 return 0; 1889 } 1890 1891 static __maybe_unused int at91_adc_suspend(struct device *dev) 1892 { 1893 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1894 struct at91_adc_state *st = iio_priv(indio_dev); 1895 1896 /* 1897 * Do a sofware reset of the ADC before we go to suspend. 1898 * this will ensure that all pins are free from being muxed by the ADC 1899 * and can be used by for other devices. 1900 * Otherwise, ADC will hog them and we can't go to suspend mode. 1901 */ 1902 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST); 1903 1904 clk_disable_unprepare(st->per_clk); 1905 regulator_disable(st->vref); 1906 regulator_disable(st->reg); 1907 1908 return pinctrl_pm_select_sleep_state(dev); 1909 } 1910 1911 static __maybe_unused int at91_adc_resume(struct device *dev) 1912 { 1913 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1914 struct at91_adc_state *st = iio_priv(indio_dev); 1915 int ret; 1916 1917 ret = pinctrl_pm_select_default_state(dev); 1918 if (ret) 1919 goto resume_failed; 1920 1921 ret = regulator_enable(st->reg); 1922 if (ret) 1923 goto resume_failed; 1924 1925 ret = regulator_enable(st->vref); 1926 if (ret) 1927 goto reg_disable_resume; 1928 1929 ret = clk_prepare_enable(st->per_clk); 1930 if (ret) 1931 goto vref_disable_resume; 1932 1933 at91_adc_hw_init(indio_dev); 1934 1935 /* reconfiguring trigger hardware state */ 1936 if (!iio_buffer_enabled(indio_dev)) 1937 return 0; 1938 1939 /* check if we are enabling triggered buffer or the touchscreen */ 1940 if (at91_adc_current_chan_is_touch(indio_dev)) 1941 return at91_adc_configure_touch(st, true); 1942 else 1943 return at91_adc_configure_trigger(st->trig, true); 1944 1945 /* not needed but more explicit */ 1946 return 0; 1947 1948 vref_disable_resume: 1949 regulator_disable(st->vref); 1950 reg_disable_resume: 1951 regulator_disable(st->reg); 1952 resume_failed: 1953 dev_err(&indio_dev->dev, "failed to resume\n"); 1954 return ret; 1955 } 1956 1957 static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume); 1958 1959 static const struct of_device_id at91_adc_dt_match[] = { 1960 { 1961 .compatible = "atmel,sama5d2-adc", 1962 }, { 1963 /* sentinel */ 1964 } 1965 }; 1966 MODULE_DEVICE_TABLE(of, at91_adc_dt_match); 1967 1968 static struct platform_driver at91_adc_driver = { 1969 .probe = at91_adc_probe, 1970 .remove = at91_adc_remove, 1971 .driver = { 1972 .name = "at91-sama5d2_adc", 1973 .of_match_table = at91_adc_dt_match, 1974 .pm = &at91_adc_pm_ops, 1975 }, 1976 }; 1977 module_platform_driver(at91_adc_driver) 1978 1979 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); 1980 MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC"); 1981 MODULE_LICENSE("GPL v2"); 1982