1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Atmel ADC driver for SAMA5D2 devices and compatible. 4 * 5 * Copyright (C) 2015 Atmel, 6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dmaengine.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/sched.h> 20 #include <linux/wait.h> 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/buffer.h> 24 #include <linux/iio/trigger.h> 25 #include <linux/iio/trigger_consumer.h> 26 #include <linux/iio/triggered_buffer.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/regulator/consumer.h> 29 30 /* Control Register */ 31 #define AT91_SAMA5D2_CR 0x00 32 /* Software Reset */ 33 #define AT91_SAMA5D2_CR_SWRST BIT(0) 34 /* Start Conversion */ 35 #define AT91_SAMA5D2_CR_START BIT(1) 36 /* Touchscreen Calibration */ 37 #define AT91_SAMA5D2_CR_TSCALIB BIT(2) 38 /* Comparison Restart */ 39 #define AT91_SAMA5D2_CR_CMPRST BIT(4) 40 41 /* Mode Register */ 42 #define AT91_SAMA5D2_MR 0x04 43 /* Trigger Selection */ 44 #define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1) 45 /* ADTRG */ 46 #define AT91_SAMA5D2_MR_TRGSEL_TRIG0 0 47 /* TIOA0 */ 48 #define AT91_SAMA5D2_MR_TRGSEL_TRIG1 1 49 /* TIOA1 */ 50 #define AT91_SAMA5D2_MR_TRGSEL_TRIG2 2 51 /* TIOA2 */ 52 #define AT91_SAMA5D2_MR_TRGSEL_TRIG3 3 53 /* PWM event line 0 */ 54 #define AT91_SAMA5D2_MR_TRGSEL_TRIG4 4 55 /* PWM event line 1 */ 56 #define AT91_SAMA5D2_MR_TRGSEL_TRIG5 5 57 /* TIOA3 */ 58 #define AT91_SAMA5D2_MR_TRGSEL_TRIG6 6 59 /* RTCOUT0 */ 60 #define AT91_SAMA5D2_MR_TRGSEL_TRIG7 7 61 /* Sleep Mode */ 62 #define AT91_SAMA5D2_MR_SLEEP BIT(5) 63 /* Fast Wake Up */ 64 #define AT91_SAMA5D2_MR_FWUP BIT(6) 65 /* Prescaler Rate Selection */ 66 #define AT91_SAMA5D2_MR_PRESCAL(v) ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET) 67 #define AT91_SAMA5D2_MR_PRESCAL_OFFSET 8 68 #define AT91_SAMA5D2_MR_PRESCAL_MAX 0xff 69 #define AT91_SAMA5D2_MR_PRESCAL_MASK GENMASK(15, 8) 70 /* Startup Time */ 71 #define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16) 72 #define AT91_SAMA5D2_MR_STARTUP_MASK GENMASK(19, 16) 73 /* Analog Change */ 74 #define AT91_SAMA5D2_MR_ANACH BIT(23) 75 /* Tracking Time */ 76 #define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24) 77 #define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xff 78 /* Transfer Time */ 79 #define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28) 80 #define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3 81 /* Use Sequence Enable */ 82 #define AT91_SAMA5D2_MR_USEQ BIT(31) 83 84 /* Channel Sequence Register 1 */ 85 #define AT91_SAMA5D2_SEQR1 0x08 86 /* Channel Sequence Register 2 */ 87 #define AT91_SAMA5D2_SEQR2 0x0c 88 /* Channel Enable Register */ 89 #define AT91_SAMA5D2_CHER 0x10 90 /* Channel Disable Register */ 91 #define AT91_SAMA5D2_CHDR 0x14 92 /* Channel Status Register */ 93 #define AT91_SAMA5D2_CHSR 0x18 94 /* Last Converted Data Register */ 95 #define AT91_SAMA5D2_LCDR 0x20 96 /* Interrupt Enable Register */ 97 #define AT91_SAMA5D2_IER 0x24 98 /* Interrupt Enable Register - TS X measurement ready */ 99 #define AT91_SAMA5D2_IER_XRDY BIT(20) 100 /* Interrupt Enable Register - TS Y measurement ready */ 101 #define AT91_SAMA5D2_IER_YRDY BIT(21) 102 /* Interrupt Enable Register - TS pressure measurement ready */ 103 #define AT91_SAMA5D2_IER_PRDY BIT(22) 104 /* Interrupt Enable Register - Data ready */ 105 #define AT91_SAMA5D2_IER_DRDY BIT(24) 106 /* Interrupt Enable Register - general overrun error */ 107 #define AT91_SAMA5D2_IER_GOVRE BIT(25) 108 /* Interrupt Enable Register - Pen detect */ 109 #define AT91_SAMA5D2_IER_PEN BIT(29) 110 /* Interrupt Enable Register - No pen detect */ 111 #define AT91_SAMA5D2_IER_NOPEN BIT(30) 112 /* Interrupt Disable Register */ 113 #define AT91_SAMA5D2_IDR 0x28 114 /* Interrupt Mask Register */ 115 #define AT91_SAMA5D2_IMR 0x2c 116 /* Interrupt Status Register */ 117 #define AT91_SAMA5D2_ISR 0x30 118 /* Interrupt Status Register - Pen touching sense status */ 119 #define AT91_SAMA5D2_ISR_PENS BIT(31) 120 /* Last Channel Trigger Mode Register */ 121 #define AT91_SAMA5D2_LCTMR 0x34 122 /* Last Channel Compare Window Register */ 123 #define AT91_SAMA5D2_LCCWR 0x38 124 /* Overrun Status Register */ 125 #define AT91_SAMA5D2_OVER 0x3c 126 /* Extended Mode Register */ 127 #define AT91_SAMA5D2_EMR 0x40 128 /* Extended Mode Register - Oversampling rate */ 129 #define AT91_SAMA5D2_EMR_OSR(V) ((V) << 16) 130 #define AT91_SAMA5D2_EMR_OSR_MASK GENMASK(17, 16) 131 #define AT91_SAMA5D2_EMR_OSR_1SAMPLES 0 132 #define AT91_SAMA5D2_EMR_OSR_4SAMPLES 1 133 #define AT91_SAMA5D2_EMR_OSR_16SAMPLES 2 134 135 /* Extended Mode Register - Averaging on single trigger event */ 136 #define AT91_SAMA5D2_EMR_ASTE(V) ((V) << 20) 137 /* Compare Window Register */ 138 #define AT91_SAMA5D2_CWR 0x44 139 /* Channel Gain Register */ 140 #define AT91_SAMA5D2_CGR 0x48 141 142 /* Channel Offset Register */ 143 #define AT91_SAMA5D2_COR 0x4c 144 #define AT91_SAMA5D2_COR_DIFF_OFFSET 16 145 146 /* Channel Data Register 0 */ 147 #define AT91_SAMA5D2_CDR0 0x50 148 /* Analog Control Register */ 149 #define AT91_SAMA5D2_ACR 0x94 150 /* Analog Control Register - Pen detect sensitivity mask */ 151 #define AT91_SAMA5D2_ACR_PENDETSENS_MASK GENMASK(1, 0) 152 153 /* Touchscreen Mode Register */ 154 #define AT91_SAMA5D2_TSMR 0xb0 155 /* Touchscreen Mode Register - No touch mode */ 156 #define AT91_SAMA5D2_TSMR_TSMODE_NONE 0 157 /* Touchscreen Mode Register - 4 wire screen, no pressure measurement */ 158 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_NO_PRESS 1 159 /* Touchscreen Mode Register - 4 wire screen, pressure measurement */ 160 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS 2 161 /* Touchscreen Mode Register - 5 wire screen */ 162 #define AT91_SAMA5D2_TSMR_TSMODE_5WIRE 3 163 /* Touchscreen Mode Register - Average samples mask */ 164 #define AT91_SAMA5D2_TSMR_TSAV_MASK GENMASK(5, 4) 165 /* Touchscreen Mode Register - Average samples */ 166 #define AT91_SAMA5D2_TSMR_TSAV(x) ((x) << 4) 167 /* Touchscreen Mode Register - Touch/trigger frequency ratio mask */ 168 #define AT91_SAMA5D2_TSMR_TSFREQ_MASK GENMASK(11, 8) 169 /* Touchscreen Mode Register - Touch/trigger frequency ratio */ 170 #define AT91_SAMA5D2_TSMR_TSFREQ(x) ((x) << 8) 171 /* Touchscreen Mode Register - Pen Debounce Time mask */ 172 #define AT91_SAMA5D2_TSMR_PENDBC_MASK GENMASK(31, 28) 173 /* Touchscreen Mode Register - Pen Debounce Time */ 174 #define AT91_SAMA5D2_TSMR_PENDBC(x) ((x) << 28) 175 /* Touchscreen Mode Register - No DMA for touch measurements */ 176 #define AT91_SAMA5D2_TSMR_NOTSDMA BIT(22) 177 /* Touchscreen Mode Register - Disable pen detection */ 178 #define AT91_SAMA5D2_TSMR_PENDET_DIS (0 << 24) 179 /* Touchscreen Mode Register - Enable pen detection */ 180 #define AT91_SAMA5D2_TSMR_PENDET_ENA BIT(24) 181 182 /* Touchscreen X Position Register */ 183 #define AT91_SAMA5D2_XPOSR 0xb4 184 /* Touchscreen Y Position Register */ 185 #define AT91_SAMA5D2_YPOSR 0xb8 186 /* Touchscreen Pressure Register */ 187 #define AT91_SAMA5D2_PRESSR 0xbc 188 /* Trigger Register */ 189 #define AT91_SAMA5D2_TRGR 0xc0 190 /* Mask for TRGMOD field of TRGR register */ 191 #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0) 192 /* No trigger, only software trigger can start conversions */ 193 #define AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER 0 194 /* Trigger Mode external trigger rising edge */ 195 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE 1 196 /* Trigger Mode external trigger falling edge */ 197 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL 2 198 /* Trigger Mode external trigger any edge */ 199 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY 3 200 /* Trigger Mode internal periodic */ 201 #define AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC 5 202 /* Trigger Mode - trigger period mask */ 203 #define AT91_SAMA5D2_TRGR_TRGPER_MASK GENMASK(31, 16) 204 /* Trigger Mode - trigger period */ 205 #define AT91_SAMA5D2_TRGR_TRGPER(x) ((x) << 16) 206 207 /* Correction Select Register */ 208 #define AT91_SAMA5D2_COSR 0xd0 209 /* Correction Value Register */ 210 #define AT91_SAMA5D2_CVR 0xd4 211 /* Channel Error Correction Register */ 212 #define AT91_SAMA5D2_CECR 0xd8 213 /* Write Protection Mode Register */ 214 #define AT91_SAMA5D2_WPMR 0xe4 215 /* Write Protection Status Register */ 216 #define AT91_SAMA5D2_WPSR 0xe8 217 /* Version Register */ 218 #define AT91_SAMA5D2_VERSION 0xfc 219 220 #define AT91_SAMA5D2_HW_TRIG_CNT 3 221 #define AT91_SAMA5D2_SINGLE_CHAN_CNT 12 222 #define AT91_SAMA5D2_DIFF_CHAN_CNT 6 223 224 #define AT91_SAMA5D2_TIMESTAMP_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \ 225 AT91_SAMA5D2_DIFF_CHAN_CNT + 1) 226 227 #define AT91_SAMA5D2_TOUCH_X_CHAN_IDX (AT91_SAMA5D2_SINGLE_CHAN_CNT + \ 228 AT91_SAMA5D2_DIFF_CHAN_CNT * 2) 229 #define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX (AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1) 230 #define AT91_SAMA5D2_TOUCH_P_CHAN_IDX (AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1) 231 #define AT91_SAMA5D2_MAX_CHAN_IDX AT91_SAMA5D2_TOUCH_P_CHAN_IDX 232 233 #define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */ 234 #define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US 200 235 236 #define AT91_SAMA5D2_XYZ_MASK GENMASK(11, 0) 237 238 #define AT91_SAMA5D2_MAX_POS_BITS 12 239 240 /* 241 * Maximum number of bytes to hold conversion from all channels 242 * without the timestamp. 243 */ 244 #define AT91_BUFFER_MAX_CONVERSION_BYTES ((AT91_SAMA5D2_SINGLE_CHAN_CNT + \ 245 AT91_SAMA5D2_DIFF_CHAN_CNT) * 2) 246 247 /* This total must also include the timestamp */ 248 #define AT91_BUFFER_MAX_BYTES (AT91_BUFFER_MAX_CONVERSION_BYTES + 8) 249 250 #define AT91_BUFFER_MAX_HWORDS (AT91_BUFFER_MAX_BYTES / 2) 251 252 #define AT91_HWFIFO_MAX_SIZE_STR "128" 253 #define AT91_HWFIFO_MAX_SIZE 128 254 255 /* Possible values for oversampling ratio */ 256 #define AT91_OSR_1SAMPLES 1 257 #define AT91_OSR_4SAMPLES 4 258 #define AT91_OSR_16SAMPLES 16 259 260 #define AT91_SAMA5D2_CHAN_SINGLE(num, addr) \ 261 { \ 262 .type = IIO_VOLTAGE, \ 263 .channel = num, \ 264 .address = addr, \ 265 .scan_index = num, \ 266 .scan_type = { \ 267 .sign = 'u', \ 268 .realbits = 14, \ 269 .storagebits = 16, \ 270 }, \ 271 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 272 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 273 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 274 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 275 .datasheet_name = "CH"#num, \ 276 .indexed = 1, \ 277 } 278 279 #define AT91_SAMA5D2_CHAN_DIFF(num, num2, addr) \ 280 { \ 281 .type = IIO_VOLTAGE, \ 282 .differential = 1, \ 283 .channel = num, \ 284 .channel2 = num2, \ 285 .address = addr, \ 286 .scan_index = num + AT91_SAMA5D2_SINGLE_CHAN_CNT, \ 287 .scan_type = { \ 288 .sign = 's', \ 289 .realbits = 14, \ 290 .storagebits = 16, \ 291 }, \ 292 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 293 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 294 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 295 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 296 .datasheet_name = "CH"#num"-CH"#num2, \ 297 .indexed = 1, \ 298 } 299 300 #define AT91_SAMA5D2_CHAN_TOUCH(num, name, mod) \ 301 { \ 302 .type = IIO_POSITIONRELATIVE, \ 303 .modified = 1, \ 304 .channel = num, \ 305 .channel2 = mod, \ 306 .scan_index = num, \ 307 .scan_type = { \ 308 .sign = 'u', \ 309 .realbits = 12, \ 310 .storagebits = 16, \ 311 }, \ 312 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 313 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 314 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 315 .datasheet_name = name, \ 316 } 317 #define AT91_SAMA5D2_CHAN_PRESSURE(num, name) \ 318 { \ 319 .type = IIO_PRESSURE, \ 320 .channel = num, \ 321 .scan_index = num, \ 322 .scan_type = { \ 323 .sign = 'u', \ 324 .realbits = 12, \ 325 .storagebits = 16, \ 326 }, \ 327 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 328 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\ 329 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 330 .datasheet_name = name, \ 331 } 332 333 #define at91_adc_readl(st, reg) readl_relaxed(st->base + reg) 334 #define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg) 335 336 struct at91_adc_soc_info { 337 unsigned startup_time; 338 unsigned min_sample_rate; 339 unsigned max_sample_rate; 340 }; 341 342 struct at91_adc_trigger { 343 char *name; 344 unsigned int trgmod_value; 345 unsigned int edge_type; 346 bool hw_trig; 347 }; 348 349 /** 350 * at91_adc_dma - at91-sama5d2 dma information struct 351 * @dma_chan: the dma channel acquired 352 * @rx_buf: dma coherent allocated area 353 * @rx_dma_buf: dma handler for the buffer 354 * @phys_addr: physical address of the ADC base register 355 * @buf_idx: index inside the dma buffer where reading was last done 356 * @rx_buf_sz: size of buffer used by DMA operation 357 * @watermark: number of conversions to copy before DMA triggers irq 358 * @dma_ts: hold the start timestamp of dma operation 359 */ 360 struct at91_adc_dma { 361 struct dma_chan *dma_chan; 362 u8 *rx_buf; 363 dma_addr_t rx_dma_buf; 364 phys_addr_t phys_addr; 365 int buf_idx; 366 int rx_buf_sz; 367 int watermark; 368 s64 dma_ts; 369 }; 370 371 /** 372 * at91_adc_touch - at91-sama5d2 touchscreen information struct 373 * @sample_period_val: the value for periodic trigger interval 374 * @touching: is the pen touching the screen or not 375 * @x_pos: temporary placeholder for pressure computation 376 * @channels_bitmask: bitmask with the touchscreen channels enabled 377 * @workq: workqueue for buffer data pushing 378 */ 379 struct at91_adc_touch { 380 u16 sample_period_val; 381 bool touching; 382 u16 x_pos; 383 unsigned long channels_bitmask; 384 struct work_struct workq; 385 }; 386 387 struct at91_adc_state { 388 void __iomem *base; 389 int irq; 390 struct clk *per_clk; 391 struct regulator *reg; 392 struct regulator *vref; 393 int vref_uv; 394 unsigned int current_sample_rate; 395 struct iio_trigger *trig; 396 const struct at91_adc_trigger *selected_trig; 397 const struct iio_chan_spec *chan; 398 bool conversion_done; 399 u32 conversion_value; 400 unsigned int oversampling_ratio; 401 struct at91_adc_soc_info soc_info; 402 wait_queue_head_t wq_data_available; 403 struct at91_adc_dma dma_st; 404 struct at91_adc_touch touch_st; 405 u16 buffer[AT91_BUFFER_MAX_HWORDS]; 406 /* 407 * lock to prevent concurrent 'single conversion' requests through 408 * sysfs. 409 */ 410 struct mutex lock; 411 }; 412 413 static const struct at91_adc_trigger at91_adc_trigger_list[] = { 414 { 415 .name = "external_rising", 416 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE, 417 .edge_type = IRQ_TYPE_EDGE_RISING, 418 .hw_trig = true, 419 }, 420 { 421 .name = "external_falling", 422 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL, 423 .edge_type = IRQ_TYPE_EDGE_FALLING, 424 .hw_trig = true, 425 }, 426 { 427 .name = "external_any", 428 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY, 429 .edge_type = IRQ_TYPE_EDGE_BOTH, 430 .hw_trig = true, 431 }, 432 { 433 .name = "software", 434 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER, 435 .edge_type = IRQ_TYPE_NONE, 436 .hw_trig = false, 437 }, 438 }; 439 440 static const struct iio_chan_spec at91_adc_channels[] = { 441 AT91_SAMA5D2_CHAN_SINGLE(0, 0x50), 442 AT91_SAMA5D2_CHAN_SINGLE(1, 0x54), 443 AT91_SAMA5D2_CHAN_SINGLE(2, 0x58), 444 AT91_SAMA5D2_CHAN_SINGLE(3, 0x5c), 445 AT91_SAMA5D2_CHAN_SINGLE(4, 0x60), 446 AT91_SAMA5D2_CHAN_SINGLE(5, 0x64), 447 AT91_SAMA5D2_CHAN_SINGLE(6, 0x68), 448 AT91_SAMA5D2_CHAN_SINGLE(7, 0x6c), 449 AT91_SAMA5D2_CHAN_SINGLE(8, 0x70), 450 AT91_SAMA5D2_CHAN_SINGLE(9, 0x74), 451 AT91_SAMA5D2_CHAN_SINGLE(10, 0x78), 452 AT91_SAMA5D2_CHAN_SINGLE(11, 0x7c), 453 AT91_SAMA5D2_CHAN_DIFF(0, 1, 0x50), 454 AT91_SAMA5D2_CHAN_DIFF(2, 3, 0x58), 455 AT91_SAMA5D2_CHAN_DIFF(4, 5, 0x60), 456 AT91_SAMA5D2_CHAN_DIFF(6, 7, 0x68), 457 AT91_SAMA5D2_CHAN_DIFF(8, 9, 0x70), 458 AT91_SAMA5D2_CHAN_DIFF(10, 11, 0x78), 459 IIO_CHAN_SOFT_TIMESTAMP(AT91_SAMA5D2_TIMESTAMP_CHAN_IDX), 460 AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_X_CHAN_IDX, "x", IIO_MOD_X), 461 AT91_SAMA5D2_CHAN_TOUCH(AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, "y", IIO_MOD_Y), 462 AT91_SAMA5D2_CHAN_PRESSURE(AT91_SAMA5D2_TOUCH_P_CHAN_IDX, "pressure"), 463 }; 464 465 static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan) 466 { 467 int i; 468 469 for (i = 0; i < indio_dev->num_channels; i++) { 470 if (indio_dev->channels[i].scan_index == chan) 471 return i; 472 } 473 return -EINVAL; 474 } 475 476 static inline struct iio_chan_spec const * 477 at91_adc_chan_get(struct iio_dev *indio_dev, int chan) 478 { 479 int index = at91_adc_chan_xlate(indio_dev, chan); 480 481 if (index < 0) 482 return NULL; 483 return indio_dev->channels + index; 484 } 485 486 static inline int at91_adc_of_xlate(struct iio_dev *indio_dev, 487 const struct of_phandle_args *iiospec) 488 { 489 return at91_adc_chan_xlate(indio_dev, iiospec->args[0]); 490 } 491 492 static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev) 493 { 494 u32 mask = 0; 495 u8 bit; 496 497 for_each_set_bit(bit, indio_dev->active_scan_mask, 498 indio_dev->num_channels) { 499 struct iio_chan_spec const *chan = 500 at91_adc_chan_get(indio_dev, bit); 501 mask |= BIT(chan->channel); 502 } 503 504 return mask & GENMASK(11, 0); 505 } 506 507 static void at91_adc_config_emr(struct at91_adc_state *st) 508 { 509 /* configure the extended mode register */ 510 unsigned int emr = at91_adc_readl(st, AT91_SAMA5D2_EMR); 511 512 /* select oversampling per single trigger event */ 513 emr |= AT91_SAMA5D2_EMR_ASTE(1); 514 515 /* delete leftover content if it's the case */ 516 emr &= ~AT91_SAMA5D2_EMR_OSR_MASK; 517 518 /* select oversampling ratio from configuration */ 519 switch (st->oversampling_ratio) { 520 case AT91_OSR_1SAMPLES: 521 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES) & 522 AT91_SAMA5D2_EMR_OSR_MASK; 523 break; 524 case AT91_OSR_4SAMPLES: 525 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES) & 526 AT91_SAMA5D2_EMR_OSR_MASK; 527 break; 528 case AT91_OSR_16SAMPLES: 529 emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES) & 530 AT91_SAMA5D2_EMR_OSR_MASK; 531 break; 532 } 533 534 at91_adc_writel(st, AT91_SAMA5D2_EMR, emr); 535 } 536 537 static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val) 538 { 539 if (st->oversampling_ratio == AT91_OSR_1SAMPLES) { 540 /* 541 * in this case we only have 12 bits of real data, but channel 542 * is registered as 14 bits, so shift left two bits 543 */ 544 *val <<= 2; 545 } else if (st->oversampling_ratio == AT91_OSR_4SAMPLES) { 546 /* 547 * in this case we have 13 bits of real data, but channel 548 * is registered as 14 bits, so left shift one bit 549 */ 550 *val <<= 1; 551 } 552 553 return IIO_VAL_INT; 554 } 555 556 static void at91_adc_adjust_val_osr_array(struct at91_adc_state *st, void *buf, 557 int len) 558 { 559 int i = 0, val; 560 u16 *buf_u16 = (u16 *) buf; 561 562 /* 563 * We are converting each two bytes (each sample). 564 * First convert the byte based array to u16, and convert each sample 565 * separately. 566 * Each value is two bytes in an array of chars, so to not shift 567 * more than we need, save the value separately. 568 * len is in bytes, so divide by two to get number of samples. 569 */ 570 while (i < len / 2) { 571 val = buf_u16[i]; 572 at91_adc_adjust_val_osr(st, &val); 573 buf_u16[i] = val; 574 i++; 575 } 576 } 577 578 static int at91_adc_configure_touch(struct at91_adc_state *st, bool state) 579 { 580 u32 clk_khz = st->current_sample_rate / 1000; 581 int i = 0; 582 u16 pendbc; 583 u32 tsmr, acr; 584 585 if (!state) { 586 /* disabling touch IRQs and setting mode to no touch enabled */ 587 at91_adc_writel(st, AT91_SAMA5D2_IDR, 588 AT91_SAMA5D2_IER_PEN | AT91_SAMA5D2_IER_NOPEN); 589 at91_adc_writel(st, AT91_SAMA5D2_TSMR, 0); 590 return 0; 591 } 592 /* 593 * debounce time is in microseconds, we need it in milliseconds to 594 * multiply with kilohertz, so, divide by 1000, but after the multiply. 595 * round up to make sure pendbc is at least 1 596 */ 597 pendbc = round_up(AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US * 598 clk_khz / 1000, 1); 599 600 /* get the required exponent */ 601 while (pendbc >> i++) 602 ; 603 604 pendbc = i; 605 606 tsmr = AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS; 607 608 tsmr |= AT91_SAMA5D2_TSMR_TSAV(2) & AT91_SAMA5D2_TSMR_TSAV_MASK; 609 tsmr |= AT91_SAMA5D2_TSMR_PENDBC(pendbc) & 610 AT91_SAMA5D2_TSMR_PENDBC_MASK; 611 tsmr |= AT91_SAMA5D2_TSMR_NOTSDMA; 612 tsmr |= AT91_SAMA5D2_TSMR_PENDET_ENA; 613 tsmr |= AT91_SAMA5D2_TSMR_TSFREQ(2) & AT91_SAMA5D2_TSMR_TSFREQ_MASK; 614 615 at91_adc_writel(st, AT91_SAMA5D2_TSMR, tsmr); 616 617 acr = at91_adc_readl(st, AT91_SAMA5D2_ACR); 618 acr &= ~AT91_SAMA5D2_ACR_PENDETSENS_MASK; 619 acr |= 0x02 & AT91_SAMA5D2_ACR_PENDETSENS_MASK; 620 at91_adc_writel(st, AT91_SAMA5D2_ACR, acr); 621 622 /* Sample Period Time = (TRGPER + 1) / ADCClock */ 623 st->touch_st.sample_period_val = 624 round_up((AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US * 625 clk_khz / 1000) - 1, 1); 626 /* enable pen detect IRQ */ 627 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN); 628 629 return 0; 630 } 631 632 static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg) 633 { 634 u32 val; 635 u32 scale, result, pos; 636 637 /* 638 * to obtain the actual position we must divide by scale 639 * and multiply with max, where 640 * max = 2^AT91_SAMA5D2_MAX_POS_BITS - 1 641 */ 642 /* first half of register is the x or y, second half is the scale */ 643 val = at91_adc_readl(st, reg); 644 if (!val) 645 dev_dbg(&iio_priv_to_dev(st)->dev, "pos is 0\n"); 646 647 pos = val & AT91_SAMA5D2_XYZ_MASK; 648 result = (pos << AT91_SAMA5D2_MAX_POS_BITS) - pos; 649 scale = (val >> 16) & AT91_SAMA5D2_XYZ_MASK; 650 if (scale == 0) { 651 dev_err(&iio_priv_to_dev(st)->dev, "scale is 0\n"); 652 return 0; 653 } 654 result /= scale; 655 656 return result; 657 } 658 659 static u16 at91_adc_touch_x_pos(struct at91_adc_state *st) 660 { 661 st->touch_st.x_pos = at91_adc_touch_pos(st, AT91_SAMA5D2_XPOSR); 662 return st->touch_st.x_pos; 663 } 664 665 static u16 at91_adc_touch_y_pos(struct at91_adc_state *st) 666 { 667 return at91_adc_touch_pos(st, AT91_SAMA5D2_YPOSR); 668 } 669 670 static u16 at91_adc_touch_pressure(struct at91_adc_state *st) 671 { 672 u32 val; 673 u32 z1, z2; 674 u32 pres; 675 u32 rxp = 1; 676 u32 factor = 1000; 677 678 /* calculate the pressure */ 679 val = at91_adc_readl(st, AT91_SAMA5D2_PRESSR); 680 z1 = val & AT91_SAMA5D2_XYZ_MASK; 681 z2 = (val >> 16) & AT91_SAMA5D2_XYZ_MASK; 682 683 if (z1 != 0) 684 pres = rxp * (st->touch_st.x_pos * factor / 1024) * 685 (z2 * factor / z1 - factor) / 686 factor; 687 else 688 pres = 0xFFFF; /* no pen contact */ 689 690 /* 691 * The pressure from device grows down, minimum is 0xFFFF, maximum 0x0. 692 * We compute it this way, but let's return it in the expected way, 693 * growing from 0 to 0xFFFF. 694 */ 695 return 0xFFFF - pres; 696 } 697 698 static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val) 699 { 700 *val = 0; 701 if (!st->touch_st.touching) 702 return -ENODATA; 703 if (chan == AT91_SAMA5D2_TOUCH_X_CHAN_IDX) 704 *val = at91_adc_touch_x_pos(st); 705 else if (chan == AT91_SAMA5D2_TOUCH_Y_CHAN_IDX) 706 *val = at91_adc_touch_y_pos(st); 707 else 708 return -ENODATA; 709 710 return IIO_VAL_INT; 711 } 712 713 static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val) 714 { 715 *val = 0; 716 if (!st->touch_st.touching) 717 return -ENODATA; 718 if (chan == AT91_SAMA5D2_TOUCH_P_CHAN_IDX) 719 *val = at91_adc_touch_pressure(st); 720 else 721 return -ENODATA; 722 723 return IIO_VAL_INT; 724 } 725 726 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state) 727 { 728 struct iio_dev *indio = iio_trigger_get_drvdata(trig); 729 struct at91_adc_state *st = iio_priv(indio); 730 u32 status = at91_adc_readl(st, AT91_SAMA5D2_TRGR); 731 732 /* clear TRGMOD */ 733 status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK; 734 735 if (state) 736 status |= st->selected_trig->trgmod_value; 737 738 /* set/unset hw trigger */ 739 at91_adc_writel(st, AT91_SAMA5D2_TRGR, status); 740 741 return 0; 742 } 743 744 static int at91_adc_reenable_trigger(struct iio_trigger *trig) 745 { 746 struct iio_dev *indio = iio_trigger_get_drvdata(trig); 747 struct at91_adc_state *st = iio_priv(indio); 748 749 /* if we are using DMA, we must not reenable irq after each trigger */ 750 if (st->dma_st.dma_chan) 751 return 0; 752 753 enable_irq(st->irq); 754 755 /* Needed to ACK the DRDY interruption */ 756 at91_adc_readl(st, AT91_SAMA5D2_LCDR); 757 758 return 0; 759 } 760 761 static const struct iio_trigger_ops at91_adc_trigger_ops = { 762 .set_trigger_state = &at91_adc_configure_trigger, 763 .try_reenable = &at91_adc_reenable_trigger, 764 .validate_device = iio_trigger_validate_own_device, 765 }; 766 767 static int at91_adc_dma_size_done(struct at91_adc_state *st) 768 { 769 struct dma_tx_state state; 770 enum dma_status status; 771 int i, size; 772 773 status = dmaengine_tx_status(st->dma_st.dma_chan, 774 st->dma_st.dma_chan->cookie, 775 &state); 776 if (status != DMA_IN_PROGRESS) 777 return 0; 778 779 /* Transferred length is size in bytes from end of buffer */ 780 i = st->dma_st.rx_buf_sz - state.residue; 781 782 /* Return available bytes */ 783 if (i >= st->dma_st.buf_idx) 784 size = i - st->dma_st.buf_idx; 785 else 786 size = st->dma_st.rx_buf_sz + i - st->dma_st.buf_idx; 787 return size; 788 } 789 790 static void at91_dma_buffer_done(void *data) 791 { 792 struct iio_dev *indio_dev = data; 793 794 iio_trigger_poll_chained(indio_dev->trig); 795 } 796 797 static int at91_adc_dma_start(struct iio_dev *indio_dev) 798 { 799 struct at91_adc_state *st = iio_priv(indio_dev); 800 struct dma_async_tx_descriptor *desc; 801 dma_cookie_t cookie; 802 int ret; 803 u8 bit; 804 805 if (!st->dma_st.dma_chan) 806 return 0; 807 808 /* we start a new DMA, so set buffer index to start */ 809 st->dma_st.buf_idx = 0; 810 811 /* 812 * compute buffer size w.r.t. watermark and enabled channels. 813 * scan_bytes is aligned so we need an exact size for DMA 814 */ 815 st->dma_st.rx_buf_sz = 0; 816 817 for_each_set_bit(bit, indio_dev->active_scan_mask, 818 indio_dev->num_channels) { 819 struct iio_chan_spec const *chan = 820 at91_adc_chan_get(indio_dev, bit); 821 822 if (!chan) 823 continue; 824 825 st->dma_st.rx_buf_sz += chan->scan_type.storagebits / 8; 826 } 827 st->dma_st.rx_buf_sz *= st->dma_st.watermark; 828 829 /* Prepare a DMA cyclic transaction */ 830 desc = dmaengine_prep_dma_cyclic(st->dma_st.dma_chan, 831 st->dma_st.rx_dma_buf, 832 st->dma_st.rx_buf_sz, 833 st->dma_st.rx_buf_sz / 2, 834 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 835 836 if (!desc) { 837 dev_err(&indio_dev->dev, "cannot prepare DMA cyclic\n"); 838 return -EBUSY; 839 } 840 841 desc->callback = at91_dma_buffer_done; 842 desc->callback_param = indio_dev; 843 844 cookie = dmaengine_submit(desc); 845 ret = dma_submit_error(cookie); 846 if (ret) { 847 dev_err(&indio_dev->dev, "cannot submit DMA cyclic\n"); 848 dmaengine_terminate_async(st->dma_st.dma_chan); 849 return ret; 850 } 851 852 /* enable general overrun error signaling */ 853 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_GOVRE); 854 /* Issue pending DMA requests */ 855 dma_async_issue_pending(st->dma_st.dma_chan); 856 857 /* consider current time as DMA start time for timestamps */ 858 st->dma_st.dma_ts = iio_get_time_ns(indio_dev); 859 860 dev_dbg(&indio_dev->dev, "DMA cyclic started\n"); 861 862 return 0; 863 } 864 865 static bool at91_adc_buffer_check_use_irq(struct iio_dev *indio, 866 struct at91_adc_state *st) 867 { 868 /* if using DMA, we do not use our own IRQ (we use DMA-controller) */ 869 if (st->dma_st.dma_chan) 870 return false; 871 /* if the trigger is not ours, then it has its own IRQ */ 872 if (iio_trigger_validate_own_device(indio->trig, indio)) 873 return false; 874 return true; 875 } 876 877 static bool at91_adc_current_chan_is_touch(struct iio_dev *indio_dev) 878 { 879 struct at91_adc_state *st = iio_priv(indio_dev); 880 881 return !!bitmap_subset(indio_dev->active_scan_mask, 882 &st->touch_st.channels_bitmask, 883 AT91_SAMA5D2_MAX_CHAN_IDX + 1); 884 } 885 886 static int at91_adc_buffer_preenable(struct iio_dev *indio_dev) 887 { 888 int ret; 889 u8 bit; 890 struct at91_adc_state *st = iio_priv(indio_dev); 891 892 /* check if we are enabling triggered buffer or the touchscreen */ 893 if (at91_adc_current_chan_is_touch(indio_dev)) 894 return at91_adc_configure_touch(st, true); 895 896 /* if we are not in triggered mode, we cannot enable the buffer. */ 897 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES)) 898 return -EINVAL; 899 900 /* we continue with the triggered buffer */ 901 ret = at91_adc_dma_start(indio_dev); 902 if (ret) { 903 dev_err(&indio_dev->dev, "buffer postenable failed\n"); 904 return ret; 905 } 906 907 for_each_set_bit(bit, indio_dev->active_scan_mask, 908 indio_dev->num_channels) { 909 struct iio_chan_spec const *chan = 910 at91_adc_chan_get(indio_dev, bit); 911 u32 cor; 912 913 if (!chan) 914 continue; 915 /* these channel types cannot be handled by this trigger */ 916 if (chan->type == IIO_POSITIONRELATIVE || 917 chan->type == IIO_PRESSURE) 918 continue; 919 920 cor = at91_adc_readl(st, AT91_SAMA5D2_COR); 921 922 if (chan->differential) 923 cor |= (BIT(chan->channel) | BIT(chan->channel2)) << 924 AT91_SAMA5D2_COR_DIFF_OFFSET; 925 else 926 cor &= ~(BIT(chan->channel) << 927 AT91_SAMA5D2_COR_DIFF_OFFSET); 928 929 at91_adc_writel(st, AT91_SAMA5D2_COR, cor); 930 931 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel)); 932 } 933 934 if (at91_adc_buffer_check_use_irq(indio_dev, st)) 935 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_DRDY); 936 937 return 0; 938 } 939 940 static int at91_adc_buffer_postenable(struct iio_dev *indio_dev) 941 { 942 if (at91_adc_current_chan_is_touch(indio_dev)) 943 return 0; 944 945 return iio_triggered_buffer_postenable(indio_dev); 946 } 947 948 static int at91_adc_buffer_postdisable(struct iio_dev *indio_dev) 949 { 950 struct at91_adc_state *st = iio_priv(indio_dev); 951 u8 bit; 952 953 /* check if we are disabling triggered buffer or the touchscreen */ 954 if (at91_adc_current_chan_is_touch(indio_dev)) 955 return at91_adc_configure_touch(st, false); 956 957 /* if we are not in triggered mode, nothing to do here */ 958 if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES)) 959 return -EINVAL; 960 961 /* 962 * For each enable channel we must disable it in hardware. 963 * In the case of DMA, we must read the last converted value 964 * to clear EOC status and not get a possible interrupt later. 965 * This value is being read by DMA from LCDR anyway, so it's not lost. 966 */ 967 for_each_set_bit(bit, indio_dev->active_scan_mask, 968 indio_dev->num_channels) { 969 struct iio_chan_spec const *chan = 970 at91_adc_chan_get(indio_dev, bit); 971 972 if (!chan) 973 continue; 974 /* these channel types are virtual, no need to do anything */ 975 if (chan->type == IIO_POSITIONRELATIVE || 976 chan->type == IIO_PRESSURE) 977 continue; 978 979 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel)); 980 981 if (st->dma_st.dma_chan) 982 at91_adc_readl(st, chan->address); 983 } 984 985 if (at91_adc_buffer_check_use_irq(indio_dev, st)) 986 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_DRDY); 987 988 /* read overflow register to clear possible overflow status */ 989 at91_adc_readl(st, AT91_SAMA5D2_OVER); 990 991 /* if we are using DMA we must clear registers and end DMA */ 992 if (st->dma_st.dma_chan) 993 dmaengine_terminate_sync(st->dma_st.dma_chan); 994 995 return 0; 996 } 997 998 static int at91_adc_buffer_predisable(struct iio_dev *indio_dev) 999 { 1000 if (at91_adc_current_chan_is_touch(indio_dev)) 1001 return 0; 1002 1003 return iio_triggered_buffer_predisable(indio_dev); 1004 } 1005 1006 static const struct iio_buffer_setup_ops at91_buffer_setup_ops = { 1007 .preenable = &at91_adc_buffer_preenable, 1008 .postdisable = &at91_adc_buffer_postdisable, 1009 .postenable = &at91_adc_buffer_postenable, 1010 .predisable = &at91_adc_buffer_predisable, 1011 }; 1012 1013 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio, 1014 char *trigger_name) 1015 { 1016 struct iio_trigger *trig; 1017 int ret; 1018 1019 trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name, 1020 indio->id, trigger_name); 1021 if (!trig) 1022 return NULL; 1023 1024 trig->dev.parent = indio->dev.parent; 1025 iio_trigger_set_drvdata(trig, indio); 1026 trig->ops = &at91_adc_trigger_ops; 1027 1028 ret = devm_iio_trigger_register(&indio->dev, trig); 1029 if (ret) 1030 return ERR_PTR(ret); 1031 1032 return trig; 1033 } 1034 1035 static int at91_adc_trigger_init(struct iio_dev *indio) 1036 { 1037 struct at91_adc_state *st = iio_priv(indio); 1038 1039 st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name); 1040 if (IS_ERR(st->trig)) { 1041 dev_err(&indio->dev, 1042 "could not allocate trigger\n"); 1043 return PTR_ERR(st->trig); 1044 } 1045 1046 return 0; 1047 } 1048 1049 static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev, 1050 struct iio_poll_func *pf) 1051 { 1052 struct at91_adc_state *st = iio_priv(indio_dev); 1053 int i = 0; 1054 int val; 1055 u8 bit; 1056 u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev); 1057 unsigned int timeout = 50; 1058 1059 /* 1060 * Check if the conversion is ready. If not, wait a little bit, and 1061 * in case of timeout exit with an error. 1062 */ 1063 while ((at91_adc_readl(st, AT91_SAMA5D2_ISR) & mask) != mask && 1064 timeout) { 1065 usleep_range(50, 100); 1066 timeout--; 1067 } 1068 1069 /* Cannot read data, not ready. Continue without reporting data */ 1070 if (!timeout) 1071 return; 1072 1073 for_each_set_bit(bit, indio_dev->active_scan_mask, 1074 indio_dev->num_channels) { 1075 struct iio_chan_spec const *chan = 1076 at91_adc_chan_get(indio_dev, bit); 1077 1078 if (!chan) 1079 continue; 1080 /* 1081 * Our external trigger only supports the voltage channels. 1082 * In case someone requested a different type of channel 1083 * just put zeroes to buffer. 1084 * This should not happen because we check the scan mode 1085 * and scan mask when we enable the buffer, and we don't allow 1086 * the buffer to start with a mixed mask (voltage and something 1087 * else). 1088 * Thus, emit a warning. 1089 */ 1090 if (chan->type == IIO_VOLTAGE) { 1091 val = at91_adc_readl(st, chan->address); 1092 at91_adc_adjust_val_osr(st, &val); 1093 st->buffer[i] = val; 1094 } else { 1095 st->buffer[i] = 0; 1096 WARN(true, "This trigger cannot handle this type of channel"); 1097 } 1098 i++; 1099 } 1100 iio_push_to_buffers_with_timestamp(indio_dev, st->buffer, 1101 pf->timestamp); 1102 } 1103 1104 static void at91_adc_trigger_handler_dma(struct iio_dev *indio_dev) 1105 { 1106 struct at91_adc_state *st = iio_priv(indio_dev); 1107 int transferred_len = at91_adc_dma_size_done(st); 1108 s64 ns = iio_get_time_ns(indio_dev); 1109 s64 interval; 1110 int sample_index = 0, sample_count, sample_size; 1111 1112 u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR); 1113 /* if we reached this point, we cannot sample faster */ 1114 if (status & AT91_SAMA5D2_IER_GOVRE) 1115 pr_info_ratelimited("%s: conversion overrun detected\n", 1116 indio_dev->name); 1117 1118 sample_size = div_s64(st->dma_st.rx_buf_sz, st->dma_st.watermark); 1119 1120 sample_count = div_s64(transferred_len, sample_size); 1121 1122 /* 1123 * interval between samples is total time since last transfer handling 1124 * divided by the number of samples (total size divided by sample size) 1125 */ 1126 interval = div_s64((ns - st->dma_st.dma_ts), sample_count); 1127 1128 while (transferred_len >= sample_size) { 1129 /* 1130 * for all the values in the current sample, 1131 * adjust the values inside the buffer for oversampling 1132 */ 1133 at91_adc_adjust_val_osr_array(st, 1134 &st->dma_st.rx_buf[st->dma_st.buf_idx], 1135 sample_size); 1136 1137 iio_push_to_buffers_with_timestamp(indio_dev, 1138 (st->dma_st.rx_buf + st->dma_st.buf_idx), 1139 (st->dma_st.dma_ts + interval * sample_index)); 1140 /* adjust remaining length */ 1141 transferred_len -= sample_size; 1142 /* adjust buffer index */ 1143 st->dma_st.buf_idx += sample_size; 1144 /* in case of reaching end of buffer, reset index */ 1145 if (st->dma_st.buf_idx >= st->dma_st.rx_buf_sz) 1146 st->dma_st.buf_idx = 0; 1147 sample_index++; 1148 } 1149 /* adjust saved time for next transfer handling */ 1150 st->dma_st.dma_ts = iio_get_time_ns(indio_dev); 1151 } 1152 1153 static irqreturn_t at91_adc_trigger_handler(int irq, void *p) 1154 { 1155 struct iio_poll_func *pf = p; 1156 struct iio_dev *indio_dev = pf->indio_dev; 1157 struct at91_adc_state *st = iio_priv(indio_dev); 1158 1159 /* 1160 * If it's not our trigger, start a conversion now, as we are 1161 * actually polling the trigger now. 1162 */ 1163 if (iio_trigger_validate_own_device(indio_dev->trig, indio_dev)) 1164 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START); 1165 1166 if (st->dma_st.dma_chan) 1167 at91_adc_trigger_handler_dma(indio_dev); 1168 else 1169 at91_adc_trigger_handler_nodma(indio_dev, pf); 1170 1171 iio_trigger_notify_done(indio_dev->trig); 1172 1173 return IRQ_HANDLED; 1174 } 1175 1176 static int at91_adc_buffer_init(struct iio_dev *indio) 1177 { 1178 return devm_iio_triggered_buffer_setup(&indio->dev, indio, 1179 &iio_pollfunc_store_time, 1180 &at91_adc_trigger_handler, &at91_buffer_setup_ops); 1181 } 1182 1183 static unsigned at91_adc_startup_time(unsigned startup_time_min, 1184 unsigned adc_clk_khz) 1185 { 1186 static const unsigned int startup_lookup[] = { 1187 0, 8, 16, 24, 1188 64, 80, 96, 112, 1189 512, 576, 640, 704, 1190 768, 832, 896, 960 1191 }; 1192 unsigned ticks_min, i; 1193 1194 /* 1195 * Since the adc frequency is checked before, there is no reason 1196 * to not meet the startup time constraint. 1197 */ 1198 1199 ticks_min = startup_time_min * adc_clk_khz / 1000; 1200 for (i = 0; i < ARRAY_SIZE(startup_lookup); i++) 1201 if (startup_lookup[i] > ticks_min) 1202 break; 1203 1204 return i; 1205 } 1206 1207 static void at91_adc_setup_samp_freq(struct at91_adc_state *st, unsigned freq) 1208 { 1209 struct iio_dev *indio_dev = iio_priv_to_dev(st); 1210 unsigned f_per, prescal, startup, mr; 1211 1212 f_per = clk_get_rate(st->per_clk); 1213 prescal = (f_per / (2 * freq)) - 1; 1214 1215 startup = at91_adc_startup_time(st->soc_info.startup_time, 1216 freq / 1000); 1217 1218 mr = at91_adc_readl(st, AT91_SAMA5D2_MR); 1219 mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK); 1220 mr |= AT91_SAMA5D2_MR_STARTUP(startup); 1221 mr |= AT91_SAMA5D2_MR_PRESCAL(prescal); 1222 at91_adc_writel(st, AT91_SAMA5D2_MR, mr); 1223 1224 dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n", 1225 freq, startup, prescal); 1226 st->current_sample_rate = freq; 1227 } 1228 1229 static inline unsigned at91_adc_get_sample_freq(struct at91_adc_state *st) 1230 { 1231 return st->current_sample_rate; 1232 } 1233 1234 static void at91_adc_touch_data_handler(struct iio_dev *indio_dev) 1235 { 1236 struct at91_adc_state *st = iio_priv(indio_dev); 1237 u8 bit; 1238 u16 val; 1239 int i = 0; 1240 1241 for_each_set_bit(bit, indio_dev->active_scan_mask, 1242 AT91_SAMA5D2_MAX_CHAN_IDX + 1) { 1243 struct iio_chan_spec const *chan = 1244 at91_adc_chan_get(indio_dev, bit); 1245 1246 if (chan->type == IIO_POSITIONRELATIVE) 1247 at91_adc_read_position(st, chan->channel, &val); 1248 else if (chan->type == IIO_PRESSURE) 1249 at91_adc_read_pressure(st, chan->channel, &val); 1250 else 1251 continue; 1252 st->buffer[i] = val; 1253 i++; 1254 } 1255 /* 1256 * Schedule work to push to buffers. 1257 * This is intended to push to the callback buffer that another driver 1258 * registered. We are still in a handler from our IRQ. If we push 1259 * directly, it means the other driver has it's callback called 1260 * from our IRQ context. Which is something we better avoid. 1261 * Let's schedule it after our IRQ is completed. 1262 */ 1263 schedule_work(&st->touch_st.workq); 1264 } 1265 1266 static void at91_adc_pen_detect_interrupt(struct at91_adc_state *st) 1267 { 1268 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_PEN); 1269 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_NOPEN | 1270 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | 1271 AT91_SAMA5D2_IER_PRDY); 1272 at91_adc_writel(st, AT91_SAMA5D2_TRGR, 1273 AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC | 1274 AT91_SAMA5D2_TRGR_TRGPER(st->touch_st.sample_period_val)); 1275 st->touch_st.touching = true; 1276 } 1277 1278 static void at91_adc_no_pen_detect_interrupt(struct at91_adc_state *st) 1279 { 1280 struct iio_dev *indio_dev = iio_priv_to_dev(st); 1281 1282 at91_adc_writel(st, AT91_SAMA5D2_TRGR, 1283 AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER); 1284 at91_adc_writel(st, AT91_SAMA5D2_IDR, AT91_SAMA5D2_IER_NOPEN | 1285 AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | 1286 AT91_SAMA5D2_IER_PRDY); 1287 st->touch_st.touching = false; 1288 1289 at91_adc_touch_data_handler(indio_dev); 1290 1291 at91_adc_writel(st, AT91_SAMA5D2_IER, AT91_SAMA5D2_IER_PEN); 1292 } 1293 1294 static void at91_adc_workq_handler(struct work_struct *workq) 1295 { 1296 struct at91_adc_touch *touch_st = container_of(workq, 1297 struct at91_adc_touch, workq); 1298 struct at91_adc_state *st = container_of(touch_st, 1299 struct at91_adc_state, touch_st); 1300 struct iio_dev *indio_dev = iio_priv_to_dev(st); 1301 1302 iio_push_to_buffers(indio_dev, st->buffer); 1303 } 1304 1305 static irqreturn_t at91_adc_interrupt(int irq, void *private) 1306 { 1307 struct iio_dev *indio = private; 1308 struct at91_adc_state *st = iio_priv(indio); 1309 u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR); 1310 u32 imr = at91_adc_readl(st, AT91_SAMA5D2_IMR); 1311 u32 rdy_mask = AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY | 1312 AT91_SAMA5D2_IER_PRDY; 1313 1314 if (!(status & imr)) 1315 return IRQ_NONE; 1316 if (status & AT91_SAMA5D2_IER_PEN) { 1317 /* pen detected IRQ */ 1318 at91_adc_pen_detect_interrupt(st); 1319 } else if ((status & AT91_SAMA5D2_IER_NOPEN)) { 1320 /* nopen detected IRQ */ 1321 at91_adc_no_pen_detect_interrupt(st); 1322 } else if ((status & AT91_SAMA5D2_ISR_PENS) && 1323 ((status & rdy_mask) == rdy_mask)) { 1324 /* periodic trigger IRQ - during pen sense */ 1325 at91_adc_touch_data_handler(indio); 1326 } else if (status & AT91_SAMA5D2_ISR_PENS) { 1327 /* 1328 * touching, but the measurements are not ready yet. 1329 * read and ignore. 1330 */ 1331 status = at91_adc_readl(st, AT91_SAMA5D2_XPOSR); 1332 status = at91_adc_readl(st, AT91_SAMA5D2_YPOSR); 1333 status = at91_adc_readl(st, AT91_SAMA5D2_PRESSR); 1334 } else if (iio_buffer_enabled(indio) && 1335 (status & AT91_SAMA5D2_IER_DRDY)) { 1336 /* triggered buffer without DMA */ 1337 disable_irq_nosync(irq); 1338 iio_trigger_poll(indio->trig); 1339 } else if (iio_buffer_enabled(indio) && st->dma_st.dma_chan) { 1340 /* triggered buffer with DMA - should not happen */ 1341 disable_irq_nosync(irq); 1342 WARN(true, "Unexpected irq occurred\n"); 1343 } else if (!iio_buffer_enabled(indio)) { 1344 /* software requested conversion */ 1345 st->conversion_value = at91_adc_readl(st, st->chan->address); 1346 st->conversion_done = true; 1347 wake_up_interruptible(&st->wq_data_available); 1348 } 1349 return IRQ_HANDLED; 1350 } 1351 1352 static int at91_adc_read_info_raw(struct iio_dev *indio_dev, 1353 struct iio_chan_spec const *chan, int *val) 1354 { 1355 struct at91_adc_state *st = iio_priv(indio_dev); 1356 u32 cor = 0; 1357 u16 tmp_val; 1358 int ret; 1359 1360 /* 1361 * Keep in mind that we cannot use software trigger or touchscreen 1362 * if external trigger is enabled 1363 */ 1364 if (chan->type == IIO_POSITIONRELATIVE) { 1365 ret = iio_device_claim_direct_mode(indio_dev); 1366 if (ret) 1367 return ret; 1368 mutex_lock(&st->lock); 1369 1370 ret = at91_adc_read_position(st, chan->channel, 1371 &tmp_val); 1372 *val = tmp_val; 1373 mutex_unlock(&st->lock); 1374 iio_device_release_direct_mode(indio_dev); 1375 1376 return at91_adc_adjust_val_osr(st, val); 1377 } 1378 if (chan->type == IIO_PRESSURE) { 1379 ret = iio_device_claim_direct_mode(indio_dev); 1380 if (ret) 1381 return ret; 1382 mutex_lock(&st->lock); 1383 1384 ret = at91_adc_read_pressure(st, chan->channel, 1385 &tmp_val); 1386 *val = tmp_val; 1387 mutex_unlock(&st->lock); 1388 iio_device_release_direct_mode(indio_dev); 1389 1390 return at91_adc_adjust_val_osr(st, val); 1391 } 1392 1393 /* in this case we have a voltage channel */ 1394 1395 ret = iio_device_claim_direct_mode(indio_dev); 1396 if (ret) 1397 return ret; 1398 mutex_lock(&st->lock); 1399 1400 st->chan = chan; 1401 1402 if (chan->differential) 1403 cor = (BIT(chan->channel) | BIT(chan->channel2)) << 1404 AT91_SAMA5D2_COR_DIFF_OFFSET; 1405 1406 at91_adc_writel(st, AT91_SAMA5D2_COR, cor); 1407 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel)); 1408 at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel)); 1409 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START); 1410 1411 ret = wait_event_interruptible_timeout(st->wq_data_available, 1412 st->conversion_done, 1413 msecs_to_jiffies(1000)); 1414 if (ret == 0) 1415 ret = -ETIMEDOUT; 1416 1417 if (ret > 0) { 1418 *val = st->conversion_value; 1419 ret = at91_adc_adjust_val_osr(st, val); 1420 if (chan->scan_type.sign == 's') 1421 *val = sign_extend32(*val, 11); 1422 st->conversion_done = false; 1423 } 1424 1425 at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel)); 1426 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel)); 1427 1428 /* Needed to ACK the DRDY interruption */ 1429 at91_adc_readl(st, AT91_SAMA5D2_LCDR); 1430 1431 mutex_unlock(&st->lock); 1432 1433 iio_device_release_direct_mode(indio_dev); 1434 return ret; 1435 } 1436 1437 static int at91_adc_read_raw(struct iio_dev *indio_dev, 1438 struct iio_chan_spec const *chan, 1439 int *val, int *val2, long mask) 1440 { 1441 struct at91_adc_state *st = iio_priv(indio_dev); 1442 1443 switch (mask) { 1444 case IIO_CHAN_INFO_RAW: 1445 return at91_adc_read_info_raw(indio_dev, chan, val); 1446 case IIO_CHAN_INFO_SCALE: 1447 *val = st->vref_uv / 1000; 1448 if (chan->differential) 1449 *val *= 2; 1450 *val2 = chan->scan_type.realbits; 1451 return IIO_VAL_FRACTIONAL_LOG2; 1452 1453 case IIO_CHAN_INFO_SAMP_FREQ: 1454 *val = at91_adc_get_sample_freq(st); 1455 return IIO_VAL_INT; 1456 1457 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1458 *val = st->oversampling_ratio; 1459 return IIO_VAL_INT; 1460 1461 default: 1462 return -EINVAL; 1463 } 1464 } 1465 1466 static int at91_adc_write_raw(struct iio_dev *indio_dev, 1467 struct iio_chan_spec const *chan, 1468 int val, int val2, long mask) 1469 { 1470 struct at91_adc_state *st = iio_priv(indio_dev); 1471 1472 switch (mask) { 1473 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 1474 if ((val != AT91_OSR_1SAMPLES) && (val != AT91_OSR_4SAMPLES) && 1475 (val != AT91_OSR_16SAMPLES)) 1476 return -EINVAL; 1477 /* if no change, optimize out */ 1478 if (val == st->oversampling_ratio) 1479 return 0; 1480 st->oversampling_ratio = val; 1481 /* update ratio */ 1482 at91_adc_config_emr(st); 1483 return 0; 1484 case IIO_CHAN_INFO_SAMP_FREQ: 1485 if (val < st->soc_info.min_sample_rate || 1486 val > st->soc_info.max_sample_rate) 1487 return -EINVAL; 1488 1489 at91_adc_setup_samp_freq(st, val); 1490 return 0; 1491 default: 1492 return -EINVAL; 1493 }; 1494 } 1495 1496 static void at91_adc_dma_init(struct platform_device *pdev) 1497 { 1498 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 1499 struct at91_adc_state *st = iio_priv(indio_dev); 1500 struct dma_slave_config config = {0}; 1501 /* 1502 * We make the buffer double the size of the fifo, 1503 * such that DMA uses one half of the buffer (full fifo size) 1504 * and the software uses the other half to read/write. 1505 */ 1506 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE * 1507 AT91_BUFFER_MAX_CONVERSION_BYTES * 2, 1508 PAGE_SIZE); 1509 1510 if (st->dma_st.dma_chan) 1511 return; 1512 1513 st->dma_st.dma_chan = dma_request_chan(&pdev->dev, "rx"); 1514 if (IS_ERR(st->dma_st.dma_chan)) { 1515 dev_info(&pdev->dev, "can't get DMA channel\n"); 1516 st->dma_st.dma_chan = NULL; 1517 goto dma_exit; 1518 } 1519 1520 st->dma_st.rx_buf = dma_alloc_coherent(st->dma_st.dma_chan->device->dev, 1521 pages * PAGE_SIZE, 1522 &st->dma_st.rx_dma_buf, 1523 GFP_KERNEL); 1524 if (!st->dma_st.rx_buf) { 1525 dev_info(&pdev->dev, "can't allocate coherent DMA area\n"); 1526 goto dma_chan_disable; 1527 } 1528 1529 /* Configure DMA channel to read data register */ 1530 config.direction = DMA_DEV_TO_MEM; 1531 config.src_addr = (phys_addr_t)(st->dma_st.phys_addr 1532 + AT91_SAMA5D2_LCDR); 1533 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1534 config.src_maxburst = 1; 1535 config.dst_maxburst = 1; 1536 1537 if (dmaengine_slave_config(st->dma_st.dma_chan, &config)) { 1538 dev_info(&pdev->dev, "can't configure DMA slave\n"); 1539 goto dma_free_area; 1540 } 1541 1542 dev_info(&pdev->dev, "using %s for rx DMA transfers\n", 1543 dma_chan_name(st->dma_st.dma_chan)); 1544 1545 return; 1546 1547 dma_free_area: 1548 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE, 1549 st->dma_st.rx_buf, st->dma_st.rx_dma_buf); 1550 dma_chan_disable: 1551 dma_release_channel(st->dma_st.dma_chan); 1552 st->dma_st.dma_chan = NULL; 1553 dma_exit: 1554 dev_info(&pdev->dev, "continuing without DMA support\n"); 1555 } 1556 1557 static void at91_adc_dma_disable(struct platform_device *pdev) 1558 { 1559 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 1560 struct at91_adc_state *st = iio_priv(indio_dev); 1561 unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE * 1562 AT91_BUFFER_MAX_CONVERSION_BYTES * 2, 1563 PAGE_SIZE); 1564 1565 /* if we are not using DMA, just return */ 1566 if (!st->dma_st.dma_chan) 1567 return; 1568 1569 /* wait for all transactions to be terminated first*/ 1570 dmaengine_terminate_sync(st->dma_st.dma_chan); 1571 1572 dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE, 1573 st->dma_st.rx_buf, st->dma_st.rx_dma_buf); 1574 dma_release_channel(st->dma_st.dma_chan); 1575 st->dma_st.dma_chan = NULL; 1576 1577 dev_info(&pdev->dev, "continuing without DMA support\n"); 1578 } 1579 1580 static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val) 1581 { 1582 struct at91_adc_state *st = iio_priv(indio_dev); 1583 1584 if (val > AT91_HWFIFO_MAX_SIZE) 1585 return -EINVAL; 1586 1587 if (!st->selected_trig->hw_trig) { 1588 dev_dbg(&indio_dev->dev, "we need hw trigger for DMA\n"); 1589 return 0; 1590 } 1591 1592 dev_dbg(&indio_dev->dev, "new watermark is %u\n", val); 1593 st->dma_st.watermark = val; 1594 1595 /* 1596 * The logic here is: if we have watermark 1, it means we do 1597 * each conversion with it's own IRQ, thus we don't need DMA. 1598 * If the watermark is higher, we do DMA to do all the transfers in bulk 1599 */ 1600 1601 if (val == 1) 1602 at91_adc_dma_disable(to_platform_device(&indio_dev->dev)); 1603 else if (val > 1) 1604 at91_adc_dma_init(to_platform_device(&indio_dev->dev)); 1605 1606 return 0; 1607 } 1608 1609 static int at91_adc_update_scan_mode(struct iio_dev *indio_dev, 1610 const unsigned long *scan_mask) 1611 { 1612 struct at91_adc_state *st = iio_priv(indio_dev); 1613 1614 if (bitmap_subset(scan_mask, &st->touch_st.channels_bitmask, 1615 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) 1616 return 0; 1617 /* 1618 * if the new bitmap is a combination of touchscreen and regular 1619 * channels, then we are not fine 1620 */ 1621 if (bitmap_intersects(&st->touch_st.channels_bitmask, scan_mask, 1622 AT91_SAMA5D2_MAX_CHAN_IDX + 1)) 1623 return -EINVAL; 1624 return 0; 1625 } 1626 1627 static void at91_adc_hw_init(struct at91_adc_state *st) 1628 { 1629 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST); 1630 at91_adc_writel(st, AT91_SAMA5D2_IDR, 0xffffffff); 1631 /* 1632 * Transfer field must be set to 2 according to the datasheet and 1633 * allows different analog settings for each channel. 1634 */ 1635 at91_adc_writel(st, AT91_SAMA5D2_MR, 1636 AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH); 1637 1638 at91_adc_setup_samp_freq(st, st->soc_info.min_sample_rate); 1639 1640 /* configure extended mode register */ 1641 at91_adc_config_emr(st); 1642 } 1643 1644 static ssize_t at91_adc_get_fifo_state(struct device *dev, 1645 struct device_attribute *attr, char *buf) 1646 { 1647 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1648 struct at91_adc_state *st = iio_priv(indio_dev); 1649 1650 return scnprintf(buf, PAGE_SIZE, "%d\n", !!st->dma_st.dma_chan); 1651 } 1652 1653 static ssize_t at91_adc_get_watermark(struct device *dev, 1654 struct device_attribute *attr, char *buf) 1655 { 1656 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1657 struct at91_adc_state *st = iio_priv(indio_dev); 1658 1659 return scnprintf(buf, PAGE_SIZE, "%d\n", st->dma_st.watermark); 1660 } 1661 1662 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444, 1663 at91_adc_get_fifo_state, NULL, 0); 1664 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444, 1665 at91_adc_get_watermark, NULL, 0); 1666 1667 static IIO_CONST_ATTR(hwfifo_watermark_min, "2"); 1668 static IIO_CONST_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR); 1669 1670 static IIO_CONST_ATTR(oversampling_ratio_available, 1671 __stringify(AT91_OSR_1SAMPLES) " " 1672 __stringify(AT91_OSR_4SAMPLES) " " 1673 __stringify(AT91_OSR_16SAMPLES)); 1674 1675 static struct attribute *at91_adc_attributes[] = { 1676 &iio_const_attr_oversampling_ratio_available.dev_attr.attr, 1677 NULL, 1678 }; 1679 1680 static const struct attribute_group at91_adc_attribute_group = { 1681 .attrs = at91_adc_attributes, 1682 }; 1683 1684 static const struct attribute *at91_adc_fifo_attributes[] = { 1685 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, 1686 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, 1687 &iio_dev_attr_hwfifo_watermark.dev_attr.attr, 1688 &iio_dev_attr_hwfifo_enabled.dev_attr.attr, 1689 NULL, 1690 }; 1691 1692 static const struct iio_info at91_adc_info = { 1693 .attrs = &at91_adc_attribute_group, 1694 .read_raw = &at91_adc_read_raw, 1695 .write_raw = &at91_adc_write_raw, 1696 .update_scan_mode = &at91_adc_update_scan_mode, 1697 .of_xlate = &at91_adc_of_xlate, 1698 .hwfifo_set_watermark = &at91_adc_set_watermark, 1699 }; 1700 1701 static int at91_adc_probe(struct platform_device *pdev) 1702 { 1703 struct iio_dev *indio_dev; 1704 struct at91_adc_state *st; 1705 struct resource *res; 1706 int ret, i; 1707 u32 edge_type = IRQ_TYPE_NONE; 1708 1709 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); 1710 if (!indio_dev) 1711 return -ENOMEM; 1712 1713 indio_dev->dev.parent = &pdev->dev; 1714 indio_dev->name = dev_name(&pdev->dev); 1715 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE; 1716 indio_dev->info = &at91_adc_info; 1717 indio_dev->channels = at91_adc_channels; 1718 indio_dev->num_channels = ARRAY_SIZE(at91_adc_channels); 1719 1720 st = iio_priv(indio_dev); 1721 1722 bitmap_set(&st->touch_st.channels_bitmask, 1723 AT91_SAMA5D2_TOUCH_X_CHAN_IDX, 1); 1724 bitmap_set(&st->touch_st.channels_bitmask, 1725 AT91_SAMA5D2_TOUCH_Y_CHAN_IDX, 1); 1726 bitmap_set(&st->touch_st.channels_bitmask, 1727 AT91_SAMA5D2_TOUCH_P_CHAN_IDX, 1); 1728 1729 st->oversampling_ratio = AT91_OSR_1SAMPLES; 1730 1731 ret = of_property_read_u32(pdev->dev.of_node, 1732 "atmel,min-sample-rate-hz", 1733 &st->soc_info.min_sample_rate); 1734 if (ret) { 1735 dev_err(&pdev->dev, 1736 "invalid or missing value for atmel,min-sample-rate-hz\n"); 1737 return ret; 1738 } 1739 1740 ret = of_property_read_u32(pdev->dev.of_node, 1741 "atmel,max-sample-rate-hz", 1742 &st->soc_info.max_sample_rate); 1743 if (ret) { 1744 dev_err(&pdev->dev, 1745 "invalid or missing value for atmel,max-sample-rate-hz\n"); 1746 return ret; 1747 } 1748 1749 ret = of_property_read_u32(pdev->dev.of_node, "atmel,startup-time-ms", 1750 &st->soc_info.startup_time); 1751 if (ret) { 1752 dev_err(&pdev->dev, 1753 "invalid or missing value for atmel,startup-time-ms\n"); 1754 return ret; 1755 } 1756 1757 ret = of_property_read_u32(pdev->dev.of_node, 1758 "atmel,trigger-edge-type", &edge_type); 1759 if (ret) { 1760 dev_dbg(&pdev->dev, 1761 "atmel,trigger-edge-type not specified, only software trigger available\n"); 1762 } 1763 1764 st->selected_trig = NULL; 1765 1766 /* find the right trigger, or no trigger at all */ 1767 for (i = 0; i < AT91_SAMA5D2_HW_TRIG_CNT + 1; i++) 1768 if (at91_adc_trigger_list[i].edge_type == edge_type) { 1769 st->selected_trig = &at91_adc_trigger_list[i]; 1770 break; 1771 } 1772 1773 if (!st->selected_trig) { 1774 dev_err(&pdev->dev, "invalid external trigger edge value\n"); 1775 return -EINVAL; 1776 } 1777 1778 init_waitqueue_head(&st->wq_data_available); 1779 mutex_init(&st->lock); 1780 INIT_WORK(&st->touch_st.workq, at91_adc_workq_handler); 1781 1782 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1783 if (!res) 1784 return -EINVAL; 1785 1786 /* if we plan to use DMA, we need the physical address of the regs */ 1787 st->dma_st.phys_addr = res->start; 1788 1789 st->base = devm_ioremap_resource(&pdev->dev, res); 1790 if (IS_ERR(st->base)) 1791 return PTR_ERR(st->base); 1792 1793 st->irq = platform_get_irq(pdev, 0); 1794 if (st->irq <= 0) { 1795 if (!st->irq) 1796 st->irq = -ENXIO; 1797 1798 return st->irq; 1799 } 1800 1801 st->per_clk = devm_clk_get(&pdev->dev, "adc_clk"); 1802 if (IS_ERR(st->per_clk)) 1803 return PTR_ERR(st->per_clk); 1804 1805 st->reg = devm_regulator_get(&pdev->dev, "vddana"); 1806 if (IS_ERR(st->reg)) 1807 return PTR_ERR(st->reg); 1808 1809 st->vref = devm_regulator_get(&pdev->dev, "vref"); 1810 if (IS_ERR(st->vref)) 1811 return PTR_ERR(st->vref); 1812 1813 ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0, 1814 pdev->dev.driver->name, indio_dev); 1815 if (ret) 1816 return ret; 1817 1818 ret = regulator_enable(st->reg); 1819 if (ret) 1820 return ret; 1821 1822 ret = regulator_enable(st->vref); 1823 if (ret) 1824 goto reg_disable; 1825 1826 st->vref_uv = regulator_get_voltage(st->vref); 1827 if (st->vref_uv <= 0) { 1828 ret = -EINVAL; 1829 goto vref_disable; 1830 } 1831 1832 at91_adc_hw_init(st); 1833 1834 ret = clk_prepare_enable(st->per_clk); 1835 if (ret) 1836 goto vref_disable; 1837 1838 platform_set_drvdata(pdev, indio_dev); 1839 1840 ret = at91_adc_buffer_init(indio_dev); 1841 if (ret < 0) { 1842 dev_err(&pdev->dev, "couldn't initialize the buffer.\n"); 1843 goto per_clk_disable_unprepare; 1844 } 1845 1846 if (st->selected_trig->hw_trig) { 1847 ret = at91_adc_trigger_init(indio_dev); 1848 if (ret < 0) { 1849 dev_err(&pdev->dev, "couldn't setup the triggers.\n"); 1850 goto per_clk_disable_unprepare; 1851 } 1852 /* 1853 * Initially the iio buffer has a length of 2 and 1854 * a watermark of 1 1855 */ 1856 st->dma_st.watermark = 1; 1857 1858 iio_buffer_set_attrs(indio_dev->buffer, 1859 at91_adc_fifo_attributes); 1860 } 1861 1862 if (dma_coerce_mask_and_coherent(&indio_dev->dev, DMA_BIT_MASK(32))) 1863 dev_info(&pdev->dev, "cannot set DMA mask to 32-bit\n"); 1864 1865 ret = iio_device_register(indio_dev); 1866 if (ret < 0) 1867 goto dma_disable; 1868 1869 if (st->selected_trig->hw_trig) 1870 dev_info(&pdev->dev, "setting up trigger as %s\n", 1871 st->selected_trig->name); 1872 1873 dev_info(&pdev->dev, "version: %x\n", 1874 readl_relaxed(st->base + AT91_SAMA5D2_VERSION)); 1875 1876 return 0; 1877 1878 dma_disable: 1879 at91_adc_dma_disable(pdev); 1880 per_clk_disable_unprepare: 1881 clk_disable_unprepare(st->per_clk); 1882 vref_disable: 1883 regulator_disable(st->vref); 1884 reg_disable: 1885 regulator_disable(st->reg); 1886 return ret; 1887 } 1888 1889 static int at91_adc_remove(struct platform_device *pdev) 1890 { 1891 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 1892 struct at91_adc_state *st = iio_priv(indio_dev); 1893 1894 iio_device_unregister(indio_dev); 1895 1896 at91_adc_dma_disable(pdev); 1897 1898 clk_disable_unprepare(st->per_clk); 1899 1900 regulator_disable(st->vref); 1901 regulator_disable(st->reg); 1902 1903 return 0; 1904 } 1905 1906 static __maybe_unused int at91_adc_suspend(struct device *dev) 1907 { 1908 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1909 struct at91_adc_state *st = iio_priv(indio_dev); 1910 1911 /* 1912 * Do a sofware reset of the ADC before we go to suspend. 1913 * this will ensure that all pins are free from being muxed by the ADC 1914 * and can be used by for other devices. 1915 * Otherwise, ADC will hog them and we can't go to suspend mode. 1916 */ 1917 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST); 1918 1919 clk_disable_unprepare(st->per_clk); 1920 regulator_disable(st->vref); 1921 regulator_disable(st->reg); 1922 1923 return pinctrl_pm_select_sleep_state(dev); 1924 } 1925 1926 static __maybe_unused int at91_adc_resume(struct device *dev) 1927 { 1928 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1929 struct at91_adc_state *st = iio_priv(indio_dev); 1930 int ret; 1931 1932 ret = pinctrl_pm_select_default_state(dev); 1933 if (ret) 1934 goto resume_failed; 1935 1936 ret = regulator_enable(st->reg); 1937 if (ret) 1938 goto resume_failed; 1939 1940 ret = regulator_enable(st->vref); 1941 if (ret) 1942 goto reg_disable_resume; 1943 1944 ret = clk_prepare_enable(st->per_clk); 1945 if (ret) 1946 goto vref_disable_resume; 1947 1948 at91_adc_hw_init(st); 1949 1950 /* reconfiguring trigger hardware state */ 1951 if (!iio_buffer_enabled(indio_dev)) 1952 return 0; 1953 1954 /* check if we are enabling triggered buffer or the touchscreen */ 1955 if (at91_adc_current_chan_is_touch(indio_dev)) 1956 return at91_adc_configure_touch(st, true); 1957 else 1958 return at91_adc_configure_trigger(st->trig, true); 1959 1960 /* not needed but more explicit */ 1961 return 0; 1962 1963 vref_disable_resume: 1964 regulator_disable(st->vref); 1965 reg_disable_resume: 1966 regulator_disable(st->reg); 1967 resume_failed: 1968 dev_err(&indio_dev->dev, "failed to resume\n"); 1969 return ret; 1970 } 1971 1972 static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume); 1973 1974 static const struct of_device_id at91_adc_dt_match[] = { 1975 { 1976 .compatible = "atmel,sama5d2-adc", 1977 }, { 1978 /* sentinel */ 1979 } 1980 }; 1981 MODULE_DEVICE_TABLE(of, at91_adc_dt_match); 1982 1983 static struct platform_driver at91_adc_driver = { 1984 .probe = at91_adc_probe, 1985 .remove = at91_adc_remove, 1986 .driver = { 1987 .name = "at91-sama5d2_adc", 1988 .of_match_table = at91_adc_dt_match, 1989 .pm = &at91_adc_pm_ops, 1990 }, 1991 }; 1992 module_platform_driver(at91_adc_driver) 1993 1994 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); 1995 MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC"); 1996 MODULE_LICENSE("GPL v2"); 1997