1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Atmel ADC driver for SAMA5D2 devices and compatible.
4  *
5  * Copyright (C) 2015 Atmel,
6  *               2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7  *		 2021 Microchip Technology, Inc. and its subsidiaries
8  *		 2021 Eugen Hristev <eugen.hristev@microchip.com>
9  */
10 
11 #include <linux/bitops.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/dmaengine.h>
16 #include <linux/interrupt.h>
17 #include <linux/io.h>
18 #include <linux/module.h>
19 #include <linux/of_device.h>
20 #include <linux/platform_device.h>
21 #include <linux/sched.h>
22 #include <linux/wait.h>
23 #include <linux/iio/iio.h>
24 #include <linux/iio/sysfs.h>
25 #include <linux/iio/buffer.h>
26 #include <linux/iio/trigger.h>
27 #include <linux/iio/trigger_consumer.h>
28 #include <linux/iio/triggered_buffer.h>
29 #include <linux/pinctrl/consumer.h>
30 #include <linux/regulator/consumer.h>
31 
32 struct at91_adc_reg_layout {
33 /* Control Register */
34 	u16				CR;
35 /* Software Reset */
36 #define	AT91_SAMA5D2_CR_SWRST		BIT(0)
37 /* Start Conversion */
38 #define	AT91_SAMA5D2_CR_START		BIT(1)
39 /* Touchscreen Calibration */
40 #define	AT91_SAMA5D2_CR_TSCALIB		BIT(2)
41 /* Comparison Restart */
42 #define	AT91_SAMA5D2_CR_CMPRST		BIT(4)
43 
44 /* Mode Register */
45 	u16				MR;
46 /* Trigger Selection */
47 #define	AT91_SAMA5D2_MR_TRGSEL(v)	((v) << 1)
48 /* ADTRG */
49 #define	AT91_SAMA5D2_MR_TRGSEL_TRIG0	0
50 /* TIOA0 */
51 #define	AT91_SAMA5D2_MR_TRGSEL_TRIG1	1
52 /* TIOA1 */
53 #define	AT91_SAMA5D2_MR_TRGSEL_TRIG2	2
54 /* TIOA2 */
55 #define	AT91_SAMA5D2_MR_TRGSEL_TRIG3	3
56 /* PWM event line 0 */
57 #define	AT91_SAMA5D2_MR_TRGSEL_TRIG4	4
58 /* PWM event line 1 */
59 #define	AT91_SAMA5D2_MR_TRGSEL_TRIG5	5
60 /* TIOA3 */
61 #define	AT91_SAMA5D2_MR_TRGSEL_TRIG6	6
62 /* RTCOUT0 */
63 #define	AT91_SAMA5D2_MR_TRGSEL_TRIG7	7
64 /* Sleep Mode */
65 #define	AT91_SAMA5D2_MR_SLEEP		BIT(5)
66 /* Fast Wake Up */
67 #define	AT91_SAMA5D2_MR_FWUP		BIT(6)
68 /* Prescaler Rate Selection */
69 #define	AT91_SAMA5D2_MR_PRESCAL(v)	((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET)
70 #define	AT91_SAMA5D2_MR_PRESCAL_OFFSET	8
71 #define	AT91_SAMA5D2_MR_PRESCAL_MAX	0xff
72 #define AT91_SAMA5D2_MR_PRESCAL_MASK	GENMASK(15, 8)
73 /* Startup Time */
74 #define	AT91_SAMA5D2_MR_STARTUP(v)	((v) << 16)
75 #define AT91_SAMA5D2_MR_STARTUP_MASK	GENMASK(19, 16)
76 /* Analog Change */
77 #define	AT91_SAMA5D2_MR_ANACH		BIT(23)
78 /* Tracking Time */
79 #define	AT91_SAMA5D2_MR_TRACKTIM(v)	((v) << 24)
80 #define	AT91_SAMA5D2_MR_TRACKTIM_MAX	0xff
81 /* Transfer Time */
82 #define	AT91_SAMA5D2_MR_TRANSFER(v)	((v) << 28)
83 #define	AT91_SAMA5D2_MR_TRANSFER_MAX	0x3
84 /* Use Sequence Enable */
85 #define	AT91_SAMA5D2_MR_USEQ		BIT(31)
86 
87 /* Channel Sequence Register 1 */
88 	u16				SEQR1;
89 /* Channel Sequence Register 2 */
90 	u16				SEQR2;
91 /* Channel Enable Register */
92 	u16				CHER;
93 /* Channel Disable Register */
94 	u16				CHDR;
95 /* Channel Status Register */
96 	u16				CHSR;
97 /* Last Converted Data Register */
98 	u16				LCDR;
99 /* Interrupt Enable Register */
100 	u16				IER;
101 /* Interrupt Enable Register - TS X measurement ready */
102 #define AT91_SAMA5D2_IER_XRDY   BIT(20)
103 /* Interrupt Enable Register - TS Y measurement ready */
104 #define AT91_SAMA5D2_IER_YRDY   BIT(21)
105 /* Interrupt Enable Register - TS pressure measurement ready */
106 #define AT91_SAMA5D2_IER_PRDY   BIT(22)
107 /* Interrupt Enable Register - Data ready */
108 #define AT91_SAMA5D2_IER_DRDY   BIT(24)
109 /* Interrupt Enable Register - general overrun error */
110 #define AT91_SAMA5D2_IER_GOVRE BIT(25)
111 /* Interrupt Enable Register - Pen detect */
112 #define AT91_SAMA5D2_IER_PEN    BIT(29)
113 /* Interrupt Enable Register - No pen detect */
114 #define AT91_SAMA5D2_IER_NOPEN  BIT(30)
115 
116 /* Interrupt Disable Register */
117 	u16				IDR;
118 /* Interrupt Mask Register */
119 	u16				IMR;
120 /* Interrupt Status Register */
121 	u16				ISR;
122 /* End of Conversion Interrupt Enable Register */
123 	u16				EOC_IER;
124 /* End of Conversion Interrupt Disable Register */
125 	u16				EOC_IDR;
126 /* End of Conversion Interrupt Mask Register */
127 	u16				EOC_IMR;
128 /* End of Conversion Interrupt Status Register */
129 	u16				EOC_ISR;
130 /* Interrupt Status Register - Pen touching sense status */
131 #define AT91_SAMA5D2_ISR_PENS   BIT(31)
132 /* Last Channel Trigger Mode Register */
133 	u16				LCTMR;
134 /* Last Channel Compare Window Register */
135 	u16				LCCWR;
136 /* Overrun Status Register */
137 	u16				OVER;
138 /* Extended Mode Register */
139 	u16				EMR;
140 /* Extended Mode Register - Oversampling rate */
141 #define AT91_SAMA5D2_EMR_OSR(V)			((V) << 16)
142 #define AT91_SAMA5D2_EMR_OSR_MASK		GENMASK(17, 16)
143 #define AT91_SAMA5D2_EMR_OSR_1SAMPLES		0
144 #define AT91_SAMA5D2_EMR_OSR_4SAMPLES		1
145 #define AT91_SAMA5D2_EMR_OSR_16SAMPLES		2
146 
147 /* Extended Mode Register - Averaging on single trigger event */
148 #define AT91_SAMA5D2_EMR_ASTE(V)		((V) << 20)
149 
150 /* Compare Window Register */
151 	u16				CWR;
152 /* Channel Gain Register */
153 	u16				CGR;
154 /* Channel Offset Register */
155 	u16				COR;
156 /* Channel Offset Register differential offset - constant, not a register */
157 	u16				COR_diff_offset;
158 /* Analog Control Register */
159 	u16				ACR;
160 /* Analog Control Register - Pen detect sensitivity mask */
161 #define AT91_SAMA5D2_ACR_PENDETSENS_MASK        GENMASK(1, 0)
162 
163 /* Touchscreen Mode Register */
164 	u16				TSMR;
165 /* Touchscreen Mode Register - No touch mode */
166 #define AT91_SAMA5D2_TSMR_TSMODE_NONE           0
167 /* Touchscreen Mode Register - 4 wire screen, no pressure measurement */
168 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_NO_PRESS 1
169 /* Touchscreen Mode Register - 4 wire screen, pressure measurement */
170 #define AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS    2
171 /* Touchscreen Mode Register - 5 wire screen */
172 #define AT91_SAMA5D2_TSMR_TSMODE_5WIRE          3
173 /* Touchscreen Mode Register - Average samples mask */
174 #define AT91_SAMA5D2_TSMR_TSAV_MASK             GENMASK(5, 4)
175 /* Touchscreen Mode Register - Average samples */
176 #define AT91_SAMA5D2_TSMR_TSAV(x)               ((x) << 4)
177 /* Touchscreen Mode Register - Touch/trigger frequency ratio mask */
178 #define AT91_SAMA5D2_TSMR_TSFREQ_MASK           GENMASK(11, 8)
179 /* Touchscreen Mode Register - Touch/trigger frequency ratio */
180 #define AT91_SAMA5D2_TSMR_TSFREQ(x)             ((x) << 8)
181 /* Touchscreen Mode Register - Pen Debounce Time mask */
182 #define AT91_SAMA5D2_TSMR_PENDBC_MASK           GENMASK(31, 28)
183 /* Touchscreen Mode Register - Pen Debounce Time */
184 #define AT91_SAMA5D2_TSMR_PENDBC(x)            ((x) << 28)
185 /* Touchscreen Mode Register - No DMA for touch measurements */
186 #define AT91_SAMA5D2_TSMR_NOTSDMA               BIT(22)
187 /* Touchscreen Mode Register - Disable pen detection */
188 #define AT91_SAMA5D2_TSMR_PENDET_DIS            (0 << 24)
189 /* Touchscreen Mode Register - Enable pen detection */
190 #define AT91_SAMA5D2_TSMR_PENDET_ENA            BIT(24)
191 
192 /* Touchscreen X Position Register */
193 	u16				XPOSR;
194 /* Touchscreen Y Position Register */
195 	u16				YPOSR;
196 /* Touchscreen Pressure Register */
197 	u16				PRESSR;
198 /* Trigger Register */
199 	u16				TRGR;
200 /* Mask for TRGMOD field of TRGR register */
201 #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0)
202 /* No trigger, only software trigger can start conversions */
203 #define AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER 0
204 /* Trigger Mode external trigger rising edge */
205 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE 1
206 /* Trigger Mode external trigger falling edge */
207 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL 2
208 /* Trigger Mode external trigger any edge */
209 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY 3
210 /* Trigger Mode internal periodic */
211 #define AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC 5
212 /* Trigger Mode - trigger period mask */
213 #define AT91_SAMA5D2_TRGR_TRGPER_MASK           GENMASK(31, 16)
214 /* Trigger Mode - trigger period */
215 #define AT91_SAMA5D2_TRGR_TRGPER(x)             ((x) << 16)
216 
217 /* Correction Select Register */
218 	u16				COSR;
219 /* Correction Value Register */
220 	u16				CVR;
221 /* Channel Error Correction Register */
222 	u16				CECR;
223 /* Write Protection Mode Register */
224 	u16				WPMR;
225 /* Write Protection Status Register */
226 	u16				WPSR;
227 /* Version Register */
228 	u16				VERSION;
229 };
230 
231 static const struct at91_adc_reg_layout sama5d2_layout = {
232 	.CR =			0x00,
233 	.MR =			0x04,
234 	.SEQR1 =		0x08,
235 	.SEQR2 =		0x0c,
236 	.CHER =			0x10,
237 	.CHDR =			0x14,
238 	.CHSR =			0x18,
239 	.LCDR =			0x20,
240 	.IER =			0x24,
241 	.IDR =			0x28,
242 	.IMR =			0x2c,
243 	.ISR =			0x30,
244 	.LCTMR =		0x34,
245 	.LCCWR =		0x38,
246 	.OVER =			0x3c,
247 	.EMR =			0x40,
248 	.CWR =			0x44,
249 	.CGR =			0x48,
250 	.COR =			0x4c,
251 	.COR_diff_offset =	16,
252 	.ACR =			0x94,
253 	.TSMR =			0xb0,
254 	.XPOSR =		0xb4,
255 	.YPOSR =		0xb8,
256 	.PRESSR =		0xbc,
257 	.TRGR =			0xc0,
258 	.COSR =			0xd0,
259 	.CVR =			0xd4,
260 	.CECR =			0xd8,
261 	.WPMR =			0xe4,
262 	.WPSR =			0xe8,
263 	.VERSION =		0xfc,
264 };
265 
266 static const struct at91_adc_reg_layout sama7g5_layout = {
267 	.CR =			0x00,
268 	.MR =			0x04,
269 	.SEQR1 =		0x08,
270 	.SEQR2 =		0x0c,
271 	.CHER =			0x10,
272 	.CHDR =			0x14,
273 	.CHSR =			0x18,
274 	.LCDR =			0x20,
275 	.IER =			0x24,
276 	.IDR =			0x28,
277 	.IMR =			0x2c,
278 	.ISR =			0x30,
279 	.EOC_IER =		0x34,
280 	.EOC_IDR =		0x38,
281 	.EOC_IMR =		0x3c,
282 	.EOC_ISR =		0x40,
283 	.OVER =			0x4c,
284 	.EMR =			0x50,
285 	.CWR =			0x54,
286 	.COR =			0x5c,
287 	.COR_diff_offset =	0,
288 	.ACR =			0xe0,
289 	.TRGR =			0x100,
290 	.COSR =			0x104,
291 	.CVR =			0x108,
292 	.CECR =			0x10c,
293 	.WPMR =			0x118,
294 	.WPSR =			0x11c,
295 	.VERSION =		0x130,
296 };
297 
298 #define AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US          2000    /* 2ms */
299 #define AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US    200
300 
301 #define AT91_SAMA5D2_XYZ_MASK		GENMASK(11, 0)
302 
303 #define AT91_SAMA5D2_MAX_POS_BITS			12
304 
305 #define AT91_HWFIFO_MAX_SIZE_STR	"128"
306 #define AT91_HWFIFO_MAX_SIZE		128
307 
308 /* Possible values for oversampling ratio */
309 #define AT91_OSR_1SAMPLES		1
310 #define AT91_OSR_4SAMPLES		4
311 #define AT91_OSR_16SAMPLES		16
312 
313 #define AT91_SAMA5D2_CHAN_SINGLE(index, num, addr)			\
314 	{								\
315 		.type = IIO_VOLTAGE,					\
316 		.channel = num,						\
317 		.address = addr,					\
318 		.scan_index = index,					\
319 		.scan_type = {						\
320 			.sign = 'u',					\
321 			.realbits = 14,					\
322 			.storagebits = 16,				\
323 		},							\
324 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
325 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
326 		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
327 				BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),	\
328 		.datasheet_name = "CH"#num,				\
329 		.indexed = 1,						\
330 	}
331 
332 #define AT91_SAMA5D2_CHAN_DIFF(index, num, num2, addr)			\
333 	{								\
334 		.type = IIO_VOLTAGE,					\
335 		.differential = 1,					\
336 		.channel = num,						\
337 		.channel2 = num2,					\
338 		.address = addr,					\
339 		.scan_index = index,					\
340 		.scan_type = {						\
341 			.sign = 's',					\
342 			.realbits = 14,					\
343 			.storagebits = 16,				\
344 		},							\
345 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
346 		.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),	\
347 		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
348 				BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),	\
349 		.datasheet_name = "CH"#num"-CH"#num2,			\
350 		.indexed = 1,						\
351 	}
352 
353 #define AT91_SAMA5D2_CHAN_TOUCH(num, name, mod)				\
354 	{								\
355 		.type = IIO_POSITIONRELATIVE,				\
356 		.modified = 1,						\
357 		.channel = num,						\
358 		.channel2 = mod,					\
359 		.scan_index = num,					\
360 		.scan_type = {						\
361 			.sign = 'u',					\
362 			.realbits = 12,					\
363 			.storagebits = 16,				\
364 		},							\
365 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
366 		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
367 				BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),	\
368 		.datasheet_name = name,					\
369 	}
370 #define AT91_SAMA5D2_CHAN_PRESSURE(num, name)				\
371 	{								\
372 		.type = IIO_PRESSURE,					\
373 		.channel = num,						\
374 		.scan_index = num,					\
375 		.scan_type = {						\
376 			.sign = 'u',					\
377 			.realbits = 12,					\
378 			.storagebits = 16,				\
379 		},							\
380 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW),		\
381 		.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ)|\
382 				BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO),	\
383 		.datasheet_name = name,					\
384 	}
385 
386 #define at91_adc_readl(st, reg)						\
387 	readl_relaxed((st)->base + (st)->soc_info.platform->layout->reg)
388 #define at91_adc_read_chan(st, reg)					\
389 	readl_relaxed((st)->base + reg)
390 #define at91_adc_writel(st, reg, val)					\
391 	writel_relaxed(val, (st)->base + (st)->soc_info.platform->layout->reg)
392 
393 /**
394  * struct at91_adc_platform - at91-sama5d2 platform information struct
395  * @layout:		pointer to the reg layout struct
396  * @adc_channels:	pointer to an array of channels for registering in
397  *			the iio subsystem
398  * @nr_channels:	number of physical channels available
399  * @touch_chan_x:	index of the touchscreen X channel
400  * @touch_chan_y:	index of the touchscreen Y channel
401  * @touch_chan_p:	index of the touchscreen P channel
402  * @max_channels:	number of total channels
403  * @max_index:		highest channel index (highest index may be higher
404  *			than the total channel number)
405  * @hw_trig_cnt:	number of possible hardware triggers
406  */
407 struct at91_adc_platform {
408 	const struct at91_adc_reg_layout	*layout;
409 	const struct iio_chan_spec		(*adc_channels)[];
410 	unsigned int				nr_channels;
411 	unsigned int				touch_chan_x;
412 	unsigned int				touch_chan_y;
413 	unsigned int				touch_chan_p;
414 	unsigned int				max_channels;
415 	unsigned int				max_index;
416 	unsigned int				hw_trig_cnt;
417 };
418 
419 /**
420  * struct at91_adc_soc_info - at91-sama5d2 soc information struct
421  * @startup_time:	device startup time
422  * @min_sample_rate:	minimum sample rate in Hz
423  * @max_sample_rate:	maximum sample rate in Hz
424  * @platform:		pointer to the platform structure
425  */
426 struct at91_adc_soc_info {
427 	unsigned			startup_time;
428 	unsigned			min_sample_rate;
429 	unsigned			max_sample_rate;
430 	const struct at91_adc_platform	*platform;
431 };
432 
433 struct at91_adc_trigger {
434 	char				*name;
435 	unsigned int			trgmod_value;
436 	unsigned int			edge_type;
437 	bool				hw_trig;
438 };
439 
440 /**
441  * struct at91_adc_dma - at91-sama5d2 dma information struct
442  * @dma_chan:		the dma channel acquired
443  * @rx_buf:		dma coherent allocated area
444  * @rx_dma_buf:		dma handler for the buffer
445  * @phys_addr:		physical address of the ADC base register
446  * @buf_idx:		index inside the dma buffer where reading was last done
447  * @rx_buf_sz:		size of buffer used by DMA operation
448  * @watermark:		number of conversions to copy before DMA triggers irq
449  * @dma_ts:		hold the start timestamp of dma operation
450  */
451 struct at91_adc_dma {
452 	struct dma_chan			*dma_chan;
453 	u8				*rx_buf;
454 	dma_addr_t			rx_dma_buf;
455 	phys_addr_t			phys_addr;
456 	int				buf_idx;
457 	int				rx_buf_sz;
458 	int				watermark;
459 	s64				dma_ts;
460 };
461 
462 /**
463  * struct at91_adc_touch - at91-sama5d2 touchscreen information struct
464  * @sample_period_val:		the value for periodic trigger interval
465  * @touching:			is the pen touching the screen or not
466  * @x_pos:			temporary placeholder for pressure computation
467  * @channels_bitmask:		bitmask with the touchscreen channels enabled
468  * @workq:			workqueue for buffer data pushing
469  */
470 struct at91_adc_touch {
471 	u16				sample_period_val;
472 	bool				touching;
473 	u16				x_pos;
474 	unsigned long			channels_bitmask;
475 	struct work_struct		workq;
476 };
477 
478 /*
479  * Buffer size requirements:
480  * No channels * bytes_per_channel(2) + timestamp bytes (8)
481  * Divided by 2 because we need half words.
482  * We assume 32 channels for now, has to be increased if needed.
483  * Nobody minds a buffer being too big.
484  */
485 #define AT91_BUFFER_MAX_HWORDS ((32 * 2 + 8) / 2)
486 
487 struct at91_adc_state {
488 	void __iomem			*base;
489 	int				irq;
490 	struct clk			*per_clk;
491 	struct regulator		*reg;
492 	struct regulator		*vref;
493 	int				vref_uv;
494 	unsigned int			current_sample_rate;
495 	struct iio_trigger		*trig;
496 	const struct at91_adc_trigger	*selected_trig;
497 	const struct iio_chan_spec	*chan;
498 	bool				conversion_done;
499 	u32				conversion_value;
500 	unsigned int			oversampling_ratio;
501 	struct at91_adc_soc_info	soc_info;
502 	wait_queue_head_t		wq_data_available;
503 	struct at91_adc_dma		dma_st;
504 	struct at91_adc_touch		touch_st;
505 	struct iio_dev			*indio_dev;
506 	/* Ensure naturally aligned timestamp */
507 	u16				buffer[AT91_BUFFER_MAX_HWORDS] __aligned(8);
508 	/*
509 	 * lock to prevent concurrent 'single conversion' requests through
510 	 * sysfs.
511 	 */
512 	struct mutex			lock;
513 };
514 
515 static const struct at91_adc_trigger at91_adc_trigger_list[] = {
516 	{
517 		.name = "external_rising",
518 		.trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE,
519 		.edge_type = IRQ_TYPE_EDGE_RISING,
520 		.hw_trig = true,
521 	},
522 	{
523 		.name = "external_falling",
524 		.trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL,
525 		.edge_type = IRQ_TYPE_EDGE_FALLING,
526 		.hw_trig = true,
527 	},
528 	{
529 		.name = "external_any",
530 		.trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY,
531 		.edge_type = IRQ_TYPE_EDGE_BOTH,
532 		.hw_trig = true,
533 	},
534 	{
535 		.name = "software",
536 		.trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER,
537 		.edge_type = IRQ_TYPE_NONE,
538 		.hw_trig = false,
539 	},
540 };
541 
542 static const struct iio_chan_spec at91_sama5d2_adc_channels[] = {
543 	AT91_SAMA5D2_CHAN_SINGLE(0, 0, 0x50),
544 	AT91_SAMA5D2_CHAN_SINGLE(1, 1, 0x54),
545 	AT91_SAMA5D2_CHAN_SINGLE(2, 2, 0x58),
546 	AT91_SAMA5D2_CHAN_SINGLE(3, 3, 0x5c),
547 	AT91_SAMA5D2_CHAN_SINGLE(4, 4, 0x60),
548 	AT91_SAMA5D2_CHAN_SINGLE(5, 5, 0x64),
549 	AT91_SAMA5D2_CHAN_SINGLE(6, 6, 0x68),
550 	AT91_SAMA5D2_CHAN_SINGLE(7, 7, 0x6c),
551 	AT91_SAMA5D2_CHAN_SINGLE(8, 8, 0x70),
552 	AT91_SAMA5D2_CHAN_SINGLE(9, 9, 0x74),
553 	AT91_SAMA5D2_CHAN_SINGLE(10, 10, 0x78),
554 	AT91_SAMA5D2_CHAN_SINGLE(11, 11, 0x7c),
555 	/* original ABI has the differential channels with a gap in between */
556 	AT91_SAMA5D2_CHAN_DIFF(12, 0, 1, 0x50),
557 	AT91_SAMA5D2_CHAN_DIFF(14, 2, 3, 0x58),
558 	AT91_SAMA5D2_CHAN_DIFF(16, 4, 5, 0x60),
559 	AT91_SAMA5D2_CHAN_DIFF(18, 6, 7, 0x68),
560 	AT91_SAMA5D2_CHAN_DIFF(20, 8, 9, 0x70),
561 	AT91_SAMA5D2_CHAN_DIFF(22, 10, 11, 0x78),
562 	IIO_CHAN_SOFT_TIMESTAMP(23),
563 	AT91_SAMA5D2_CHAN_TOUCH(24, "x", IIO_MOD_X),
564 	AT91_SAMA5D2_CHAN_TOUCH(25, "y", IIO_MOD_Y),
565 	AT91_SAMA5D2_CHAN_PRESSURE(26, "pressure"),
566 };
567 
568 static const struct iio_chan_spec at91_sama7g5_adc_channels[] = {
569 	AT91_SAMA5D2_CHAN_SINGLE(0, 0, 0x60),
570 	AT91_SAMA5D2_CHAN_SINGLE(1, 1, 0x64),
571 	AT91_SAMA5D2_CHAN_SINGLE(2, 2, 0x68),
572 	AT91_SAMA5D2_CHAN_SINGLE(3, 3, 0x6c),
573 	AT91_SAMA5D2_CHAN_SINGLE(4, 4, 0x70),
574 	AT91_SAMA5D2_CHAN_SINGLE(5, 5, 0x74),
575 	AT91_SAMA5D2_CHAN_SINGLE(6, 6, 0x78),
576 	AT91_SAMA5D2_CHAN_SINGLE(7, 7, 0x7c),
577 	AT91_SAMA5D2_CHAN_SINGLE(8, 8, 0x80),
578 	AT91_SAMA5D2_CHAN_SINGLE(9, 9, 0x84),
579 	AT91_SAMA5D2_CHAN_SINGLE(10, 10, 0x88),
580 	AT91_SAMA5D2_CHAN_SINGLE(11, 11, 0x8c),
581 	AT91_SAMA5D2_CHAN_SINGLE(12, 12, 0x90),
582 	AT91_SAMA5D2_CHAN_SINGLE(13, 13, 0x94),
583 	AT91_SAMA5D2_CHAN_SINGLE(14, 14, 0x98),
584 	AT91_SAMA5D2_CHAN_SINGLE(15, 15, 0x9c),
585 	AT91_SAMA5D2_CHAN_DIFF(16, 0, 1, 0x60),
586 	AT91_SAMA5D2_CHAN_DIFF(17, 2, 3, 0x68),
587 	AT91_SAMA5D2_CHAN_DIFF(18, 4, 5, 0x70),
588 	AT91_SAMA5D2_CHAN_DIFF(19, 6, 7, 0x78),
589 	AT91_SAMA5D2_CHAN_DIFF(20, 8, 9, 0x80),
590 	AT91_SAMA5D2_CHAN_DIFF(21, 10, 11, 0x88),
591 	AT91_SAMA5D2_CHAN_DIFF(22, 12, 13, 0x90),
592 	AT91_SAMA5D2_CHAN_DIFF(23, 14, 15, 0x98),
593 	IIO_CHAN_SOFT_TIMESTAMP(24),
594 };
595 
596 static const struct at91_adc_platform sama5d2_platform = {
597 	.layout = &sama5d2_layout,
598 	.adc_channels = &at91_sama5d2_adc_channels,
599 #define AT91_SAMA5D2_SINGLE_CHAN_CNT 12
600 #define AT91_SAMA5D2_DIFF_CHAN_CNT 6
601 	.nr_channels = AT91_SAMA5D2_SINGLE_CHAN_CNT +
602 		       AT91_SAMA5D2_DIFF_CHAN_CNT,
603 #define AT91_SAMA5D2_TOUCH_X_CHAN_IDX	(AT91_SAMA5D2_SINGLE_CHAN_CNT + \
604 					AT91_SAMA5D2_DIFF_CHAN_CNT * 2)
605 	.touch_chan_x = AT91_SAMA5D2_TOUCH_X_CHAN_IDX,
606 #define AT91_SAMA5D2_TOUCH_Y_CHAN_IDX	(AT91_SAMA5D2_TOUCH_X_CHAN_IDX + 1)
607 	.touch_chan_y = AT91_SAMA5D2_TOUCH_Y_CHAN_IDX,
608 #define AT91_SAMA5D2_TOUCH_P_CHAN_IDX	(AT91_SAMA5D2_TOUCH_Y_CHAN_IDX + 1)
609 	.touch_chan_p = AT91_SAMA5D2_TOUCH_P_CHAN_IDX,
610 #define AT91_SAMA5D2_MAX_CHAN_IDX	AT91_SAMA5D2_TOUCH_P_CHAN_IDX
611 	.max_channels = ARRAY_SIZE(at91_sama5d2_adc_channels),
612 	.max_index = AT91_SAMA5D2_MAX_CHAN_IDX,
613 #define AT91_SAMA5D2_HW_TRIG_CNT	3
614 	.hw_trig_cnt = AT91_SAMA5D2_HW_TRIG_CNT,
615 };
616 
617 static const struct at91_adc_platform sama7g5_platform = {
618 	.layout = &sama7g5_layout,
619 	.adc_channels = &at91_sama7g5_adc_channels,
620 #define AT91_SAMA7G5_SINGLE_CHAN_CNT	16
621 #define AT91_SAMA7G5_DIFF_CHAN_CNT	8
622 	.nr_channels = AT91_SAMA7G5_SINGLE_CHAN_CNT +
623 		       AT91_SAMA7G5_DIFF_CHAN_CNT,
624 #define AT91_SAMA7G5_MAX_CHAN_IDX	(AT91_SAMA7G5_SINGLE_CHAN_CNT + \
625 					AT91_SAMA7G5_DIFF_CHAN_CNT)
626 	.max_channels = ARRAY_SIZE(at91_sama7g5_adc_channels),
627 	.max_index = AT91_SAMA7G5_MAX_CHAN_IDX,
628 #define AT91_SAMA7G5_HW_TRIG_CNT	3
629 	.hw_trig_cnt = AT91_SAMA7G5_HW_TRIG_CNT,
630 };
631 
632 static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan)
633 {
634 	int i;
635 
636 	for (i = 0; i < indio_dev->num_channels; i++) {
637 		if (indio_dev->channels[i].scan_index == chan)
638 			return i;
639 	}
640 	return -EINVAL;
641 }
642 
643 static inline struct iio_chan_spec const *
644 at91_adc_chan_get(struct iio_dev *indio_dev, int chan)
645 {
646 	int index = at91_adc_chan_xlate(indio_dev, chan);
647 
648 	if (index < 0)
649 		return NULL;
650 	return indio_dev->channels + index;
651 }
652 
653 static inline int at91_adc_of_xlate(struct iio_dev *indio_dev,
654 				    const struct of_phandle_args *iiospec)
655 {
656 	return at91_adc_chan_xlate(indio_dev, iiospec->args[0]);
657 }
658 
659 static unsigned int at91_adc_active_scan_mask_to_reg(struct iio_dev *indio_dev)
660 {
661 	u32 mask = 0;
662 	u8 bit;
663 	struct at91_adc_state *st = iio_priv(indio_dev);
664 
665 	for_each_set_bit(bit, indio_dev->active_scan_mask,
666 			 indio_dev->num_channels) {
667 		struct iio_chan_spec const *chan =
668 			 at91_adc_chan_get(indio_dev, bit);
669 		mask |= BIT(chan->channel);
670 	}
671 
672 	return mask & GENMASK(st->soc_info.platform->nr_channels, 0);
673 }
674 
675 static void at91_adc_cor(struct at91_adc_state *st,
676 			 struct iio_chan_spec const *chan)
677 {
678 	u32 cor, cur_cor;
679 
680 	cor = BIT(chan->channel) | BIT(chan->channel2);
681 
682 	cur_cor = at91_adc_readl(st, COR);
683 	cor <<= st->soc_info.platform->layout->COR_diff_offset;
684 	if (chan->differential)
685 		at91_adc_writel(st, COR, cur_cor | cor);
686 	else
687 		at91_adc_writel(st, COR, cur_cor & ~cor);
688 }
689 
690 static void at91_adc_irq_status(struct at91_adc_state *st, u32 *status,
691 				u32 *eoc)
692 {
693 	*status = at91_adc_readl(st, ISR);
694 	if (st->soc_info.platform->layout->EOC_ISR)
695 		*eoc = at91_adc_readl(st, EOC_ISR);
696 	else
697 		*eoc = *status;
698 }
699 
700 static void at91_adc_irq_mask(struct at91_adc_state *st, u32 *status, u32 *eoc)
701 {
702 	*status = at91_adc_readl(st, IMR);
703 	if (st->soc_info.platform->layout->EOC_IMR)
704 		*eoc = at91_adc_readl(st, EOC_IMR);
705 	else
706 		*eoc = *status;
707 }
708 
709 static void at91_adc_eoc_dis(struct at91_adc_state *st, unsigned int channel)
710 {
711 	/*
712 	 * On some products having the EOC bits in a separate register,
713 	 * errata recommends not writing this register (EOC_IDR).
714 	 * On products having the EOC bits in the IDR register, it's fine to write it.
715 	 */
716 	if (!st->soc_info.platform->layout->EOC_IDR)
717 		at91_adc_writel(st, IDR, BIT(channel));
718 }
719 
720 static void at91_adc_eoc_ena(struct at91_adc_state *st, unsigned int channel)
721 {
722 	if (!st->soc_info.platform->layout->EOC_IDR)
723 		at91_adc_writel(st, IER, BIT(channel));
724 	else
725 		at91_adc_writel(st, EOC_IER, BIT(channel));
726 }
727 
728 static void at91_adc_config_emr(struct at91_adc_state *st)
729 {
730 	/* configure the extended mode register */
731 	unsigned int emr = at91_adc_readl(st, EMR);
732 
733 	/* select oversampling per single trigger event */
734 	emr |= AT91_SAMA5D2_EMR_ASTE(1);
735 
736 	/* delete leftover content if it's the case */
737 	emr &= ~AT91_SAMA5D2_EMR_OSR_MASK;
738 
739 	/* select oversampling ratio from configuration */
740 	switch (st->oversampling_ratio) {
741 	case AT91_OSR_1SAMPLES:
742 		emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_1SAMPLES) &
743 		       AT91_SAMA5D2_EMR_OSR_MASK;
744 		break;
745 	case AT91_OSR_4SAMPLES:
746 		emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_4SAMPLES) &
747 		       AT91_SAMA5D2_EMR_OSR_MASK;
748 		break;
749 	case AT91_OSR_16SAMPLES:
750 		emr |= AT91_SAMA5D2_EMR_OSR(AT91_SAMA5D2_EMR_OSR_16SAMPLES) &
751 		       AT91_SAMA5D2_EMR_OSR_MASK;
752 		break;
753 	}
754 
755 	at91_adc_writel(st, EMR, emr);
756 }
757 
758 static int at91_adc_adjust_val_osr(struct at91_adc_state *st, int *val)
759 {
760 	if (st->oversampling_ratio == AT91_OSR_1SAMPLES) {
761 		/*
762 		 * in this case we only have 12 bits of real data, but channel
763 		 * is registered as 14 bits, so shift left two bits
764 		 */
765 		*val <<= 2;
766 	} else if (st->oversampling_ratio == AT91_OSR_4SAMPLES) {
767 		/*
768 		 * in this case we have 13 bits of real data, but channel
769 		 * is registered as 14 bits, so left shift one bit
770 		 */
771 		*val <<= 1;
772 	}
773 
774 	return IIO_VAL_INT;
775 }
776 
777 static void at91_adc_adjust_val_osr_array(struct at91_adc_state *st, void *buf,
778 					  int len)
779 {
780 	int i = 0, val;
781 	u16 *buf_u16 = (u16 *) buf;
782 
783 	/*
784 	 * We are converting each two bytes (each sample).
785 	 * First convert the byte based array to u16, and convert each sample
786 	 * separately.
787 	 * Each value is two bytes in an array of chars, so to not shift
788 	 * more than we need, save the value separately.
789 	 * len is in bytes, so divide by two to get number of samples.
790 	 */
791 	while (i < len / 2) {
792 		val = buf_u16[i];
793 		at91_adc_adjust_val_osr(st, &val);
794 		buf_u16[i] = val;
795 		i++;
796 	}
797 }
798 
799 static int at91_adc_configure_touch(struct at91_adc_state *st, bool state)
800 {
801 	u32 clk_khz = st->current_sample_rate / 1000;
802 	int i = 0;
803 	u16 pendbc;
804 	u32 tsmr, acr;
805 
806 	if (!state) {
807 		/* disabling touch IRQs and setting mode to no touch enabled */
808 		at91_adc_writel(st, IDR,
809 				AT91_SAMA5D2_IER_PEN | AT91_SAMA5D2_IER_NOPEN);
810 		at91_adc_writel(st, TSMR, 0);
811 		return 0;
812 	}
813 	/*
814 	 * debounce time is in microseconds, we need it in milliseconds to
815 	 * multiply with kilohertz, so, divide by 1000, but after the multiply.
816 	 * round up to make sure pendbc is at least 1
817 	 */
818 	pendbc = round_up(AT91_SAMA5D2_TOUCH_PEN_DETECT_DEBOUNCE_US *
819 			  clk_khz / 1000, 1);
820 
821 	/* get the required exponent */
822 	while (pendbc >> i++)
823 		;
824 
825 	pendbc = i;
826 
827 	tsmr = AT91_SAMA5D2_TSMR_TSMODE_4WIRE_PRESS;
828 
829 	tsmr |= AT91_SAMA5D2_TSMR_TSAV(2) & AT91_SAMA5D2_TSMR_TSAV_MASK;
830 	tsmr |= AT91_SAMA5D2_TSMR_PENDBC(pendbc) &
831 		AT91_SAMA5D2_TSMR_PENDBC_MASK;
832 	tsmr |= AT91_SAMA5D2_TSMR_NOTSDMA;
833 	tsmr |= AT91_SAMA5D2_TSMR_PENDET_ENA;
834 	tsmr |= AT91_SAMA5D2_TSMR_TSFREQ(2) & AT91_SAMA5D2_TSMR_TSFREQ_MASK;
835 
836 	at91_adc_writel(st, TSMR, tsmr);
837 
838 	acr =  at91_adc_readl(st, ACR);
839 	acr &= ~AT91_SAMA5D2_ACR_PENDETSENS_MASK;
840 	acr |= 0x02 & AT91_SAMA5D2_ACR_PENDETSENS_MASK;
841 	at91_adc_writel(st, ACR, acr);
842 
843 	/* Sample Period Time = (TRGPER + 1) / ADCClock */
844 	st->touch_st.sample_period_val =
845 				 round_up((AT91_SAMA5D2_TOUCH_SAMPLE_PERIOD_US *
846 				 clk_khz / 1000) - 1, 1);
847 	/* enable pen detect IRQ */
848 	at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN);
849 
850 	return 0;
851 }
852 
853 static u16 at91_adc_touch_pos(struct at91_adc_state *st, int reg)
854 {
855 	u32 val = 0;
856 	u32 scale, result, pos;
857 
858 	/*
859 	 * to obtain the actual position we must divide by scale
860 	 * and multiply with max, where
861 	 * max = 2^AT91_SAMA5D2_MAX_POS_BITS - 1
862 	 */
863 	/* first half of register is the x or y, second half is the scale */
864 	if (reg == st->soc_info.platform->layout->XPOSR)
865 		val = at91_adc_readl(st, XPOSR);
866 	else if (reg == st->soc_info.platform->layout->YPOSR)
867 		val = at91_adc_readl(st, YPOSR);
868 
869 	if (!val)
870 		dev_dbg(&st->indio_dev->dev, "pos is 0\n");
871 
872 	pos = val & AT91_SAMA5D2_XYZ_MASK;
873 	result = (pos << AT91_SAMA5D2_MAX_POS_BITS) - pos;
874 	scale = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
875 	if (scale == 0) {
876 		dev_err(&st->indio_dev->dev, "scale is 0\n");
877 		return 0;
878 	}
879 	result /= scale;
880 
881 	return result;
882 }
883 
884 static u16 at91_adc_touch_x_pos(struct at91_adc_state *st)
885 {
886 	st->touch_st.x_pos = at91_adc_touch_pos(st, st->soc_info.platform->layout->XPOSR);
887 	return st->touch_st.x_pos;
888 }
889 
890 static u16 at91_adc_touch_y_pos(struct at91_adc_state *st)
891 {
892 	return at91_adc_touch_pos(st, st->soc_info.platform->layout->YPOSR);
893 }
894 
895 static u16 at91_adc_touch_pressure(struct at91_adc_state *st)
896 {
897 	u32 val;
898 	u32 z1, z2;
899 	u32 pres;
900 	u32 rxp = 1;
901 	u32 factor = 1000;
902 
903 	/* calculate the pressure */
904 	val = at91_adc_readl(st, PRESSR);
905 	z1 = val & AT91_SAMA5D2_XYZ_MASK;
906 	z2 = (val >> 16) & AT91_SAMA5D2_XYZ_MASK;
907 
908 	if (z1 != 0)
909 		pres = rxp * (st->touch_st.x_pos * factor / 1024) *
910 			(z2 * factor / z1 - factor) /
911 			factor;
912 	else
913 		pres = 0xFFFF;       /* no pen contact */
914 
915 	/*
916 	 * The pressure from device grows down, minimum is 0xFFFF, maximum 0x0.
917 	 * We compute it this way, but let's return it in the expected way,
918 	 * growing from 0 to 0xFFFF.
919 	 */
920 	return 0xFFFF - pres;
921 }
922 
923 static int at91_adc_read_position(struct at91_adc_state *st, int chan, u16 *val)
924 {
925 	*val = 0;
926 	if (!st->touch_st.touching)
927 		return -ENODATA;
928 	if (chan == st->soc_info.platform->touch_chan_x)
929 		*val = at91_adc_touch_x_pos(st);
930 	else if (chan == st->soc_info.platform->touch_chan_y)
931 		*val = at91_adc_touch_y_pos(st);
932 	else
933 		return -ENODATA;
934 
935 	return IIO_VAL_INT;
936 }
937 
938 static int at91_adc_read_pressure(struct at91_adc_state *st, int chan, u16 *val)
939 {
940 	*val = 0;
941 	if (!st->touch_st.touching)
942 		return -ENODATA;
943 	if (chan == st->soc_info.platform->touch_chan_p)
944 		*val = at91_adc_touch_pressure(st);
945 	else
946 		return -ENODATA;
947 
948 	return IIO_VAL_INT;
949 }
950 
951 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
952 {
953 	struct iio_dev *indio = iio_trigger_get_drvdata(trig);
954 	struct at91_adc_state *st = iio_priv(indio);
955 	u32 status = at91_adc_readl(st, TRGR);
956 
957 	/* clear TRGMOD */
958 	status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK;
959 
960 	if (state)
961 		status |= st->selected_trig->trgmod_value;
962 
963 	/* set/unset hw trigger */
964 	at91_adc_writel(st, TRGR, status);
965 
966 	return 0;
967 }
968 
969 static void at91_adc_reenable_trigger(struct iio_trigger *trig)
970 {
971 	struct iio_dev *indio = iio_trigger_get_drvdata(trig);
972 	struct at91_adc_state *st = iio_priv(indio);
973 
974 	/* if we are using DMA, we must not reenable irq after each trigger */
975 	if (st->dma_st.dma_chan)
976 		return;
977 
978 	enable_irq(st->irq);
979 
980 	/* Needed to ACK the DRDY interruption */
981 	at91_adc_readl(st, LCDR);
982 }
983 
984 static const struct iio_trigger_ops at91_adc_trigger_ops = {
985 	.set_trigger_state = &at91_adc_configure_trigger,
986 	.reenable = &at91_adc_reenable_trigger,
987 	.validate_device = iio_trigger_validate_own_device,
988 };
989 
990 static int at91_adc_dma_size_done(struct at91_adc_state *st)
991 {
992 	struct dma_tx_state state;
993 	enum dma_status status;
994 	int i, size;
995 
996 	status = dmaengine_tx_status(st->dma_st.dma_chan,
997 				     st->dma_st.dma_chan->cookie,
998 				     &state);
999 	if (status != DMA_IN_PROGRESS)
1000 		return 0;
1001 
1002 	/* Transferred length is size in bytes from end of buffer */
1003 	i = st->dma_st.rx_buf_sz - state.residue;
1004 
1005 	/* Return available bytes */
1006 	if (i >= st->dma_st.buf_idx)
1007 		size = i - st->dma_st.buf_idx;
1008 	else
1009 		size = st->dma_st.rx_buf_sz + i - st->dma_st.buf_idx;
1010 	return size;
1011 }
1012 
1013 static void at91_dma_buffer_done(void *data)
1014 {
1015 	struct iio_dev *indio_dev = data;
1016 
1017 	iio_trigger_poll_chained(indio_dev->trig);
1018 }
1019 
1020 static int at91_adc_dma_start(struct iio_dev *indio_dev)
1021 {
1022 	struct at91_adc_state *st = iio_priv(indio_dev);
1023 	struct dma_async_tx_descriptor *desc;
1024 	dma_cookie_t cookie;
1025 	int ret;
1026 	u8 bit;
1027 
1028 	if (!st->dma_st.dma_chan)
1029 		return 0;
1030 
1031 	/* we start a new DMA, so set buffer index to start */
1032 	st->dma_st.buf_idx = 0;
1033 
1034 	/*
1035 	 * compute buffer size w.r.t. watermark and enabled channels.
1036 	 * scan_bytes is aligned so we need an exact size for DMA
1037 	 */
1038 	st->dma_st.rx_buf_sz = 0;
1039 
1040 	for_each_set_bit(bit, indio_dev->active_scan_mask,
1041 			 indio_dev->num_channels) {
1042 		struct iio_chan_spec const *chan =
1043 					 at91_adc_chan_get(indio_dev, bit);
1044 
1045 		if (!chan)
1046 			continue;
1047 
1048 		st->dma_st.rx_buf_sz += chan->scan_type.storagebits / 8;
1049 	}
1050 	st->dma_st.rx_buf_sz *= st->dma_st.watermark;
1051 
1052 	/* Prepare a DMA cyclic transaction */
1053 	desc = dmaengine_prep_dma_cyclic(st->dma_st.dma_chan,
1054 					 st->dma_st.rx_dma_buf,
1055 					 st->dma_st.rx_buf_sz,
1056 					 st->dma_st.rx_buf_sz / 2,
1057 					 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1058 
1059 	if (!desc) {
1060 		dev_err(&indio_dev->dev, "cannot prepare DMA cyclic\n");
1061 		return -EBUSY;
1062 	}
1063 
1064 	desc->callback = at91_dma_buffer_done;
1065 	desc->callback_param = indio_dev;
1066 
1067 	cookie = dmaengine_submit(desc);
1068 	ret = dma_submit_error(cookie);
1069 	if (ret) {
1070 		dev_err(&indio_dev->dev, "cannot submit DMA cyclic\n");
1071 		dmaengine_terminate_async(st->dma_st.dma_chan);
1072 		return ret;
1073 	}
1074 
1075 	/* enable general overrun error signaling */
1076 	at91_adc_writel(st, IER, AT91_SAMA5D2_IER_GOVRE);
1077 	/* Issue pending DMA requests */
1078 	dma_async_issue_pending(st->dma_st.dma_chan);
1079 
1080 	/* consider current time as DMA start time for timestamps */
1081 	st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
1082 
1083 	dev_dbg(&indio_dev->dev, "DMA cyclic started\n");
1084 
1085 	return 0;
1086 }
1087 
1088 static bool at91_adc_buffer_check_use_irq(struct iio_dev *indio,
1089 					  struct at91_adc_state *st)
1090 {
1091 	/* if using DMA, we do not use our own IRQ (we use DMA-controller) */
1092 	if (st->dma_st.dma_chan)
1093 		return false;
1094 	/* if the trigger is not ours, then it has its own IRQ */
1095 	if (iio_trigger_validate_own_device(indio->trig, indio))
1096 		return false;
1097 	return true;
1098 }
1099 
1100 static bool at91_adc_current_chan_is_touch(struct iio_dev *indio_dev)
1101 {
1102 	struct at91_adc_state *st = iio_priv(indio_dev);
1103 
1104 	return !!bitmap_subset(indio_dev->active_scan_mask,
1105 			       &st->touch_st.channels_bitmask,
1106 			       st->soc_info.platform->max_index + 1);
1107 }
1108 
1109 static int at91_adc_buffer_prepare(struct iio_dev *indio_dev)
1110 {
1111 	int ret;
1112 	u8 bit;
1113 	struct at91_adc_state *st = iio_priv(indio_dev);
1114 
1115 	/* check if we are enabling triggered buffer or the touchscreen */
1116 	if (at91_adc_current_chan_is_touch(indio_dev))
1117 		return at91_adc_configure_touch(st, true);
1118 
1119 	/* if we are not in triggered mode, we cannot enable the buffer. */
1120 	if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES))
1121 		return -EINVAL;
1122 
1123 	/* we continue with the triggered buffer */
1124 	ret = at91_adc_dma_start(indio_dev);
1125 	if (ret) {
1126 		dev_err(&indio_dev->dev, "buffer prepare failed\n");
1127 		return ret;
1128 	}
1129 
1130 	for_each_set_bit(bit, indio_dev->active_scan_mask,
1131 			 indio_dev->num_channels) {
1132 		struct iio_chan_spec const *chan =
1133 					at91_adc_chan_get(indio_dev, bit);
1134 		if (!chan)
1135 			continue;
1136 		/* these channel types cannot be handled by this trigger */
1137 		if (chan->type == IIO_POSITIONRELATIVE ||
1138 		    chan->type == IIO_PRESSURE)
1139 			continue;
1140 
1141 		at91_adc_cor(st, chan);
1142 
1143 		at91_adc_writel(st, CHER, BIT(chan->channel));
1144 	}
1145 
1146 	if (at91_adc_buffer_check_use_irq(indio_dev, st))
1147 		at91_adc_writel(st, IER, AT91_SAMA5D2_IER_DRDY);
1148 
1149 	return 0;
1150 }
1151 
1152 static int at91_adc_buffer_postdisable(struct iio_dev *indio_dev)
1153 {
1154 	struct at91_adc_state *st = iio_priv(indio_dev);
1155 	u8 bit;
1156 
1157 	/* check if we are disabling triggered buffer or the touchscreen */
1158 	if (at91_adc_current_chan_is_touch(indio_dev))
1159 		return at91_adc_configure_touch(st, false);
1160 
1161 	/* if we are not in triggered mode, nothing to do here */
1162 	if (!(indio_dev->currentmode & INDIO_ALL_TRIGGERED_MODES))
1163 		return -EINVAL;
1164 
1165 	/*
1166 	 * For each enable channel we must disable it in hardware.
1167 	 * In the case of DMA, we must read the last converted value
1168 	 * to clear EOC status and not get a possible interrupt later.
1169 	 * This value is being read by DMA from LCDR anyway, so it's not lost.
1170 	 */
1171 	for_each_set_bit(bit, indio_dev->active_scan_mask,
1172 			 indio_dev->num_channels) {
1173 		struct iio_chan_spec const *chan =
1174 					at91_adc_chan_get(indio_dev, bit);
1175 
1176 		if (!chan)
1177 			continue;
1178 		/* these channel types are virtual, no need to do anything */
1179 		if (chan->type == IIO_POSITIONRELATIVE ||
1180 		    chan->type == IIO_PRESSURE)
1181 			continue;
1182 
1183 		at91_adc_writel(st, CHDR, BIT(chan->channel));
1184 
1185 		if (st->dma_st.dma_chan)
1186 			at91_adc_read_chan(st, chan->address);
1187 	}
1188 
1189 	if (at91_adc_buffer_check_use_irq(indio_dev, st))
1190 		at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_DRDY);
1191 
1192 	/* read overflow register to clear possible overflow status */
1193 	at91_adc_readl(st, OVER);
1194 
1195 	/* if we are using DMA we must clear registers and end DMA */
1196 	if (st->dma_st.dma_chan)
1197 		dmaengine_terminate_sync(st->dma_st.dma_chan);
1198 
1199 	return 0;
1200 }
1201 
1202 static const struct iio_buffer_setup_ops at91_buffer_setup_ops = {
1203 	.postdisable = &at91_adc_buffer_postdisable,
1204 };
1205 
1206 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio,
1207 						     char *trigger_name)
1208 {
1209 	struct iio_trigger *trig;
1210 	int ret;
1211 
1212 	trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name,
1213 				iio_device_id(indio), trigger_name);
1214 	if (!trig)
1215 		return NULL;
1216 
1217 	trig->dev.parent = indio->dev.parent;
1218 	iio_trigger_set_drvdata(trig, indio);
1219 	trig->ops = &at91_adc_trigger_ops;
1220 
1221 	ret = devm_iio_trigger_register(&indio->dev, trig);
1222 	if (ret)
1223 		return ERR_PTR(ret);
1224 
1225 	return trig;
1226 }
1227 static void at91_adc_trigger_handler_nodma(struct iio_dev *indio_dev,
1228 					   struct iio_poll_func *pf)
1229 {
1230 	struct at91_adc_state *st = iio_priv(indio_dev);
1231 	int i = 0;
1232 	int val;
1233 	u8 bit;
1234 	u32 mask = at91_adc_active_scan_mask_to_reg(indio_dev);
1235 	unsigned int timeout = 50;
1236 	u32 status, imr, eoc = 0, eoc_imr;
1237 
1238 	/*
1239 	 * Check if the conversion is ready. If not, wait a little bit, and
1240 	 * in case of timeout exit with an error.
1241 	 */
1242 	while (((eoc & mask) != mask) && timeout) {
1243 		at91_adc_irq_status(st, &status, &eoc);
1244 		at91_adc_irq_mask(st, &imr, &eoc_imr);
1245 		usleep_range(50, 100);
1246 		timeout--;
1247 	}
1248 
1249 	/* Cannot read data, not ready. Continue without reporting data */
1250 	if (!timeout)
1251 		return;
1252 
1253 	for_each_set_bit(bit, indio_dev->active_scan_mask,
1254 			 indio_dev->num_channels) {
1255 		struct iio_chan_spec const *chan =
1256 					at91_adc_chan_get(indio_dev, bit);
1257 
1258 		if (!chan)
1259 			continue;
1260 		/*
1261 		 * Our external trigger only supports the voltage channels.
1262 		 * In case someone requested a different type of channel
1263 		 * just put zeroes to buffer.
1264 		 * This should not happen because we check the scan mode
1265 		 * and scan mask when we enable the buffer, and we don't allow
1266 		 * the buffer to start with a mixed mask (voltage and something
1267 		 * else).
1268 		 * Thus, emit a warning.
1269 		 */
1270 		if (chan->type == IIO_VOLTAGE) {
1271 			val = at91_adc_read_chan(st, chan->address);
1272 			at91_adc_adjust_val_osr(st, &val);
1273 			st->buffer[i] = val;
1274 		} else {
1275 			st->buffer[i] = 0;
1276 			WARN(true, "This trigger cannot handle this type of channel");
1277 		}
1278 		i++;
1279 	}
1280 	iio_push_to_buffers_with_timestamp(indio_dev, st->buffer,
1281 					   pf->timestamp);
1282 }
1283 
1284 static void at91_adc_trigger_handler_dma(struct iio_dev *indio_dev)
1285 {
1286 	struct at91_adc_state *st = iio_priv(indio_dev);
1287 	int transferred_len = at91_adc_dma_size_done(st);
1288 	s64 ns = iio_get_time_ns(indio_dev);
1289 	s64 interval;
1290 	int sample_index = 0, sample_count, sample_size;
1291 
1292 	u32 status = at91_adc_readl(st, ISR);
1293 	/* if we reached this point, we cannot sample faster */
1294 	if (status & AT91_SAMA5D2_IER_GOVRE)
1295 		pr_info_ratelimited("%s: conversion overrun detected\n",
1296 				    indio_dev->name);
1297 
1298 	sample_size = div_s64(st->dma_st.rx_buf_sz, st->dma_st.watermark);
1299 
1300 	sample_count = div_s64(transferred_len, sample_size);
1301 
1302 	/*
1303 	 * interval between samples is total time since last transfer handling
1304 	 * divided by the number of samples (total size divided by sample size)
1305 	 */
1306 	interval = div_s64((ns - st->dma_st.dma_ts), sample_count);
1307 
1308 	while (transferred_len >= sample_size) {
1309 		/*
1310 		 * for all the values in the current sample,
1311 		 * adjust the values inside the buffer for oversampling
1312 		 */
1313 		at91_adc_adjust_val_osr_array(st,
1314 					&st->dma_st.rx_buf[st->dma_st.buf_idx],
1315 					sample_size);
1316 
1317 		iio_push_to_buffers_with_timestamp(indio_dev,
1318 				(st->dma_st.rx_buf + st->dma_st.buf_idx),
1319 				(st->dma_st.dma_ts + interval * sample_index));
1320 		/* adjust remaining length */
1321 		transferred_len -= sample_size;
1322 		/* adjust buffer index */
1323 		st->dma_st.buf_idx += sample_size;
1324 		/* in case of reaching end of buffer, reset index */
1325 		if (st->dma_st.buf_idx >= st->dma_st.rx_buf_sz)
1326 			st->dma_st.buf_idx = 0;
1327 		sample_index++;
1328 	}
1329 	/* adjust saved time for next transfer handling */
1330 	st->dma_st.dma_ts = iio_get_time_ns(indio_dev);
1331 }
1332 
1333 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
1334 {
1335 	struct iio_poll_func *pf = p;
1336 	struct iio_dev *indio_dev = pf->indio_dev;
1337 	struct at91_adc_state *st = iio_priv(indio_dev);
1338 
1339 	/*
1340 	 * If it's not our trigger, start a conversion now, as we are
1341 	 * actually polling the trigger now.
1342 	 */
1343 	if (iio_trigger_validate_own_device(indio_dev->trig, indio_dev))
1344 		at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START);
1345 
1346 	if (st->dma_st.dma_chan)
1347 		at91_adc_trigger_handler_dma(indio_dev);
1348 	else
1349 		at91_adc_trigger_handler_nodma(indio_dev, pf);
1350 
1351 	iio_trigger_notify_done(indio_dev->trig);
1352 
1353 	return IRQ_HANDLED;
1354 }
1355 
1356 static unsigned at91_adc_startup_time(unsigned startup_time_min,
1357 				      unsigned adc_clk_khz)
1358 {
1359 	static const unsigned int startup_lookup[] = {
1360 		  0,   8,  16,  24,
1361 		 64,  80,  96, 112,
1362 		512, 576, 640, 704,
1363 		768, 832, 896, 960
1364 		};
1365 	unsigned ticks_min, i;
1366 
1367 	/*
1368 	 * Since the adc frequency is checked before, there is no reason
1369 	 * to not meet the startup time constraint.
1370 	 */
1371 
1372 	ticks_min = startup_time_min * adc_clk_khz / 1000;
1373 	for (i = 0; i < ARRAY_SIZE(startup_lookup); i++)
1374 		if (startup_lookup[i] > ticks_min)
1375 			break;
1376 
1377 	return i;
1378 }
1379 
1380 static void at91_adc_setup_samp_freq(struct iio_dev *indio_dev, unsigned freq)
1381 {
1382 	struct at91_adc_state *st = iio_priv(indio_dev);
1383 	unsigned f_per, prescal, startup, mr;
1384 
1385 	f_per = clk_get_rate(st->per_clk);
1386 	prescal = (f_per / (2 * freq)) - 1;
1387 
1388 	startup = at91_adc_startup_time(st->soc_info.startup_time,
1389 					freq / 1000);
1390 
1391 	mr = at91_adc_readl(st, MR);
1392 	mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK);
1393 	mr |= AT91_SAMA5D2_MR_STARTUP(startup);
1394 	mr |= AT91_SAMA5D2_MR_PRESCAL(prescal);
1395 	at91_adc_writel(st, MR, mr);
1396 
1397 	dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n",
1398 		freq, startup, prescal);
1399 	st->current_sample_rate = freq;
1400 }
1401 
1402 static inline unsigned at91_adc_get_sample_freq(struct at91_adc_state *st)
1403 {
1404 	return st->current_sample_rate;
1405 }
1406 
1407 static void at91_adc_touch_data_handler(struct iio_dev *indio_dev)
1408 {
1409 	struct at91_adc_state *st = iio_priv(indio_dev);
1410 	u8 bit;
1411 	u16 val;
1412 	int i = 0;
1413 
1414 	for_each_set_bit(bit, indio_dev->active_scan_mask,
1415 			 st->soc_info.platform->max_index + 1) {
1416 		struct iio_chan_spec const *chan =
1417 					 at91_adc_chan_get(indio_dev, bit);
1418 
1419 		if (chan->type == IIO_POSITIONRELATIVE)
1420 			at91_adc_read_position(st, chan->channel, &val);
1421 		else if (chan->type == IIO_PRESSURE)
1422 			at91_adc_read_pressure(st, chan->channel, &val);
1423 		else
1424 			continue;
1425 		st->buffer[i] = val;
1426 		i++;
1427 	}
1428 	/*
1429 	 * Schedule work to push to buffers.
1430 	 * This is intended to push to the callback buffer that another driver
1431 	 * registered. We are still in a handler from our IRQ. If we push
1432 	 * directly, it means the other driver has it's callback called
1433 	 * from our IRQ context. Which is something we better avoid.
1434 	 * Let's schedule it after our IRQ is completed.
1435 	 */
1436 	schedule_work(&st->touch_st.workq);
1437 }
1438 
1439 static void at91_adc_pen_detect_interrupt(struct at91_adc_state *st)
1440 {
1441 	at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_PEN);
1442 	at91_adc_writel(st, IER, AT91_SAMA5D2_IER_NOPEN |
1443 			AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1444 			AT91_SAMA5D2_IER_PRDY);
1445 	at91_adc_writel(st, TRGR, AT91_SAMA5D2_TRGR_TRGMOD_PERIODIC |
1446 			AT91_SAMA5D2_TRGR_TRGPER(st->touch_st.sample_period_val));
1447 	st->touch_st.touching = true;
1448 }
1449 
1450 static void at91_adc_no_pen_detect_interrupt(struct iio_dev *indio_dev)
1451 {
1452 	struct at91_adc_state *st = iio_priv(indio_dev);
1453 
1454 	at91_adc_writel(st, TRGR, AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER);
1455 	at91_adc_writel(st, IDR, AT91_SAMA5D2_IER_NOPEN |
1456 			AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1457 			AT91_SAMA5D2_IER_PRDY);
1458 	st->touch_st.touching = false;
1459 
1460 	at91_adc_touch_data_handler(indio_dev);
1461 
1462 	at91_adc_writel(st, IER, AT91_SAMA5D2_IER_PEN);
1463 }
1464 
1465 static void at91_adc_workq_handler(struct work_struct *workq)
1466 {
1467 	struct at91_adc_touch *touch_st = container_of(workq,
1468 					struct at91_adc_touch, workq);
1469 	struct at91_adc_state *st = container_of(touch_st,
1470 					struct at91_adc_state, touch_st);
1471 	struct iio_dev *indio_dev = st->indio_dev;
1472 
1473 	iio_push_to_buffers(indio_dev, st->buffer);
1474 }
1475 
1476 static irqreturn_t at91_adc_interrupt(int irq, void *private)
1477 {
1478 	struct iio_dev *indio = private;
1479 	struct at91_adc_state *st = iio_priv(indio);
1480 	u32 status, eoc, imr, eoc_imr;
1481 	u32 rdy_mask = AT91_SAMA5D2_IER_XRDY | AT91_SAMA5D2_IER_YRDY |
1482 			AT91_SAMA5D2_IER_PRDY;
1483 
1484 	at91_adc_irq_status(st, &status, &eoc);
1485 	at91_adc_irq_mask(st, &imr, &eoc_imr);
1486 
1487 	if (!(status & imr) && !(eoc & eoc_imr))
1488 		return IRQ_NONE;
1489 	if (status & AT91_SAMA5D2_IER_PEN) {
1490 		/* pen detected IRQ */
1491 		at91_adc_pen_detect_interrupt(st);
1492 	} else if ((status & AT91_SAMA5D2_IER_NOPEN)) {
1493 		/* nopen detected IRQ */
1494 		at91_adc_no_pen_detect_interrupt(indio);
1495 	} else if ((status & AT91_SAMA5D2_ISR_PENS) &&
1496 		   ((status & rdy_mask) == rdy_mask)) {
1497 		/* periodic trigger IRQ - during pen sense */
1498 		at91_adc_touch_data_handler(indio);
1499 	} else if (status & AT91_SAMA5D2_ISR_PENS) {
1500 		/*
1501 		 * touching, but the measurements are not ready yet.
1502 		 * read and ignore.
1503 		 */
1504 		status = at91_adc_readl(st, XPOSR);
1505 		status = at91_adc_readl(st, YPOSR);
1506 		status = at91_adc_readl(st, PRESSR);
1507 	} else if (iio_buffer_enabled(indio) &&
1508 		   (status & AT91_SAMA5D2_IER_DRDY)) {
1509 		/* triggered buffer without DMA */
1510 		disable_irq_nosync(irq);
1511 		iio_trigger_poll(indio->trig);
1512 	} else if (iio_buffer_enabled(indio) && st->dma_st.dma_chan) {
1513 		/* triggered buffer with DMA - should not happen */
1514 		disable_irq_nosync(irq);
1515 		WARN(true, "Unexpected irq occurred\n");
1516 	} else if (!iio_buffer_enabled(indio)) {
1517 		/* software requested conversion */
1518 		st->conversion_value = at91_adc_read_chan(st, st->chan->address);
1519 		st->conversion_done = true;
1520 		wake_up_interruptible(&st->wq_data_available);
1521 	}
1522 	return IRQ_HANDLED;
1523 }
1524 
1525 static int at91_adc_read_info_raw(struct iio_dev *indio_dev,
1526 				  struct iio_chan_spec const *chan, int *val)
1527 {
1528 	struct at91_adc_state *st = iio_priv(indio_dev);
1529 	u16 tmp_val;
1530 	int ret;
1531 
1532 	/*
1533 	 * Keep in mind that we cannot use software trigger or touchscreen
1534 	 * if external trigger is enabled
1535 	 */
1536 	if (chan->type == IIO_POSITIONRELATIVE) {
1537 		ret = iio_device_claim_direct_mode(indio_dev);
1538 		if (ret)
1539 			return ret;
1540 		mutex_lock(&st->lock);
1541 
1542 		ret = at91_adc_read_position(st, chan->channel,
1543 					     &tmp_val);
1544 		*val = tmp_val;
1545 		mutex_unlock(&st->lock);
1546 		iio_device_release_direct_mode(indio_dev);
1547 
1548 		return at91_adc_adjust_val_osr(st, val);
1549 	}
1550 	if (chan->type == IIO_PRESSURE) {
1551 		ret = iio_device_claim_direct_mode(indio_dev);
1552 		if (ret)
1553 			return ret;
1554 		mutex_lock(&st->lock);
1555 
1556 		ret = at91_adc_read_pressure(st, chan->channel,
1557 					     &tmp_val);
1558 		*val = tmp_val;
1559 		mutex_unlock(&st->lock);
1560 		iio_device_release_direct_mode(indio_dev);
1561 
1562 		return at91_adc_adjust_val_osr(st, val);
1563 	}
1564 
1565 	/* in this case we have a voltage channel */
1566 
1567 	ret = iio_device_claim_direct_mode(indio_dev);
1568 	if (ret)
1569 		return ret;
1570 	mutex_lock(&st->lock);
1571 
1572 	st->chan = chan;
1573 
1574 	at91_adc_cor(st, chan);
1575 	at91_adc_writel(st, CHER, BIT(chan->channel));
1576 	at91_adc_eoc_ena(st, chan->channel);
1577 	at91_adc_writel(st, CR, AT91_SAMA5D2_CR_START);
1578 
1579 	ret = wait_event_interruptible_timeout(st->wq_data_available,
1580 					       st->conversion_done,
1581 					       msecs_to_jiffies(1000));
1582 	if (ret == 0)
1583 		ret = -ETIMEDOUT;
1584 
1585 	if (ret > 0) {
1586 		*val = st->conversion_value;
1587 		ret = at91_adc_adjust_val_osr(st, val);
1588 		if (chan->scan_type.sign == 's')
1589 			*val = sign_extend32(*val,
1590 					     chan->scan_type.realbits - 1);
1591 		st->conversion_done = false;
1592 	}
1593 
1594 	at91_adc_eoc_dis(st, st->chan->channel);
1595 	at91_adc_writel(st, CHDR, BIT(chan->channel));
1596 
1597 	/* Needed to ACK the DRDY interruption */
1598 	at91_adc_readl(st, LCDR);
1599 
1600 	mutex_unlock(&st->lock);
1601 
1602 	iio_device_release_direct_mode(indio_dev);
1603 	return ret;
1604 }
1605 
1606 static int at91_adc_read_raw(struct iio_dev *indio_dev,
1607 			     struct iio_chan_spec const *chan,
1608 			     int *val, int *val2, long mask)
1609 {
1610 	struct at91_adc_state *st = iio_priv(indio_dev);
1611 
1612 	switch (mask) {
1613 	case IIO_CHAN_INFO_RAW:
1614 		return at91_adc_read_info_raw(indio_dev, chan, val);
1615 	case IIO_CHAN_INFO_SCALE:
1616 		*val = st->vref_uv / 1000;
1617 		if (chan->differential)
1618 			*val *= 2;
1619 		*val2 = chan->scan_type.realbits;
1620 		return IIO_VAL_FRACTIONAL_LOG2;
1621 
1622 	case IIO_CHAN_INFO_SAMP_FREQ:
1623 		*val = at91_adc_get_sample_freq(st);
1624 		return IIO_VAL_INT;
1625 
1626 	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1627 		*val = st->oversampling_ratio;
1628 		return IIO_VAL_INT;
1629 
1630 	default:
1631 		return -EINVAL;
1632 	}
1633 }
1634 
1635 static int at91_adc_write_raw(struct iio_dev *indio_dev,
1636 			      struct iio_chan_spec const *chan,
1637 			      int val, int val2, long mask)
1638 {
1639 	struct at91_adc_state *st = iio_priv(indio_dev);
1640 
1641 	switch (mask) {
1642 	case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1643 		if ((val != AT91_OSR_1SAMPLES) && (val != AT91_OSR_4SAMPLES) &&
1644 		    (val != AT91_OSR_16SAMPLES))
1645 			return -EINVAL;
1646 		/* if no change, optimize out */
1647 		if (val == st->oversampling_ratio)
1648 			return 0;
1649 		st->oversampling_ratio = val;
1650 		/* update ratio */
1651 		at91_adc_config_emr(st);
1652 		return 0;
1653 	case IIO_CHAN_INFO_SAMP_FREQ:
1654 		if (val < st->soc_info.min_sample_rate ||
1655 		    val > st->soc_info.max_sample_rate)
1656 			return -EINVAL;
1657 
1658 		at91_adc_setup_samp_freq(indio_dev, val);
1659 		return 0;
1660 	default:
1661 		return -EINVAL;
1662 	}
1663 }
1664 
1665 static void at91_adc_dma_init(struct at91_adc_state *st)
1666 {
1667 	struct device *dev = &st->indio_dev->dev;
1668 	struct dma_slave_config config = {0};
1669 	/* we have 2 bytes for each channel */
1670 	unsigned int sample_size = st->soc_info.platform->nr_channels * 2;
1671 	/*
1672 	 * We make the buffer double the size of the fifo,
1673 	 * such that DMA uses one half of the buffer (full fifo size)
1674 	 * and the software uses the other half to read/write.
1675 	 */
1676 	unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
1677 					  sample_size * 2, PAGE_SIZE);
1678 
1679 	if (st->dma_st.dma_chan)
1680 		return;
1681 
1682 	st->dma_st.dma_chan = dma_request_chan(dev, "rx");
1683 	if (IS_ERR(st->dma_st.dma_chan))  {
1684 		dev_info(dev, "can't get DMA channel\n");
1685 		st->dma_st.dma_chan = NULL;
1686 		goto dma_exit;
1687 	}
1688 
1689 	st->dma_st.rx_buf = dma_alloc_coherent(st->dma_st.dma_chan->device->dev,
1690 					       pages * PAGE_SIZE,
1691 					       &st->dma_st.rx_dma_buf,
1692 					       GFP_KERNEL);
1693 	if (!st->dma_st.rx_buf) {
1694 		dev_info(dev, "can't allocate coherent DMA area\n");
1695 		goto dma_chan_disable;
1696 	}
1697 
1698 	/* Configure DMA channel to read data register */
1699 	config.direction = DMA_DEV_TO_MEM;
1700 	config.src_addr = (phys_addr_t)(st->dma_st.phys_addr
1701 			  + st->soc_info.platform->layout->LCDR);
1702 	config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
1703 	config.src_maxburst = 1;
1704 	config.dst_maxburst = 1;
1705 
1706 	if (dmaengine_slave_config(st->dma_st.dma_chan, &config)) {
1707 		dev_info(dev, "can't configure DMA slave\n");
1708 		goto dma_free_area;
1709 	}
1710 
1711 	dev_info(dev, "using %s for rx DMA transfers\n",
1712 		 dma_chan_name(st->dma_st.dma_chan));
1713 
1714 	return;
1715 
1716 dma_free_area:
1717 	dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
1718 			  st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
1719 dma_chan_disable:
1720 	dma_release_channel(st->dma_st.dma_chan);
1721 	st->dma_st.dma_chan = NULL;
1722 dma_exit:
1723 	dev_info(dev, "continuing without DMA support\n");
1724 }
1725 
1726 static void at91_adc_dma_disable(struct at91_adc_state *st)
1727 {
1728 	struct device *dev = &st->indio_dev->dev;
1729 	/* we have 2 bytes for each channel */
1730 	unsigned int sample_size = st->soc_info.platform->nr_channels * 2;
1731 	unsigned int pages = DIV_ROUND_UP(AT91_HWFIFO_MAX_SIZE *
1732 					  sample_size * 2, PAGE_SIZE);
1733 
1734 	/* if we are not using DMA, just return */
1735 	if (!st->dma_st.dma_chan)
1736 		return;
1737 
1738 	/* wait for all transactions to be terminated first*/
1739 	dmaengine_terminate_sync(st->dma_st.dma_chan);
1740 
1741 	dma_free_coherent(st->dma_st.dma_chan->device->dev, pages * PAGE_SIZE,
1742 			  st->dma_st.rx_buf, st->dma_st.rx_dma_buf);
1743 	dma_release_channel(st->dma_st.dma_chan);
1744 	st->dma_st.dma_chan = NULL;
1745 
1746 	dev_info(dev, "continuing without DMA support\n");
1747 }
1748 
1749 static int at91_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
1750 {
1751 	struct at91_adc_state *st = iio_priv(indio_dev);
1752 	int ret;
1753 
1754 	if (val > AT91_HWFIFO_MAX_SIZE)
1755 		return -EINVAL;
1756 
1757 	if (!st->selected_trig->hw_trig) {
1758 		dev_dbg(&indio_dev->dev, "we need hw trigger for DMA\n");
1759 		return 0;
1760 	}
1761 
1762 	dev_dbg(&indio_dev->dev, "new watermark is %u\n", val);
1763 	st->dma_st.watermark = val;
1764 
1765 	/*
1766 	 * The logic here is: if we have watermark 1, it means we do
1767 	 * each conversion with it's own IRQ, thus we don't need DMA.
1768 	 * If the watermark is higher, we do DMA to do all the transfers in bulk
1769 	 */
1770 
1771 	if (val == 1)
1772 		at91_adc_dma_disable(st);
1773 	else if (val > 1)
1774 		at91_adc_dma_init(st);
1775 
1776 	/*
1777 	 * We can start the DMA only after setting the watermark and
1778 	 * having the DMA initialization completed
1779 	 */
1780 	ret = at91_adc_buffer_prepare(indio_dev);
1781 	if (ret)
1782 		at91_adc_dma_disable(st);
1783 
1784 	return ret;
1785 }
1786 
1787 static int at91_adc_update_scan_mode(struct iio_dev *indio_dev,
1788 				     const unsigned long *scan_mask)
1789 {
1790 	struct at91_adc_state *st = iio_priv(indio_dev);
1791 
1792 	if (bitmap_subset(scan_mask, &st->touch_st.channels_bitmask,
1793 			  st->soc_info.platform->max_index + 1))
1794 		return 0;
1795 	/*
1796 	 * if the new bitmap is a combination of touchscreen and regular
1797 	 * channels, then we are not fine
1798 	 */
1799 	if (bitmap_intersects(&st->touch_st.channels_bitmask, scan_mask,
1800 			      st->soc_info.platform->max_index + 1))
1801 		return -EINVAL;
1802 	return 0;
1803 }
1804 
1805 static void at91_adc_hw_init(struct iio_dev *indio_dev)
1806 {
1807 	struct at91_adc_state *st = iio_priv(indio_dev);
1808 
1809 	at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST);
1810 	if (st->soc_info.platform->layout->EOC_IDR)
1811 		at91_adc_writel(st, EOC_IDR, 0xffffffff);
1812 	at91_adc_writel(st, IDR, 0xffffffff);
1813 	/*
1814 	 * Transfer field must be set to 2 according to the datasheet and
1815 	 * allows different analog settings for each channel.
1816 	 */
1817 	at91_adc_writel(st, MR,
1818 			AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH);
1819 
1820 	at91_adc_setup_samp_freq(indio_dev, st->soc_info.min_sample_rate);
1821 
1822 	/* configure extended mode register */
1823 	at91_adc_config_emr(st);
1824 }
1825 
1826 static ssize_t at91_adc_get_fifo_state(struct device *dev,
1827 				       struct device_attribute *attr, char *buf)
1828 {
1829 	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1830 	struct at91_adc_state *st = iio_priv(indio_dev);
1831 
1832 	return scnprintf(buf, PAGE_SIZE, "%d\n", !!st->dma_st.dma_chan);
1833 }
1834 
1835 static ssize_t at91_adc_get_watermark(struct device *dev,
1836 				      struct device_attribute *attr, char *buf)
1837 {
1838 	struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1839 	struct at91_adc_state *st = iio_priv(indio_dev);
1840 
1841 	return scnprintf(buf, PAGE_SIZE, "%d\n", st->dma_st.watermark);
1842 }
1843 
1844 static IIO_DEVICE_ATTR(hwfifo_enabled, 0444,
1845 		       at91_adc_get_fifo_state, NULL, 0);
1846 static IIO_DEVICE_ATTR(hwfifo_watermark, 0444,
1847 		       at91_adc_get_watermark, NULL, 0);
1848 
1849 static IIO_CONST_ATTR(hwfifo_watermark_min, "2");
1850 static IIO_CONST_ATTR(hwfifo_watermark_max, AT91_HWFIFO_MAX_SIZE_STR);
1851 
1852 static IIO_CONST_ATTR(oversampling_ratio_available,
1853 		      __stringify(AT91_OSR_1SAMPLES) " "
1854 		      __stringify(AT91_OSR_4SAMPLES) " "
1855 		      __stringify(AT91_OSR_16SAMPLES));
1856 
1857 static struct attribute *at91_adc_attributes[] = {
1858 	&iio_const_attr_oversampling_ratio_available.dev_attr.attr,
1859 	NULL,
1860 };
1861 
1862 static const struct attribute_group at91_adc_attribute_group = {
1863 	.attrs = at91_adc_attributes,
1864 };
1865 
1866 static const struct attribute *at91_adc_fifo_attributes[] = {
1867 	&iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
1868 	&iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
1869 	&iio_dev_attr_hwfifo_watermark.dev_attr.attr,
1870 	&iio_dev_attr_hwfifo_enabled.dev_attr.attr,
1871 	NULL,
1872 };
1873 
1874 static const struct iio_info at91_adc_info = {
1875 	.attrs = &at91_adc_attribute_group,
1876 	.read_raw = &at91_adc_read_raw,
1877 	.write_raw = &at91_adc_write_raw,
1878 	.update_scan_mode = &at91_adc_update_scan_mode,
1879 	.of_xlate = &at91_adc_of_xlate,
1880 	.hwfifo_set_watermark = &at91_adc_set_watermark,
1881 };
1882 
1883 static int at91_adc_buffer_and_trigger_init(struct device *dev,
1884 					    struct iio_dev *indio)
1885 {
1886 	struct at91_adc_state *st = iio_priv(indio);
1887 	const struct attribute **fifo_attrs;
1888 	int ret;
1889 
1890 	if (st->selected_trig->hw_trig)
1891 		fifo_attrs = at91_adc_fifo_attributes;
1892 	else
1893 		fifo_attrs = NULL;
1894 
1895 	ret = devm_iio_triggered_buffer_setup_ext(&indio->dev, indio,
1896 		&iio_pollfunc_store_time, &at91_adc_trigger_handler,
1897 		IIO_BUFFER_DIRECTION_IN, &at91_buffer_setup_ops, fifo_attrs);
1898 	if (ret < 0) {
1899 		dev_err(dev, "couldn't initialize the buffer.\n");
1900 		return ret;
1901 	}
1902 
1903 	if (!st->selected_trig->hw_trig)
1904 		return 0;
1905 
1906 	st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name);
1907 	if (IS_ERR(st->trig)) {
1908 		dev_err(dev, "could not allocate trigger\n");
1909 		return PTR_ERR(st->trig);
1910 	}
1911 
1912 	/*
1913 	 * Initially the iio buffer has a length of 2 and
1914 	 * a watermark of 1
1915 	 */
1916 	st->dma_st.watermark = 1;
1917 
1918 	return 0;
1919 }
1920 
1921 static int at91_adc_probe(struct platform_device *pdev)
1922 {
1923 	struct iio_dev *indio_dev;
1924 	struct at91_adc_state *st;
1925 	struct resource	*res;
1926 	int ret, i;
1927 	u32 edge_type = IRQ_TYPE_NONE;
1928 
1929 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
1930 	if (!indio_dev)
1931 		return -ENOMEM;
1932 
1933 	st = iio_priv(indio_dev);
1934 	st->indio_dev = indio_dev;
1935 
1936 	st->soc_info.platform = of_device_get_match_data(&pdev->dev);
1937 
1938 	indio_dev->name = dev_name(&pdev->dev);
1939 	indio_dev->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
1940 	indio_dev->info = &at91_adc_info;
1941 	indio_dev->channels = *st->soc_info.platform->adc_channels;
1942 	indio_dev->num_channels = st->soc_info.platform->max_channels;
1943 
1944 	bitmap_set(&st->touch_st.channels_bitmask,
1945 		   st->soc_info.platform->touch_chan_x, 1);
1946 	bitmap_set(&st->touch_st.channels_bitmask,
1947 		   st->soc_info.platform->touch_chan_y, 1);
1948 	bitmap_set(&st->touch_st.channels_bitmask,
1949 		   st->soc_info.platform->touch_chan_p, 1);
1950 
1951 	st->oversampling_ratio = AT91_OSR_1SAMPLES;
1952 
1953 	ret = of_property_read_u32(pdev->dev.of_node,
1954 				   "atmel,min-sample-rate-hz",
1955 				   &st->soc_info.min_sample_rate);
1956 	if (ret) {
1957 		dev_err(&pdev->dev,
1958 			"invalid or missing value for atmel,min-sample-rate-hz\n");
1959 		return ret;
1960 	}
1961 
1962 	ret = of_property_read_u32(pdev->dev.of_node,
1963 				   "atmel,max-sample-rate-hz",
1964 				   &st->soc_info.max_sample_rate);
1965 	if (ret) {
1966 		dev_err(&pdev->dev,
1967 			"invalid or missing value for atmel,max-sample-rate-hz\n");
1968 		return ret;
1969 	}
1970 
1971 	ret = of_property_read_u32(pdev->dev.of_node, "atmel,startup-time-ms",
1972 				   &st->soc_info.startup_time);
1973 	if (ret) {
1974 		dev_err(&pdev->dev,
1975 			"invalid or missing value for atmel,startup-time-ms\n");
1976 		return ret;
1977 	}
1978 
1979 	ret = of_property_read_u32(pdev->dev.of_node,
1980 				   "atmel,trigger-edge-type", &edge_type);
1981 	if (ret) {
1982 		dev_dbg(&pdev->dev,
1983 			"atmel,trigger-edge-type not specified, only software trigger available\n");
1984 	}
1985 
1986 	st->selected_trig = NULL;
1987 
1988 	/* find the right trigger, or no trigger at all */
1989 	for (i = 0; i < st->soc_info.platform->hw_trig_cnt + 1; i++)
1990 		if (at91_adc_trigger_list[i].edge_type == edge_type) {
1991 			st->selected_trig = &at91_adc_trigger_list[i];
1992 			break;
1993 		}
1994 
1995 	if (!st->selected_trig) {
1996 		dev_err(&pdev->dev, "invalid external trigger edge value\n");
1997 		return -EINVAL;
1998 	}
1999 
2000 	init_waitqueue_head(&st->wq_data_available);
2001 	mutex_init(&st->lock);
2002 	INIT_WORK(&st->touch_st.workq, at91_adc_workq_handler);
2003 
2004 	st->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2005 	if (IS_ERR(st->base))
2006 		return PTR_ERR(st->base);
2007 
2008 	/* if we plan to use DMA, we need the physical address of the regs */
2009 	st->dma_st.phys_addr = res->start;
2010 
2011 	st->irq = platform_get_irq(pdev, 0);
2012 	if (st->irq <= 0) {
2013 		if (!st->irq)
2014 			st->irq = -ENXIO;
2015 
2016 		return st->irq;
2017 	}
2018 
2019 	st->per_clk = devm_clk_get(&pdev->dev, "adc_clk");
2020 	if (IS_ERR(st->per_clk))
2021 		return PTR_ERR(st->per_clk);
2022 
2023 	st->reg = devm_regulator_get(&pdev->dev, "vddana");
2024 	if (IS_ERR(st->reg))
2025 		return PTR_ERR(st->reg);
2026 
2027 	st->vref = devm_regulator_get(&pdev->dev, "vref");
2028 	if (IS_ERR(st->vref))
2029 		return PTR_ERR(st->vref);
2030 
2031 	ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0,
2032 			       pdev->dev.driver->name, indio_dev);
2033 	if (ret)
2034 		return ret;
2035 
2036 	ret = regulator_enable(st->reg);
2037 	if (ret)
2038 		return ret;
2039 
2040 	ret = regulator_enable(st->vref);
2041 	if (ret)
2042 		goto reg_disable;
2043 
2044 	st->vref_uv = regulator_get_voltage(st->vref);
2045 	if (st->vref_uv <= 0) {
2046 		ret = -EINVAL;
2047 		goto vref_disable;
2048 	}
2049 
2050 	ret = clk_prepare_enable(st->per_clk);
2051 	if (ret)
2052 		goto vref_disable;
2053 
2054 	at91_adc_hw_init(indio_dev);
2055 
2056 	platform_set_drvdata(pdev, indio_dev);
2057 
2058 	ret = at91_adc_buffer_and_trigger_init(&pdev->dev, indio_dev);
2059 	if (ret < 0)
2060 		goto per_clk_disable_unprepare;
2061 
2062 	if (dma_coerce_mask_and_coherent(&indio_dev->dev, DMA_BIT_MASK(32)))
2063 		dev_info(&pdev->dev, "cannot set DMA mask to 32-bit\n");
2064 
2065 	ret = iio_device_register(indio_dev);
2066 	if (ret < 0)
2067 		goto dma_disable;
2068 
2069 	if (st->selected_trig->hw_trig)
2070 		dev_info(&pdev->dev, "setting up trigger as %s\n",
2071 			 st->selected_trig->name);
2072 
2073 	dev_info(&pdev->dev, "version: %x\n",
2074 		 readl_relaxed(st->base + st->soc_info.platform->layout->VERSION));
2075 
2076 	return 0;
2077 
2078 dma_disable:
2079 	at91_adc_dma_disable(st);
2080 per_clk_disable_unprepare:
2081 	clk_disable_unprepare(st->per_clk);
2082 vref_disable:
2083 	regulator_disable(st->vref);
2084 reg_disable:
2085 	regulator_disable(st->reg);
2086 	return ret;
2087 }
2088 
2089 static int at91_adc_remove(struct platform_device *pdev)
2090 {
2091 	struct iio_dev *indio_dev = platform_get_drvdata(pdev);
2092 	struct at91_adc_state *st = iio_priv(indio_dev);
2093 
2094 	iio_device_unregister(indio_dev);
2095 
2096 	at91_adc_dma_disable(st);
2097 
2098 	clk_disable_unprepare(st->per_clk);
2099 
2100 	regulator_disable(st->vref);
2101 	regulator_disable(st->reg);
2102 
2103 	return 0;
2104 }
2105 
2106 static __maybe_unused int at91_adc_suspend(struct device *dev)
2107 {
2108 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
2109 	struct at91_adc_state *st = iio_priv(indio_dev);
2110 
2111 	/*
2112 	 * Do a sofware reset of the ADC before we go to suspend.
2113 	 * this will ensure that all pins are free from being muxed by the ADC
2114 	 * and can be used by for other devices.
2115 	 * Otherwise, ADC will hog them and we can't go to suspend mode.
2116 	 */
2117 	at91_adc_writel(st, CR, AT91_SAMA5D2_CR_SWRST);
2118 
2119 	clk_disable_unprepare(st->per_clk);
2120 	regulator_disable(st->vref);
2121 	regulator_disable(st->reg);
2122 
2123 	return pinctrl_pm_select_sleep_state(dev);
2124 }
2125 
2126 static __maybe_unused int at91_adc_resume(struct device *dev)
2127 {
2128 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
2129 	struct at91_adc_state *st = iio_priv(indio_dev);
2130 	int ret;
2131 
2132 	ret = pinctrl_pm_select_default_state(dev);
2133 	if (ret)
2134 		goto resume_failed;
2135 
2136 	ret = regulator_enable(st->reg);
2137 	if (ret)
2138 		goto resume_failed;
2139 
2140 	ret = regulator_enable(st->vref);
2141 	if (ret)
2142 		goto reg_disable_resume;
2143 
2144 	ret = clk_prepare_enable(st->per_clk);
2145 	if (ret)
2146 		goto vref_disable_resume;
2147 
2148 	at91_adc_hw_init(indio_dev);
2149 
2150 	/* reconfiguring trigger hardware state */
2151 	if (!iio_buffer_enabled(indio_dev))
2152 		return 0;
2153 
2154 	/* check if we are enabling triggered buffer or the touchscreen */
2155 	if (at91_adc_current_chan_is_touch(indio_dev))
2156 		return at91_adc_configure_touch(st, true);
2157 	else
2158 		return at91_adc_configure_trigger(st->trig, true);
2159 
2160 	/* not needed but more explicit */
2161 	return 0;
2162 
2163 vref_disable_resume:
2164 	regulator_disable(st->vref);
2165 reg_disable_resume:
2166 	regulator_disable(st->reg);
2167 resume_failed:
2168 	dev_err(&indio_dev->dev, "failed to resume\n");
2169 	return ret;
2170 }
2171 
2172 static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume);
2173 
2174 static const struct of_device_id at91_adc_dt_match[] = {
2175 	{
2176 		.compatible = "atmel,sama5d2-adc",
2177 		.data = (const void *)&sama5d2_platform,
2178 	}, {
2179 		.compatible = "microchip,sama7g5-adc",
2180 		.data = (const void *)&sama7g5_platform,
2181 	}, {
2182 		/* sentinel */
2183 	}
2184 };
2185 MODULE_DEVICE_TABLE(of, at91_adc_dt_match);
2186 
2187 static struct platform_driver at91_adc_driver = {
2188 	.probe = at91_adc_probe,
2189 	.remove = at91_adc_remove,
2190 	.driver = {
2191 		.name = "at91-sama5d2_adc",
2192 		.of_match_table = at91_adc_dt_match,
2193 		.pm = &at91_adc_pm_ops,
2194 	},
2195 };
2196 module_platform_driver(at91_adc_driver)
2197 
2198 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@microchip.com>");
2199 MODULE_AUTHOR("Eugen Hristev <eugen.hristev@microchip.com");
2200 MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC");
2201 MODULE_LICENSE("GPL v2");
2202