1 /* 2 * Atmel ADC driver for SAMA5D2 devices and compatible. 3 * 4 * Copyright (C) 2015 Atmel, 5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com> 6 * 7 * This software is licensed under the terms of the GNU General Public 8 * License version 2, as published by the Free Software Foundation, and 9 * may be copied, distributed, and modified under those terms. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/bitops.h> 18 #include <linux/clk.h> 19 #include <linux/interrupt.h> 20 #include <linux/io.h> 21 #include <linux/module.h> 22 #include <linux/of_device.h> 23 #include <linux/platform_device.h> 24 #include <linux/sched.h> 25 #include <linux/wait.h> 26 #include <linux/iio/iio.h> 27 #include <linux/iio/sysfs.h> 28 #include <linux/regulator/consumer.h> 29 30 /* Control Register */ 31 #define AT91_SAMA5D2_CR 0x00 32 /* Software Reset */ 33 #define AT91_SAMA5D2_CR_SWRST BIT(0) 34 /* Start Conversion */ 35 #define AT91_SAMA5D2_CR_START BIT(1) 36 /* Touchscreen Calibration */ 37 #define AT91_SAMA5D2_CR_TSCALIB BIT(2) 38 /* Comparison Restart */ 39 #define AT91_SAMA5D2_CR_CMPRST BIT(4) 40 41 /* Mode Register */ 42 #define AT91_SAMA5D2_MR 0x04 43 /* Trigger Selection */ 44 #define AT91_SAMA5D2_MR_TRGSEL(v) ((v) << 1) 45 /* ADTRG */ 46 #define AT91_SAMA5D2_MR_TRGSEL_TRIG0 0 47 /* TIOA0 */ 48 #define AT91_SAMA5D2_MR_TRGSEL_TRIG1 1 49 /* TIOA1 */ 50 #define AT91_SAMA5D2_MR_TRGSEL_TRIG2 2 51 /* TIOA2 */ 52 #define AT91_SAMA5D2_MR_TRGSEL_TRIG3 3 53 /* PWM event line 0 */ 54 #define AT91_SAMA5D2_MR_TRGSEL_TRIG4 4 55 /* PWM event line 1 */ 56 #define AT91_SAMA5D2_MR_TRGSEL_TRIG5 5 57 /* TIOA3 */ 58 #define AT91_SAMA5D2_MR_TRGSEL_TRIG6 6 59 /* RTCOUT0 */ 60 #define AT91_SAMA5D2_MR_TRGSEL_TRIG7 7 61 /* Sleep Mode */ 62 #define AT91_SAMA5D2_MR_SLEEP BIT(5) 63 /* Fast Wake Up */ 64 #define AT91_SAMA5D2_MR_FWUP BIT(6) 65 /* Prescaler Rate Selection */ 66 #define AT91_SAMA5D2_MR_PRESCAL(v) ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET) 67 #define AT91_SAMA5D2_MR_PRESCAL_OFFSET 8 68 #define AT91_SAMA5D2_MR_PRESCAL_MAX 0xff 69 /* Startup Time */ 70 #define AT91_SAMA5D2_MR_STARTUP(v) ((v) << 16) 71 /* Analog Change */ 72 #define AT91_SAMA5D2_MR_ANACH BIT(23) 73 /* Tracking Time */ 74 #define AT91_SAMA5D2_MR_TRACKTIM(v) ((v) << 24) 75 #define AT91_SAMA5D2_MR_TRACKTIM_MAX 0xff 76 /* Transfer Time */ 77 #define AT91_SAMA5D2_MR_TRANSFER(v) ((v) << 28) 78 #define AT91_SAMA5D2_MR_TRANSFER_MAX 0x3 79 /* Use Sequence Enable */ 80 #define AT91_SAMA5D2_MR_USEQ BIT(31) 81 82 /* Channel Sequence Register 1 */ 83 #define AT91_SAMA5D2_SEQR1 0x08 84 /* Channel Sequence Register 2 */ 85 #define AT91_SAMA5D2_SEQR2 0x0c 86 /* Channel Enable Register */ 87 #define AT91_SAMA5D2_CHER 0x10 88 /* Channel Disable Register */ 89 #define AT91_SAMA5D2_CHDR 0x14 90 /* Channel Status Register */ 91 #define AT91_SAMA5D2_CHSR 0x18 92 /* Last Converted Data Register */ 93 #define AT91_SAMA5D2_LCDR 0x20 94 /* Interrupt Enable Register */ 95 #define AT91_SAMA5D2_IER 0x24 96 /* Interrupt Disable Register */ 97 #define AT91_SAMA5D2_IDR 0x28 98 /* Interrupt Mask Register */ 99 #define AT91_SAMA5D2_IMR 0x2c 100 /* Interrupt Status Register */ 101 #define AT91_SAMA5D2_ISR 0x30 102 /* Last Channel Trigger Mode Register */ 103 #define AT91_SAMA5D2_LCTMR 0x34 104 /* Last Channel Compare Window Register */ 105 #define AT91_SAMA5D2_LCCWR 0x38 106 /* Overrun Status Register */ 107 #define AT91_SAMA5D2_OVER 0x3c 108 /* Extended Mode Register */ 109 #define AT91_SAMA5D2_EMR 0x40 110 /* Compare Window Register */ 111 #define AT91_SAMA5D2_CWR 0x44 112 /* Channel Gain Register */ 113 #define AT91_SAMA5D2_CGR 0x48 114 /* Channel Offset Register */ 115 #define AT91_SAMA5D2_COR 0x4c 116 /* Channel Data Register 0 */ 117 #define AT91_SAMA5D2_CDR0 0x50 118 /* Analog Control Register */ 119 #define AT91_SAMA5D2_ACR 0x94 120 /* Touchscreen Mode Register */ 121 #define AT91_SAMA5D2_TSMR 0xb0 122 /* Touchscreen X Position Register */ 123 #define AT91_SAMA5D2_XPOSR 0xb4 124 /* Touchscreen Y Position Register */ 125 #define AT91_SAMA5D2_YPOSR 0xb8 126 /* Touchscreen Pressure Register */ 127 #define AT91_SAMA5D2_PRESSR 0xbc 128 /* Trigger Register */ 129 #define AT91_SAMA5D2_TRGR 0xc0 130 /* Correction Select Register */ 131 #define AT91_SAMA5D2_COSR 0xd0 132 /* Correction Value Register */ 133 #define AT91_SAMA5D2_CVR 0xd4 134 /* Channel Error Correction Register */ 135 #define AT91_SAMA5D2_CECR 0xd8 136 /* Write Protection Mode Register */ 137 #define AT91_SAMA5D2_WPMR 0xe4 138 /* Write Protection Status Register */ 139 #define AT91_SAMA5D2_WPSR 0xe8 140 /* Version Register */ 141 #define AT91_SAMA5D2_VERSION 0xfc 142 143 #define AT91_AT91_SAMA5D2_CHAN(num, addr) \ 144 { \ 145 .type = IIO_VOLTAGE, \ 146 .channel = num, \ 147 .address = addr, \ 148 .scan_type = { \ 149 .sign = 'u', \ 150 .realbits = 12, \ 151 }, \ 152 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 153 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 154 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\ 155 .datasheet_name = "CH"#num, \ 156 .indexed = 1, \ 157 } 158 159 #define at91_adc_readl(st, reg) readl_relaxed(st->base + reg) 160 #define at91_adc_writel(st, reg, val) writel_relaxed(val, st->base + reg) 161 162 struct at91_adc_soc_info { 163 unsigned startup_time; 164 unsigned min_sample_rate; 165 unsigned max_sample_rate; 166 }; 167 168 struct at91_adc_state { 169 void __iomem *base; 170 int irq; 171 struct clk *per_clk; 172 struct regulator *reg; 173 struct regulator *vref; 174 int vref_uv; 175 const struct iio_chan_spec *chan; 176 bool conversion_done; 177 u32 conversion_value; 178 struct at91_adc_soc_info soc_info; 179 wait_queue_head_t wq_data_available; 180 /* 181 * lock to prevent concurrent 'single conversion' requests through 182 * sysfs. 183 */ 184 struct mutex lock; 185 }; 186 187 static const struct iio_chan_spec at91_adc_channels[] = { 188 AT91_AT91_SAMA5D2_CHAN(0, 0x50), 189 AT91_AT91_SAMA5D2_CHAN(1, 0x54), 190 AT91_AT91_SAMA5D2_CHAN(2, 0x58), 191 AT91_AT91_SAMA5D2_CHAN(3, 0x5c), 192 AT91_AT91_SAMA5D2_CHAN(4, 0x60), 193 AT91_AT91_SAMA5D2_CHAN(5, 0x64), 194 AT91_AT91_SAMA5D2_CHAN(6, 0x68), 195 AT91_AT91_SAMA5D2_CHAN(7, 0x6c), 196 AT91_AT91_SAMA5D2_CHAN(8, 0x70), 197 AT91_AT91_SAMA5D2_CHAN(9, 0x74), 198 AT91_AT91_SAMA5D2_CHAN(10, 0x78), 199 AT91_AT91_SAMA5D2_CHAN(11, 0x7c), 200 }; 201 202 static unsigned at91_adc_startup_time(unsigned startup_time_min, 203 unsigned adc_clk_khz) 204 { 205 const unsigned startup_lookup[] = { 206 0, 8, 16, 24, 207 64, 80, 96, 112, 208 512, 576, 640, 704, 209 768, 832, 896, 960 210 }; 211 unsigned ticks_min, i; 212 213 /* 214 * Since the adc frequency is checked before, there is no reason 215 * to not meet the startup time constraint. 216 */ 217 218 ticks_min = startup_time_min * adc_clk_khz / 1000; 219 for (i = 0; i < ARRAY_SIZE(startup_lookup); i++) 220 if (startup_lookup[i] > ticks_min) 221 break; 222 223 return i; 224 } 225 226 static void at91_adc_setup_samp_freq(struct at91_adc_state *st, unsigned freq) 227 { 228 struct iio_dev *indio_dev = iio_priv_to_dev(st); 229 unsigned f_per, prescal, startup; 230 231 f_per = clk_get_rate(st->per_clk); 232 prescal = (f_per / (2 * freq)) - 1; 233 234 startup = at91_adc_startup_time(st->soc_info.startup_time, 235 freq / 1000); 236 237 at91_adc_writel(st, AT91_SAMA5D2_MR, 238 AT91_SAMA5D2_MR_TRANSFER(2) 239 | AT91_SAMA5D2_MR_STARTUP(startup) 240 | AT91_SAMA5D2_MR_PRESCAL(prescal)); 241 242 dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n", 243 freq, startup, prescal); 244 } 245 246 static unsigned at91_adc_get_sample_freq(struct at91_adc_state *st) 247 { 248 unsigned f_adc, f_per = clk_get_rate(st->per_clk); 249 unsigned mr, prescal; 250 251 mr = at91_adc_readl(st, AT91_SAMA5D2_MR); 252 prescal = (mr >> AT91_SAMA5D2_MR_PRESCAL_OFFSET) 253 & AT91_SAMA5D2_MR_PRESCAL_MAX; 254 f_adc = f_per / (2 * (prescal + 1)); 255 256 return f_adc; 257 } 258 259 static irqreturn_t at91_adc_interrupt(int irq, void *private) 260 { 261 struct iio_dev *indio = private; 262 struct at91_adc_state *st = iio_priv(indio); 263 u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR); 264 u32 imr = at91_adc_readl(st, AT91_SAMA5D2_IMR); 265 266 if (status & imr) { 267 st->conversion_value = at91_adc_readl(st, st->chan->address); 268 st->conversion_done = true; 269 wake_up_interruptible(&st->wq_data_available); 270 return IRQ_HANDLED; 271 } 272 273 return IRQ_NONE; 274 } 275 276 static int at91_adc_read_raw(struct iio_dev *indio_dev, 277 struct iio_chan_spec const *chan, 278 int *val, int *val2, long mask) 279 { 280 struct at91_adc_state *st = iio_priv(indio_dev); 281 int ret; 282 283 switch (mask) { 284 case IIO_CHAN_INFO_RAW: 285 mutex_lock(&st->lock); 286 287 st->chan = chan; 288 289 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel)); 290 at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel)); 291 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START); 292 293 ret = wait_event_interruptible_timeout(st->wq_data_available, 294 st->conversion_done, 295 msecs_to_jiffies(1000)); 296 if (ret == 0) 297 ret = -ETIMEDOUT; 298 299 if (ret > 0) { 300 *val = st->conversion_value; 301 ret = IIO_VAL_INT; 302 st->conversion_done = false; 303 } 304 305 at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel)); 306 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel)); 307 308 mutex_unlock(&st->lock); 309 return ret; 310 311 case IIO_CHAN_INFO_SCALE: 312 *val = st->vref_uv / 1000; 313 *val2 = chan->scan_type.realbits; 314 return IIO_VAL_FRACTIONAL_LOG2; 315 316 case IIO_CHAN_INFO_SAMP_FREQ: 317 *val = at91_adc_get_sample_freq(st); 318 return IIO_VAL_INT; 319 320 default: 321 return -EINVAL; 322 } 323 } 324 325 static int at91_adc_write_raw(struct iio_dev *indio_dev, 326 struct iio_chan_spec const *chan, 327 int val, int val2, long mask) 328 { 329 struct at91_adc_state *st = iio_priv(indio_dev); 330 331 if (mask != IIO_CHAN_INFO_SAMP_FREQ) 332 return -EINVAL; 333 334 if (val < st->soc_info.min_sample_rate || 335 val > st->soc_info.max_sample_rate) 336 return -EINVAL; 337 338 at91_adc_setup_samp_freq(st, val); 339 340 return 0; 341 } 342 343 static const struct iio_info at91_adc_info = { 344 .read_raw = &at91_adc_read_raw, 345 .write_raw = &at91_adc_write_raw, 346 .driver_module = THIS_MODULE, 347 }; 348 349 static int at91_adc_probe(struct platform_device *pdev) 350 { 351 struct iio_dev *indio_dev; 352 struct at91_adc_state *st; 353 struct resource *res; 354 int ret; 355 356 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); 357 if (!indio_dev) 358 return -ENOMEM; 359 360 indio_dev->dev.parent = &pdev->dev; 361 indio_dev->name = dev_name(&pdev->dev); 362 indio_dev->modes = INDIO_DIRECT_MODE; 363 indio_dev->info = &at91_adc_info; 364 indio_dev->channels = at91_adc_channels; 365 indio_dev->num_channels = ARRAY_SIZE(at91_adc_channels); 366 367 st = iio_priv(indio_dev); 368 369 ret = of_property_read_u32(pdev->dev.of_node, 370 "atmel,min-sample-rate-hz", 371 &st->soc_info.min_sample_rate); 372 if (ret) { 373 dev_err(&pdev->dev, 374 "invalid or missing value for atmel,min-sample-rate-hz\n"); 375 return ret; 376 } 377 378 ret = of_property_read_u32(pdev->dev.of_node, 379 "atmel,max-sample-rate-hz", 380 &st->soc_info.max_sample_rate); 381 if (ret) { 382 dev_err(&pdev->dev, 383 "invalid or missing value for atmel,max-sample-rate-hz\n"); 384 return ret; 385 } 386 387 ret = of_property_read_u32(pdev->dev.of_node, "atmel,startup-time-ms", 388 &st->soc_info.startup_time); 389 if (ret) { 390 dev_err(&pdev->dev, 391 "invalid or missing value for atmel,startup-time-ms\n"); 392 return ret; 393 } 394 395 init_waitqueue_head(&st->wq_data_available); 396 mutex_init(&st->lock); 397 398 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 399 if (!res) 400 return -EINVAL; 401 402 st->base = devm_ioremap_resource(&pdev->dev, res); 403 if (IS_ERR(st->base)) 404 return PTR_ERR(st->base); 405 406 st->irq = platform_get_irq(pdev, 0); 407 if (st->irq <= 0) { 408 if (!st->irq) 409 st->irq = -ENXIO; 410 411 return st->irq; 412 } 413 414 st->per_clk = devm_clk_get(&pdev->dev, "adc_clk"); 415 if (IS_ERR(st->per_clk)) 416 return PTR_ERR(st->per_clk); 417 418 st->reg = devm_regulator_get(&pdev->dev, "vddana"); 419 if (IS_ERR(st->reg)) 420 return PTR_ERR(st->reg); 421 422 st->vref = devm_regulator_get(&pdev->dev, "vref"); 423 if (IS_ERR(st->vref)) 424 return PTR_ERR(st->vref); 425 426 ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0, 427 pdev->dev.driver->name, indio_dev); 428 if (ret) 429 return ret; 430 431 ret = regulator_enable(st->reg); 432 if (ret) 433 return ret; 434 435 ret = regulator_enable(st->vref); 436 if (ret) 437 goto reg_disable; 438 439 st->vref_uv = regulator_get_voltage(st->vref); 440 if (st->vref_uv <= 0) { 441 ret = -EINVAL; 442 goto vref_disable; 443 } 444 445 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST); 446 at91_adc_writel(st, AT91_SAMA5D2_IDR, 0xffffffff); 447 448 at91_adc_setup_samp_freq(st, st->soc_info.min_sample_rate); 449 450 ret = clk_prepare_enable(st->per_clk); 451 if (ret) 452 goto vref_disable; 453 454 ret = iio_device_register(indio_dev); 455 if (ret < 0) 456 goto per_clk_disable_unprepare; 457 458 dev_info(&pdev->dev, "version: %x\n", 459 readl_relaxed(st->base + AT91_SAMA5D2_VERSION)); 460 461 return 0; 462 463 per_clk_disable_unprepare: 464 clk_disable_unprepare(st->per_clk); 465 vref_disable: 466 regulator_disable(st->vref); 467 reg_disable: 468 regulator_disable(st->reg); 469 return ret; 470 } 471 472 static int at91_adc_remove(struct platform_device *pdev) 473 { 474 struct iio_dev *indio_dev = platform_get_drvdata(pdev); 475 struct at91_adc_state *st = iio_priv(indio_dev); 476 477 iio_device_unregister(indio_dev); 478 479 clk_disable_unprepare(st->per_clk); 480 481 regulator_disable(st->vref); 482 regulator_disable(st->reg); 483 484 return 0; 485 } 486 487 static const struct of_device_id at91_adc_dt_match[] = { 488 { 489 .compatible = "atmel,sama5d2-adc", 490 }, { 491 /* sentinel */ 492 } 493 }; 494 MODULE_DEVICE_TABLE(of, at91_adc_dt_match); 495 496 static struct platform_driver at91_adc_driver = { 497 .probe = at91_adc_probe, 498 .remove = at91_adc_remove, 499 .driver = { 500 .name = "at91-sama5d2_adc", 501 .of_match_table = at91_adc_dt_match, 502 }, 503 }; 504 module_platform_driver(at91_adc_driver) 505 506 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>"); 507 MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC"); 508 MODULE_LICENSE("GPL v2"); 509