1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Aspeed AST2400/2500/2600 ADC 4 * 5 * Copyright (C) 2017 Google, Inc. 6 * Copyright (C) 2021 Aspeed Technology Inc. 7 * 8 * ADC clock formula: 9 * Ast2400/Ast2500: 10 * clock period = period of PCLK * 2 * (ADC0C[31:17] + 1) * (ADC0C[9:0] + 1) 11 * Ast2600: 12 * clock period = period of PCLK * 2 * (ADC0C[15:0] + 1) 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/clk-provider.h> 17 #include <linux/err.h> 18 #include <linux/errno.h> 19 #include <linux/io.h> 20 #include <linux/module.h> 21 #include <linux/of_platform.h> 22 #include <linux/platform_device.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/reset.h> 25 #include <linux/spinlock.h> 26 #include <linux/types.h> 27 #include <linux/bitfield.h> 28 #include <linux/regmap.h> 29 #include <linux/mfd/syscon.h> 30 31 #include <linux/iio/iio.h> 32 #include <linux/iio/driver.h> 33 #include <linux/iopoll.h> 34 35 #define ASPEED_RESOLUTION_BITS 10 36 #define ASPEED_CLOCKS_PER_SAMPLE 12 37 38 #define ASPEED_REG_ENGINE_CONTROL 0x00 39 #define ASPEED_REG_INTERRUPT_CONTROL 0x04 40 #define ASPEED_REG_VGA_DETECT_CONTROL 0x08 41 #define ASPEED_REG_CLOCK_CONTROL 0x0C 42 #define ASPEED_REG_COMPENSATION_TRIM 0xC4 43 /* 44 * The register offset between 0xC8~0xCC can be read and won't affect the 45 * hardware logic in each version of ADC. 46 */ 47 #define ASPEED_REG_MAX 0xD0 48 49 #define ASPEED_ADC_ENGINE_ENABLE BIT(0) 50 #define ASPEED_ADC_OP_MODE GENMASK(3, 1) 51 #define ASPEED_ADC_OP_MODE_PWR_DOWN 0 52 #define ASPEED_ADC_OP_MODE_STANDBY 1 53 #define ASPEED_ADC_OP_MODE_NORMAL 7 54 #define ASPEED_ADC_CTRL_COMPENSATION BIT(4) 55 #define ASPEED_ADC_AUTO_COMPENSATION BIT(5) 56 /* 57 * Bit 6 determines not only the reference voltage range but also the dividing 58 * circuit for battery sensing. 59 */ 60 #define ASPEED_ADC_REF_VOLTAGE GENMASK(7, 6) 61 #define ASPEED_ADC_REF_VOLTAGE_2500mV 0 62 #define ASPEED_ADC_REF_VOLTAGE_1200mV 1 63 #define ASPEED_ADC_REF_VOLTAGE_EXT_HIGH 2 64 #define ASPEED_ADC_REF_VOLTAGE_EXT_LOW 3 65 #define ASPEED_ADC_BAT_SENSING_DIV BIT(6) 66 #define ASPEED_ADC_BAT_SENSING_DIV_2_3 0 67 #define ASPEED_ADC_BAT_SENSING_DIV_1_3 1 68 #define ASPEED_ADC_CTRL_INIT_RDY BIT(8) 69 #define ASPEED_ADC_CH7_MODE BIT(12) 70 #define ASPEED_ADC_CH7_NORMAL 0 71 #define ASPEED_ADC_CH7_BAT 1 72 #define ASPEED_ADC_BAT_SENSING_ENABLE BIT(13) 73 #define ASPEED_ADC_CTRL_CHANNEL GENMASK(31, 16) 74 #define ASPEED_ADC_CTRL_CHANNEL_ENABLE(ch) FIELD_PREP(ASPEED_ADC_CTRL_CHANNEL, BIT(ch)) 75 76 #define ASPEED_ADC_INIT_POLLING_TIME 500 77 #define ASPEED_ADC_INIT_TIMEOUT 500000 78 /* 79 * When the sampling rate is too high, the ADC may not have enough charging 80 * time, resulting in a low voltage value. Thus, the default uses a slow 81 * sampling rate for most use cases. 82 */ 83 #define ASPEED_ADC_DEF_SAMPLING_RATE 65000 84 85 struct aspeed_adc_trim_locate { 86 const unsigned int offset; 87 const unsigned int field; 88 }; 89 90 struct aspeed_adc_model_data { 91 const char *model_name; 92 unsigned int min_sampling_rate; // Hz 93 unsigned int max_sampling_rate; // Hz 94 unsigned int vref_fixed_mv; 95 bool wait_init_sequence; 96 bool need_prescaler; 97 bool bat_sense_sup; 98 u8 scaler_bit_width; 99 unsigned int num_channels; 100 const struct aspeed_adc_trim_locate *trim_locate; 101 }; 102 103 struct adc_gain { 104 u8 mult; 105 u8 div; 106 }; 107 108 struct aspeed_adc_data { 109 struct device *dev; 110 const struct aspeed_adc_model_data *model_data; 111 struct regulator *regulator; 112 void __iomem *base; 113 spinlock_t clk_lock; 114 struct clk_hw *fixed_div_clk; 115 struct clk_hw *clk_prescaler; 116 struct clk_hw *clk_scaler; 117 struct reset_control *rst; 118 int vref_mv; 119 u32 sample_period_ns; 120 int cv; 121 bool battery_sensing; 122 struct adc_gain battery_mode_gain; 123 }; 124 125 #define ASPEED_CHAN(_idx, _data_reg_addr) { \ 126 .type = IIO_VOLTAGE, \ 127 .indexed = 1, \ 128 .channel = (_idx), \ 129 .address = (_data_reg_addr), \ 130 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 131 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 132 BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 133 BIT(IIO_CHAN_INFO_OFFSET), \ 134 } 135 136 static const struct iio_chan_spec aspeed_adc_iio_channels[] = { 137 ASPEED_CHAN(0, 0x10), 138 ASPEED_CHAN(1, 0x12), 139 ASPEED_CHAN(2, 0x14), 140 ASPEED_CHAN(3, 0x16), 141 ASPEED_CHAN(4, 0x18), 142 ASPEED_CHAN(5, 0x1A), 143 ASPEED_CHAN(6, 0x1C), 144 ASPEED_CHAN(7, 0x1E), 145 ASPEED_CHAN(8, 0x20), 146 ASPEED_CHAN(9, 0x22), 147 ASPEED_CHAN(10, 0x24), 148 ASPEED_CHAN(11, 0x26), 149 ASPEED_CHAN(12, 0x28), 150 ASPEED_CHAN(13, 0x2A), 151 ASPEED_CHAN(14, 0x2C), 152 ASPEED_CHAN(15, 0x2E), 153 }; 154 155 #define ASPEED_BAT_CHAN(_idx, _data_reg_addr) { \ 156 .type = IIO_VOLTAGE, \ 157 .indexed = 1, \ 158 .channel = (_idx), \ 159 .address = (_data_reg_addr), \ 160 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 161 BIT(IIO_CHAN_INFO_OFFSET), \ 162 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 163 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 164 } 165 static const struct iio_chan_spec aspeed_adc_iio_bat_channels[] = { 166 ASPEED_CHAN(0, 0x10), 167 ASPEED_CHAN(1, 0x12), 168 ASPEED_CHAN(2, 0x14), 169 ASPEED_CHAN(3, 0x16), 170 ASPEED_CHAN(4, 0x18), 171 ASPEED_CHAN(5, 0x1A), 172 ASPEED_CHAN(6, 0x1C), 173 ASPEED_BAT_CHAN(7, 0x1E), 174 }; 175 176 static int aspeed_adc_set_trim_data(struct iio_dev *indio_dev) 177 { 178 struct device_node *syscon; 179 struct regmap *scu; 180 u32 scu_otp, trimming_val; 181 struct aspeed_adc_data *data = iio_priv(indio_dev); 182 183 syscon = of_find_node_by_name(NULL, "syscon"); 184 if (syscon == NULL) { 185 dev_warn(data->dev, "Couldn't find syscon node\n"); 186 return -EOPNOTSUPP; 187 } 188 scu = syscon_node_to_regmap(syscon); 189 if (IS_ERR(scu)) { 190 dev_warn(data->dev, "Failed to get syscon regmap\n"); 191 return -EOPNOTSUPP; 192 } 193 if (data->model_data->trim_locate) { 194 if (regmap_read(scu, data->model_data->trim_locate->offset, 195 &scu_otp)) { 196 dev_warn(data->dev, 197 "Failed to get adc trimming data\n"); 198 trimming_val = 0x8; 199 } else { 200 trimming_val = 201 ((scu_otp) & 202 (data->model_data->trim_locate->field)) >> 203 __ffs(data->model_data->trim_locate->field); 204 } 205 dev_dbg(data->dev, 206 "trimming val = %d, offset = %08x, fields = %08x\n", 207 trimming_val, data->model_data->trim_locate->offset, 208 data->model_data->trim_locate->field); 209 writel(trimming_val, data->base + ASPEED_REG_COMPENSATION_TRIM); 210 } 211 return 0; 212 } 213 214 static int aspeed_adc_compensation(struct iio_dev *indio_dev) 215 { 216 struct aspeed_adc_data *data = iio_priv(indio_dev); 217 u32 index, adc_raw = 0; 218 u32 adc_engine_control_reg_val; 219 220 adc_engine_control_reg_val = 221 readl(data->base + ASPEED_REG_ENGINE_CONTROL); 222 adc_engine_control_reg_val &= ~ASPEED_ADC_OP_MODE; 223 adc_engine_control_reg_val |= 224 (FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) | 225 ASPEED_ADC_ENGINE_ENABLE); 226 /* 227 * Enable compensating sensing: 228 * After that, the input voltage of ADC will force to half of the reference 229 * voltage. So the expected reading raw data will become half of the max 230 * value. We can get compensating value = 0x200 - ADC read raw value. 231 * It is recommended to average at least 10 samples to get a final CV. 232 */ 233 writel(adc_engine_control_reg_val | ASPEED_ADC_CTRL_COMPENSATION | 234 ASPEED_ADC_CTRL_CHANNEL_ENABLE(0), 235 data->base + ASPEED_REG_ENGINE_CONTROL); 236 /* 237 * After enable compensating sensing mode need to wait some time for ADC stable 238 * Experiment result is 1ms. 239 */ 240 mdelay(1); 241 242 for (index = 0; index < 16; index++) { 243 /* 244 * Waiting for the sampling period ensures that the value acquired 245 * is fresh each time. 246 */ 247 ndelay(data->sample_period_ns); 248 adc_raw += readw(data->base + aspeed_adc_iio_channels[0].address); 249 } 250 adc_raw >>= 4; 251 data->cv = BIT(ASPEED_RESOLUTION_BITS - 1) - adc_raw; 252 writel(adc_engine_control_reg_val, 253 data->base + ASPEED_REG_ENGINE_CONTROL); 254 dev_dbg(data->dev, "Compensating value = %d\n", data->cv); 255 256 return 0; 257 } 258 259 static int aspeed_adc_set_sampling_rate(struct iio_dev *indio_dev, u32 rate) 260 { 261 struct aspeed_adc_data *data = iio_priv(indio_dev); 262 263 if (rate < data->model_data->min_sampling_rate || 264 rate > data->model_data->max_sampling_rate) 265 return -EINVAL; 266 /* Each sampling needs 12 clocks to convert.*/ 267 clk_set_rate(data->clk_scaler->clk, rate * ASPEED_CLOCKS_PER_SAMPLE); 268 rate = clk_get_rate(data->clk_scaler->clk); 269 data->sample_period_ns = DIV_ROUND_UP_ULL( 270 (u64)NSEC_PER_SEC * ASPEED_CLOCKS_PER_SAMPLE, rate); 271 dev_dbg(data->dev, "Adc clock = %d sample period = %d ns", rate, 272 data->sample_period_ns); 273 274 return 0; 275 } 276 277 static int aspeed_adc_read_raw(struct iio_dev *indio_dev, 278 struct iio_chan_spec const *chan, 279 int *val, int *val2, long mask) 280 { 281 struct aspeed_adc_data *data = iio_priv(indio_dev); 282 u32 adc_engine_control_reg_val; 283 284 switch (mask) { 285 case IIO_CHAN_INFO_RAW: 286 if (data->battery_sensing && chan->channel == 7) { 287 adc_engine_control_reg_val = 288 readl(data->base + ASPEED_REG_ENGINE_CONTROL); 289 writel(adc_engine_control_reg_val | 290 FIELD_PREP(ASPEED_ADC_CH7_MODE, 291 ASPEED_ADC_CH7_BAT) | 292 ASPEED_ADC_BAT_SENSING_ENABLE, 293 data->base + ASPEED_REG_ENGINE_CONTROL); 294 /* 295 * After enable battery sensing mode need to wait some time for adc stable 296 * Experiment result is 1ms. 297 */ 298 mdelay(1); 299 *val = readw(data->base + chan->address); 300 *val = (*val * data->battery_mode_gain.mult) / 301 data->battery_mode_gain.div; 302 /* Restore control register value */ 303 writel(adc_engine_control_reg_val, 304 data->base + ASPEED_REG_ENGINE_CONTROL); 305 } else 306 *val = readw(data->base + chan->address); 307 return IIO_VAL_INT; 308 309 case IIO_CHAN_INFO_OFFSET: 310 if (data->battery_sensing && chan->channel == 7) 311 *val = (data->cv * data->battery_mode_gain.mult) / 312 data->battery_mode_gain.div; 313 else 314 *val = data->cv; 315 return IIO_VAL_INT; 316 317 case IIO_CHAN_INFO_SCALE: 318 *val = data->vref_mv; 319 *val2 = ASPEED_RESOLUTION_BITS; 320 return IIO_VAL_FRACTIONAL_LOG2; 321 322 case IIO_CHAN_INFO_SAMP_FREQ: 323 *val = clk_get_rate(data->clk_scaler->clk) / 324 ASPEED_CLOCKS_PER_SAMPLE; 325 return IIO_VAL_INT; 326 327 default: 328 return -EINVAL; 329 } 330 } 331 332 static int aspeed_adc_write_raw(struct iio_dev *indio_dev, 333 struct iio_chan_spec const *chan, 334 int val, int val2, long mask) 335 { 336 switch (mask) { 337 case IIO_CHAN_INFO_SAMP_FREQ: 338 return aspeed_adc_set_sampling_rate(indio_dev, val); 339 340 case IIO_CHAN_INFO_SCALE: 341 case IIO_CHAN_INFO_RAW: 342 /* 343 * Technically, these could be written but the only reasons 344 * for doing so seem better handled in userspace. EPERM is 345 * returned to signal this is a policy choice rather than a 346 * hardware limitation. 347 */ 348 return -EPERM; 349 350 default: 351 return -EINVAL; 352 } 353 } 354 355 static int aspeed_adc_reg_access(struct iio_dev *indio_dev, 356 unsigned int reg, unsigned int writeval, 357 unsigned int *readval) 358 { 359 struct aspeed_adc_data *data = iio_priv(indio_dev); 360 361 if (!readval || reg % 4 || reg > ASPEED_REG_MAX) 362 return -EINVAL; 363 364 *readval = readl(data->base + reg); 365 366 return 0; 367 } 368 369 static const struct iio_info aspeed_adc_iio_info = { 370 .read_raw = aspeed_adc_read_raw, 371 .write_raw = aspeed_adc_write_raw, 372 .debugfs_reg_access = aspeed_adc_reg_access, 373 }; 374 375 static void aspeed_adc_unregister_fixed_divider(void *data) 376 { 377 struct clk_hw *clk = data; 378 379 clk_hw_unregister_fixed_factor(clk); 380 } 381 382 static void aspeed_adc_reset_assert(void *data) 383 { 384 struct reset_control *rst = data; 385 386 reset_control_assert(rst); 387 } 388 389 static void aspeed_adc_clk_disable_unprepare(void *data) 390 { 391 struct clk *clk = data; 392 393 clk_disable_unprepare(clk); 394 } 395 396 static void aspeed_adc_power_down(void *data) 397 { 398 struct aspeed_adc_data *priv_data = data; 399 400 writel(FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_PWR_DOWN), 401 priv_data->base + ASPEED_REG_ENGINE_CONTROL); 402 } 403 404 static void aspeed_adc_reg_disable(void *data) 405 { 406 struct regulator *reg = data; 407 408 regulator_disable(reg); 409 } 410 411 static int aspeed_adc_vref_config(struct iio_dev *indio_dev) 412 { 413 struct aspeed_adc_data *data = iio_priv(indio_dev); 414 int ret; 415 u32 adc_engine_control_reg_val; 416 417 if (data->model_data->vref_fixed_mv) { 418 data->vref_mv = data->model_data->vref_fixed_mv; 419 return 0; 420 } 421 adc_engine_control_reg_val = 422 readl(data->base + ASPEED_REG_ENGINE_CONTROL); 423 data->regulator = devm_regulator_get_optional(data->dev, "vref"); 424 if (!IS_ERR(data->regulator)) { 425 ret = regulator_enable(data->regulator); 426 if (ret) 427 return ret; 428 ret = devm_add_action_or_reset( 429 data->dev, aspeed_adc_reg_disable, data->regulator); 430 if (ret) 431 return ret; 432 data->vref_mv = regulator_get_voltage(data->regulator); 433 /* Conversion from uV to mV */ 434 data->vref_mv /= 1000; 435 if ((data->vref_mv >= 1550) && (data->vref_mv <= 2700)) 436 writel(adc_engine_control_reg_val | 437 FIELD_PREP( 438 ASPEED_ADC_REF_VOLTAGE, 439 ASPEED_ADC_REF_VOLTAGE_EXT_HIGH), 440 data->base + ASPEED_REG_ENGINE_CONTROL); 441 else if ((data->vref_mv >= 900) && (data->vref_mv <= 1650)) 442 writel(adc_engine_control_reg_val | 443 FIELD_PREP( 444 ASPEED_ADC_REF_VOLTAGE, 445 ASPEED_ADC_REF_VOLTAGE_EXT_LOW), 446 data->base + ASPEED_REG_ENGINE_CONTROL); 447 else { 448 dev_err(data->dev, "Regulator voltage %d not support", 449 data->vref_mv); 450 return -EOPNOTSUPP; 451 } 452 } else { 453 if (PTR_ERR(data->regulator) != -ENODEV) 454 return PTR_ERR(data->regulator); 455 data->vref_mv = 2500000; 456 of_property_read_u32(data->dev->of_node, 457 "aspeed,int-vref-microvolt", 458 &data->vref_mv); 459 /* Conversion from uV to mV */ 460 data->vref_mv /= 1000; 461 if (data->vref_mv == 2500) 462 writel(adc_engine_control_reg_val | 463 FIELD_PREP(ASPEED_ADC_REF_VOLTAGE, 464 ASPEED_ADC_REF_VOLTAGE_2500mV), 465 data->base + ASPEED_REG_ENGINE_CONTROL); 466 else if (data->vref_mv == 1200) 467 writel(adc_engine_control_reg_val | 468 FIELD_PREP(ASPEED_ADC_REF_VOLTAGE, 469 ASPEED_ADC_REF_VOLTAGE_1200mV), 470 data->base + ASPEED_REG_ENGINE_CONTROL); 471 else { 472 dev_err(data->dev, "Voltage %d not support", data->vref_mv); 473 return -EOPNOTSUPP; 474 } 475 } 476 477 return 0; 478 } 479 480 static int aspeed_adc_probe(struct platform_device *pdev) 481 { 482 struct iio_dev *indio_dev; 483 struct aspeed_adc_data *data; 484 int ret; 485 u32 adc_engine_control_reg_val; 486 unsigned long scaler_flags = 0; 487 char clk_name[32], clk_parent_name[32]; 488 489 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*data)); 490 if (!indio_dev) 491 return -ENOMEM; 492 493 data = iio_priv(indio_dev); 494 data->dev = &pdev->dev; 495 data->model_data = of_device_get_match_data(&pdev->dev); 496 platform_set_drvdata(pdev, indio_dev); 497 498 data->base = devm_platform_ioremap_resource(pdev, 0); 499 if (IS_ERR(data->base)) 500 return PTR_ERR(data->base); 501 502 /* Register ADC clock prescaler with source specified by device tree. */ 503 spin_lock_init(&data->clk_lock); 504 snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), "%s", 505 of_clk_get_parent_name(pdev->dev.of_node, 0)); 506 snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-fixed-div", 507 data->model_data->model_name); 508 data->fixed_div_clk = clk_hw_register_fixed_factor( 509 &pdev->dev, clk_name, clk_parent_name, 0, 1, 2); 510 if (IS_ERR(data->fixed_div_clk)) 511 return PTR_ERR(data->fixed_div_clk); 512 513 ret = devm_add_action_or_reset(data->dev, 514 aspeed_adc_unregister_fixed_divider, 515 data->fixed_div_clk); 516 if (ret) 517 return ret; 518 snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), clk_name); 519 520 if (data->model_data->need_prescaler) { 521 snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-prescaler", 522 data->model_data->model_name); 523 data->clk_prescaler = devm_clk_hw_register_divider( 524 &pdev->dev, clk_name, clk_parent_name, 0, 525 data->base + ASPEED_REG_CLOCK_CONTROL, 17, 15, 0, 526 &data->clk_lock); 527 if (IS_ERR(data->clk_prescaler)) 528 return PTR_ERR(data->clk_prescaler); 529 snprintf(clk_parent_name, ARRAY_SIZE(clk_parent_name), 530 clk_name); 531 scaler_flags = CLK_SET_RATE_PARENT; 532 } 533 /* 534 * Register ADC clock scaler downstream from the prescaler. Allow rate 535 * setting to adjust the prescaler as well. 536 */ 537 snprintf(clk_name, ARRAY_SIZE(clk_name), "%s-scaler", 538 data->model_data->model_name); 539 data->clk_scaler = devm_clk_hw_register_divider( 540 &pdev->dev, clk_name, clk_parent_name, scaler_flags, 541 data->base + ASPEED_REG_CLOCK_CONTROL, 0, 542 data->model_data->scaler_bit_width, 0, &data->clk_lock); 543 if (IS_ERR(data->clk_scaler)) 544 return PTR_ERR(data->clk_scaler); 545 546 data->rst = devm_reset_control_get_shared(&pdev->dev, NULL); 547 if (IS_ERR(data->rst)) { 548 dev_err(&pdev->dev, 549 "invalid or missing reset controller device tree entry"); 550 return PTR_ERR(data->rst); 551 } 552 reset_control_deassert(data->rst); 553 554 ret = devm_add_action_or_reset(data->dev, aspeed_adc_reset_assert, 555 data->rst); 556 if (ret) 557 return ret; 558 559 ret = aspeed_adc_vref_config(indio_dev); 560 if (ret) 561 return ret; 562 563 if (of_find_property(data->dev->of_node, "aspeed,trim-data-valid", 564 NULL)) { 565 ret = aspeed_adc_set_trim_data(indio_dev); 566 if (ret) 567 return ret; 568 } 569 570 if (of_find_property(data->dev->of_node, "aspeed,battery-sensing", 571 NULL)) { 572 if (data->model_data->bat_sense_sup) { 573 data->battery_sensing = 1; 574 if (readl(data->base + ASPEED_REG_ENGINE_CONTROL) & 575 ASPEED_ADC_BAT_SENSING_DIV) { 576 data->battery_mode_gain.mult = 3; 577 data->battery_mode_gain.div = 1; 578 } else { 579 data->battery_mode_gain.mult = 3; 580 data->battery_mode_gain.div = 2; 581 } 582 } else 583 dev_warn(&pdev->dev, 584 "Failed to enable battery-sensing mode\n"); 585 } 586 587 ret = clk_prepare_enable(data->clk_scaler->clk); 588 if (ret) 589 return ret; 590 ret = devm_add_action_or_reset(data->dev, 591 aspeed_adc_clk_disable_unprepare, 592 data->clk_scaler->clk); 593 if (ret) 594 return ret; 595 ret = aspeed_adc_set_sampling_rate(indio_dev, 596 ASPEED_ADC_DEF_SAMPLING_RATE); 597 if (ret) 598 return ret; 599 600 adc_engine_control_reg_val = 601 readl(data->base + ASPEED_REG_ENGINE_CONTROL); 602 adc_engine_control_reg_val |= 603 FIELD_PREP(ASPEED_ADC_OP_MODE, ASPEED_ADC_OP_MODE_NORMAL) | 604 ASPEED_ADC_ENGINE_ENABLE; 605 /* Enable engine in normal mode. */ 606 writel(adc_engine_control_reg_val, 607 data->base + ASPEED_REG_ENGINE_CONTROL); 608 609 ret = devm_add_action_or_reset(data->dev, aspeed_adc_power_down, 610 data); 611 if (ret) 612 return ret; 613 614 if (data->model_data->wait_init_sequence) { 615 /* Wait for initial sequence complete. */ 616 ret = readl_poll_timeout(data->base + ASPEED_REG_ENGINE_CONTROL, 617 adc_engine_control_reg_val, 618 adc_engine_control_reg_val & 619 ASPEED_ADC_CTRL_INIT_RDY, 620 ASPEED_ADC_INIT_POLLING_TIME, 621 ASPEED_ADC_INIT_TIMEOUT); 622 if (ret) 623 return ret; 624 } 625 626 aspeed_adc_compensation(indio_dev); 627 /* Start all channels in normal mode. */ 628 adc_engine_control_reg_val = 629 readl(data->base + ASPEED_REG_ENGINE_CONTROL); 630 adc_engine_control_reg_val |= ASPEED_ADC_CTRL_CHANNEL; 631 writel(adc_engine_control_reg_val, 632 data->base + ASPEED_REG_ENGINE_CONTROL); 633 634 indio_dev->name = data->model_data->model_name; 635 indio_dev->info = &aspeed_adc_iio_info; 636 indio_dev->modes = INDIO_DIRECT_MODE; 637 indio_dev->channels = data->battery_sensing ? 638 aspeed_adc_iio_bat_channels : 639 aspeed_adc_iio_channels; 640 indio_dev->num_channels = data->model_data->num_channels; 641 642 ret = devm_iio_device_register(data->dev, indio_dev); 643 return ret; 644 } 645 646 static const struct aspeed_adc_trim_locate ast2500_adc_trim = { 647 .offset = 0x154, 648 .field = GENMASK(31, 28), 649 }; 650 651 static const struct aspeed_adc_trim_locate ast2600_adc0_trim = { 652 .offset = 0x5d0, 653 .field = GENMASK(3, 0), 654 }; 655 656 static const struct aspeed_adc_trim_locate ast2600_adc1_trim = { 657 .offset = 0x5d0, 658 .field = GENMASK(7, 4), 659 }; 660 661 static const struct aspeed_adc_model_data ast2400_model_data = { 662 .model_name = "ast2400-adc", 663 .vref_fixed_mv = 2500, 664 .min_sampling_rate = 10000, 665 .max_sampling_rate = 500000, 666 .need_prescaler = true, 667 .scaler_bit_width = 10, 668 .num_channels = 16, 669 }; 670 671 static const struct aspeed_adc_model_data ast2500_model_data = { 672 .model_name = "ast2500-adc", 673 .vref_fixed_mv = 1800, 674 .min_sampling_rate = 1, 675 .max_sampling_rate = 1000000, 676 .wait_init_sequence = true, 677 .need_prescaler = true, 678 .scaler_bit_width = 10, 679 .num_channels = 16, 680 .trim_locate = &ast2500_adc_trim, 681 }; 682 683 static const struct aspeed_adc_model_data ast2600_adc0_model_data = { 684 .model_name = "ast2600-adc0", 685 .min_sampling_rate = 10000, 686 .max_sampling_rate = 500000, 687 .wait_init_sequence = true, 688 .bat_sense_sup = true, 689 .scaler_bit_width = 16, 690 .num_channels = 8, 691 .trim_locate = &ast2600_adc0_trim, 692 }; 693 694 static const struct aspeed_adc_model_data ast2600_adc1_model_data = { 695 .model_name = "ast2600-adc1", 696 .min_sampling_rate = 10000, 697 .max_sampling_rate = 500000, 698 .wait_init_sequence = true, 699 .bat_sense_sup = true, 700 .scaler_bit_width = 16, 701 .num_channels = 8, 702 .trim_locate = &ast2600_adc1_trim, 703 }; 704 705 static const struct of_device_id aspeed_adc_matches[] = { 706 { .compatible = "aspeed,ast2400-adc", .data = &ast2400_model_data }, 707 { .compatible = "aspeed,ast2500-adc", .data = &ast2500_model_data }, 708 { .compatible = "aspeed,ast2600-adc0", .data = &ast2600_adc0_model_data }, 709 { .compatible = "aspeed,ast2600-adc1", .data = &ast2600_adc1_model_data }, 710 {}, 711 }; 712 MODULE_DEVICE_TABLE(of, aspeed_adc_matches); 713 714 static struct platform_driver aspeed_adc_driver = { 715 .probe = aspeed_adc_probe, 716 .driver = { 717 .name = KBUILD_MODNAME, 718 .of_match_table = aspeed_adc_matches, 719 } 720 }; 721 722 module_platform_driver(aspeed_adc_driver); 723 724 MODULE_AUTHOR("Rick Altherr <raltherr@google.com>"); 725 MODULE_DESCRIPTION("Aspeed AST2400/2500/2600 ADC Driver"); 726 MODULE_LICENSE("GPL"); 727