1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices Generic AXI ADC IP core 4 * Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip 5 * 6 * Copyright 2012-2020 Analog Devices Inc. 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/io.h> 12 #include <linux/delay.h> 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/slab.h> 17 18 #include <linux/iio/iio.h> 19 #include <linux/iio/sysfs.h> 20 #include <linux/iio/buffer.h> 21 #include <linux/iio/buffer-dmaengine.h> 22 23 #include <linux/fpga/adi-axi-common.h> 24 #include <linux/iio/adc/adi-axi-adc.h> 25 26 /* 27 * Register definitions: 28 * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map 29 */ 30 31 /* ADC controls */ 32 33 #define ADI_AXI_REG_RSTN 0x0040 34 #define ADI_AXI_REG_RSTN_CE_N BIT(2) 35 #define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1) 36 #define ADI_AXI_REG_RSTN_RSTN BIT(0) 37 38 /* ADC Channel controls */ 39 40 #define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40) 41 #define ADI_AXI_REG_CHAN_CTRL_LB_OWR BIT(11) 42 #define ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR BIT(10) 43 #define ADI_AXI_REG_CHAN_CTRL_IQCOR_EN BIT(9) 44 #define ADI_AXI_REG_CHAN_CTRL_DCFILT_EN BIT(8) 45 #define ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT BIT(6) 46 #define ADI_AXI_REG_CHAN_CTRL_FMT_TYPE BIT(5) 47 #define ADI_AXI_REG_CHAN_CTRL_FMT_EN BIT(4) 48 #define ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR BIT(1) 49 #define ADI_AXI_REG_CHAN_CTRL_ENABLE BIT(0) 50 51 #define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \ 52 (ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT | \ 53 ADI_AXI_REG_CHAN_CTRL_FMT_EN | \ 54 ADI_AXI_REG_CHAN_CTRL_ENABLE) 55 56 struct adi_axi_adc_core_info { 57 unsigned int version; 58 }; 59 60 struct adi_axi_adc_state { 61 struct mutex lock; 62 63 struct adi_axi_adc_client *client; 64 void __iomem *regs; 65 }; 66 67 struct adi_axi_adc_client { 68 struct list_head entry; 69 struct adi_axi_adc_conv conv; 70 struct adi_axi_adc_state *state; 71 struct device *dev; 72 const struct adi_axi_adc_core_info *info; 73 }; 74 75 static LIST_HEAD(registered_clients); 76 static DEFINE_MUTEX(registered_clients_lock); 77 78 static struct adi_axi_adc_client *conv_to_client(struct adi_axi_adc_conv *conv) 79 { 80 return container_of(conv, struct adi_axi_adc_client, conv); 81 } 82 83 void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv) 84 { 85 struct adi_axi_adc_client *cl = conv_to_client(conv); 86 87 return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN); 88 } 89 EXPORT_SYMBOL_GPL(adi_axi_adc_conv_priv); 90 91 static void adi_axi_adc_write(struct adi_axi_adc_state *st, 92 unsigned int reg, 93 unsigned int val) 94 { 95 iowrite32(val, st->regs + reg); 96 } 97 98 static unsigned int adi_axi_adc_read(struct adi_axi_adc_state *st, 99 unsigned int reg) 100 { 101 return ioread32(st->regs + reg); 102 } 103 104 static int adi_axi_adc_config_dma_buffer(struct device *dev, 105 struct iio_dev *indio_dev) 106 { 107 const char *dma_name; 108 109 if (!device_property_present(dev, "dmas")) 110 return 0; 111 112 if (device_property_read_string(dev, "dma-names", &dma_name)) 113 dma_name = "rx"; 114 115 return devm_iio_dmaengine_buffer_setup(indio_dev->dev.parent, 116 indio_dev, dma_name); 117 } 118 119 static int adi_axi_adc_read_raw(struct iio_dev *indio_dev, 120 struct iio_chan_spec const *chan, 121 int *val, int *val2, long mask) 122 { 123 struct adi_axi_adc_state *st = iio_priv(indio_dev); 124 struct adi_axi_adc_conv *conv = &st->client->conv; 125 126 if (!conv->read_raw) 127 return -EOPNOTSUPP; 128 129 return conv->read_raw(conv, chan, val, val2, mask); 130 } 131 132 static int adi_axi_adc_write_raw(struct iio_dev *indio_dev, 133 struct iio_chan_spec const *chan, 134 int val, int val2, long mask) 135 { 136 struct adi_axi_adc_state *st = iio_priv(indio_dev); 137 struct adi_axi_adc_conv *conv = &st->client->conv; 138 139 if (!conv->write_raw) 140 return -EOPNOTSUPP; 141 142 return conv->write_raw(conv, chan, val, val2, mask); 143 } 144 145 static int adi_axi_adc_update_scan_mode(struct iio_dev *indio_dev, 146 const unsigned long *scan_mask) 147 { 148 struct adi_axi_adc_state *st = iio_priv(indio_dev); 149 struct adi_axi_adc_conv *conv = &st->client->conv; 150 unsigned int i, ctrl; 151 152 for (i = 0; i < conv->chip_info->num_channels; i++) { 153 ctrl = adi_axi_adc_read(st, ADI_AXI_REG_CHAN_CTRL(i)); 154 155 if (test_bit(i, scan_mask)) 156 ctrl |= ADI_AXI_REG_CHAN_CTRL_ENABLE; 157 else 158 ctrl &= ~ADI_AXI_REG_CHAN_CTRL_ENABLE; 159 160 adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i), ctrl); 161 } 162 163 return 0; 164 } 165 166 static struct adi_axi_adc_conv *adi_axi_adc_conv_register(struct device *dev, 167 size_t sizeof_priv) 168 { 169 struct adi_axi_adc_client *cl; 170 size_t alloc_size; 171 172 alloc_size = ALIGN(sizeof(struct adi_axi_adc_client), IIO_ALIGN); 173 if (sizeof_priv) 174 alloc_size += ALIGN(sizeof_priv, IIO_ALIGN); 175 176 cl = kzalloc(alloc_size, GFP_KERNEL); 177 if (!cl) 178 return ERR_PTR(-ENOMEM); 179 180 mutex_lock(®istered_clients_lock); 181 182 cl->dev = get_device(dev); 183 184 list_add_tail(&cl->entry, ®istered_clients); 185 186 mutex_unlock(®istered_clients_lock); 187 188 return &cl->conv; 189 } 190 191 static void adi_axi_adc_conv_unregister(struct adi_axi_adc_conv *conv) 192 { 193 struct adi_axi_adc_client *cl = conv_to_client(conv); 194 195 mutex_lock(®istered_clients_lock); 196 197 list_del(&cl->entry); 198 put_device(cl->dev); 199 200 mutex_unlock(®istered_clients_lock); 201 202 kfree(cl); 203 } 204 205 static void devm_adi_axi_adc_conv_release(void *conv) 206 { 207 adi_axi_adc_conv_unregister(conv); 208 } 209 210 struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev, 211 size_t sizeof_priv) 212 { 213 struct adi_axi_adc_conv *conv; 214 int ret; 215 216 conv = adi_axi_adc_conv_register(dev, sizeof_priv); 217 if (IS_ERR(conv)) 218 return conv; 219 220 ret = devm_add_action_or_reset(dev, devm_adi_axi_adc_conv_release, 221 conv); 222 if (ret) 223 return ERR_PTR(ret); 224 225 return conv; 226 } 227 EXPORT_SYMBOL_GPL(devm_adi_axi_adc_conv_register); 228 229 static ssize_t in_voltage_scale_available_show(struct device *dev, 230 struct device_attribute *attr, 231 char *buf) 232 { 233 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 234 struct adi_axi_adc_state *st = iio_priv(indio_dev); 235 struct adi_axi_adc_conv *conv = &st->client->conv; 236 size_t len = 0; 237 int i; 238 239 for (i = 0; i < conv->chip_info->num_scales; i++) { 240 const unsigned int *s = conv->chip_info->scale_table[i]; 241 242 len += scnprintf(buf + len, PAGE_SIZE - len, 243 "%u.%06u ", s[0], s[1]); 244 } 245 buf[len - 1] = '\n'; 246 247 return len; 248 } 249 250 static IIO_DEVICE_ATTR_RO(in_voltage_scale_available, 0); 251 252 enum { 253 ADI_AXI_ATTR_SCALE_AVAIL, 254 }; 255 256 #define ADI_AXI_ATTR(_en_, _file_) \ 257 [ADI_AXI_ATTR_##_en_] = &iio_dev_attr_##_file_.dev_attr.attr 258 259 static struct attribute *adi_axi_adc_attributes[] = { 260 ADI_AXI_ATTR(SCALE_AVAIL, in_voltage_scale_available), 261 NULL 262 }; 263 264 static umode_t axi_adc_attr_is_visible(struct kobject *kobj, 265 struct attribute *attr, int n) 266 { 267 struct device *dev = kobj_to_dev(kobj); 268 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 269 struct adi_axi_adc_state *st = iio_priv(indio_dev); 270 struct adi_axi_adc_conv *conv = &st->client->conv; 271 272 switch (n) { 273 case ADI_AXI_ATTR_SCALE_AVAIL: 274 if (!conv->chip_info->num_scales) 275 return 0; 276 return attr->mode; 277 default: 278 return attr->mode; 279 } 280 } 281 282 static const struct attribute_group adi_axi_adc_attribute_group = { 283 .attrs = adi_axi_adc_attributes, 284 .is_visible = axi_adc_attr_is_visible, 285 }; 286 287 static const struct iio_info adi_axi_adc_info = { 288 .read_raw = &adi_axi_adc_read_raw, 289 .write_raw = &adi_axi_adc_write_raw, 290 .attrs = &adi_axi_adc_attribute_group, 291 .update_scan_mode = &adi_axi_adc_update_scan_mode, 292 }; 293 294 static const struct adi_axi_adc_core_info adi_axi_adc_10_0_a_info = { 295 .version = ADI_AXI_PCORE_VER(10, 0, 'a'), 296 }; 297 298 static struct adi_axi_adc_client *adi_axi_adc_attach_client(struct device *dev) 299 { 300 const struct adi_axi_adc_core_info *info; 301 struct adi_axi_adc_client *cl; 302 struct device_node *cln; 303 304 info = of_device_get_match_data(dev); 305 if (!info) 306 return ERR_PTR(-ENODEV); 307 308 cln = of_parse_phandle(dev->of_node, "adi,adc-dev", 0); 309 if (!cln) { 310 dev_err(dev, "No 'adi,adc-dev' node defined\n"); 311 return ERR_PTR(-ENODEV); 312 } 313 314 mutex_lock(®istered_clients_lock); 315 316 list_for_each_entry(cl, ®istered_clients, entry) { 317 if (!cl->dev) 318 continue; 319 320 if (cl->dev->of_node != cln) 321 continue; 322 323 if (!try_module_get(cl->dev->driver->owner)) { 324 mutex_unlock(®istered_clients_lock); 325 of_node_put(cln); 326 return ERR_PTR(-ENODEV); 327 } 328 329 get_device(cl->dev); 330 cl->info = info; 331 mutex_unlock(®istered_clients_lock); 332 of_node_put(cln); 333 return cl; 334 } 335 336 mutex_unlock(®istered_clients_lock); 337 of_node_put(cln); 338 339 return ERR_PTR(-EPROBE_DEFER); 340 } 341 342 static int adi_axi_adc_setup_channels(struct device *dev, 343 struct adi_axi_adc_state *st) 344 { 345 struct adi_axi_adc_conv *conv = &st->client->conv; 346 int i, ret; 347 348 if (conv->preenable_setup) { 349 ret = conv->preenable_setup(conv); 350 if (ret) 351 return ret; 352 } 353 354 for (i = 0; i < conv->chip_info->num_channels; i++) { 355 adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i), 356 ADI_AXI_REG_CHAN_CTRL_DEFAULTS); 357 } 358 359 return 0; 360 } 361 362 static void axi_adc_reset(struct adi_axi_adc_state *st) 363 { 364 adi_axi_adc_write(st, ADI_AXI_REG_RSTN, 0); 365 mdelay(10); 366 adi_axi_adc_write(st, ADI_AXI_REG_RSTN, ADI_AXI_REG_RSTN_MMCM_RSTN); 367 mdelay(10); 368 adi_axi_adc_write(st, ADI_AXI_REG_RSTN, 369 ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN); 370 } 371 372 static void adi_axi_adc_cleanup(void *data) 373 { 374 struct adi_axi_adc_client *cl = data; 375 376 put_device(cl->dev); 377 module_put(cl->dev->driver->owner); 378 } 379 380 static int adi_axi_adc_probe(struct platform_device *pdev) 381 { 382 struct adi_axi_adc_conv *conv; 383 struct iio_dev *indio_dev; 384 struct adi_axi_adc_client *cl; 385 struct adi_axi_adc_state *st; 386 unsigned int ver; 387 int ret; 388 389 cl = adi_axi_adc_attach_client(&pdev->dev); 390 if (IS_ERR(cl)) 391 return PTR_ERR(cl); 392 393 ret = devm_add_action_or_reset(&pdev->dev, adi_axi_adc_cleanup, cl); 394 if (ret) 395 return ret; 396 397 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); 398 if (indio_dev == NULL) 399 return -ENOMEM; 400 401 st = iio_priv(indio_dev); 402 st->client = cl; 403 cl->state = st; 404 mutex_init(&st->lock); 405 406 st->regs = devm_platform_ioremap_resource(pdev, 0); 407 if (IS_ERR(st->regs)) 408 return PTR_ERR(st->regs); 409 410 conv = &st->client->conv; 411 412 axi_adc_reset(st); 413 414 ver = adi_axi_adc_read(st, ADI_AXI_REG_VERSION); 415 416 if (cl->info->version > ver) { 417 dev_err(&pdev->dev, 418 "IP core version is too old. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n", 419 ADI_AXI_PCORE_VER_MAJOR(cl->info->version), 420 ADI_AXI_PCORE_VER_MINOR(cl->info->version), 421 ADI_AXI_PCORE_VER_PATCH(cl->info->version), 422 ADI_AXI_PCORE_VER_MAJOR(ver), 423 ADI_AXI_PCORE_VER_MINOR(ver), 424 ADI_AXI_PCORE_VER_PATCH(ver)); 425 return -ENODEV; 426 } 427 428 indio_dev->info = &adi_axi_adc_info; 429 indio_dev->name = "adi-axi-adc"; 430 indio_dev->modes = INDIO_DIRECT_MODE; 431 indio_dev->num_channels = conv->chip_info->num_channels; 432 indio_dev->channels = conv->chip_info->channels; 433 434 ret = adi_axi_adc_config_dma_buffer(&pdev->dev, indio_dev); 435 if (ret) 436 return ret; 437 438 ret = adi_axi_adc_setup_channels(&pdev->dev, st); 439 if (ret) 440 return ret; 441 442 ret = devm_iio_device_register(&pdev->dev, indio_dev); 443 if (ret) 444 return ret; 445 446 dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n", 447 ADI_AXI_PCORE_VER_MAJOR(ver), 448 ADI_AXI_PCORE_VER_MINOR(ver), 449 ADI_AXI_PCORE_VER_PATCH(ver)); 450 451 return 0; 452 } 453 454 /* Match table for of_platform binding */ 455 static const struct of_device_id adi_axi_adc_of_match[] = { 456 { .compatible = "adi,axi-adc-10.0.a", .data = &adi_axi_adc_10_0_a_info }, 457 { /* end of list */ } 458 }; 459 MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match); 460 461 static struct platform_driver adi_axi_adc_driver = { 462 .driver = { 463 .name = KBUILD_MODNAME, 464 .of_match_table = adi_axi_adc_of_match, 465 }, 466 .probe = adi_axi_adc_probe, 467 }; 468 module_platform_driver(adi_axi_adc_driver); 469 470 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 471 MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver"); 472 MODULE_LICENSE("GPL v2"); 473