1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices AD9467 SPI ADC driver 4 * 5 * Copyright 2012-2020 Analog Devices Inc. 6 */ 7 8 #include <linux/module.h> 9 #include <linux/device.h> 10 #include <linux/kernel.h> 11 #include <linux/slab.h> 12 #include <linux/spi/spi.h> 13 #include <linux/err.h> 14 #include <linux/delay.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/of_device.h> 17 18 19 #include <linux/iio/iio.h> 20 #include <linux/iio/sysfs.h> 21 22 #include <linux/clk.h> 23 24 #include <linux/iio/adc/adi-axi-adc.h> 25 26 /* 27 * ADI High-Speed ADC common spi interface registers 28 * See Application-Note AN-877: 29 * https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf 30 */ 31 32 #define AN877_ADC_REG_CHIP_PORT_CONF 0x00 33 #define AN877_ADC_REG_CHIP_ID 0x01 34 #define AN877_ADC_REG_CHIP_GRADE 0x02 35 #define AN877_ADC_REG_CHAN_INDEX 0x05 36 #define AN877_ADC_REG_TRANSFER 0xFF 37 #define AN877_ADC_REG_MODES 0x08 38 #define AN877_ADC_REG_TEST_IO 0x0D 39 #define AN877_ADC_REG_ADC_INPUT 0x0F 40 #define AN877_ADC_REG_OFFSET 0x10 41 #define AN877_ADC_REG_OUTPUT_MODE 0x14 42 #define AN877_ADC_REG_OUTPUT_ADJUST 0x15 43 #define AN877_ADC_REG_OUTPUT_PHASE 0x16 44 #define AN877_ADC_REG_OUTPUT_DELAY 0x17 45 #define AN877_ADC_REG_VREF 0x18 46 #define AN877_ADC_REG_ANALOG_INPUT 0x2C 47 48 /* AN877_ADC_REG_TEST_IO */ 49 #define AN877_ADC_TESTMODE_OFF 0x0 50 #define AN877_ADC_TESTMODE_MIDSCALE_SHORT 0x1 51 #define AN877_ADC_TESTMODE_POS_FULLSCALE 0x2 52 #define AN877_ADC_TESTMODE_NEG_FULLSCALE 0x3 53 #define AN877_ADC_TESTMODE_ALT_CHECKERBOARD 0x4 54 #define AN877_ADC_TESTMODE_PN23_SEQ 0x5 55 #define AN877_ADC_TESTMODE_PN9_SEQ 0x6 56 #define AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE 0x7 57 #define AN877_ADC_TESTMODE_USER 0x8 58 #define AN877_ADC_TESTMODE_BIT_TOGGLE 0x9 59 #define AN877_ADC_TESTMODE_SYNC 0xA 60 #define AN877_ADC_TESTMODE_ONE_BIT_HIGH 0xB 61 #define AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY 0xC 62 #define AN877_ADC_TESTMODE_RAMP 0xF 63 64 /* AN877_ADC_REG_TRANSFER */ 65 #define AN877_ADC_TRANSFER_SYNC 0x1 66 67 /* AN877_ADC_REG_OUTPUT_MODE */ 68 #define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY 0x0 69 #define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT 0x1 70 #define AN877_ADC_OUTPUT_MODE_GRAY_CODE 0x2 71 72 /* AN877_ADC_REG_OUTPUT_PHASE */ 73 #define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN 0x20 74 #define AN877_ADC_INVERT_DCO_CLK 0x80 75 76 /* AN877_ADC_REG_OUTPUT_DELAY */ 77 #define AN877_ADC_DCO_DELAY_ENABLE 0x80 78 79 /* 80 * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC 81 */ 82 83 #define CHIPID_AD9467 0x50 84 #define AD9467_DEF_OUTPUT_MODE 0x08 85 #define AD9467_REG_VREF_MASK 0x0F 86 87 enum { 88 ID_AD9467, 89 }; 90 91 struct ad9467_state { 92 struct spi_device *spi; 93 struct clk *clk; 94 unsigned int output_mode; 95 96 struct gpio_desc *pwrdown_gpio; 97 struct gpio_desc *reset_gpio; 98 }; 99 100 static int ad9467_spi_read(struct spi_device *spi, unsigned int reg) 101 { 102 unsigned char tbuf[2], rbuf[1]; 103 int ret; 104 105 tbuf[0] = 0x80 | (reg >> 8); 106 tbuf[1] = reg & 0xFF; 107 108 ret = spi_write_then_read(spi, 109 tbuf, ARRAY_SIZE(tbuf), 110 rbuf, ARRAY_SIZE(rbuf)); 111 112 if (ret < 0) 113 return ret; 114 115 return rbuf[0]; 116 } 117 118 static int ad9467_spi_write(struct spi_device *spi, unsigned int reg, 119 unsigned int val) 120 { 121 unsigned char buf[3]; 122 123 buf[0] = reg >> 8; 124 buf[1] = reg & 0xFF; 125 buf[2] = val; 126 127 return spi_write(spi, buf, ARRAY_SIZE(buf)); 128 } 129 130 static int ad9467_reg_access(struct adi_axi_adc_conv *conv, unsigned int reg, 131 unsigned int writeval, unsigned int *readval) 132 { 133 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 134 struct spi_device *spi = st->spi; 135 int ret; 136 137 if (readval == NULL) { 138 ret = ad9467_spi_write(spi, reg, writeval); 139 ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER, 140 AN877_ADC_TRANSFER_SYNC); 141 return ret; 142 } 143 144 ret = ad9467_spi_read(spi, reg); 145 if (ret < 0) 146 return ret; 147 *readval = ret; 148 149 return 0; 150 } 151 152 static const unsigned int ad9467_scale_table[][2] = { 153 {2000, 0}, {2100, 6}, {2200, 7}, 154 {2300, 8}, {2400, 9}, {2500, 10}, 155 }; 156 157 static void __ad9467_get_scale(struct adi_axi_adc_conv *conv, int index, 158 unsigned int *val, unsigned int *val2) 159 { 160 const struct adi_axi_adc_chip_info *info = conv->chip_info; 161 const struct iio_chan_spec *chan = &info->channels[0]; 162 unsigned int tmp; 163 164 tmp = (info->scale_table[index][0] * 1000000ULL) >> 165 chan->scan_type.realbits; 166 *val = tmp / 1000000; 167 *val2 = tmp % 1000000; 168 } 169 170 #define AD9467_CHAN(_chan, _si, _bits, _sign) \ 171 { \ 172 .type = IIO_VOLTAGE, \ 173 .indexed = 1, \ 174 .channel = _chan, \ 175 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 176 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 177 .scan_index = _si, \ 178 .scan_type = { \ 179 .sign = _sign, \ 180 .realbits = _bits, \ 181 .storagebits = 16, \ 182 }, \ 183 } 184 185 static const struct iio_chan_spec ad9467_channels[] = { 186 AD9467_CHAN(0, 0, 16, 'S'), 187 }; 188 189 static const struct adi_axi_adc_chip_info ad9467_chip_tbl[] = { 190 [ID_AD9467] = { 191 .id = CHIPID_AD9467, 192 .max_rate = 250000000UL, 193 .scale_table = ad9467_scale_table, 194 .num_scales = ARRAY_SIZE(ad9467_scale_table), 195 .channels = ad9467_channels, 196 .num_channels = ARRAY_SIZE(ad9467_channels), 197 }, 198 }; 199 200 static int ad9467_get_scale(struct adi_axi_adc_conv *conv, int *val, int *val2) 201 { 202 const struct adi_axi_adc_chip_info *info = conv->chip_info; 203 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 204 unsigned int i, vref_val, vref_mask; 205 206 vref_val = ad9467_spi_read(st->spi, AN877_ADC_REG_VREF); 207 208 switch (info->id) { 209 case CHIPID_AD9467: 210 vref_mask = AD9467_REG_VREF_MASK; 211 break; 212 default: 213 vref_mask = 0xFFFF; 214 break; 215 } 216 217 vref_val &= vref_mask; 218 219 for (i = 0; i < info->num_scales; i++) { 220 if (vref_val == info->scale_table[i][1]) 221 break; 222 } 223 224 if (i == info->num_scales) 225 return -ERANGE; 226 227 __ad9467_get_scale(conv, i, val, val2); 228 229 return IIO_VAL_INT_PLUS_MICRO; 230 } 231 232 static int ad9467_set_scale(struct adi_axi_adc_conv *conv, int val, int val2) 233 { 234 const struct adi_axi_adc_chip_info *info = conv->chip_info; 235 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 236 unsigned int scale_val[2]; 237 unsigned int i; 238 239 if (val != 0) 240 return -EINVAL; 241 242 for (i = 0; i < info->num_scales; i++) { 243 __ad9467_get_scale(conv, i, &scale_val[0], &scale_val[1]); 244 if (scale_val[0] != val || scale_val[1] != val2) 245 continue; 246 247 ad9467_spi_write(st->spi, AN877_ADC_REG_VREF, 248 info->scale_table[i][1]); 249 ad9467_spi_write(st->spi, AN877_ADC_REG_TRANSFER, 250 AN877_ADC_TRANSFER_SYNC); 251 return 0; 252 } 253 254 return -EINVAL; 255 } 256 257 static int ad9467_read_raw(struct adi_axi_adc_conv *conv, 258 struct iio_chan_spec const *chan, 259 int *val, int *val2, long m) 260 { 261 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 262 263 switch (m) { 264 case IIO_CHAN_INFO_SCALE: 265 return ad9467_get_scale(conv, val, val2); 266 case IIO_CHAN_INFO_SAMP_FREQ: 267 *val = clk_get_rate(st->clk); 268 269 return IIO_VAL_INT; 270 default: 271 return -EINVAL; 272 } 273 } 274 275 static int ad9467_write_raw(struct adi_axi_adc_conv *conv, 276 struct iio_chan_spec const *chan, 277 int val, int val2, long mask) 278 { 279 const struct adi_axi_adc_chip_info *info = conv->chip_info; 280 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 281 long r_clk; 282 283 switch (mask) { 284 case IIO_CHAN_INFO_SCALE: 285 return ad9467_set_scale(conv, val, val2); 286 case IIO_CHAN_INFO_SAMP_FREQ: 287 r_clk = clk_round_rate(st->clk, val); 288 if (r_clk < 0 || r_clk > info->max_rate) { 289 dev_warn(&st->spi->dev, 290 "Error setting ADC sample rate %ld", r_clk); 291 return -EINVAL; 292 } 293 294 return clk_set_rate(st->clk, r_clk); 295 default: 296 return -EINVAL; 297 } 298 } 299 300 static int ad9467_outputmode_set(struct spi_device *spi, unsigned int mode) 301 { 302 int ret; 303 304 ret = ad9467_spi_write(spi, AN877_ADC_REG_OUTPUT_MODE, mode); 305 if (ret < 0) 306 return ret; 307 308 return ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER, 309 AN877_ADC_TRANSFER_SYNC); 310 } 311 312 static int ad9467_preenable_setup(struct adi_axi_adc_conv *conv) 313 { 314 struct ad9467_state *st = adi_axi_adc_conv_priv(conv); 315 316 return ad9467_outputmode_set(st->spi, st->output_mode); 317 } 318 319 static int ad9467_setup(struct ad9467_state *st, unsigned int chip_id) 320 { 321 switch (chip_id) { 322 case CHIPID_AD9467: 323 st->output_mode = AD9467_DEF_OUTPUT_MODE | 324 AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT; 325 return 0; 326 default: 327 return -EINVAL; 328 } 329 } 330 331 static void ad9467_clk_disable(void *data) 332 { 333 struct ad9467_state *st = data; 334 335 clk_disable_unprepare(st->clk); 336 } 337 338 static int ad9467_probe(struct spi_device *spi) 339 { 340 const struct adi_axi_adc_chip_info *info; 341 struct adi_axi_adc_conv *conv; 342 struct ad9467_state *st; 343 unsigned int id; 344 int ret; 345 346 info = of_device_get_match_data(&spi->dev); 347 if (!info) 348 return -ENODEV; 349 350 conv = devm_adi_axi_adc_conv_register(&spi->dev, sizeof(*st)); 351 if (IS_ERR(conv)) 352 return PTR_ERR(conv); 353 354 st = adi_axi_adc_conv_priv(conv); 355 st->spi = spi; 356 357 st->clk = devm_clk_get(&spi->dev, "adc-clk"); 358 if (IS_ERR(st->clk)) 359 return PTR_ERR(st->clk); 360 361 ret = clk_prepare_enable(st->clk); 362 if (ret < 0) 363 return ret; 364 365 ret = devm_add_action_or_reset(&spi->dev, ad9467_clk_disable, st); 366 if (ret) 367 return ret; 368 369 st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown", 370 GPIOD_OUT_LOW); 371 if (IS_ERR(st->pwrdown_gpio)) 372 return PTR_ERR(st->pwrdown_gpio); 373 374 st->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", 375 GPIOD_OUT_LOW); 376 if (IS_ERR(st->reset_gpio)) 377 return PTR_ERR(st->reset_gpio); 378 379 if (st->reset_gpio) { 380 udelay(1); 381 ret = gpiod_direction_output(st->reset_gpio, 1); 382 if (ret) 383 return ret; 384 mdelay(10); 385 } 386 387 spi_set_drvdata(spi, st); 388 389 conv->chip_info = info; 390 391 id = ad9467_spi_read(spi, AN877_ADC_REG_CHIP_ID); 392 if (id != conv->chip_info->id) { 393 dev_err(&spi->dev, "Unrecognized CHIP_ID 0x%X\n", id); 394 return -ENODEV; 395 } 396 397 conv->reg_access = ad9467_reg_access; 398 conv->write_raw = ad9467_write_raw; 399 conv->read_raw = ad9467_read_raw; 400 conv->preenable_setup = ad9467_preenable_setup; 401 402 return ad9467_setup(st, id); 403 } 404 405 static const struct of_device_id ad9467_of_match[] = { 406 { .compatible = "adi,ad9467", .data = &ad9467_chip_tbl[ID_AD9467], }, 407 {} 408 }; 409 MODULE_DEVICE_TABLE(of, ad9467_of_match); 410 411 static struct spi_driver ad9467_driver = { 412 .driver = { 413 .name = "ad9467", 414 .of_match_table = ad9467_of_match, 415 }, 416 .probe = ad9467_probe, 417 }; 418 module_spi_driver(ad9467_driver); 419 420 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 421 MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver"); 422 MODULE_LICENSE("GPL v2"); 423