1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * AD7887 SPI ADC driver 4 * 5 * Copyright 2010-2011 Analog Devices Inc. 6 */ 7 8 #include <linux/device.h> 9 #include <linux/kernel.h> 10 #include <linux/slab.h> 11 #include <linux/sysfs.h> 12 #include <linux/spi/spi.h> 13 #include <linux/regulator/consumer.h> 14 #include <linux/err.h> 15 #include <linux/module.h> 16 #include <linux/interrupt.h> 17 #include <linux/bitops.h> 18 19 #include <linux/iio/iio.h> 20 #include <linux/iio/sysfs.h> 21 #include <linux/iio/buffer.h> 22 23 #include <linux/iio/trigger_consumer.h> 24 #include <linux/iio/triggered_buffer.h> 25 26 #include <linux/platform_data/ad7887.h> 27 28 #define AD7887_REF_DIS BIT(5) /* on-chip reference disable */ 29 #define AD7887_DUAL BIT(4) /* dual-channel mode */ 30 #define AD7887_CH_AIN1 BIT(3) /* convert on channel 1, DUAL=1 */ 31 #define AD7887_CH_AIN0 0 /* convert on channel 0, DUAL=0,1 */ 32 #define AD7887_PM_MODE1 0 /* CS based shutdown */ 33 #define AD7887_PM_MODE2 1 /* full on */ 34 #define AD7887_PM_MODE3 2 /* auto shutdown after conversion */ 35 #define AD7887_PM_MODE4 3 /* standby mode */ 36 37 enum ad7887_channels { 38 AD7887_CH0, 39 AD7887_CH0_CH1, 40 AD7887_CH1, 41 }; 42 43 /** 44 * struct ad7887_chip_info - chip specifc information 45 * @int_vref_mv: the internal reference voltage 46 * @channels: channels specification 47 * @num_channels: number of channels 48 * @dual_channels: channels specification in dual mode 49 * @num_dual_channels: number of channels in dual mode 50 */ 51 struct ad7887_chip_info { 52 u16 int_vref_mv; 53 const struct iio_chan_spec *channels; 54 unsigned int num_channels; 55 const struct iio_chan_spec *dual_channels; 56 unsigned int num_dual_channels; 57 }; 58 59 struct ad7887_state { 60 struct spi_device *spi; 61 const struct ad7887_chip_info *chip_info; 62 struct regulator *reg; 63 struct spi_transfer xfer[4]; 64 struct spi_message msg[3]; 65 struct spi_message *ring_msg; 66 unsigned char tx_cmd_buf[4]; 67 68 /* 69 * DMA (thus cache coherency maintenance) requires the 70 * transfer buffers to live in their own cache lines. 71 * Buffer needs to be large enough to hold two 16 bit samples and a 72 * 64 bit aligned 64 bit timestamp. 73 */ 74 unsigned char data[ALIGN(4, sizeof(s64)) + sizeof(s64)] 75 ____cacheline_aligned; 76 }; 77 78 enum ad7887_supported_device_ids { 79 ID_AD7887 80 }; 81 82 static int ad7887_ring_preenable(struct iio_dev *indio_dev) 83 { 84 struct ad7887_state *st = iio_priv(indio_dev); 85 86 /* We know this is a single long so can 'cheat' */ 87 switch (*indio_dev->active_scan_mask) { 88 case (1 << 0): 89 st->ring_msg = &st->msg[AD7887_CH0]; 90 break; 91 case (1 << 1): 92 st->ring_msg = &st->msg[AD7887_CH1]; 93 /* Dummy read: push CH1 setting down to hardware */ 94 spi_sync(st->spi, st->ring_msg); 95 break; 96 case ((1 << 1) | (1 << 0)): 97 st->ring_msg = &st->msg[AD7887_CH0_CH1]; 98 break; 99 } 100 101 return 0; 102 } 103 104 static int ad7887_ring_postdisable(struct iio_dev *indio_dev) 105 { 106 struct ad7887_state *st = iio_priv(indio_dev); 107 108 /* dummy read: restore default CH0 settin */ 109 return spi_sync(st->spi, &st->msg[AD7887_CH0]); 110 } 111 112 /** 113 * ad7887_trigger_handler() bh of trigger launched polling to ring buffer 114 * 115 * Currently there is no option in this driver to disable the saving of 116 * timestamps within the ring. 117 **/ 118 static irqreturn_t ad7887_trigger_handler(int irq, void *p) 119 { 120 struct iio_poll_func *pf = p; 121 struct iio_dev *indio_dev = pf->indio_dev; 122 struct ad7887_state *st = iio_priv(indio_dev); 123 int b_sent; 124 125 b_sent = spi_sync(st->spi, st->ring_msg); 126 if (b_sent) 127 goto done; 128 129 iio_push_to_buffers_with_timestamp(indio_dev, st->data, 130 iio_get_time_ns(indio_dev)); 131 done: 132 iio_trigger_notify_done(indio_dev->trig); 133 134 return IRQ_HANDLED; 135 } 136 137 static const struct iio_buffer_setup_ops ad7887_ring_setup_ops = { 138 .preenable = &ad7887_ring_preenable, 139 .postenable = &iio_triggered_buffer_postenable, 140 .predisable = &iio_triggered_buffer_predisable, 141 .postdisable = &ad7887_ring_postdisable, 142 }; 143 144 static int ad7887_scan_direct(struct ad7887_state *st, unsigned ch) 145 { 146 int ret = spi_sync(st->spi, &st->msg[ch]); 147 if (ret) 148 return ret; 149 150 return (st->data[(ch * 2)] << 8) | st->data[(ch * 2) + 1]; 151 } 152 153 static int ad7887_read_raw(struct iio_dev *indio_dev, 154 struct iio_chan_spec const *chan, 155 int *val, 156 int *val2, 157 long m) 158 { 159 int ret; 160 struct ad7887_state *st = iio_priv(indio_dev); 161 162 switch (m) { 163 case IIO_CHAN_INFO_RAW: 164 ret = iio_device_claim_direct_mode(indio_dev); 165 if (ret) 166 return ret; 167 ret = ad7887_scan_direct(st, chan->address); 168 iio_device_release_direct_mode(indio_dev); 169 170 if (ret < 0) 171 return ret; 172 *val = ret >> chan->scan_type.shift; 173 *val &= GENMASK(chan->scan_type.realbits - 1, 0); 174 return IIO_VAL_INT; 175 case IIO_CHAN_INFO_SCALE: 176 if (st->reg) { 177 *val = regulator_get_voltage(st->reg); 178 if (*val < 0) 179 return *val; 180 *val /= 1000; 181 } else { 182 *val = st->chip_info->int_vref_mv; 183 } 184 185 *val2 = chan->scan_type.realbits; 186 187 return IIO_VAL_FRACTIONAL_LOG2; 188 } 189 return -EINVAL; 190 } 191 192 #define AD7887_CHANNEL(x) { \ 193 .type = IIO_VOLTAGE, \ 194 .indexed = 1, \ 195 .channel = (x), \ 196 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 197 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 198 .address = (x), \ 199 .scan_index = (x), \ 200 .scan_type = { \ 201 .sign = 'u', \ 202 .realbits = 12, \ 203 .storagebits = 16, \ 204 .shift = 0, \ 205 .endianness = IIO_BE, \ 206 }, \ 207 } 208 209 static const struct iio_chan_spec ad7887_channels[] = { 210 AD7887_CHANNEL(0), 211 IIO_CHAN_SOFT_TIMESTAMP(1), 212 }; 213 214 static const struct iio_chan_spec ad7887_dual_channels[] = { 215 AD7887_CHANNEL(0), 216 AD7887_CHANNEL(1), 217 IIO_CHAN_SOFT_TIMESTAMP(2), 218 }; 219 220 static const struct ad7887_chip_info ad7887_chip_info_tbl[] = { 221 /* 222 * More devices added in future 223 */ 224 [ID_AD7887] = { 225 .channels = ad7887_channels, 226 .num_channels = ARRAY_SIZE(ad7887_channels), 227 .dual_channels = ad7887_dual_channels, 228 .num_dual_channels = ARRAY_SIZE(ad7887_dual_channels), 229 .int_vref_mv = 2500, 230 }, 231 }; 232 233 static const struct iio_info ad7887_info = { 234 .read_raw = &ad7887_read_raw, 235 }; 236 237 static int ad7887_probe(struct spi_device *spi) 238 { 239 struct ad7887_platform_data *pdata = spi->dev.platform_data; 240 struct ad7887_state *st; 241 struct iio_dev *indio_dev; 242 uint8_t mode; 243 int ret; 244 245 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 246 if (indio_dev == NULL) 247 return -ENOMEM; 248 249 st = iio_priv(indio_dev); 250 251 if (!pdata || !pdata->use_onchip_ref) { 252 st->reg = devm_regulator_get(&spi->dev, "vref"); 253 if (IS_ERR(st->reg)) 254 return PTR_ERR(st->reg); 255 256 ret = regulator_enable(st->reg); 257 if (ret) 258 return ret; 259 } 260 261 st->chip_info = 262 &ad7887_chip_info_tbl[spi_get_device_id(spi)->driver_data]; 263 264 spi_set_drvdata(spi, indio_dev); 265 st->spi = spi; 266 267 /* Estabilish that the iio_dev is a child of the spi device */ 268 indio_dev->dev.parent = &spi->dev; 269 indio_dev->dev.of_node = spi->dev.of_node; 270 indio_dev->name = spi_get_device_id(spi)->name; 271 indio_dev->info = &ad7887_info; 272 indio_dev->modes = INDIO_DIRECT_MODE; 273 274 /* Setup default message */ 275 276 mode = AD7887_PM_MODE4; 277 if (!pdata || !pdata->use_onchip_ref) 278 mode |= AD7887_REF_DIS; 279 if (pdata && pdata->en_dual) 280 mode |= AD7887_DUAL; 281 282 st->tx_cmd_buf[0] = AD7887_CH_AIN0 | mode; 283 284 st->xfer[0].rx_buf = &st->data[0]; 285 st->xfer[0].tx_buf = &st->tx_cmd_buf[0]; 286 st->xfer[0].len = 2; 287 288 spi_message_init(&st->msg[AD7887_CH0]); 289 spi_message_add_tail(&st->xfer[0], &st->msg[AD7887_CH0]); 290 291 if (pdata && pdata->en_dual) { 292 st->tx_cmd_buf[2] = AD7887_CH_AIN1 | mode; 293 294 st->xfer[1].rx_buf = &st->data[0]; 295 st->xfer[1].tx_buf = &st->tx_cmd_buf[2]; 296 st->xfer[1].len = 2; 297 298 st->xfer[2].rx_buf = &st->data[2]; 299 st->xfer[2].tx_buf = &st->tx_cmd_buf[0]; 300 st->xfer[2].len = 2; 301 302 spi_message_init(&st->msg[AD7887_CH0_CH1]); 303 spi_message_add_tail(&st->xfer[1], &st->msg[AD7887_CH0_CH1]); 304 spi_message_add_tail(&st->xfer[2], &st->msg[AD7887_CH0_CH1]); 305 306 st->xfer[3].rx_buf = &st->data[2]; 307 st->xfer[3].tx_buf = &st->tx_cmd_buf[2]; 308 st->xfer[3].len = 2; 309 310 spi_message_init(&st->msg[AD7887_CH1]); 311 spi_message_add_tail(&st->xfer[3], &st->msg[AD7887_CH1]); 312 313 indio_dev->channels = st->chip_info->dual_channels; 314 indio_dev->num_channels = st->chip_info->num_dual_channels; 315 } else { 316 indio_dev->channels = st->chip_info->channels; 317 indio_dev->num_channels = st->chip_info->num_channels; 318 } 319 320 ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time, 321 &ad7887_trigger_handler, &ad7887_ring_setup_ops); 322 if (ret) 323 goto error_disable_reg; 324 325 ret = iio_device_register(indio_dev); 326 if (ret) 327 goto error_unregister_ring; 328 329 return 0; 330 error_unregister_ring: 331 iio_triggered_buffer_cleanup(indio_dev); 332 error_disable_reg: 333 if (st->reg) 334 regulator_disable(st->reg); 335 336 return ret; 337 } 338 339 static int ad7887_remove(struct spi_device *spi) 340 { 341 struct iio_dev *indio_dev = spi_get_drvdata(spi); 342 struct ad7887_state *st = iio_priv(indio_dev); 343 344 iio_device_unregister(indio_dev); 345 iio_triggered_buffer_cleanup(indio_dev); 346 if (st->reg) 347 regulator_disable(st->reg); 348 349 return 0; 350 } 351 352 static const struct spi_device_id ad7887_id[] = { 353 {"ad7887", ID_AD7887}, 354 {} 355 }; 356 MODULE_DEVICE_TABLE(spi, ad7887_id); 357 358 static struct spi_driver ad7887_driver = { 359 .driver = { 360 .name = "ad7887", 361 }, 362 .probe = ad7887_probe, 363 .remove = ad7887_remove, 364 .id_table = ad7887_id, 365 }; 366 module_spi_driver(ad7887_driver); 367 368 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 369 MODULE_DESCRIPTION("Analog Devices AD7887 ADC"); 370 MODULE_LICENSE("GPL v2"); 371