1 /* 2 * AD7785/AD7792/AD7793/AD7794/AD7795 SPI ADC driver 3 * 4 * Copyright 2011-2012 Analog Devices Inc. 5 * 6 * Licensed under the GPL-2. 7 */ 8 9 #include <linux/interrupt.h> 10 #include <linux/device.h> 11 #include <linux/kernel.h> 12 #include <linux/slab.h> 13 #include <linux/sysfs.h> 14 #include <linux/spi/spi.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/err.h> 17 #include <linux/sched.h> 18 #include <linux/delay.h> 19 #include <linux/module.h> 20 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/buffer.h> 24 #include <linux/iio/trigger.h> 25 #include <linux/iio/trigger_consumer.h> 26 #include <linux/iio/triggered_buffer.h> 27 #include <linux/iio/adc/ad_sigma_delta.h> 28 #include <linux/platform_data/ad7793.h> 29 30 /* Registers */ 31 #define AD7793_REG_COMM 0 /* Communications Register (WO, 8-bit) */ 32 #define AD7793_REG_STAT 0 /* Status Register (RO, 8-bit) */ 33 #define AD7793_REG_MODE 1 /* Mode Register (RW, 16-bit */ 34 #define AD7793_REG_CONF 2 /* Configuration Register (RW, 16-bit) */ 35 #define AD7793_REG_DATA 3 /* Data Register (RO, 16-/24-bit) */ 36 #define AD7793_REG_ID 4 /* ID Register (RO, 8-bit) */ 37 #define AD7793_REG_IO 5 /* IO Register (RO, 8-bit) */ 38 #define AD7793_REG_OFFSET 6 /* Offset Register (RW, 16-bit 39 * (AD7792)/24-bit (AD7793)) */ 40 #define AD7793_REG_FULLSALE 7 /* Full-Scale Register 41 * (RW, 16-bit (AD7792)/24-bit (AD7793)) */ 42 43 /* Communications Register Bit Designations (AD7793_REG_COMM) */ 44 #define AD7793_COMM_WEN (1 << 7) /* Write Enable */ 45 #define AD7793_COMM_WRITE (0 << 6) /* Write Operation */ 46 #define AD7793_COMM_READ (1 << 6) /* Read Operation */ 47 #define AD7793_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */ 48 #define AD7793_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */ 49 50 /* Status Register Bit Designations (AD7793_REG_STAT) */ 51 #define AD7793_STAT_RDY (1 << 7) /* Ready */ 52 #define AD7793_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */ 53 #define AD7793_STAT_CH3 (1 << 2) /* Channel 3 */ 54 #define AD7793_STAT_CH2 (1 << 1) /* Channel 2 */ 55 #define AD7793_STAT_CH1 (1 << 0) /* Channel 1 */ 56 57 /* Mode Register Bit Designations (AD7793_REG_MODE) */ 58 #define AD7793_MODE_SEL(x) (((x) & 0x7) << 13) /* Operation Mode Select */ 59 #define AD7793_MODE_SEL_MASK (0x7 << 13) /* Operation Mode Select mask */ 60 #define AD7793_MODE_CLKSRC(x) (((x) & 0x3) << 6) /* ADC Clock Source Select */ 61 #define AD7793_MODE_RATE(x) ((x) & 0xF) /* Filter Update Rate Select */ 62 63 #define AD7793_MODE_CONT 0 /* Continuous Conversion Mode */ 64 #define AD7793_MODE_SINGLE 1 /* Single Conversion Mode */ 65 #define AD7793_MODE_IDLE 2 /* Idle Mode */ 66 #define AD7793_MODE_PWRDN 3 /* Power-Down Mode */ 67 #define AD7793_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */ 68 #define AD7793_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */ 69 #define AD7793_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */ 70 #define AD7793_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */ 71 72 #define AD7793_CLK_INT 0 /* Internal 64 kHz Clock not 73 * available at the CLK pin */ 74 #define AD7793_CLK_INT_CO 1 /* Internal 64 kHz Clock available 75 * at the CLK pin */ 76 #define AD7793_CLK_EXT 2 /* External 64 kHz Clock */ 77 #define AD7793_CLK_EXT_DIV2 3 /* External Clock divided by 2 */ 78 79 /* Configuration Register Bit Designations (AD7793_REG_CONF) */ 80 #define AD7793_CONF_VBIAS(x) (((x) & 0x3) << 14) /* Bias Voltage 81 * Generator Enable */ 82 #define AD7793_CONF_BO_EN (1 << 13) /* Burnout Current Enable */ 83 #define AD7793_CONF_UNIPOLAR (1 << 12) /* Unipolar/Bipolar Enable */ 84 #define AD7793_CONF_BOOST (1 << 11) /* Boost Enable */ 85 #define AD7793_CONF_GAIN(x) (((x) & 0x7) << 8) /* Gain Select */ 86 #define AD7793_CONF_REFSEL(x) ((x) << 6) /* INT/EXT Reference Select */ 87 #define AD7793_CONF_BUF (1 << 4) /* Buffered Mode Enable */ 88 #define AD7793_CONF_CHAN(x) ((x) & 0xf) /* Channel select */ 89 #define AD7793_CONF_CHAN_MASK 0xf /* Channel select mask */ 90 91 #define AD7793_CH_AIN1P_AIN1M 0 /* AIN1(+) - AIN1(-) */ 92 #define AD7793_CH_AIN2P_AIN2M 1 /* AIN2(+) - AIN2(-) */ 93 #define AD7793_CH_AIN3P_AIN3M 2 /* AIN3(+) - AIN3(-) */ 94 #define AD7793_CH_AIN1M_AIN1M 3 /* AIN1(-) - AIN1(-) */ 95 #define AD7793_CH_TEMP 6 /* Temp Sensor */ 96 #define AD7793_CH_AVDD_MONITOR 7 /* AVDD Monitor */ 97 98 #define AD7795_CH_AIN4P_AIN4M 4 /* AIN4(+) - AIN4(-) */ 99 #define AD7795_CH_AIN5P_AIN5M 5 /* AIN5(+) - AIN5(-) */ 100 #define AD7795_CH_AIN6P_AIN6M 6 /* AIN6(+) - AIN6(-) */ 101 #define AD7795_CH_AIN1M_AIN1M 8 /* AIN1(-) - AIN1(-) */ 102 103 /* ID Register Bit Designations (AD7793_REG_ID) */ 104 #define AD7785_ID 0x3 105 #define AD7792_ID 0xA 106 #define AD7793_ID 0xB 107 #define AD7794_ID 0xF 108 #define AD7795_ID 0xF 109 #define AD7796_ID 0xA 110 #define AD7797_ID 0xB 111 #define AD7798_ID 0x8 112 #define AD7799_ID 0x9 113 #define AD7793_ID_MASK 0xF 114 115 /* IO (Excitation Current Sources) Register Bit Designations (AD7793_REG_IO) */ 116 #define AD7793_IO_IEXC1_IOUT1_IEXC2_IOUT2 0 /* IEXC1 connect to IOUT1, 117 * IEXC2 connect to IOUT2 */ 118 #define AD7793_IO_IEXC1_IOUT2_IEXC2_IOUT1 1 /* IEXC1 connect to IOUT2, 119 * IEXC2 connect to IOUT1 */ 120 #define AD7793_IO_IEXC1_IEXC2_IOUT1 2 /* Both current sources 121 * IEXC1,2 connect to IOUT1 */ 122 #define AD7793_IO_IEXC1_IEXC2_IOUT2 3 /* Both current sources 123 * IEXC1,2 connect to IOUT2 */ 124 125 #define AD7793_IO_IXCEN_10uA (1 << 0) /* Excitation Current 10uA */ 126 #define AD7793_IO_IXCEN_210uA (2 << 0) /* Excitation Current 210uA */ 127 #define AD7793_IO_IXCEN_1mA (3 << 0) /* Excitation Current 1mA */ 128 129 /* NOTE: 130 * The AD7792/AD7793 features a dual use data out ready DOUT/RDY output. 131 * In order to avoid contentions on the SPI bus, it's therefore necessary 132 * to use spi bus locking. 133 * 134 * The DOUT/RDY output must also be wired to an interrupt capable GPIO. 135 */ 136 137 #define AD7793_FLAG_HAS_CLKSEL BIT(0) 138 #define AD7793_FLAG_HAS_REFSEL BIT(1) 139 #define AD7793_FLAG_HAS_VBIAS BIT(2) 140 #define AD7793_HAS_EXITATION_CURRENT BIT(3) 141 #define AD7793_FLAG_HAS_GAIN BIT(4) 142 #define AD7793_FLAG_HAS_BUFFER BIT(5) 143 144 struct ad7793_chip_info { 145 unsigned int id; 146 const struct iio_chan_spec *channels; 147 unsigned int num_channels; 148 unsigned int flags; 149 150 const struct iio_info *iio_info; 151 const u16 *sample_freq_avail; 152 }; 153 154 struct ad7793_state { 155 const struct ad7793_chip_info *chip_info; 156 struct regulator *reg; 157 u16 int_vref_mv; 158 u16 mode; 159 u16 conf; 160 u32 scale_avail[8][2]; 161 162 struct ad_sigma_delta sd; 163 164 }; 165 166 enum ad7793_supported_device_ids { 167 ID_AD7785, 168 ID_AD7792, 169 ID_AD7793, 170 ID_AD7794, 171 ID_AD7795, 172 ID_AD7796, 173 ID_AD7797, 174 ID_AD7798, 175 ID_AD7799, 176 }; 177 178 static struct ad7793_state *ad_sigma_delta_to_ad7793(struct ad_sigma_delta *sd) 179 { 180 return container_of(sd, struct ad7793_state, sd); 181 } 182 183 static int ad7793_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 184 { 185 struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd); 186 187 st->conf &= ~AD7793_CONF_CHAN_MASK; 188 st->conf |= AD7793_CONF_CHAN(channel); 189 190 return ad_sd_write_reg(&st->sd, AD7793_REG_CONF, 2, st->conf); 191 } 192 193 static int ad7793_set_mode(struct ad_sigma_delta *sd, 194 enum ad_sigma_delta_mode mode) 195 { 196 struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd); 197 198 st->mode &= ~AD7793_MODE_SEL_MASK; 199 st->mode |= AD7793_MODE_SEL(mode); 200 201 return ad_sd_write_reg(&st->sd, AD7793_REG_MODE, 2, st->mode); 202 } 203 204 static const struct ad_sigma_delta_info ad7793_sigma_delta_info = { 205 .set_channel = ad7793_set_channel, 206 .set_mode = ad7793_set_mode, 207 .has_registers = true, 208 .addr_shift = 3, 209 .read_mask = BIT(6), 210 }; 211 212 static const struct ad_sd_calib_data ad7793_calib_arr[6] = { 213 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN1P_AIN1M}, 214 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN1P_AIN1M}, 215 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN2P_AIN2M}, 216 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN2P_AIN2M}, 217 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN3P_AIN3M}, 218 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN3P_AIN3M} 219 }; 220 221 static int ad7793_calibrate_all(struct ad7793_state *st) 222 { 223 return ad_sd_calibrate_all(&st->sd, ad7793_calib_arr, 224 ARRAY_SIZE(ad7793_calib_arr)); 225 } 226 227 static int ad7793_check_platform_data(struct ad7793_state *st, 228 const struct ad7793_platform_data *pdata) 229 { 230 if ((pdata->current_source_direction == AD7793_IEXEC1_IEXEC2_IOUT1 || 231 pdata->current_source_direction == AD7793_IEXEC1_IEXEC2_IOUT2) && 232 ((pdata->exitation_current != AD7793_IX_10uA) && 233 (pdata->exitation_current != AD7793_IX_210uA))) 234 return -EINVAL; 235 236 if (!(st->chip_info->flags & AD7793_FLAG_HAS_CLKSEL) && 237 pdata->clock_src != AD7793_CLK_SRC_INT) 238 return -EINVAL; 239 240 if (!(st->chip_info->flags & AD7793_FLAG_HAS_REFSEL) && 241 pdata->refsel != AD7793_REFSEL_REFIN1) 242 return -EINVAL; 243 244 if (!(st->chip_info->flags & AD7793_FLAG_HAS_VBIAS) && 245 pdata->bias_voltage != AD7793_BIAS_VOLTAGE_DISABLED) 246 return -EINVAL; 247 248 if (!(st->chip_info->flags & AD7793_HAS_EXITATION_CURRENT) && 249 pdata->exitation_current != AD7793_IX_DISABLED) 250 return -EINVAL; 251 252 return 0; 253 } 254 255 static int ad7793_setup(struct iio_dev *indio_dev, 256 const struct ad7793_platform_data *pdata, 257 unsigned int vref_mv) 258 { 259 struct ad7793_state *st = iio_priv(indio_dev); 260 int i, ret = -1; 261 unsigned long long scale_uv; 262 u32 id; 263 264 ret = ad7793_check_platform_data(st, pdata); 265 if (ret) 266 return ret; 267 268 /* reset the serial interface */ 269 ret = spi_write(st->sd.spi, (u8 *)&ret, sizeof(ret)); 270 if (ret < 0) 271 goto out; 272 usleep_range(500, 2000); /* Wait for at least 500us */ 273 274 /* write/read test for device presence */ 275 ret = ad_sd_read_reg(&st->sd, AD7793_REG_ID, 1, &id); 276 if (ret) 277 goto out; 278 279 id &= AD7793_ID_MASK; 280 281 if (id != st->chip_info->id) { 282 dev_err(&st->sd.spi->dev, "device ID query failed\n"); 283 goto out; 284 } 285 286 st->mode = AD7793_MODE_RATE(1); 287 st->conf = 0; 288 289 if (st->chip_info->flags & AD7793_FLAG_HAS_CLKSEL) 290 st->mode |= AD7793_MODE_CLKSRC(pdata->clock_src); 291 if (st->chip_info->flags & AD7793_FLAG_HAS_REFSEL) 292 st->conf |= AD7793_CONF_REFSEL(pdata->refsel); 293 if (st->chip_info->flags & AD7793_FLAG_HAS_VBIAS) 294 st->conf |= AD7793_CONF_VBIAS(pdata->bias_voltage); 295 if (pdata->buffered || !(st->chip_info->flags & AD7793_FLAG_HAS_BUFFER)) 296 st->conf |= AD7793_CONF_BUF; 297 if (pdata->boost_enable && 298 (st->chip_info->flags & AD7793_FLAG_HAS_VBIAS)) 299 st->conf |= AD7793_CONF_BOOST; 300 if (pdata->burnout_current) 301 st->conf |= AD7793_CONF_BO_EN; 302 if (pdata->unipolar) 303 st->conf |= AD7793_CONF_UNIPOLAR; 304 305 if (!(st->chip_info->flags & AD7793_FLAG_HAS_GAIN)) 306 st->conf |= AD7793_CONF_GAIN(7); 307 308 ret = ad7793_set_mode(&st->sd, AD_SD_MODE_IDLE); 309 if (ret) 310 goto out; 311 312 ret = ad7793_set_channel(&st->sd, 0); 313 if (ret) 314 goto out; 315 316 if (st->chip_info->flags & AD7793_HAS_EXITATION_CURRENT) { 317 ret = ad_sd_write_reg(&st->sd, AD7793_REG_IO, 1, 318 pdata->exitation_current | 319 (pdata->current_source_direction << 2)); 320 if (ret) 321 goto out; 322 } 323 324 ret = ad7793_calibrate_all(st); 325 if (ret) 326 goto out; 327 328 /* Populate available ADC input ranges */ 329 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { 330 scale_uv = ((u64)vref_mv * 100000000) 331 >> (st->chip_info->channels[0].scan_type.realbits - 332 (!!(st->conf & AD7793_CONF_UNIPOLAR) ? 0 : 1)); 333 scale_uv >>= i; 334 335 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; 336 st->scale_avail[i][0] = scale_uv; 337 } 338 339 return 0; 340 out: 341 dev_err(&st->sd.spi->dev, "setup failed\n"); 342 return ret; 343 } 344 345 static const u16 ad7793_sample_freq_avail[16] = {0, 470, 242, 123, 62, 50, 39, 346 33, 19, 17, 16, 12, 10, 8, 6, 4}; 347 348 static const u16 ad7797_sample_freq_avail[16] = {0, 0, 0, 123, 62, 50, 0, 349 33, 0, 17, 16, 12, 10, 8, 6, 4}; 350 351 static ssize_t ad7793_read_frequency(struct device *dev, 352 struct device_attribute *attr, 353 char *buf) 354 { 355 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 356 struct ad7793_state *st = iio_priv(indio_dev); 357 358 return sprintf(buf, "%d\n", 359 st->chip_info->sample_freq_avail[AD7793_MODE_RATE(st->mode)]); 360 } 361 362 static ssize_t ad7793_write_frequency(struct device *dev, 363 struct device_attribute *attr, 364 const char *buf, 365 size_t len) 366 { 367 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 368 struct ad7793_state *st = iio_priv(indio_dev); 369 long lval; 370 int i, ret; 371 372 ret = kstrtol(buf, 10, &lval); 373 if (ret) 374 return ret; 375 376 if (lval == 0) 377 return -EINVAL; 378 379 for (i = 0; i < 16; i++) 380 if (lval == st->chip_info->sample_freq_avail[i]) 381 break; 382 if (i == 16) 383 return -EINVAL; 384 385 ret = iio_device_claim_direct_mode(indio_dev); 386 if (ret) 387 return ret; 388 st->mode &= ~AD7793_MODE_RATE(-1); 389 st->mode |= AD7793_MODE_RATE(i); 390 ad_sd_write_reg(&st->sd, AD7793_REG_MODE, sizeof(st->mode), st->mode); 391 iio_device_release_direct_mode(indio_dev); 392 393 return len; 394 } 395 396 static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO, 397 ad7793_read_frequency, 398 ad7793_write_frequency); 399 400 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( 401 "470 242 123 62 50 39 33 19 17 16 12 10 8 6 4"); 402 403 static IIO_CONST_ATTR_NAMED(sampling_frequency_available_ad7797, 404 sampling_frequency_available, "123 62 50 33 17 16 12 10 8 6 4"); 405 406 static ssize_t ad7793_show_scale_available(struct device *dev, 407 struct device_attribute *attr, char *buf) 408 { 409 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 410 struct ad7793_state *st = iio_priv(indio_dev); 411 int i, len = 0; 412 413 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) 414 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0], 415 st->scale_avail[i][1]); 416 417 len += sprintf(buf + len, "\n"); 418 419 return len; 420 } 421 422 static IIO_DEVICE_ATTR_NAMED(in_m_in_scale_available, 423 in_voltage-voltage_scale_available, S_IRUGO, 424 ad7793_show_scale_available, NULL, 0); 425 426 static struct attribute *ad7793_attributes[] = { 427 &iio_dev_attr_sampling_frequency.dev_attr.attr, 428 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 429 &iio_dev_attr_in_m_in_scale_available.dev_attr.attr, 430 NULL 431 }; 432 433 static const struct attribute_group ad7793_attribute_group = { 434 .attrs = ad7793_attributes, 435 }; 436 437 static struct attribute *ad7797_attributes[] = { 438 &iio_dev_attr_sampling_frequency.dev_attr.attr, 439 &iio_const_attr_sampling_frequency_available_ad7797.dev_attr.attr, 440 NULL 441 }; 442 443 static const struct attribute_group ad7797_attribute_group = { 444 .attrs = ad7797_attributes, 445 }; 446 447 static int ad7793_read_raw(struct iio_dev *indio_dev, 448 struct iio_chan_spec const *chan, 449 int *val, 450 int *val2, 451 long m) 452 { 453 struct ad7793_state *st = iio_priv(indio_dev); 454 int ret; 455 unsigned long long scale_uv; 456 bool unipolar = !!(st->conf & AD7793_CONF_UNIPOLAR); 457 458 switch (m) { 459 case IIO_CHAN_INFO_RAW: 460 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val); 461 if (ret < 0) 462 return ret; 463 464 return IIO_VAL_INT; 465 466 case IIO_CHAN_INFO_SCALE: 467 switch (chan->type) { 468 case IIO_VOLTAGE: 469 if (chan->differential) { 470 *val = st-> 471 scale_avail[(st->conf >> 8) & 0x7][0]; 472 *val2 = st-> 473 scale_avail[(st->conf >> 8) & 0x7][1]; 474 return IIO_VAL_INT_PLUS_NANO; 475 } 476 /* 1170mV / 2^23 * 6 */ 477 scale_uv = (1170ULL * 1000000000ULL * 6ULL); 478 break; 479 case IIO_TEMP: 480 /* 1170mV / 0.81 mV/C / 2^23 */ 481 scale_uv = 1444444444444444ULL; 482 break; 483 default: 484 return -EINVAL; 485 } 486 487 scale_uv >>= (chan->scan_type.realbits - (unipolar ? 0 : 1)); 488 *val = 0; 489 *val2 = scale_uv; 490 return IIO_VAL_INT_PLUS_NANO; 491 case IIO_CHAN_INFO_OFFSET: 492 if (!unipolar) 493 *val = -(1 << (chan->scan_type.realbits - 1)); 494 else 495 *val = 0; 496 497 /* Kelvin to Celsius */ 498 if (chan->type == IIO_TEMP) { 499 unsigned long long offset; 500 unsigned int shift; 501 502 shift = chan->scan_type.realbits - (unipolar ? 0 : 1); 503 offset = 273ULL << shift; 504 do_div(offset, 1444); 505 *val -= offset; 506 } 507 return IIO_VAL_INT; 508 } 509 return -EINVAL; 510 } 511 512 static int ad7793_write_raw(struct iio_dev *indio_dev, 513 struct iio_chan_spec const *chan, 514 int val, 515 int val2, 516 long mask) 517 { 518 struct ad7793_state *st = iio_priv(indio_dev); 519 int ret, i; 520 unsigned int tmp; 521 522 ret = iio_device_claim_direct_mode(indio_dev); 523 if (ret) 524 return ret; 525 526 switch (mask) { 527 case IIO_CHAN_INFO_SCALE: 528 ret = -EINVAL; 529 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) 530 if (val2 == st->scale_avail[i][1]) { 531 ret = 0; 532 tmp = st->conf; 533 st->conf &= ~AD7793_CONF_GAIN(-1); 534 st->conf |= AD7793_CONF_GAIN(i); 535 536 if (tmp == st->conf) 537 break; 538 539 ad_sd_write_reg(&st->sd, AD7793_REG_CONF, 540 sizeof(st->conf), st->conf); 541 ad7793_calibrate_all(st); 542 break; 543 } 544 break; 545 default: 546 ret = -EINVAL; 547 } 548 549 iio_device_release_direct_mode(indio_dev); 550 return ret; 551 } 552 553 static int ad7793_write_raw_get_fmt(struct iio_dev *indio_dev, 554 struct iio_chan_spec const *chan, 555 long mask) 556 { 557 return IIO_VAL_INT_PLUS_NANO; 558 } 559 560 static const struct iio_info ad7793_info = { 561 .read_raw = &ad7793_read_raw, 562 .write_raw = &ad7793_write_raw, 563 .write_raw_get_fmt = &ad7793_write_raw_get_fmt, 564 .attrs = &ad7793_attribute_group, 565 .validate_trigger = ad_sd_validate_trigger, 566 .driver_module = THIS_MODULE, 567 }; 568 569 static const struct iio_info ad7797_info = { 570 .read_raw = &ad7793_read_raw, 571 .write_raw = &ad7793_write_raw, 572 .write_raw_get_fmt = &ad7793_write_raw_get_fmt, 573 .attrs = &ad7793_attribute_group, 574 .validate_trigger = ad_sd_validate_trigger, 575 .driver_module = THIS_MODULE, 576 }; 577 578 #define DECLARE_AD7793_CHANNELS(_name, _b, _sb, _s) \ 579 const struct iio_chan_spec _name##_channels[] = { \ 580 AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), (_s)), \ 581 AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), (_s)), \ 582 AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), (_s)), \ 583 AD_SD_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), (_s)), \ 584 AD_SD_TEMP_CHANNEL(4, AD7793_CH_TEMP, (_b), (_sb), (_s)), \ 585 AD_SD_SUPPLY_CHANNEL(5, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), (_s)), \ 586 IIO_CHAN_SOFT_TIMESTAMP(6), \ 587 } 588 589 #define DECLARE_AD7795_CHANNELS(_name, _b, _sb) \ 590 const struct iio_chan_spec _name##_channels[] = { \ 591 AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \ 592 AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \ 593 AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \ 594 AD_SD_DIFF_CHANNEL(3, 3, 3, AD7795_CH_AIN4P_AIN4M, (_b), (_sb), 0), \ 595 AD_SD_DIFF_CHANNEL(4, 4, 4, AD7795_CH_AIN5P_AIN5M, (_b), (_sb), 0), \ 596 AD_SD_DIFF_CHANNEL(5, 5, 5, AD7795_CH_AIN6P_AIN6M, (_b), (_sb), 0), \ 597 AD_SD_SHORTED_CHANNEL(6, 0, AD7795_CH_AIN1M_AIN1M, (_b), (_sb), 0), \ 598 AD_SD_TEMP_CHANNEL(7, AD7793_CH_TEMP, (_b), (_sb), 0), \ 599 AD_SD_SUPPLY_CHANNEL(8, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \ 600 IIO_CHAN_SOFT_TIMESTAMP(9), \ 601 } 602 603 #define DECLARE_AD7797_CHANNELS(_name, _b, _sb) \ 604 const struct iio_chan_spec _name##_channels[] = { \ 605 AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \ 606 AD_SD_SHORTED_CHANNEL(1, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \ 607 AD_SD_TEMP_CHANNEL(2, AD7793_CH_TEMP, (_b), (_sb), 0), \ 608 AD_SD_SUPPLY_CHANNEL(3, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \ 609 IIO_CHAN_SOFT_TIMESTAMP(4), \ 610 } 611 612 #define DECLARE_AD7799_CHANNELS(_name, _b, _sb) \ 613 const struct iio_chan_spec _name##_channels[] = { \ 614 AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \ 615 AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \ 616 AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \ 617 AD_SD_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \ 618 AD_SD_SUPPLY_CHANNEL(4, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \ 619 IIO_CHAN_SOFT_TIMESTAMP(5), \ 620 } 621 622 static DECLARE_AD7793_CHANNELS(ad7785, 20, 32, 4); 623 static DECLARE_AD7793_CHANNELS(ad7792, 16, 32, 0); 624 static DECLARE_AD7793_CHANNELS(ad7793, 24, 32, 0); 625 static DECLARE_AD7795_CHANNELS(ad7794, 16, 32); 626 static DECLARE_AD7795_CHANNELS(ad7795, 24, 32); 627 static DECLARE_AD7797_CHANNELS(ad7796, 16, 16); 628 static DECLARE_AD7797_CHANNELS(ad7797, 24, 32); 629 static DECLARE_AD7799_CHANNELS(ad7798, 16, 16); 630 static DECLARE_AD7799_CHANNELS(ad7799, 24, 32); 631 632 static const struct ad7793_chip_info ad7793_chip_info_tbl[] = { 633 [ID_AD7785] = { 634 .id = AD7785_ID, 635 .channels = ad7785_channels, 636 .num_channels = ARRAY_SIZE(ad7785_channels), 637 .iio_info = &ad7793_info, 638 .sample_freq_avail = ad7793_sample_freq_avail, 639 .flags = AD7793_FLAG_HAS_CLKSEL | 640 AD7793_FLAG_HAS_REFSEL | 641 AD7793_FLAG_HAS_VBIAS | 642 AD7793_HAS_EXITATION_CURRENT | 643 AD7793_FLAG_HAS_GAIN | 644 AD7793_FLAG_HAS_BUFFER, 645 }, 646 [ID_AD7792] = { 647 .id = AD7792_ID, 648 .channels = ad7792_channels, 649 .num_channels = ARRAY_SIZE(ad7792_channels), 650 .iio_info = &ad7793_info, 651 .sample_freq_avail = ad7793_sample_freq_avail, 652 .flags = AD7793_FLAG_HAS_CLKSEL | 653 AD7793_FLAG_HAS_REFSEL | 654 AD7793_FLAG_HAS_VBIAS | 655 AD7793_HAS_EXITATION_CURRENT | 656 AD7793_FLAG_HAS_GAIN | 657 AD7793_FLAG_HAS_BUFFER, 658 }, 659 [ID_AD7793] = { 660 .id = AD7793_ID, 661 .channels = ad7793_channels, 662 .num_channels = ARRAY_SIZE(ad7793_channels), 663 .iio_info = &ad7793_info, 664 .sample_freq_avail = ad7793_sample_freq_avail, 665 .flags = AD7793_FLAG_HAS_CLKSEL | 666 AD7793_FLAG_HAS_REFSEL | 667 AD7793_FLAG_HAS_VBIAS | 668 AD7793_HAS_EXITATION_CURRENT | 669 AD7793_FLAG_HAS_GAIN | 670 AD7793_FLAG_HAS_BUFFER, 671 }, 672 [ID_AD7794] = { 673 .id = AD7794_ID, 674 .channels = ad7794_channels, 675 .num_channels = ARRAY_SIZE(ad7794_channels), 676 .iio_info = &ad7793_info, 677 .sample_freq_avail = ad7793_sample_freq_avail, 678 .flags = AD7793_FLAG_HAS_CLKSEL | 679 AD7793_FLAG_HAS_REFSEL | 680 AD7793_FLAG_HAS_VBIAS | 681 AD7793_HAS_EXITATION_CURRENT | 682 AD7793_FLAG_HAS_GAIN | 683 AD7793_FLAG_HAS_BUFFER, 684 }, 685 [ID_AD7795] = { 686 .id = AD7795_ID, 687 .channels = ad7795_channels, 688 .num_channels = ARRAY_SIZE(ad7795_channels), 689 .iio_info = &ad7793_info, 690 .sample_freq_avail = ad7793_sample_freq_avail, 691 .flags = AD7793_FLAG_HAS_CLKSEL | 692 AD7793_FLAG_HAS_REFSEL | 693 AD7793_FLAG_HAS_VBIAS | 694 AD7793_HAS_EXITATION_CURRENT | 695 AD7793_FLAG_HAS_GAIN | 696 AD7793_FLAG_HAS_BUFFER, 697 }, 698 [ID_AD7796] = { 699 .id = AD7796_ID, 700 .channels = ad7796_channels, 701 .num_channels = ARRAY_SIZE(ad7796_channels), 702 .iio_info = &ad7797_info, 703 .sample_freq_avail = ad7797_sample_freq_avail, 704 .flags = AD7793_FLAG_HAS_CLKSEL, 705 }, 706 [ID_AD7797] = { 707 .id = AD7797_ID, 708 .channels = ad7797_channels, 709 .num_channels = ARRAY_SIZE(ad7797_channels), 710 .iio_info = &ad7797_info, 711 .sample_freq_avail = ad7797_sample_freq_avail, 712 .flags = AD7793_FLAG_HAS_CLKSEL, 713 }, 714 [ID_AD7798] = { 715 .id = AD7798_ID, 716 .channels = ad7798_channels, 717 .num_channels = ARRAY_SIZE(ad7798_channels), 718 .iio_info = &ad7793_info, 719 .sample_freq_avail = ad7793_sample_freq_avail, 720 .flags = AD7793_FLAG_HAS_GAIN | 721 AD7793_FLAG_HAS_BUFFER, 722 }, 723 [ID_AD7799] = { 724 .id = AD7799_ID, 725 .channels = ad7799_channels, 726 .num_channels = ARRAY_SIZE(ad7799_channels), 727 .iio_info = &ad7793_info, 728 .sample_freq_avail = ad7793_sample_freq_avail, 729 .flags = AD7793_FLAG_HAS_GAIN | 730 AD7793_FLAG_HAS_BUFFER, 731 }, 732 }; 733 734 static int ad7793_probe(struct spi_device *spi) 735 { 736 const struct ad7793_platform_data *pdata = spi->dev.platform_data; 737 struct ad7793_state *st; 738 struct iio_dev *indio_dev; 739 int ret, vref_mv = 0; 740 741 if (!pdata) { 742 dev_err(&spi->dev, "no platform data?\n"); 743 return -ENODEV; 744 } 745 746 if (!spi->irq) { 747 dev_err(&spi->dev, "no IRQ?\n"); 748 return -ENODEV; 749 } 750 751 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 752 if (indio_dev == NULL) 753 return -ENOMEM; 754 755 st = iio_priv(indio_dev); 756 757 ad_sd_init(&st->sd, indio_dev, spi, &ad7793_sigma_delta_info); 758 759 if (pdata->refsel != AD7793_REFSEL_INTERNAL) { 760 st->reg = devm_regulator_get(&spi->dev, "refin"); 761 if (IS_ERR(st->reg)) 762 return PTR_ERR(st->reg); 763 764 ret = regulator_enable(st->reg); 765 if (ret) 766 return ret; 767 768 vref_mv = regulator_get_voltage(st->reg); 769 if (vref_mv < 0) { 770 ret = vref_mv; 771 goto error_disable_reg; 772 } 773 774 vref_mv /= 1000; 775 } else { 776 vref_mv = 1170; /* Build-in ref */ 777 } 778 779 st->chip_info = 780 &ad7793_chip_info_tbl[spi_get_device_id(spi)->driver_data]; 781 782 spi_set_drvdata(spi, indio_dev); 783 784 indio_dev->dev.parent = &spi->dev; 785 indio_dev->dev.of_node = spi->dev.of_node; 786 indio_dev->name = spi_get_device_id(spi)->name; 787 indio_dev->modes = INDIO_DIRECT_MODE; 788 indio_dev->channels = st->chip_info->channels; 789 indio_dev->num_channels = st->chip_info->num_channels; 790 indio_dev->info = st->chip_info->iio_info; 791 792 ret = ad_sd_setup_buffer_and_trigger(indio_dev); 793 if (ret) 794 goto error_disable_reg; 795 796 ret = ad7793_setup(indio_dev, pdata, vref_mv); 797 if (ret) 798 goto error_remove_trigger; 799 800 ret = iio_device_register(indio_dev); 801 if (ret) 802 goto error_remove_trigger; 803 804 return 0; 805 806 error_remove_trigger: 807 ad_sd_cleanup_buffer_and_trigger(indio_dev); 808 error_disable_reg: 809 if (pdata->refsel != AD7793_REFSEL_INTERNAL) 810 regulator_disable(st->reg); 811 812 return ret; 813 } 814 815 static int ad7793_remove(struct spi_device *spi) 816 { 817 const struct ad7793_platform_data *pdata = spi->dev.platform_data; 818 struct iio_dev *indio_dev = spi_get_drvdata(spi); 819 struct ad7793_state *st = iio_priv(indio_dev); 820 821 iio_device_unregister(indio_dev); 822 ad_sd_cleanup_buffer_and_trigger(indio_dev); 823 824 if (pdata->refsel != AD7793_REFSEL_INTERNAL) 825 regulator_disable(st->reg); 826 827 return 0; 828 } 829 830 static const struct spi_device_id ad7793_id[] = { 831 {"ad7785", ID_AD7785}, 832 {"ad7792", ID_AD7792}, 833 {"ad7793", ID_AD7793}, 834 {"ad7794", ID_AD7794}, 835 {"ad7795", ID_AD7795}, 836 {"ad7796", ID_AD7796}, 837 {"ad7797", ID_AD7797}, 838 {"ad7798", ID_AD7798}, 839 {"ad7799", ID_AD7799}, 840 {} 841 }; 842 MODULE_DEVICE_TABLE(spi, ad7793_id); 843 844 static struct spi_driver ad7793_driver = { 845 .driver = { 846 .name = "ad7793", 847 }, 848 .probe = ad7793_probe, 849 .remove = ad7793_remove, 850 .id_table = ad7793_id, 851 }; 852 module_spi_driver(ad7793_driver); 853 854 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); 855 MODULE_DESCRIPTION("Analog Devices AD7793 and similar ADCs"); 856 MODULE_LICENSE("GPL v2"); 857