1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Analog Devices AD7466/7/8 AD7476/5/7/8 (A) SPI ADC driver 4 * TI ADC081S/ADC101S/ADC121S 8/10/12-bit SPI ADC driver 5 * 6 * Copyright 2010 Analog Devices Inc. 7 */ 8 9 #include <linux/device.h> 10 #include <linux/kernel.h> 11 #include <linux/slab.h> 12 #include <linux/sysfs.h> 13 #include <linux/spi/spi.h> 14 #include <linux/regulator/consumer.h> 15 #include <linux/gpio/consumer.h> 16 #include <linux/err.h> 17 #include <linux/module.h> 18 #include <linux/bitops.h> 19 #include <linux/delay.h> 20 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/buffer.h> 24 #include <linux/iio/trigger_consumer.h> 25 #include <linux/iio/triggered_buffer.h> 26 27 struct ad7476_state; 28 29 struct ad7476_chip_info { 30 unsigned int int_vref_uv; 31 struct iio_chan_spec channel[2]; 32 /* channels used when convst gpio is defined */ 33 struct iio_chan_spec convst_channel[2]; 34 void (*reset)(struct ad7476_state *); 35 }; 36 37 struct ad7476_state { 38 struct spi_device *spi; 39 const struct ad7476_chip_info *chip_info; 40 struct regulator *reg; 41 struct gpio_desc *convst_gpio; 42 struct spi_transfer xfer; 43 struct spi_message msg; 44 /* 45 * DMA (thus cache coherency maintenance) requires the 46 * transfer buffers to live in their own cache lines. 47 * Make the buffer large enough for one 16 bit sample and one 64 bit 48 * aligned 64 bit timestamp. 49 */ 50 unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)] 51 ____cacheline_aligned; 52 }; 53 54 enum ad7476_supported_device_ids { 55 ID_AD7091R, 56 ID_AD7276, 57 ID_AD7277, 58 ID_AD7278, 59 ID_AD7466, 60 ID_AD7467, 61 ID_AD7468, 62 ID_AD7495, 63 ID_AD7940, 64 ID_ADC081S, 65 ID_ADC101S, 66 ID_ADC121S, 67 ID_ADS7866, 68 ID_ADS7867, 69 ID_ADS7868, 70 ID_LTC2314_14, 71 }; 72 73 static void ad7091_convst(struct ad7476_state *st) 74 { 75 if (!st->convst_gpio) 76 return; 77 78 gpiod_set_value(st->convst_gpio, 0); 79 udelay(1); /* CONVST pulse width: 10 ns min */ 80 gpiod_set_value(st->convst_gpio, 1); 81 udelay(1); /* Conversion time: 650 ns max */ 82 } 83 84 static irqreturn_t ad7476_trigger_handler(int irq, void *p) 85 { 86 struct iio_poll_func *pf = p; 87 struct iio_dev *indio_dev = pf->indio_dev; 88 struct ad7476_state *st = iio_priv(indio_dev); 89 int b_sent; 90 91 ad7091_convst(st); 92 93 b_sent = spi_sync(st->spi, &st->msg); 94 if (b_sent < 0) 95 goto done; 96 97 iio_push_to_buffers_with_timestamp(indio_dev, st->data, 98 iio_get_time_ns(indio_dev)); 99 done: 100 iio_trigger_notify_done(indio_dev->trig); 101 102 return IRQ_HANDLED; 103 } 104 105 static void ad7091_reset(struct ad7476_state *st) 106 { 107 /* Any transfers with 8 scl cycles will reset the device */ 108 spi_read(st->spi, st->data, 1); 109 } 110 111 static int ad7476_scan_direct(struct ad7476_state *st) 112 { 113 int ret; 114 115 ad7091_convst(st); 116 117 ret = spi_sync(st->spi, &st->msg); 118 if (ret) 119 return ret; 120 121 return be16_to_cpup((__be16 *)st->data); 122 } 123 124 static int ad7476_read_raw(struct iio_dev *indio_dev, 125 struct iio_chan_spec const *chan, 126 int *val, 127 int *val2, 128 long m) 129 { 130 int ret; 131 struct ad7476_state *st = iio_priv(indio_dev); 132 int scale_uv; 133 134 switch (m) { 135 case IIO_CHAN_INFO_RAW: 136 ret = iio_device_claim_direct_mode(indio_dev); 137 if (ret) 138 return ret; 139 ret = ad7476_scan_direct(st); 140 iio_device_release_direct_mode(indio_dev); 141 142 if (ret < 0) 143 return ret; 144 *val = (ret >> st->chip_info->channel[0].scan_type.shift) & 145 GENMASK(st->chip_info->channel[0].scan_type.realbits - 1, 0); 146 return IIO_VAL_INT; 147 case IIO_CHAN_INFO_SCALE: 148 if (!st->chip_info->int_vref_uv) { 149 scale_uv = regulator_get_voltage(st->reg); 150 if (scale_uv < 0) 151 return scale_uv; 152 } else { 153 scale_uv = st->chip_info->int_vref_uv; 154 } 155 *val = scale_uv / 1000; 156 *val2 = chan->scan_type.realbits; 157 return IIO_VAL_FRACTIONAL_LOG2; 158 } 159 return -EINVAL; 160 } 161 162 #define _AD7476_CHAN(bits, _shift, _info_mask_sep) \ 163 { \ 164 .type = IIO_VOLTAGE, \ 165 .indexed = 1, \ 166 .info_mask_separate = _info_mask_sep, \ 167 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 168 .scan_type = { \ 169 .sign = 'u', \ 170 .realbits = (bits), \ 171 .storagebits = 16, \ 172 .shift = (_shift), \ 173 .endianness = IIO_BE, \ 174 }, \ 175 } 176 177 #define ADC081S_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \ 178 BIT(IIO_CHAN_INFO_RAW)) 179 #define AD7476_CHAN(bits) _AD7476_CHAN((bits), 13 - (bits), \ 180 BIT(IIO_CHAN_INFO_RAW)) 181 #define AD7940_CHAN(bits) _AD7476_CHAN((bits), 15 - (bits), \ 182 BIT(IIO_CHAN_INFO_RAW)) 183 #define AD7091R_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), 0) 184 #define AD7091R_CONVST_CHAN(bits) _AD7476_CHAN((bits), 16 - (bits), \ 185 BIT(IIO_CHAN_INFO_RAW)) 186 #define ADS786X_CHAN(bits) _AD7476_CHAN((bits), 12 - (bits), \ 187 BIT(IIO_CHAN_INFO_RAW)) 188 189 static const struct ad7476_chip_info ad7476_chip_info_tbl[] = { 190 [ID_AD7091R] = { 191 .channel[0] = AD7091R_CHAN(12), 192 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 193 .convst_channel[0] = AD7091R_CONVST_CHAN(12), 194 .convst_channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 195 .reset = ad7091_reset, 196 }, 197 [ID_AD7276] = { 198 .channel[0] = AD7940_CHAN(12), 199 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 200 }, 201 [ID_AD7277] = { 202 .channel[0] = AD7940_CHAN(10), 203 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 204 }, 205 [ID_AD7278] = { 206 .channel[0] = AD7940_CHAN(8), 207 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 208 }, 209 [ID_AD7466] = { 210 .channel[0] = AD7476_CHAN(12), 211 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 212 }, 213 [ID_AD7467] = { 214 .channel[0] = AD7476_CHAN(10), 215 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 216 }, 217 [ID_AD7468] = { 218 .channel[0] = AD7476_CHAN(8), 219 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 220 }, 221 [ID_AD7495] = { 222 .channel[0] = AD7476_CHAN(12), 223 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 224 .int_vref_uv = 2500000, 225 }, 226 [ID_AD7940] = { 227 .channel[0] = AD7940_CHAN(14), 228 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 229 }, 230 [ID_ADC081S] = { 231 .channel[0] = ADC081S_CHAN(8), 232 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 233 }, 234 [ID_ADC101S] = { 235 .channel[0] = ADC081S_CHAN(10), 236 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 237 }, 238 [ID_ADC121S] = { 239 .channel[0] = ADC081S_CHAN(12), 240 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 241 }, 242 [ID_ADS7866] = { 243 .channel[0] = ADS786X_CHAN(12), 244 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 245 }, 246 [ID_ADS7867] = { 247 .channel[0] = ADS786X_CHAN(10), 248 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 249 }, 250 [ID_ADS7868] = { 251 .channel[0] = ADS786X_CHAN(8), 252 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 253 }, 254 [ID_LTC2314_14] = { 255 .channel[0] = AD7940_CHAN(14), 256 .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1), 257 }, 258 }; 259 260 static const struct iio_info ad7476_info = { 261 .read_raw = &ad7476_read_raw, 262 }; 263 264 static void ad7476_reg_disable(void *data) 265 { 266 struct ad7476_state *st = data; 267 268 regulator_disable(st->reg); 269 } 270 271 static int ad7476_probe(struct spi_device *spi) 272 { 273 struct ad7476_state *st; 274 struct iio_dev *indio_dev; 275 int ret; 276 277 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 278 if (!indio_dev) 279 return -ENOMEM; 280 281 st = iio_priv(indio_dev); 282 st->chip_info = 283 &ad7476_chip_info_tbl[spi_get_device_id(spi)->driver_data]; 284 285 st->reg = devm_regulator_get(&spi->dev, "vcc"); 286 if (IS_ERR(st->reg)) 287 return PTR_ERR(st->reg); 288 289 ret = regulator_enable(st->reg); 290 if (ret) 291 return ret; 292 293 ret = devm_add_action_or_reset(&spi->dev, ad7476_reg_disable, 294 st); 295 if (ret) 296 return ret; 297 298 st->convst_gpio = devm_gpiod_get_optional(&spi->dev, 299 "adi,conversion-start", 300 GPIOD_OUT_LOW); 301 if (IS_ERR(st->convst_gpio)) 302 return PTR_ERR(st->convst_gpio); 303 304 spi_set_drvdata(spi, indio_dev); 305 306 st->spi = spi; 307 308 indio_dev->name = spi_get_device_id(spi)->name; 309 indio_dev->modes = INDIO_DIRECT_MODE; 310 indio_dev->channels = st->chip_info->channel; 311 indio_dev->num_channels = 2; 312 indio_dev->info = &ad7476_info; 313 314 if (st->convst_gpio) 315 indio_dev->channels = st->chip_info->convst_channel; 316 /* Setup default message */ 317 318 st->xfer.rx_buf = &st->data; 319 st->xfer.len = st->chip_info->channel[0].scan_type.storagebits / 8; 320 321 spi_message_init(&st->msg); 322 spi_message_add_tail(&st->xfer, &st->msg); 323 324 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, NULL, 325 &ad7476_trigger_handler, NULL); 326 if (ret) 327 return ret; 328 329 if (st->chip_info->reset) 330 st->chip_info->reset(st); 331 332 return devm_iio_device_register(&spi->dev, indio_dev); 333 } 334 335 static const struct spi_device_id ad7476_id[] = { 336 {"ad7091", ID_AD7091R}, 337 {"ad7091r", ID_AD7091R}, 338 {"ad7273", ID_AD7277}, 339 {"ad7274", ID_AD7276}, 340 {"ad7276", ID_AD7276}, 341 {"ad7277", ID_AD7277}, 342 {"ad7278", ID_AD7278}, 343 {"ad7466", ID_AD7466}, 344 {"ad7467", ID_AD7467}, 345 {"ad7468", ID_AD7468}, 346 {"ad7475", ID_AD7466}, 347 {"ad7476", ID_AD7466}, 348 {"ad7476a", ID_AD7466}, 349 {"ad7477", ID_AD7467}, 350 {"ad7477a", ID_AD7467}, 351 {"ad7478", ID_AD7468}, 352 {"ad7478a", ID_AD7468}, 353 {"ad7495", ID_AD7495}, 354 {"ad7910", ID_AD7467}, 355 {"ad7920", ID_AD7466}, 356 {"ad7940", ID_AD7940}, 357 {"adc081s", ID_ADC081S}, 358 {"adc101s", ID_ADC101S}, 359 {"adc121s", ID_ADC121S}, 360 {"ads7866", ID_ADS7866}, 361 {"ads7867", ID_ADS7867}, 362 {"ads7868", ID_ADS7868}, 363 {"ltc2314-14", ID_LTC2314_14}, 364 {} 365 }; 366 MODULE_DEVICE_TABLE(spi, ad7476_id); 367 368 static struct spi_driver ad7476_driver = { 369 .driver = { 370 .name = "ad7476", 371 }, 372 .probe = ad7476_probe, 373 .id_table = ad7476_id, 374 }; 375 module_spi_driver(ad7476_driver); 376 377 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 378 MODULE_DESCRIPTION("Analog Devices AD7476 and similar 1-channel ADCs"); 379 MODULE_LICENSE("GPL v2"); 380