1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AD7190 AD7192 AD7193 AD7195 SPI ADC driver 4 * 5 * Copyright 2011-2015 Analog Devices Inc. 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/clk.h> 10 #include <linux/device.h> 11 #include <linux/kernel.h> 12 #include <linux/slab.h> 13 #include <linux/sysfs.h> 14 #include <linux/spi/spi.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/err.h> 17 #include <linux/sched.h> 18 #include <linux/delay.h> 19 #include <linux/of_device.h> 20 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/buffer.h> 24 #include <linux/iio/trigger.h> 25 #include <linux/iio/trigger_consumer.h> 26 #include <linux/iio/triggered_buffer.h> 27 #include <linux/iio/adc/ad_sigma_delta.h> 28 29 /* Registers */ 30 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */ 31 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */ 32 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */ 33 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */ 34 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */ 35 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */ 36 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */ 37 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */ 38 /* (AD7792)/24-bit (AD7192)) */ 39 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */ 40 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */ 41 42 /* Communications Register Bit Designations (AD7192_REG_COMM) */ 43 #define AD7192_COMM_WEN BIT(7) /* Write Enable */ 44 #define AD7192_COMM_WRITE 0 /* Write Operation */ 45 #define AD7192_COMM_READ BIT(6) /* Read Operation */ 46 #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */ 47 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */ 48 49 /* Status Register Bit Designations (AD7192_REG_STAT) */ 50 #define AD7192_STAT_RDY BIT(7) /* Ready */ 51 #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */ 52 #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */ 53 #define AD7192_STAT_PARITY BIT(4) /* Parity */ 54 #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */ 55 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */ 56 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */ 57 58 /* Mode Register Bit Designations (AD7192_REG_MODE) */ 59 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */ 60 #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */ 61 #define AD7192_MODE_DAT_STA BIT(20) /* Status Register transmission */ 62 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */ 63 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */ 64 #define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/ 65 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */ 66 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/ 67 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */ 68 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */ 69 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */ 70 71 /* Mode Register: AD7192_MODE_SEL options */ 72 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */ 73 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */ 74 #define AD7192_MODE_IDLE 2 /* Idle Mode */ 75 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */ 76 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */ 77 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */ 78 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */ 79 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */ 80 81 /* Mode Register: AD7192_MODE_CLKSRC options */ 82 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/ 83 /* from MCLK1 to MCLK2 */ 84 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */ 85 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */ 86 /* available at the MCLK2 pin */ 87 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/ 88 /* at the MCLK2 pin */ 89 90 /* Configuration Register Bit Designations (AD7192_REG_CONF) */ 91 92 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */ 93 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */ 94 #define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */ 95 #define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */ 96 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */ 97 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */ 98 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */ 99 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */ 100 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */ 101 102 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */ 103 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */ 104 #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */ 105 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */ 106 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */ 107 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */ 108 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */ 109 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */ 110 111 #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */ 112 #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */ 113 #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */ 114 #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */ 115 #define AD7193_CH_TEMP 0x100 /* Temp senseor */ 116 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */ 117 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */ 118 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */ 119 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */ 120 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */ 121 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */ 122 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */ 123 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */ 124 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */ 125 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */ 126 127 /* ID Register Bit Designations (AD7192_REG_ID) */ 128 #define CHIPID_AD7190 0x4 129 #define CHIPID_AD7192 0x0 130 #define CHIPID_AD7193 0x2 131 #define CHIPID_AD7195 0x6 132 #define AD7192_ID_MASK 0x0F 133 134 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */ 135 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */ 136 #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */ 137 #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */ 138 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */ 139 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */ 140 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */ 141 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */ 142 143 #define AD7192_EXT_FREQ_MHZ_MIN 2457600 144 #define AD7192_EXT_FREQ_MHZ_MAX 5120000 145 #define AD7192_INT_FREQ_MHZ 4915200 146 147 #define AD7192_NO_SYNC_FILTER 1 148 #define AD7192_SYNC3_FILTER 3 149 #define AD7192_SYNC4_FILTER 4 150 151 /* NOTE: 152 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output. 153 * In order to avoid contentions on the SPI bus, it's therefore necessary 154 * to use spi bus locking. 155 * 156 * The DOUT/RDY output must also be wired to an interrupt capable GPIO. 157 */ 158 159 enum { 160 AD7192_SYSCALIB_ZERO_SCALE, 161 AD7192_SYSCALIB_FULL_SCALE, 162 }; 163 164 enum { 165 ID_AD7190, 166 ID_AD7192, 167 ID_AD7193, 168 ID_AD7195, 169 }; 170 171 struct ad7192_chip_info { 172 unsigned int chip_id; 173 const char *name; 174 }; 175 176 struct ad7192_state { 177 const struct ad7192_chip_info *chip_info; 178 struct regulator *avdd; 179 struct regulator *dvdd; 180 struct clk *mclk; 181 u16 int_vref_mv; 182 u32 fclk; 183 u32 f_order; 184 u32 mode; 185 u32 conf; 186 u32 scale_avail[8][2]; 187 u8 gpocon; 188 u8 clock_sel; 189 struct mutex lock; /* protect sensor state */ 190 u8 syscalib_mode[8]; 191 192 struct ad_sigma_delta sd; 193 }; 194 195 static const char * const ad7192_syscalib_modes[] = { 196 [AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale", 197 [AD7192_SYSCALIB_FULL_SCALE] = "full_scale", 198 }; 199 200 static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev, 201 const struct iio_chan_spec *chan, 202 unsigned int mode) 203 { 204 struct ad7192_state *st = iio_priv(indio_dev); 205 206 st->syscalib_mode[chan->channel] = mode; 207 208 return 0; 209 } 210 211 static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev, 212 const struct iio_chan_spec *chan) 213 { 214 struct ad7192_state *st = iio_priv(indio_dev); 215 216 return st->syscalib_mode[chan->channel]; 217 } 218 219 static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev, 220 uintptr_t private, 221 const struct iio_chan_spec *chan, 222 const char *buf, size_t len) 223 { 224 struct ad7192_state *st = iio_priv(indio_dev); 225 bool sys_calib; 226 int ret, temp; 227 228 ret = strtobool(buf, &sys_calib); 229 if (ret) 230 return ret; 231 232 temp = st->syscalib_mode[chan->channel]; 233 if (sys_calib) { 234 if (temp == AD7192_SYSCALIB_ZERO_SCALE) 235 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO, 236 chan->address); 237 else 238 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL, 239 chan->address); 240 } 241 242 return ret ? ret : len; 243 } 244 245 static const struct iio_enum ad7192_syscalib_mode_enum = { 246 .items = ad7192_syscalib_modes, 247 .num_items = ARRAY_SIZE(ad7192_syscalib_modes), 248 .set = ad7192_set_syscalib_mode, 249 .get = ad7192_get_syscalib_mode 250 }; 251 252 static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = { 253 { 254 .name = "sys_calibration", 255 .write = ad7192_write_syscalib, 256 .shared = IIO_SEPARATE, 257 }, 258 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE, 259 &ad7192_syscalib_mode_enum), 260 IIO_ENUM_AVAILABLE("sys_calibration_mode", &ad7192_syscalib_mode_enum), 261 {} 262 }; 263 264 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd) 265 { 266 return container_of(sd, struct ad7192_state, sd); 267 } 268 269 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 270 { 271 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 272 273 st->conf &= ~AD7192_CONF_CHAN_MASK; 274 st->conf |= AD7192_CONF_CHAN(channel); 275 276 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 277 } 278 279 static int ad7192_set_mode(struct ad_sigma_delta *sd, 280 enum ad_sigma_delta_mode mode) 281 { 282 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 283 284 st->mode &= ~AD7192_MODE_SEL_MASK; 285 st->mode |= AD7192_MODE_SEL(mode); 286 287 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 288 } 289 290 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = { 291 .set_channel = ad7192_set_channel, 292 .set_mode = ad7192_set_mode, 293 .has_registers = true, 294 .addr_shift = 3, 295 .read_mask = BIT(6), 296 .irq_flags = IRQF_TRIGGER_FALLING, 297 }; 298 299 static const struct ad_sd_calib_data ad7192_calib_arr[8] = { 300 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1}, 301 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1}, 302 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2}, 303 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2}, 304 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3}, 305 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3}, 306 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4}, 307 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4} 308 }; 309 310 static int ad7192_calibrate_all(struct ad7192_state *st) 311 { 312 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr, 313 ARRAY_SIZE(ad7192_calib_arr)); 314 } 315 316 static inline bool ad7192_valid_external_frequency(u32 freq) 317 { 318 return (freq >= AD7192_EXT_FREQ_MHZ_MIN && 319 freq <= AD7192_EXT_FREQ_MHZ_MAX); 320 } 321 322 static int ad7192_of_clock_select(struct ad7192_state *st) 323 { 324 struct device_node *np = st->sd.spi->dev.of_node; 325 unsigned int clock_sel; 326 327 clock_sel = AD7192_CLK_INT; 328 329 /* use internal clock */ 330 if (st->mclk) { 331 if (of_property_read_bool(np, "adi,int-clock-output-enable")) 332 clock_sel = AD7192_CLK_INT_CO; 333 } else { 334 if (of_property_read_bool(np, "adi,clock-xtal")) 335 clock_sel = AD7192_CLK_EXT_MCLK1_2; 336 else 337 clock_sel = AD7192_CLK_EXT_MCLK2; 338 } 339 340 return clock_sel; 341 } 342 343 static int ad7192_setup(struct ad7192_state *st, struct device_node *np) 344 { 345 struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi); 346 bool rej60_en, refin2_en; 347 bool buf_en, bipolar, burnout_curr_en; 348 unsigned long long scale_uv; 349 int i, ret, id; 350 351 /* reset the serial interface */ 352 ret = ad_sd_reset(&st->sd, 48); 353 if (ret < 0) 354 return ret; 355 usleep_range(500, 1000); /* Wait for at least 500us */ 356 357 /* write/read test for device presence */ 358 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id); 359 if (ret) 360 return ret; 361 362 id &= AD7192_ID_MASK; 363 364 if (id != st->chip_info->chip_id) 365 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n", 366 id); 367 368 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) | 369 AD7192_MODE_CLKSRC(st->clock_sel) | 370 AD7192_MODE_RATE(480); 371 372 st->conf = AD7192_CONF_GAIN(0); 373 374 rej60_en = of_property_read_bool(np, "adi,rejection-60-Hz-enable"); 375 if (rej60_en) 376 st->mode |= AD7192_MODE_REJ60; 377 378 refin2_en = of_property_read_bool(np, "adi,refin2-pins-enable"); 379 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195) 380 st->conf |= AD7192_CONF_REFSEL; 381 382 st->conf &= ~AD7192_CONF_CHOP; 383 st->f_order = AD7192_NO_SYNC_FILTER; 384 385 buf_en = of_property_read_bool(np, "adi,buffer-enable"); 386 if (buf_en) 387 st->conf |= AD7192_CONF_BUF; 388 389 bipolar = of_property_read_bool(np, "bipolar"); 390 if (!bipolar) 391 st->conf |= AD7192_CONF_UNIPOLAR; 392 393 burnout_curr_en = of_property_read_bool(np, 394 "adi,burnout-currents-enable"); 395 if (burnout_curr_en && buf_en) { 396 st->conf |= AD7192_CONF_BURN; 397 } else if (burnout_curr_en) { 398 dev_warn(&st->sd.spi->dev, 399 "Can't enable burnout currents: see CHOP or buffer\n"); 400 } 401 402 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 403 if (ret) 404 return ret; 405 406 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 407 if (ret) 408 return ret; 409 410 ret = ad7192_calibrate_all(st); 411 if (ret) 412 return ret; 413 414 /* Populate available ADC input ranges */ 415 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { 416 scale_uv = ((u64)st->int_vref_mv * 100000000) 417 >> (indio_dev->channels[0].scan_type.realbits - 418 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1)); 419 scale_uv >>= i; 420 421 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; 422 st->scale_avail[i][0] = scale_uv; 423 } 424 425 return 0; 426 } 427 428 static ssize_t ad7192_show_ac_excitation(struct device *dev, 429 struct device_attribute *attr, 430 char *buf) 431 { 432 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 433 struct ad7192_state *st = iio_priv(indio_dev); 434 435 return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX)); 436 } 437 438 static ssize_t ad7192_show_bridge_switch(struct device *dev, 439 struct device_attribute *attr, 440 char *buf) 441 { 442 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 443 struct ad7192_state *st = iio_priv(indio_dev); 444 445 return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW)); 446 } 447 448 static ssize_t ad7192_set(struct device *dev, 449 struct device_attribute *attr, 450 const char *buf, 451 size_t len) 452 { 453 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 454 struct ad7192_state *st = iio_priv(indio_dev); 455 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 456 int ret; 457 bool val; 458 459 ret = strtobool(buf, &val); 460 if (ret < 0) 461 return ret; 462 463 ret = iio_device_claim_direct_mode(indio_dev); 464 if (ret) 465 return ret; 466 467 switch ((u32)this_attr->address) { 468 case AD7192_REG_GPOCON: 469 if (val) 470 st->gpocon |= AD7192_GPOCON_BPDSW; 471 else 472 st->gpocon &= ~AD7192_GPOCON_BPDSW; 473 474 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon); 475 break; 476 case AD7192_REG_MODE: 477 if (val) 478 st->mode |= AD7192_MODE_ACX; 479 else 480 st->mode &= ~AD7192_MODE_ACX; 481 482 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 483 break; 484 default: 485 ret = -EINVAL; 486 } 487 488 iio_device_release_direct_mode(indio_dev); 489 490 return ret ? ret : len; 491 } 492 493 static void ad7192_get_available_filter_freq(struct ad7192_state *st, 494 int *freq) 495 { 496 unsigned int fadc; 497 498 /* Formulas for filter at page 25 of the datasheet */ 499 fadc = DIV_ROUND_CLOSEST(st->fclk, 500 AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode)); 501 freq[0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); 502 503 fadc = DIV_ROUND_CLOSEST(st->fclk, 504 AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode)); 505 freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024); 506 507 fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode)); 508 freq[2] = DIV_ROUND_CLOSEST(fadc * 230, 1024); 509 freq[3] = DIV_ROUND_CLOSEST(fadc * 272, 1024); 510 } 511 512 static ssize_t ad7192_show_filter_avail(struct device *dev, 513 struct device_attribute *attr, 514 char *buf) 515 { 516 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 517 struct ad7192_state *st = iio_priv(indio_dev); 518 unsigned int freq_avail[4], i; 519 size_t len = 0; 520 521 ad7192_get_available_filter_freq(st, freq_avail); 522 523 for (i = 0; i < ARRAY_SIZE(freq_avail); i++) 524 len += scnprintf(buf + len, PAGE_SIZE - len, 525 "%d.%d ", freq_avail[i] / 1000, 526 freq_avail[i] % 1000); 527 528 buf[len - 1] = '\n'; 529 530 return len; 531 } 532 533 static IIO_DEVICE_ATTR(filter_low_pass_3db_frequency_available, 534 0444, ad7192_show_filter_avail, NULL, 0); 535 536 static IIO_DEVICE_ATTR(bridge_switch_en, 0644, 537 ad7192_show_bridge_switch, ad7192_set, 538 AD7192_REG_GPOCON); 539 540 static IIO_DEVICE_ATTR(ac_excitation_en, 0644, 541 ad7192_show_ac_excitation, ad7192_set, 542 AD7192_REG_MODE); 543 544 static struct attribute *ad7192_attributes[] = { 545 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr, 546 &iio_dev_attr_bridge_switch_en.dev_attr.attr, 547 &iio_dev_attr_ac_excitation_en.dev_attr.attr, 548 NULL 549 }; 550 551 static const struct attribute_group ad7192_attribute_group = { 552 .attrs = ad7192_attributes, 553 }; 554 555 static struct attribute *ad7195_attributes[] = { 556 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr, 557 &iio_dev_attr_bridge_switch_en.dev_attr.attr, 558 NULL 559 }; 560 561 static const struct attribute_group ad7195_attribute_group = { 562 .attrs = ad7195_attributes, 563 }; 564 565 static unsigned int ad7192_get_temp_scale(bool unipolar) 566 { 567 return unipolar ? 2815 * 2 : 2815; 568 } 569 570 static int ad7192_set_3db_filter_freq(struct ad7192_state *st, 571 int val, int val2) 572 { 573 int freq_avail[4], i, ret, freq; 574 unsigned int diff_new, diff_old; 575 int idx = 0; 576 577 diff_old = U32_MAX; 578 freq = val * 1000 + val2; 579 580 ad7192_get_available_filter_freq(st, freq_avail); 581 582 for (i = 0; i < ARRAY_SIZE(freq_avail); i++) { 583 diff_new = abs(freq - freq_avail[i]); 584 if (diff_new < diff_old) { 585 diff_old = diff_new; 586 idx = i; 587 } 588 } 589 590 switch (idx) { 591 case 0: 592 st->f_order = AD7192_SYNC4_FILTER; 593 st->mode &= ~AD7192_MODE_SINC3; 594 595 st->conf |= AD7192_CONF_CHOP; 596 break; 597 case 1: 598 st->f_order = AD7192_SYNC3_FILTER; 599 st->mode |= AD7192_MODE_SINC3; 600 601 st->conf |= AD7192_CONF_CHOP; 602 break; 603 case 2: 604 st->f_order = AD7192_NO_SYNC_FILTER; 605 st->mode &= ~AD7192_MODE_SINC3; 606 607 st->conf &= ~AD7192_CONF_CHOP; 608 break; 609 case 3: 610 st->f_order = AD7192_NO_SYNC_FILTER; 611 st->mode |= AD7192_MODE_SINC3; 612 613 st->conf &= ~AD7192_CONF_CHOP; 614 break; 615 } 616 617 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 618 if (ret < 0) 619 return ret; 620 621 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 622 } 623 624 static int ad7192_get_3db_filter_freq(struct ad7192_state *st) 625 { 626 unsigned int fadc; 627 628 fadc = DIV_ROUND_CLOSEST(st->fclk, 629 st->f_order * AD7192_MODE_RATE(st->mode)); 630 631 if (st->conf & AD7192_CONF_CHOP) 632 return DIV_ROUND_CLOSEST(fadc * 240, 1024); 633 if (st->mode & AD7192_MODE_SINC3) 634 return DIV_ROUND_CLOSEST(fadc * 272, 1024); 635 else 636 return DIV_ROUND_CLOSEST(fadc * 230, 1024); 637 } 638 639 static int ad7192_read_raw(struct iio_dev *indio_dev, 640 struct iio_chan_spec const *chan, 641 int *val, 642 int *val2, 643 long m) 644 { 645 struct ad7192_state *st = iio_priv(indio_dev); 646 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR); 647 648 switch (m) { 649 case IIO_CHAN_INFO_RAW: 650 return ad_sigma_delta_single_conversion(indio_dev, chan, val); 651 case IIO_CHAN_INFO_SCALE: 652 switch (chan->type) { 653 case IIO_VOLTAGE: 654 mutex_lock(&st->lock); 655 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0]; 656 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1]; 657 mutex_unlock(&st->lock); 658 return IIO_VAL_INT_PLUS_NANO; 659 case IIO_TEMP: 660 *val = 0; 661 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar); 662 return IIO_VAL_INT_PLUS_NANO; 663 default: 664 return -EINVAL; 665 } 666 case IIO_CHAN_INFO_OFFSET: 667 if (!unipolar) 668 *val = -(1 << (chan->scan_type.realbits - 1)); 669 else 670 *val = 0; 671 /* Kelvin to Celsius */ 672 if (chan->type == IIO_TEMP) 673 *val -= 273 * ad7192_get_temp_scale(unipolar); 674 return IIO_VAL_INT; 675 case IIO_CHAN_INFO_SAMP_FREQ: 676 *val = st->fclk / 677 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode)); 678 return IIO_VAL_INT; 679 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 680 *val = ad7192_get_3db_filter_freq(st); 681 *val2 = 1000; 682 return IIO_VAL_FRACTIONAL; 683 } 684 685 return -EINVAL; 686 } 687 688 static int ad7192_write_raw(struct iio_dev *indio_dev, 689 struct iio_chan_spec const *chan, 690 int val, 691 int val2, 692 long mask) 693 { 694 struct ad7192_state *st = iio_priv(indio_dev); 695 int ret, i, div; 696 unsigned int tmp; 697 698 ret = iio_device_claim_direct_mode(indio_dev); 699 if (ret) 700 return ret; 701 702 switch (mask) { 703 case IIO_CHAN_INFO_SCALE: 704 ret = -EINVAL; 705 mutex_lock(&st->lock); 706 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) 707 if (val2 == st->scale_avail[i][1]) { 708 ret = 0; 709 tmp = st->conf; 710 st->conf &= ~AD7192_CONF_GAIN(-1); 711 st->conf |= AD7192_CONF_GAIN(i); 712 if (tmp == st->conf) 713 break; 714 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 715 3, st->conf); 716 ad7192_calibrate_all(st); 717 break; 718 } 719 mutex_unlock(&st->lock); 720 break; 721 case IIO_CHAN_INFO_SAMP_FREQ: 722 if (!val) { 723 ret = -EINVAL; 724 break; 725 } 726 727 div = st->fclk / (val * st->f_order * 1024); 728 if (div < 1 || div > 1023) { 729 ret = -EINVAL; 730 break; 731 } 732 733 st->mode &= ~AD7192_MODE_RATE(-1); 734 st->mode |= AD7192_MODE_RATE(div); 735 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 736 break; 737 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 738 ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000); 739 break; 740 default: 741 ret = -EINVAL; 742 } 743 744 iio_device_release_direct_mode(indio_dev); 745 746 return ret; 747 } 748 749 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev, 750 struct iio_chan_spec const *chan, 751 long mask) 752 { 753 switch (mask) { 754 case IIO_CHAN_INFO_SCALE: 755 return IIO_VAL_INT_PLUS_NANO; 756 case IIO_CHAN_INFO_SAMP_FREQ: 757 return IIO_VAL_INT; 758 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 759 return IIO_VAL_INT_PLUS_MICRO; 760 default: 761 return -EINVAL; 762 } 763 } 764 765 static int ad7192_read_avail(struct iio_dev *indio_dev, 766 struct iio_chan_spec const *chan, 767 const int **vals, int *type, int *length, 768 long mask) 769 { 770 struct ad7192_state *st = iio_priv(indio_dev); 771 772 switch (mask) { 773 case IIO_CHAN_INFO_SCALE: 774 *vals = (int *)st->scale_avail; 775 *type = IIO_VAL_INT_PLUS_NANO; 776 /* Values are stored in a 2D matrix */ 777 *length = ARRAY_SIZE(st->scale_avail) * 2; 778 779 return IIO_AVAIL_LIST; 780 } 781 782 return -EINVAL; 783 } 784 785 static const struct iio_info ad7192_info = { 786 .read_raw = ad7192_read_raw, 787 .write_raw = ad7192_write_raw, 788 .write_raw_get_fmt = ad7192_write_raw_get_fmt, 789 .read_avail = ad7192_read_avail, 790 .attrs = &ad7192_attribute_group, 791 .validate_trigger = ad_sd_validate_trigger, 792 }; 793 794 static const struct iio_info ad7195_info = { 795 .read_raw = ad7192_read_raw, 796 .write_raw = ad7192_write_raw, 797 .write_raw_get_fmt = ad7192_write_raw_get_fmt, 798 .read_avail = ad7192_read_avail, 799 .attrs = &ad7195_attribute_group, 800 .validate_trigger = ad_sd_validate_trigger, 801 }; 802 803 #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _extend_name, \ 804 _type, _mask_type_av, _ext_info) \ 805 { \ 806 .type = (_type), \ 807 .differential = ((_channel2) == -1 ? 0 : 1), \ 808 .indexed = 1, \ 809 .channel = (_channel1), \ 810 .channel2 = (_channel2), \ 811 .address = (_address), \ 812 .extend_name = (_extend_name), \ 813 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 814 BIT(IIO_CHAN_INFO_OFFSET), \ 815 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 816 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 817 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 818 .info_mask_shared_by_type_available = (_mask_type_av), \ 819 .ext_info = (_ext_info), \ 820 .scan_index = (_si), \ 821 .scan_type = { \ 822 .sign = 'u', \ 823 .realbits = 24, \ 824 .storagebits = 32, \ 825 .endianness = IIO_BE, \ 826 }, \ 827 } 828 829 #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \ 830 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, NULL, \ 831 IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE), \ 832 ad7192_calibsys_ext_info) 833 834 #define AD719x_CHANNEL(_si, _channel1, _address) \ 835 __AD719x_CHANNEL(_si, _channel1, -1, _address, NULL, IIO_VOLTAGE, \ 836 BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info) 837 838 #define AD719x_SHORTED_CHANNEL(_si, _channel1, _address) \ 839 __AD719x_CHANNEL(_si, _channel1, -1, _address, "shorted", IIO_VOLTAGE, \ 840 BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info) 841 842 #define AD719x_TEMP_CHANNEL(_si, _address) \ 843 __AD719x_CHANNEL(_si, 0, -1, _address, NULL, IIO_TEMP, 0, NULL) 844 845 static const struct iio_chan_spec ad7192_channels[] = { 846 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M), 847 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M), 848 AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP), 849 AD719x_SHORTED_CHANNEL(3, 2, AD7192_CH_AIN2P_AIN2M), 850 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1), 851 AD719x_CHANNEL(5, 2, AD7192_CH_AIN2), 852 AD719x_CHANNEL(6, 3, AD7192_CH_AIN3), 853 AD719x_CHANNEL(7, 4, AD7192_CH_AIN4), 854 IIO_CHAN_SOFT_TIMESTAMP(8), 855 }; 856 857 static const struct iio_chan_spec ad7193_channels[] = { 858 AD719x_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M), 859 AD719x_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M), 860 AD719x_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M), 861 AD719x_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M), 862 AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP), 863 AD719x_SHORTED_CHANNEL(5, 2, AD7193_CH_AIN2P_AIN2M), 864 AD719x_CHANNEL(6, 1, AD7193_CH_AIN1), 865 AD719x_CHANNEL(7, 2, AD7193_CH_AIN2), 866 AD719x_CHANNEL(8, 3, AD7193_CH_AIN3), 867 AD719x_CHANNEL(9, 4, AD7193_CH_AIN4), 868 AD719x_CHANNEL(10, 5, AD7193_CH_AIN5), 869 AD719x_CHANNEL(11, 6, AD7193_CH_AIN6), 870 AD719x_CHANNEL(12, 7, AD7193_CH_AIN7), 871 AD719x_CHANNEL(13, 8, AD7193_CH_AIN8), 872 IIO_CHAN_SOFT_TIMESTAMP(14), 873 }; 874 875 static const struct ad7192_chip_info ad7192_chip_info_tbl[] = { 876 [ID_AD7190] = { 877 .chip_id = CHIPID_AD7190, 878 .name = "ad7190", 879 }, 880 [ID_AD7192] = { 881 .chip_id = CHIPID_AD7192, 882 .name = "ad7192", 883 }, 884 [ID_AD7193] = { 885 .chip_id = CHIPID_AD7193, 886 .name = "ad7193", 887 }, 888 [ID_AD7195] = { 889 .chip_id = CHIPID_AD7195, 890 .name = "ad7195", 891 }, 892 }; 893 894 static int ad7192_channels_config(struct iio_dev *indio_dev) 895 { 896 struct ad7192_state *st = iio_priv(indio_dev); 897 898 switch (st->chip_info->chip_id) { 899 case CHIPID_AD7193: 900 indio_dev->channels = ad7193_channels; 901 indio_dev->num_channels = ARRAY_SIZE(ad7193_channels); 902 break; 903 default: 904 indio_dev->channels = ad7192_channels; 905 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels); 906 break; 907 } 908 909 return 0; 910 } 911 912 static void ad7192_reg_disable(void *reg) 913 { 914 regulator_disable(reg); 915 } 916 917 static void ad7192_clk_disable(void *clk) 918 { 919 clk_disable_unprepare(clk); 920 } 921 922 static int ad7192_probe(struct spi_device *spi) 923 { 924 struct ad7192_state *st; 925 struct iio_dev *indio_dev; 926 int ret; 927 928 if (!spi->irq) { 929 dev_err(&spi->dev, "no IRQ?\n"); 930 return -ENODEV; 931 } 932 933 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 934 if (!indio_dev) 935 return -ENOMEM; 936 937 st = iio_priv(indio_dev); 938 939 mutex_init(&st->lock); 940 941 st->avdd = devm_regulator_get(&spi->dev, "avdd"); 942 if (IS_ERR(st->avdd)) 943 return PTR_ERR(st->avdd); 944 945 ret = regulator_enable(st->avdd); 946 if (ret) { 947 dev_err(&spi->dev, "Failed to enable specified AVdd supply\n"); 948 return ret; 949 } 950 951 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->avdd); 952 if (ret) 953 return ret; 954 955 st->dvdd = devm_regulator_get(&spi->dev, "dvdd"); 956 if (IS_ERR(st->dvdd)) 957 return PTR_ERR(st->dvdd); 958 959 ret = regulator_enable(st->dvdd); 960 if (ret) { 961 dev_err(&spi->dev, "Failed to enable specified DVdd supply\n"); 962 return ret; 963 } 964 965 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->dvdd); 966 if (ret) 967 return ret; 968 969 ret = regulator_get_voltage(st->avdd); 970 if (ret < 0) { 971 dev_err(&spi->dev, "Device tree error, reference voltage undefined\n"); 972 return ret; 973 } 974 st->int_vref_mv = ret / 1000; 975 976 st->chip_info = of_device_get_match_data(&spi->dev); 977 indio_dev->name = st->chip_info->name; 978 indio_dev->modes = INDIO_DIRECT_MODE; 979 980 ret = ad7192_channels_config(indio_dev); 981 if (ret < 0) 982 return ret; 983 984 if (st->chip_info->chip_id == CHIPID_AD7195) 985 indio_dev->info = &ad7195_info; 986 else 987 indio_dev->info = &ad7192_info; 988 989 ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info); 990 991 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev); 992 if (ret) 993 return ret; 994 995 st->fclk = AD7192_INT_FREQ_MHZ; 996 997 st->mclk = devm_clk_get_optional(&spi->dev, "mclk"); 998 if (IS_ERR(st->mclk)) 999 return PTR_ERR(st->mclk); 1000 1001 st->clock_sel = ad7192_of_clock_select(st); 1002 1003 if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 || 1004 st->clock_sel == AD7192_CLK_EXT_MCLK2) { 1005 ret = clk_prepare_enable(st->mclk); 1006 if (ret < 0) 1007 return ret; 1008 1009 ret = devm_add_action_or_reset(&spi->dev, ad7192_clk_disable, 1010 st->mclk); 1011 if (ret) 1012 return ret; 1013 1014 st->fclk = clk_get_rate(st->mclk); 1015 if (!ad7192_valid_external_frequency(st->fclk)) { 1016 dev_err(&spi->dev, 1017 "External clock frequency out of bounds\n"); 1018 return -EINVAL; 1019 } 1020 } 1021 1022 ret = ad7192_setup(st, spi->dev.of_node); 1023 if (ret) 1024 return ret; 1025 1026 return devm_iio_device_register(&spi->dev, indio_dev); 1027 } 1028 1029 static const struct of_device_id ad7192_of_match[] = { 1030 { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] }, 1031 { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] }, 1032 { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] }, 1033 { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] }, 1034 {} 1035 }; 1036 MODULE_DEVICE_TABLE(of, ad7192_of_match); 1037 1038 static struct spi_driver ad7192_driver = { 1039 .driver = { 1040 .name = "ad7192", 1041 .of_match_table = ad7192_of_match, 1042 }, 1043 .probe = ad7192_probe, 1044 }; 1045 module_spi_driver(ad7192_driver); 1046 1047 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 1048 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC"); 1049 MODULE_LICENSE("GPL v2"); 1050