1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AD7190 AD7192 AD7193 AD7195 SPI ADC driver 4 * 5 * Copyright 2011-2015 Analog Devices Inc. 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/clk.h> 10 #include <linux/device.h> 11 #include <linux/kernel.h> 12 #include <linux/slab.h> 13 #include <linux/sysfs.h> 14 #include <linux/spi/spi.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/err.h> 17 #include <linux/sched.h> 18 #include <linux/delay.h> 19 #include <linux/of_device.h> 20 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/buffer.h> 24 #include <linux/iio/trigger.h> 25 #include <linux/iio/trigger_consumer.h> 26 #include <linux/iio/triggered_buffer.h> 27 #include <linux/iio/adc/ad_sigma_delta.h> 28 29 /* Registers */ 30 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */ 31 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */ 32 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */ 33 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */ 34 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */ 35 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */ 36 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */ 37 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */ 38 /* (AD7792)/24-bit (AD7192)) */ 39 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */ 40 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */ 41 42 /* Communications Register Bit Designations (AD7192_REG_COMM) */ 43 #define AD7192_COMM_WEN BIT(7) /* Write Enable */ 44 #define AD7192_COMM_WRITE 0 /* Write Operation */ 45 #define AD7192_COMM_READ BIT(6) /* Read Operation */ 46 #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */ 47 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */ 48 49 /* Status Register Bit Designations (AD7192_REG_STAT) */ 50 #define AD7192_STAT_RDY BIT(7) /* Ready */ 51 #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */ 52 #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */ 53 #define AD7192_STAT_PARITY BIT(4) /* Parity */ 54 #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */ 55 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */ 56 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */ 57 58 /* Mode Register Bit Designations (AD7192_REG_MODE) */ 59 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */ 60 #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */ 61 #define AD7192_MODE_DAT_STA BIT(20) /* Status Register transmission */ 62 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */ 63 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */ 64 #define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/ 65 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */ 66 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/ 67 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */ 68 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */ 69 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */ 70 71 /* Mode Register: AD7192_MODE_SEL options */ 72 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */ 73 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */ 74 #define AD7192_MODE_IDLE 2 /* Idle Mode */ 75 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */ 76 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */ 77 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */ 78 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */ 79 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */ 80 81 /* Mode Register: AD7192_MODE_CLKSRC options */ 82 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/ 83 /* from MCLK1 to MCLK2 */ 84 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */ 85 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */ 86 /* available at the MCLK2 pin */ 87 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/ 88 /* at the MCLK2 pin */ 89 90 /* Configuration Register Bit Designations (AD7192_REG_CONF) */ 91 92 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */ 93 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */ 94 #define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */ 95 #define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */ 96 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */ 97 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */ 98 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */ 99 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */ 100 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */ 101 102 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */ 103 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */ 104 #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */ 105 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */ 106 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */ 107 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */ 108 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */ 109 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */ 110 111 #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */ 112 #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */ 113 #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */ 114 #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */ 115 #define AD7193_CH_TEMP 0x100 /* Temp senseor */ 116 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */ 117 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */ 118 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */ 119 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */ 120 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */ 121 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */ 122 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */ 123 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */ 124 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */ 125 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */ 126 127 /* ID Register Bit Designations (AD7192_REG_ID) */ 128 #define CHIPID_AD7190 0x4 129 #define CHIPID_AD7192 0x0 130 #define CHIPID_AD7193 0x2 131 #define CHIPID_AD7195 0x6 132 #define AD7192_ID_MASK 0x0F 133 134 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */ 135 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */ 136 #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */ 137 #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */ 138 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */ 139 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */ 140 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */ 141 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */ 142 143 #define AD7192_EXT_FREQ_MHZ_MIN 2457600 144 #define AD7192_EXT_FREQ_MHZ_MAX 5120000 145 #define AD7192_INT_FREQ_MHZ 4915200 146 147 #define AD7192_NO_SYNC_FILTER 1 148 #define AD7192_SYNC3_FILTER 3 149 #define AD7192_SYNC4_FILTER 4 150 151 /* NOTE: 152 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output. 153 * In order to avoid contentions on the SPI bus, it's therefore necessary 154 * to use spi bus locking. 155 * 156 * The DOUT/RDY output must also be wired to an interrupt capable GPIO. 157 */ 158 159 enum { 160 AD7192_SYSCALIB_ZERO_SCALE, 161 AD7192_SYSCALIB_FULL_SCALE, 162 }; 163 164 enum { 165 ID_AD7190, 166 ID_AD7192, 167 ID_AD7193, 168 ID_AD7195, 169 }; 170 171 struct ad7192_chip_info { 172 unsigned int chip_id; 173 const char *name; 174 }; 175 176 struct ad7192_state { 177 const struct ad7192_chip_info *chip_info; 178 struct regulator *avdd; 179 struct regulator *dvdd; 180 struct clk *mclk; 181 u16 int_vref_mv; 182 u32 fclk; 183 u32 f_order; 184 u32 mode; 185 u32 conf; 186 u32 scale_avail[8][2]; 187 u8 gpocon; 188 u8 clock_sel; 189 struct mutex lock; /* protect sensor state */ 190 u8 syscalib_mode[8]; 191 192 struct ad_sigma_delta sd; 193 }; 194 195 static const char * const ad7192_syscalib_modes[] = { 196 [AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale", 197 [AD7192_SYSCALIB_FULL_SCALE] = "full_scale", 198 }; 199 200 static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev, 201 const struct iio_chan_spec *chan, 202 unsigned int mode) 203 { 204 struct ad7192_state *st = iio_priv(indio_dev); 205 206 st->syscalib_mode[chan->channel] = mode; 207 208 return 0; 209 } 210 211 static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev, 212 const struct iio_chan_spec *chan) 213 { 214 struct ad7192_state *st = iio_priv(indio_dev); 215 216 return st->syscalib_mode[chan->channel]; 217 } 218 219 static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev, 220 uintptr_t private, 221 const struct iio_chan_spec *chan, 222 const char *buf, size_t len) 223 { 224 struct ad7192_state *st = iio_priv(indio_dev); 225 bool sys_calib; 226 int ret, temp; 227 228 ret = strtobool(buf, &sys_calib); 229 if (ret) 230 return ret; 231 232 temp = st->syscalib_mode[chan->channel]; 233 if (sys_calib) { 234 if (temp == AD7192_SYSCALIB_ZERO_SCALE) 235 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO, 236 chan->address); 237 else 238 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL, 239 chan->address); 240 } 241 242 return ret ? ret : len; 243 } 244 245 static const struct iio_enum ad7192_syscalib_mode_enum = { 246 .items = ad7192_syscalib_modes, 247 .num_items = ARRAY_SIZE(ad7192_syscalib_modes), 248 .set = ad7192_set_syscalib_mode, 249 .get = ad7192_get_syscalib_mode 250 }; 251 252 static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = { 253 { 254 .name = "sys_calibration", 255 .write = ad7192_write_syscalib, 256 .shared = IIO_SEPARATE, 257 }, 258 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE, 259 &ad7192_syscalib_mode_enum), 260 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE, 261 &ad7192_syscalib_mode_enum), 262 {} 263 }; 264 265 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd) 266 { 267 return container_of(sd, struct ad7192_state, sd); 268 } 269 270 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 271 { 272 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 273 274 st->conf &= ~AD7192_CONF_CHAN_MASK; 275 st->conf |= AD7192_CONF_CHAN(channel); 276 277 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 278 } 279 280 static int ad7192_set_mode(struct ad_sigma_delta *sd, 281 enum ad_sigma_delta_mode mode) 282 { 283 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 284 285 st->mode &= ~AD7192_MODE_SEL_MASK; 286 st->mode |= AD7192_MODE_SEL(mode); 287 288 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 289 } 290 291 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = { 292 .set_channel = ad7192_set_channel, 293 .set_mode = ad7192_set_mode, 294 .has_registers = true, 295 .addr_shift = 3, 296 .read_mask = BIT(6), 297 .irq_flags = IRQF_TRIGGER_FALLING, 298 }; 299 300 static const struct ad_sd_calib_data ad7192_calib_arr[8] = { 301 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1}, 302 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1}, 303 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2}, 304 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2}, 305 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3}, 306 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3}, 307 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4}, 308 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4} 309 }; 310 311 static int ad7192_calibrate_all(struct ad7192_state *st) 312 { 313 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr, 314 ARRAY_SIZE(ad7192_calib_arr)); 315 } 316 317 static inline bool ad7192_valid_external_frequency(u32 freq) 318 { 319 return (freq >= AD7192_EXT_FREQ_MHZ_MIN && 320 freq <= AD7192_EXT_FREQ_MHZ_MAX); 321 } 322 323 static int ad7192_of_clock_select(struct ad7192_state *st) 324 { 325 struct device_node *np = st->sd.spi->dev.of_node; 326 unsigned int clock_sel; 327 328 clock_sel = AD7192_CLK_INT; 329 330 /* use internal clock */ 331 if (st->mclk) { 332 if (of_property_read_bool(np, "adi,int-clock-output-enable")) 333 clock_sel = AD7192_CLK_INT_CO; 334 } else { 335 if (of_property_read_bool(np, "adi,clock-xtal")) 336 clock_sel = AD7192_CLK_EXT_MCLK1_2; 337 else 338 clock_sel = AD7192_CLK_EXT_MCLK2; 339 } 340 341 return clock_sel; 342 } 343 344 static int ad7192_setup(struct ad7192_state *st, struct device_node *np) 345 { 346 struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi); 347 bool rej60_en, refin2_en; 348 bool buf_en, bipolar, burnout_curr_en; 349 unsigned long long scale_uv; 350 int i, ret, id; 351 352 /* reset the serial interface */ 353 ret = ad_sd_reset(&st->sd, 48); 354 if (ret < 0) 355 return ret; 356 usleep_range(500, 1000); /* Wait for at least 500us */ 357 358 /* write/read test for device presence */ 359 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id); 360 if (ret) 361 return ret; 362 363 id &= AD7192_ID_MASK; 364 365 if (id != st->chip_info->chip_id) 366 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n", 367 id); 368 369 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) | 370 AD7192_MODE_CLKSRC(st->clock_sel) | 371 AD7192_MODE_RATE(480); 372 373 st->conf = AD7192_CONF_GAIN(0); 374 375 rej60_en = of_property_read_bool(np, "adi,rejection-60-Hz-enable"); 376 if (rej60_en) 377 st->mode |= AD7192_MODE_REJ60; 378 379 refin2_en = of_property_read_bool(np, "adi,refin2-pins-enable"); 380 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195) 381 st->conf |= AD7192_CONF_REFSEL; 382 383 st->conf &= ~AD7192_CONF_CHOP; 384 st->f_order = AD7192_NO_SYNC_FILTER; 385 386 buf_en = of_property_read_bool(np, "adi,buffer-enable"); 387 if (buf_en) 388 st->conf |= AD7192_CONF_BUF; 389 390 bipolar = of_property_read_bool(np, "bipolar"); 391 if (!bipolar) 392 st->conf |= AD7192_CONF_UNIPOLAR; 393 394 burnout_curr_en = of_property_read_bool(np, 395 "adi,burnout-currents-enable"); 396 if (burnout_curr_en && buf_en) { 397 st->conf |= AD7192_CONF_BURN; 398 } else if (burnout_curr_en) { 399 dev_warn(&st->sd.spi->dev, 400 "Can't enable burnout currents: see CHOP or buffer\n"); 401 } 402 403 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 404 if (ret) 405 return ret; 406 407 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 408 if (ret) 409 return ret; 410 411 ret = ad7192_calibrate_all(st); 412 if (ret) 413 return ret; 414 415 /* Populate available ADC input ranges */ 416 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { 417 scale_uv = ((u64)st->int_vref_mv * 100000000) 418 >> (indio_dev->channels[0].scan_type.realbits - 419 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1)); 420 scale_uv >>= i; 421 422 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; 423 st->scale_avail[i][0] = scale_uv; 424 } 425 426 return 0; 427 } 428 429 static ssize_t ad7192_show_ac_excitation(struct device *dev, 430 struct device_attribute *attr, 431 char *buf) 432 { 433 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 434 struct ad7192_state *st = iio_priv(indio_dev); 435 436 return sysfs_emit(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX)); 437 } 438 439 static ssize_t ad7192_show_bridge_switch(struct device *dev, 440 struct device_attribute *attr, 441 char *buf) 442 { 443 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 444 struct ad7192_state *st = iio_priv(indio_dev); 445 446 return sysfs_emit(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW)); 447 } 448 449 static ssize_t ad7192_set(struct device *dev, 450 struct device_attribute *attr, 451 const char *buf, 452 size_t len) 453 { 454 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 455 struct ad7192_state *st = iio_priv(indio_dev); 456 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 457 int ret; 458 bool val; 459 460 ret = strtobool(buf, &val); 461 if (ret < 0) 462 return ret; 463 464 ret = iio_device_claim_direct_mode(indio_dev); 465 if (ret) 466 return ret; 467 468 switch ((u32)this_attr->address) { 469 case AD7192_REG_GPOCON: 470 if (val) 471 st->gpocon |= AD7192_GPOCON_BPDSW; 472 else 473 st->gpocon &= ~AD7192_GPOCON_BPDSW; 474 475 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon); 476 break; 477 case AD7192_REG_MODE: 478 if (val) 479 st->mode |= AD7192_MODE_ACX; 480 else 481 st->mode &= ~AD7192_MODE_ACX; 482 483 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 484 break; 485 default: 486 ret = -EINVAL; 487 } 488 489 iio_device_release_direct_mode(indio_dev); 490 491 return ret ? ret : len; 492 } 493 494 static void ad7192_get_available_filter_freq(struct ad7192_state *st, 495 int *freq) 496 { 497 unsigned int fadc; 498 499 /* Formulas for filter at page 25 of the datasheet */ 500 fadc = DIV_ROUND_CLOSEST(st->fclk, 501 AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode)); 502 freq[0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); 503 504 fadc = DIV_ROUND_CLOSEST(st->fclk, 505 AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode)); 506 freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024); 507 508 fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode)); 509 freq[2] = DIV_ROUND_CLOSEST(fadc * 230, 1024); 510 freq[3] = DIV_ROUND_CLOSEST(fadc * 272, 1024); 511 } 512 513 static ssize_t ad7192_show_filter_avail(struct device *dev, 514 struct device_attribute *attr, 515 char *buf) 516 { 517 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 518 struct ad7192_state *st = iio_priv(indio_dev); 519 unsigned int freq_avail[4], i; 520 size_t len = 0; 521 522 ad7192_get_available_filter_freq(st, freq_avail); 523 524 for (i = 0; i < ARRAY_SIZE(freq_avail); i++) 525 len += scnprintf(buf + len, PAGE_SIZE - len, 526 "%d.%d ", freq_avail[i] / 1000, 527 freq_avail[i] % 1000); 528 529 buf[len - 1] = '\n'; 530 531 return len; 532 } 533 534 static IIO_DEVICE_ATTR(filter_low_pass_3db_frequency_available, 535 0444, ad7192_show_filter_avail, NULL, 0); 536 537 static IIO_DEVICE_ATTR(bridge_switch_en, 0644, 538 ad7192_show_bridge_switch, ad7192_set, 539 AD7192_REG_GPOCON); 540 541 static IIO_DEVICE_ATTR(ac_excitation_en, 0644, 542 ad7192_show_ac_excitation, ad7192_set, 543 AD7192_REG_MODE); 544 545 static struct attribute *ad7192_attributes[] = { 546 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr, 547 &iio_dev_attr_bridge_switch_en.dev_attr.attr, 548 &iio_dev_attr_ac_excitation_en.dev_attr.attr, 549 NULL 550 }; 551 552 static const struct attribute_group ad7192_attribute_group = { 553 .attrs = ad7192_attributes, 554 }; 555 556 static struct attribute *ad7195_attributes[] = { 557 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr, 558 &iio_dev_attr_bridge_switch_en.dev_attr.attr, 559 NULL 560 }; 561 562 static const struct attribute_group ad7195_attribute_group = { 563 .attrs = ad7195_attributes, 564 }; 565 566 static unsigned int ad7192_get_temp_scale(bool unipolar) 567 { 568 return unipolar ? 2815 * 2 : 2815; 569 } 570 571 static int ad7192_set_3db_filter_freq(struct ad7192_state *st, 572 int val, int val2) 573 { 574 int freq_avail[4], i, ret, freq; 575 unsigned int diff_new, diff_old; 576 int idx = 0; 577 578 diff_old = U32_MAX; 579 freq = val * 1000 + val2; 580 581 ad7192_get_available_filter_freq(st, freq_avail); 582 583 for (i = 0; i < ARRAY_SIZE(freq_avail); i++) { 584 diff_new = abs(freq - freq_avail[i]); 585 if (diff_new < diff_old) { 586 diff_old = diff_new; 587 idx = i; 588 } 589 } 590 591 switch (idx) { 592 case 0: 593 st->f_order = AD7192_SYNC4_FILTER; 594 st->mode &= ~AD7192_MODE_SINC3; 595 596 st->conf |= AD7192_CONF_CHOP; 597 break; 598 case 1: 599 st->f_order = AD7192_SYNC3_FILTER; 600 st->mode |= AD7192_MODE_SINC3; 601 602 st->conf |= AD7192_CONF_CHOP; 603 break; 604 case 2: 605 st->f_order = AD7192_NO_SYNC_FILTER; 606 st->mode &= ~AD7192_MODE_SINC3; 607 608 st->conf &= ~AD7192_CONF_CHOP; 609 break; 610 case 3: 611 st->f_order = AD7192_NO_SYNC_FILTER; 612 st->mode |= AD7192_MODE_SINC3; 613 614 st->conf &= ~AD7192_CONF_CHOP; 615 break; 616 } 617 618 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 619 if (ret < 0) 620 return ret; 621 622 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 623 } 624 625 static int ad7192_get_3db_filter_freq(struct ad7192_state *st) 626 { 627 unsigned int fadc; 628 629 fadc = DIV_ROUND_CLOSEST(st->fclk, 630 st->f_order * AD7192_MODE_RATE(st->mode)); 631 632 if (st->conf & AD7192_CONF_CHOP) 633 return DIV_ROUND_CLOSEST(fadc * 240, 1024); 634 if (st->mode & AD7192_MODE_SINC3) 635 return DIV_ROUND_CLOSEST(fadc * 272, 1024); 636 else 637 return DIV_ROUND_CLOSEST(fadc * 230, 1024); 638 } 639 640 static int ad7192_read_raw(struct iio_dev *indio_dev, 641 struct iio_chan_spec const *chan, 642 int *val, 643 int *val2, 644 long m) 645 { 646 struct ad7192_state *st = iio_priv(indio_dev); 647 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR); 648 649 switch (m) { 650 case IIO_CHAN_INFO_RAW: 651 return ad_sigma_delta_single_conversion(indio_dev, chan, val); 652 case IIO_CHAN_INFO_SCALE: 653 switch (chan->type) { 654 case IIO_VOLTAGE: 655 mutex_lock(&st->lock); 656 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0]; 657 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1]; 658 mutex_unlock(&st->lock); 659 return IIO_VAL_INT_PLUS_NANO; 660 case IIO_TEMP: 661 *val = 0; 662 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar); 663 return IIO_VAL_INT_PLUS_NANO; 664 default: 665 return -EINVAL; 666 } 667 case IIO_CHAN_INFO_OFFSET: 668 if (!unipolar) 669 *val = -(1 << (chan->scan_type.realbits - 1)); 670 else 671 *val = 0; 672 /* Kelvin to Celsius */ 673 if (chan->type == IIO_TEMP) 674 *val -= 273 * ad7192_get_temp_scale(unipolar); 675 return IIO_VAL_INT; 676 case IIO_CHAN_INFO_SAMP_FREQ: 677 *val = st->fclk / 678 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode)); 679 return IIO_VAL_INT; 680 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 681 *val = ad7192_get_3db_filter_freq(st); 682 *val2 = 1000; 683 return IIO_VAL_FRACTIONAL; 684 } 685 686 return -EINVAL; 687 } 688 689 static int ad7192_write_raw(struct iio_dev *indio_dev, 690 struct iio_chan_spec const *chan, 691 int val, 692 int val2, 693 long mask) 694 { 695 struct ad7192_state *st = iio_priv(indio_dev); 696 int ret, i, div; 697 unsigned int tmp; 698 699 ret = iio_device_claim_direct_mode(indio_dev); 700 if (ret) 701 return ret; 702 703 switch (mask) { 704 case IIO_CHAN_INFO_SCALE: 705 ret = -EINVAL; 706 mutex_lock(&st->lock); 707 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) 708 if (val2 == st->scale_avail[i][1]) { 709 ret = 0; 710 tmp = st->conf; 711 st->conf &= ~AD7192_CONF_GAIN(-1); 712 st->conf |= AD7192_CONF_GAIN(i); 713 if (tmp == st->conf) 714 break; 715 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 716 3, st->conf); 717 ad7192_calibrate_all(st); 718 break; 719 } 720 mutex_unlock(&st->lock); 721 break; 722 case IIO_CHAN_INFO_SAMP_FREQ: 723 if (!val) { 724 ret = -EINVAL; 725 break; 726 } 727 728 div = st->fclk / (val * st->f_order * 1024); 729 if (div < 1 || div > 1023) { 730 ret = -EINVAL; 731 break; 732 } 733 734 st->mode &= ~AD7192_MODE_RATE(-1); 735 st->mode |= AD7192_MODE_RATE(div); 736 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 737 break; 738 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 739 ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000); 740 break; 741 default: 742 ret = -EINVAL; 743 } 744 745 iio_device_release_direct_mode(indio_dev); 746 747 return ret; 748 } 749 750 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev, 751 struct iio_chan_spec const *chan, 752 long mask) 753 { 754 switch (mask) { 755 case IIO_CHAN_INFO_SCALE: 756 return IIO_VAL_INT_PLUS_NANO; 757 case IIO_CHAN_INFO_SAMP_FREQ: 758 return IIO_VAL_INT; 759 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 760 return IIO_VAL_INT_PLUS_MICRO; 761 default: 762 return -EINVAL; 763 } 764 } 765 766 static int ad7192_read_avail(struct iio_dev *indio_dev, 767 struct iio_chan_spec const *chan, 768 const int **vals, int *type, int *length, 769 long mask) 770 { 771 struct ad7192_state *st = iio_priv(indio_dev); 772 773 switch (mask) { 774 case IIO_CHAN_INFO_SCALE: 775 *vals = (int *)st->scale_avail; 776 *type = IIO_VAL_INT_PLUS_NANO; 777 /* Values are stored in a 2D matrix */ 778 *length = ARRAY_SIZE(st->scale_avail) * 2; 779 780 return IIO_AVAIL_LIST; 781 } 782 783 return -EINVAL; 784 } 785 786 static const struct iio_info ad7192_info = { 787 .read_raw = ad7192_read_raw, 788 .write_raw = ad7192_write_raw, 789 .write_raw_get_fmt = ad7192_write_raw_get_fmt, 790 .read_avail = ad7192_read_avail, 791 .attrs = &ad7192_attribute_group, 792 .validate_trigger = ad_sd_validate_trigger, 793 }; 794 795 static const struct iio_info ad7195_info = { 796 .read_raw = ad7192_read_raw, 797 .write_raw = ad7192_write_raw, 798 .write_raw_get_fmt = ad7192_write_raw_get_fmt, 799 .read_avail = ad7192_read_avail, 800 .attrs = &ad7195_attribute_group, 801 .validate_trigger = ad_sd_validate_trigger, 802 }; 803 804 #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _extend_name, \ 805 _type, _mask_type_av, _ext_info) \ 806 { \ 807 .type = (_type), \ 808 .differential = ((_channel2) == -1 ? 0 : 1), \ 809 .indexed = 1, \ 810 .channel = (_channel1), \ 811 .channel2 = (_channel2), \ 812 .address = (_address), \ 813 .extend_name = (_extend_name), \ 814 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 815 BIT(IIO_CHAN_INFO_OFFSET), \ 816 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 817 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 818 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 819 .info_mask_shared_by_type_available = (_mask_type_av), \ 820 .ext_info = (_ext_info), \ 821 .scan_index = (_si), \ 822 .scan_type = { \ 823 .sign = 'u', \ 824 .realbits = 24, \ 825 .storagebits = 32, \ 826 .endianness = IIO_BE, \ 827 }, \ 828 } 829 830 #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \ 831 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, NULL, \ 832 IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE), \ 833 ad7192_calibsys_ext_info) 834 835 #define AD719x_CHANNEL(_si, _channel1, _address) \ 836 __AD719x_CHANNEL(_si, _channel1, -1, _address, NULL, IIO_VOLTAGE, \ 837 BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info) 838 839 #define AD719x_SHORTED_CHANNEL(_si, _channel1, _address) \ 840 __AD719x_CHANNEL(_si, _channel1, -1, _address, "shorted", IIO_VOLTAGE, \ 841 BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info) 842 843 #define AD719x_TEMP_CHANNEL(_si, _address) \ 844 __AD719x_CHANNEL(_si, 0, -1, _address, NULL, IIO_TEMP, 0, NULL) 845 846 static const struct iio_chan_spec ad7192_channels[] = { 847 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M), 848 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M), 849 AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP), 850 AD719x_SHORTED_CHANNEL(3, 2, AD7192_CH_AIN2P_AIN2M), 851 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1), 852 AD719x_CHANNEL(5, 2, AD7192_CH_AIN2), 853 AD719x_CHANNEL(6, 3, AD7192_CH_AIN3), 854 AD719x_CHANNEL(7, 4, AD7192_CH_AIN4), 855 IIO_CHAN_SOFT_TIMESTAMP(8), 856 }; 857 858 static const struct iio_chan_spec ad7193_channels[] = { 859 AD719x_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M), 860 AD719x_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M), 861 AD719x_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M), 862 AD719x_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M), 863 AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP), 864 AD719x_SHORTED_CHANNEL(5, 2, AD7193_CH_AIN2P_AIN2M), 865 AD719x_CHANNEL(6, 1, AD7193_CH_AIN1), 866 AD719x_CHANNEL(7, 2, AD7193_CH_AIN2), 867 AD719x_CHANNEL(8, 3, AD7193_CH_AIN3), 868 AD719x_CHANNEL(9, 4, AD7193_CH_AIN4), 869 AD719x_CHANNEL(10, 5, AD7193_CH_AIN5), 870 AD719x_CHANNEL(11, 6, AD7193_CH_AIN6), 871 AD719x_CHANNEL(12, 7, AD7193_CH_AIN7), 872 AD719x_CHANNEL(13, 8, AD7193_CH_AIN8), 873 IIO_CHAN_SOFT_TIMESTAMP(14), 874 }; 875 876 static const struct ad7192_chip_info ad7192_chip_info_tbl[] = { 877 [ID_AD7190] = { 878 .chip_id = CHIPID_AD7190, 879 .name = "ad7190", 880 }, 881 [ID_AD7192] = { 882 .chip_id = CHIPID_AD7192, 883 .name = "ad7192", 884 }, 885 [ID_AD7193] = { 886 .chip_id = CHIPID_AD7193, 887 .name = "ad7193", 888 }, 889 [ID_AD7195] = { 890 .chip_id = CHIPID_AD7195, 891 .name = "ad7195", 892 }, 893 }; 894 895 static int ad7192_channels_config(struct iio_dev *indio_dev) 896 { 897 struct ad7192_state *st = iio_priv(indio_dev); 898 899 switch (st->chip_info->chip_id) { 900 case CHIPID_AD7193: 901 indio_dev->channels = ad7193_channels; 902 indio_dev->num_channels = ARRAY_SIZE(ad7193_channels); 903 break; 904 default: 905 indio_dev->channels = ad7192_channels; 906 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels); 907 break; 908 } 909 910 return 0; 911 } 912 913 static void ad7192_reg_disable(void *reg) 914 { 915 regulator_disable(reg); 916 } 917 918 static void ad7192_clk_disable(void *clk) 919 { 920 clk_disable_unprepare(clk); 921 } 922 923 static int ad7192_probe(struct spi_device *spi) 924 { 925 struct ad7192_state *st; 926 struct iio_dev *indio_dev; 927 int ret; 928 929 if (!spi->irq) { 930 dev_err(&spi->dev, "no IRQ?\n"); 931 return -ENODEV; 932 } 933 934 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 935 if (!indio_dev) 936 return -ENOMEM; 937 938 st = iio_priv(indio_dev); 939 940 mutex_init(&st->lock); 941 942 st->avdd = devm_regulator_get(&spi->dev, "avdd"); 943 if (IS_ERR(st->avdd)) 944 return PTR_ERR(st->avdd); 945 946 ret = regulator_enable(st->avdd); 947 if (ret) { 948 dev_err(&spi->dev, "Failed to enable specified AVdd supply\n"); 949 return ret; 950 } 951 952 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->avdd); 953 if (ret) 954 return ret; 955 956 st->dvdd = devm_regulator_get(&spi->dev, "dvdd"); 957 if (IS_ERR(st->dvdd)) 958 return PTR_ERR(st->dvdd); 959 960 ret = regulator_enable(st->dvdd); 961 if (ret) { 962 dev_err(&spi->dev, "Failed to enable specified DVdd supply\n"); 963 return ret; 964 } 965 966 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->dvdd); 967 if (ret) 968 return ret; 969 970 ret = regulator_get_voltage(st->avdd); 971 if (ret < 0) { 972 dev_err(&spi->dev, "Device tree error, reference voltage undefined\n"); 973 return ret; 974 } 975 st->int_vref_mv = ret / 1000; 976 977 st->chip_info = of_device_get_match_data(&spi->dev); 978 indio_dev->name = st->chip_info->name; 979 indio_dev->modes = INDIO_DIRECT_MODE; 980 981 ret = ad7192_channels_config(indio_dev); 982 if (ret < 0) 983 return ret; 984 985 if (st->chip_info->chip_id == CHIPID_AD7195) 986 indio_dev->info = &ad7195_info; 987 else 988 indio_dev->info = &ad7192_info; 989 990 ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info); 991 992 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev); 993 if (ret) 994 return ret; 995 996 st->fclk = AD7192_INT_FREQ_MHZ; 997 998 st->mclk = devm_clk_get_optional(&spi->dev, "mclk"); 999 if (IS_ERR(st->mclk)) 1000 return PTR_ERR(st->mclk); 1001 1002 st->clock_sel = ad7192_of_clock_select(st); 1003 1004 if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 || 1005 st->clock_sel == AD7192_CLK_EXT_MCLK2) { 1006 ret = clk_prepare_enable(st->mclk); 1007 if (ret < 0) 1008 return ret; 1009 1010 ret = devm_add_action_or_reset(&spi->dev, ad7192_clk_disable, 1011 st->mclk); 1012 if (ret) 1013 return ret; 1014 1015 st->fclk = clk_get_rate(st->mclk); 1016 if (!ad7192_valid_external_frequency(st->fclk)) { 1017 dev_err(&spi->dev, 1018 "External clock frequency out of bounds\n"); 1019 return -EINVAL; 1020 } 1021 } 1022 1023 ret = ad7192_setup(st, spi->dev.of_node); 1024 if (ret) 1025 return ret; 1026 1027 return devm_iio_device_register(&spi->dev, indio_dev); 1028 } 1029 1030 static const struct of_device_id ad7192_of_match[] = { 1031 { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] }, 1032 { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] }, 1033 { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] }, 1034 { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] }, 1035 {} 1036 }; 1037 MODULE_DEVICE_TABLE(of, ad7192_of_match); 1038 1039 static struct spi_driver ad7192_driver = { 1040 .driver = { 1041 .name = "ad7192", 1042 .of_match_table = ad7192_of_match, 1043 }, 1044 .probe = ad7192_probe, 1045 }; 1046 module_spi_driver(ad7192_driver); 1047 1048 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 1049 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC"); 1050 MODULE_LICENSE("GPL v2"); 1051 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA); 1052