1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AD7190 AD7192 AD7193 AD7195 SPI ADC driver 4 * 5 * Copyright 2011-2015 Analog Devices Inc. 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/clk.h> 10 #include <linux/device.h> 11 #include <linux/kernel.h> 12 #include <linux/slab.h> 13 #include <linux/sysfs.h> 14 #include <linux/spi/spi.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/err.h> 17 #include <linux/sched.h> 18 #include <linux/delay.h> 19 #include <linux/of_device.h> 20 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/buffer.h> 24 #include <linux/iio/trigger.h> 25 #include <linux/iio/trigger_consumer.h> 26 #include <linux/iio/triggered_buffer.h> 27 #include <linux/iio/adc/ad_sigma_delta.h> 28 29 /* Registers */ 30 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */ 31 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */ 32 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */ 33 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */ 34 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */ 35 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */ 36 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */ 37 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */ 38 /* (AD7792)/24-bit (AD7192)) */ 39 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */ 40 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */ 41 42 /* Communications Register Bit Designations (AD7192_REG_COMM) */ 43 #define AD7192_COMM_WEN BIT(7) /* Write Enable */ 44 #define AD7192_COMM_WRITE 0 /* Write Operation */ 45 #define AD7192_COMM_READ BIT(6) /* Read Operation */ 46 #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */ 47 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */ 48 49 /* Status Register Bit Designations (AD7192_REG_STAT) */ 50 #define AD7192_STAT_RDY BIT(7) /* Ready */ 51 #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */ 52 #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */ 53 #define AD7192_STAT_PARITY BIT(4) /* Parity */ 54 #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */ 55 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */ 56 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */ 57 58 /* Mode Register Bit Designations (AD7192_REG_MODE) */ 59 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */ 60 #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */ 61 #define AD7192_MODE_DAT_STA BIT(20) /* Status Register transmission */ 62 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */ 63 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */ 64 #define AD7192_MODE_ACX BIT(14) /* AC excitation enable(AD7195 only)*/ 65 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */ 66 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/ 67 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */ 68 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */ 69 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */ 70 71 /* Mode Register: AD7192_MODE_SEL options */ 72 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */ 73 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */ 74 #define AD7192_MODE_IDLE 2 /* Idle Mode */ 75 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */ 76 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */ 77 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */ 78 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */ 79 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */ 80 81 /* Mode Register: AD7192_MODE_CLKSRC options */ 82 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/ 83 /* from MCLK1 to MCLK2 */ 84 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */ 85 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */ 86 /* available at the MCLK2 pin */ 87 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/ 88 /* at the MCLK2 pin */ 89 90 /* Configuration Register Bit Designations (AD7192_REG_CONF) */ 91 92 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */ 93 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */ 94 #define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */ 95 #define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */ 96 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */ 97 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */ 98 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */ 99 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */ 100 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */ 101 102 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */ 103 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */ 104 #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */ 105 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */ 106 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */ 107 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */ 108 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */ 109 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */ 110 111 #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */ 112 #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */ 113 #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */ 114 #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */ 115 #define AD7193_CH_TEMP 0x100 /* Temp senseor */ 116 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */ 117 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */ 118 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */ 119 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */ 120 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */ 121 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */ 122 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */ 123 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */ 124 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */ 125 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */ 126 127 /* ID Register Bit Designations (AD7192_REG_ID) */ 128 #define CHIPID_AD7190 0x4 129 #define CHIPID_AD7192 0x0 130 #define CHIPID_AD7193 0x2 131 #define CHIPID_AD7195 0x6 132 #define AD7192_ID_MASK 0x0F 133 134 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */ 135 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */ 136 #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */ 137 #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */ 138 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */ 139 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */ 140 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */ 141 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */ 142 143 #define AD7192_EXT_FREQ_MHZ_MIN 2457600 144 #define AD7192_EXT_FREQ_MHZ_MAX 5120000 145 #define AD7192_INT_FREQ_MHZ 4915200 146 147 #define AD7192_NO_SYNC_FILTER 1 148 #define AD7192_SYNC3_FILTER 3 149 #define AD7192_SYNC4_FILTER 4 150 151 /* NOTE: 152 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output. 153 * In order to avoid contentions on the SPI bus, it's therefore necessary 154 * to use spi bus locking. 155 * 156 * The DOUT/RDY output must also be wired to an interrupt capable GPIO. 157 */ 158 159 enum { 160 AD7192_SYSCALIB_ZERO_SCALE, 161 AD7192_SYSCALIB_FULL_SCALE, 162 }; 163 164 enum { 165 ID_AD7190, 166 ID_AD7192, 167 ID_AD7193, 168 ID_AD7195, 169 }; 170 171 struct ad7192_chip_info { 172 unsigned int chip_id; 173 const char *name; 174 }; 175 176 struct ad7192_state { 177 const struct ad7192_chip_info *chip_info; 178 struct regulator *avdd; 179 struct regulator *dvdd; 180 struct clk *mclk; 181 u16 int_vref_mv; 182 u32 fclk; 183 u32 f_order; 184 u32 mode; 185 u32 conf; 186 u32 scale_avail[8][2]; 187 u8 gpocon; 188 u8 clock_sel; 189 struct mutex lock; /* protect sensor state */ 190 u8 syscalib_mode[8]; 191 192 struct ad_sigma_delta sd; 193 }; 194 195 static const char * const ad7192_syscalib_modes[] = { 196 [AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale", 197 [AD7192_SYSCALIB_FULL_SCALE] = "full_scale", 198 }; 199 200 static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev, 201 const struct iio_chan_spec *chan, 202 unsigned int mode) 203 { 204 struct ad7192_state *st = iio_priv(indio_dev); 205 206 st->syscalib_mode[chan->channel] = mode; 207 208 return 0; 209 } 210 211 static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev, 212 const struct iio_chan_spec *chan) 213 { 214 struct ad7192_state *st = iio_priv(indio_dev); 215 216 return st->syscalib_mode[chan->channel]; 217 } 218 219 static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev, 220 uintptr_t private, 221 const struct iio_chan_spec *chan, 222 const char *buf, size_t len) 223 { 224 struct ad7192_state *st = iio_priv(indio_dev); 225 bool sys_calib; 226 int ret, temp; 227 228 ret = strtobool(buf, &sys_calib); 229 if (ret) 230 return ret; 231 232 temp = st->syscalib_mode[chan->channel]; 233 if (sys_calib) { 234 if (temp == AD7192_SYSCALIB_ZERO_SCALE) 235 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO, 236 chan->address); 237 else 238 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL, 239 chan->address); 240 } 241 242 return ret ? ret : len; 243 } 244 245 static const struct iio_enum ad7192_syscalib_mode_enum = { 246 .items = ad7192_syscalib_modes, 247 .num_items = ARRAY_SIZE(ad7192_syscalib_modes), 248 .set = ad7192_set_syscalib_mode, 249 .get = ad7192_get_syscalib_mode 250 }; 251 252 static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = { 253 { 254 .name = "sys_calibration", 255 .write = ad7192_write_syscalib, 256 .shared = IIO_SEPARATE, 257 }, 258 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE, 259 &ad7192_syscalib_mode_enum), 260 IIO_ENUM_AVAILABLE("sys_calibration_mode", &ad7192_syscalib_mode_enum), 261 {} 262 }; 263 264 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd) 265 { 266 return container_of(sd, struct ad7192_state, sd); 267 } 268 269 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 270 { 271 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 272 273 st->conf &= ~AD7192_CONF_CHAN_MASK; 274 st->conf |= AD7192_CONF_CHAN(channel); 275 276 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 277 } 278 279 static int ad7192_set_mode(struct ad_sigma_delta *sd, 280 enum ad_sigma_delta_mode mode) 281 { 282 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 283 284 st->mode &= ~AD7192_MODE_SEL_MASK; 285 st->mode |= AD7192_MODE_SEL(mode); 286 287 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 288 } 289 290 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = { 291 .set_channel = ad7192_set_channel, 292 .set_mode = ad7192_set_mode, 293 .has_registers = true, 294 .addr_shift = 3, 295 .read_mask = BIT(6), 296 }; 297 298 static const struct ad_sd_calib_data ad7192_calib_arr[8] = { 299 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1}, 300 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1}, 301 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2}, 302 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2}, 303 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3}, 304 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3}, 305 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4}, 306 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4} 307 }; 308 309 static int ad7192_calibrate_all(struct ad7192_state *st) 310 { 311 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr, 312 ARRAY_SIZE(ad7192_calib_arr)); 313 } 314 315 static inline bool ad7192_valid_external_frequency(u32 freq) 316 { 317 return (freq >= AD7192_EXT_FREQ_MHZ_MIN && 318 freq <= AD7192_EXT_FREQ_MHZ_MAX); 319 } 320 321 static int ad7192_of_clock_select(struct ad7192_state *st) 322 { 323 struct device_node *np = st->sd.spi->dev.of_node; 324 unsigned int clock_sel; 325 326 clock_sel = AD7192_CLK_INT; 327 328 /* use internal clock */ 329 if (st->mclk) { 330 if (of_property_read_bool(np, "adi,int-clock-output-enable")) 331 clock_sel = AD7192_CLK_INT_CO; 332 } else { 333 if (of_property_read_bool(np, "adi,clock-xtal")) 334 clock_sel = AD7192_CLK_EXT_MCLK1_2; 335 else 336 clock_sel = AD7192_CLK_EXT_MCLK2; 337 } 338 339 return clock_sel; 340 } 341 342 static int ad7192_setup(struct ad7192_state *st, struct device_node *np) 343 { 344 struct iio_dev *indio_dev = spi_get_drvdata(st->sd.spi); 345 bool rej60_en, refin2_en; 346 bool buf_en, bipolar, burnout_curr_en; 347 unsigned long long scale_uv; 348 int i, ret, id; 349 350 /* reset the serial interface */ 351 ret = ad_sd_reset(&st->sd, 48); 352 if (ret < 0) 353 return ret; 354 usleep_range(500, 1000); /* Wait for at least 500us */ 355 356 /* write/read test for device presence */ 357 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id); 358 if (ret) 359 return ret; 360 361 id &= AD7192_ID_MASK; 362 363 if (id != st->chip_info->chip_id) 364 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X)\n", 365 id); 366 367 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) | 368 AD7192_MODE_CLKSRC(st->clock_sel) | 369 AD7192_MODE_RATE(480); 370 371 st->conf = AD7192_CONF_GAIN(0); 372 373 rej60_en = of_property_read_bool(np, "adi,rejection-60-Hz-enable"); 374 if (rej60_en) 375 st->mode |= AD7192_MODE_REJ60; 376 377 refin2_en = of_property_read_bool(np, "adi,refin2-pins-enable"); 378 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195) 379 st->conf |= AD7192_CONF_REFSEL; 380 381 st->conf &= ~AD7192_CONF_CHOP; 382 st->f_order = AD7192_NO_SYNC_FILTER; 383 384 buf_en = of_property_read_bool(np, "adi,buffer-enable"); 385 if (buf_en) 386 st->conf |= AD7192_CONF_BUF; 387 388 bipolar = of_property_read_bool(np, "bipolar"); 389 if (!bipolar) 390 st->conf |= AD7192_CONF_UNIPOLAR; 391 392 burnout_curr_en = of_property_read_bool(np, 393 "adi,burnout-currents-enable"); 394 if (burnout_curr_en && buf_en) { 395 st->conf |= AD7192_CONF_BURN; 396 } else if (burnout_curr_en) { 397 dev_warn(&st->sd.spi->dev, 398 "Can't enable burnout currents: see CHOP or buffer\n"); 399 } 400 401 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 402 if (ret) 403 return ret; 404 405 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 406 if (ret) 407 return ret; 408 409 ret = ad7192_calibrate_all(st); 410 if (ret) 411 return ret; 412 413 /* Populate available ADC input ranges */ 414 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { 415 scale_uv = ((u64)st->int_vref_mv * 100000000) 416 >> (indio_dev->channels[0].scan_type.realbits - 417 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1)); 418 scale_uv >>= i; 419 420 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; 421 st->scale_avail[i][0] = scale_uv; 422 } 423 424 return 0; 425 } 426 427 static ssize_t ad7192_show_ac_excitation(struct device *dev, 428 struct device_attribute *attr, 429 char *buf) 430 { 431 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 432 struct ad7192_state *st = iio_priv(indio_dev); 433 434 return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX)); 435 } 436 437 static ssize_t ad7192_show_bridge_switch(struct device *dev, 438 struct device_attribute *attr, 439 char *buf) 440 { 441 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 442 struct ad7192_state *st = iio_priv(indio_dev); 443 444 return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW)); 445 } 446 447 static ssize_t ad7192_set(struct device *dev, 448 struct device_attribute *attr, 449 const char *buf, 450 size_t len) 451 { 452 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 453 struct ad7192_state *st = iio_priv(indio_dev); 454 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 455 int ret; 456 bool val; 457 458 ret = strtobool(buf, &val); 459 if (ret < 0) 460 return ret; 461 462 ret = iio_device_claim_direct_mode(indio_dev); 463 if (ret) 464 return ret; 465 466 switch ((u32)this_attr->address) { 467 case AD7192_REG_GPOCON: 468 if (val) 469 st->gpocon |= AD7192_GPOCON_BPDSW; 470 else 471 st->gpocon &= ~AD7192_GPOCON_BPDSW; 472 473 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon); 474 break; 475 case AD7192_REG_MODE: 476 if (val) 477 st->mode |= AD7192_MODE_ACX; 478 else 479 st->mode &= ~AD7192_MODE_ACX; 480 481 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 482 break; 483 default: 484 ret = -EINVAL; 485 } 486 487 iio_device_release_direct_mode(indio_dev); 488 489 return ret ? ret : len; 490 } 491 492 static void ad7192_get_available_filter_freq(struct ad7192_state *st, 493 int *freq) 494 { 495 unsigned int fadc; 496 497 /* Formulas for filter at page 25 of the datasheet */ 498 fadc = DIV_ROUND_CLOSEST(st->fclk, 499 AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode)); 500 freq[0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); 501 502 fadc = DIV_ROUND_CLOSEST(st->fclk, 503 AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode)); 504 freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024); 505 506 fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode)); 507 freq[2] = DIV_ROUND_CLOSEST(fadc * 230, 1024); 508 freq[3] = DIV_ROUND_CLOSEST(fadc * 272, 1024); 509 } 510 511 static ssize_t ad7192_show_filter_avail(struct device *dev, 512 struct device_attribute *attr, 513 char *buf) 514 { 515 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 516 struct ad7192_state *st = iio_priv(indio_dev); 517 unsigned int freq_avail[4], i; 518 size_t len = 0; 519 520 ad7192_get_available_filter_freq(st, freq_avail); 521 522 for (i = 0; i < ARRAY_SIZE(freq_avail); i++) 523 len += scnprintf(buf + len, PAGE_SIZE - len, 524 "%d.%d ", freq_avail[i] / 1000, 525 freq_avail[i] % 1000); 526 527 buf[len - 1] = '\n'; 528 529 return len; 530 } 531 532 static IIO_DEVICE_ATTR(filter_low_pass_3db_frequency_available, 533 0444, ad7192_show_filter_avail, NULL, 0); 534 535 static IIO_DEVICE_ATTR(bridge_switch_en, 0644, 536 ad7192_show_bridge_switch, ad7192_set, 537 AD7192_REG_GPOCON); 538 539 static IIO_DEVICE_ATTR(ac_excitation_en, 0644, 540 ad7192_show_ac_excitation, ad7192_set, 541 AD7192_REG_MODE); 542 543 static struct attribute *ad7192_attributes[] = { 544 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr, 545 &iio_dev_attr_bridge_switch_en.dev_attr.attr, 546 &iio_dev_attr_ac_excitation_en.dev_attr.attr, 547 NULL 548 }; 549 550 static const struct attribute_group ad7192_attribute_group = { 551 .attrs = ad7192_attributes, 552 }; 553 554 static struct attribute *ad7195_attributes[] = { 555 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr, 556 &iio_dev_attr_bridge_switch_en.dev_attr.attr, 557 NULL 558 }; 559 560 static const struct attribute_group ad7195_attribute_group = { 561 .attrs = ad7195_attributes, 562 }; 563 564 static unsigned int ad7192_get_temp_scale(bool unipolar) 565 { 566 return unipolar ? 2815 * 2 : 2815; 567 } 568 569 static int ad7192_set_3db_filter_freq(struct ad7192_state *st, 570 int val, int val2) 571 { 572 int freq_avail[4], i, ret, freq; 573 unsigned int diff_new, diff_old; 574 int idx = 0; 575 576 diff_old = U32_MAX; 577 freq = val * 1000 + val2; 578 579 ad7192_get_available_filter_freq(st, freq_avail); 580 581 for (i = 0; i < ARRAY_SIZE(freq_avail); i++) { 582 diff_new = abs(freq - freq_avail[i]); 583 if (diff_new < diff_old) { 584 diff_old = diff_new; 585 idx = i; 586 } 587 } 588 589 switch (idx) { 590 case 0: 591 st->f_order = AD7192_SYNC4_FILTER; 592 st->mode &= ~AD7192_MODE_SINC3; 593 594 st->conf |= AD7192_CONF_CHOP; 595 break; 596 case 1: 597 st->f_order = AD7192_SYNC3_FILTER; 598 st->mode |= AD7192_MODE_SINC3; 599 600 st->conf |= AD7192_CONF_CHOP; 601 break; 602 case 2: 603 st->f_order = AD7192_NO_SYNC_FILTER; 604 st->mode &= ~AD7192_MODE_SINC3; 605 606 st->conf &= ~AD7192_CONF_CHOP; 607 break; 608 case 3: 609 st->f_order = AD7192_NO_SYNC_FILTER; 610 st->mode |= AD7192_MODE_SINC3; 611 612 st->conf &= ~AD7192_CONF_CHOP; 613 break; 614 } 615 616 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 617 if (ret < 0) 618 return ret; 619 620 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 621 } 622 623 static int ad7192_get_3db_filter_freq(struct ad7192_state *st) 624 { 625 unsigned int fadc; 626 627 fadc = DIV_ROUND_CLOSEST(st->fclk, 628 st->f_order * AD7192_MODE_RATE(st->mode)); 629 630 if (st->conf & AD7192_CONF_CHOP) 631 return DIV_ROUND_CLOSEST(fadc * 240, 1024); 632 if (st->mode & AD7192_MODE_SINC3) 633 return DIV_ROUND_CLOSEST(fadc * 272, 1024); 634 else 635 return DIV_ROUND_CLOSEST(fadc * 230, 1024); 636 } 637 638 static int ad7192_read_raw(struct iio_dev *indio_dev, 639 struct iio_chan_spec const *chan, 640 int *val, 641 int *val2, 642 long m) 643 { 644 struct ad7192_state *st = iio_priv(indio_dev); 645 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR); 646 647 switch (m) { 648 case IIO_CHAN_INFO_RAW: 649 return ad_sigma_delta_single_conversion(indio_dev, chan, val); 650 case IIO_CHAN_INFO_SCALE: 651 switch (chan->type) { 652 case IIO_VOLTAGE: 653 mutex_lock(&st->lock); 654 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0]; 655 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1]; 656 mutex_unlock(&st->lock); 657 return IIO_VAL_INT_PLUS_NANO; 658 case IIO_TEMP: 659 *val = 0; 660 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar); 661 return IIO_VAL_INT_PLUS_NANO; 662 default: 663 return -EINVAL; 664 } 665 case IIO_CHAN_INFO_OFFSET: 666 if (!unipolar) 667 *val = -(1 << (chan->scan_type.realbits - 1)); 668 else 669 *val = 0; 670 /* Kelvin to Celsius */ 671 if (chan->type == IIO_TEMP) 672 *val -= 273 * ad7192_get_temp_scale(unipolar); 673 return IIO_VAL_INT; 674 case IIO_CHAN_INFO_SAMP_FREQ: 675 *val = st->fclk / 676 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode)); 677 return IIO_VAL_INT; 678 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 679 *val = ad7192_get_3db_filter_freq(st); 680 *val2 = 1000; 681 return IIO_VAL_FRACTIONAL; 682 } 683 684 return -EINVAL; 685 } 686 687 static int ad7192_write_raw(struct iio_dev *indio_dev, 688 struct iio_chan_spec const *chan, 689 int val, 690 int val2, 691 long mask) 692 { 693 struct ad7192_state *st = iio_priv(indio_dev); 694 int ret, i, div; 695 unsigned int tmp; 696 697 ret = iio_device_claim_direct_mode(indio_dev); 698 if (ret) 699 return ret; 700 701 switch (mask) { 702 case IIO_CHAN_INFO_SCALE: 703 ret = -EINVAL; 704 mutex_lock(&st->lock); 705 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) 706 if (val2 == st->scale_avail[i][1]) { 707 ret = 0; 708 tmp = st->conf; 709 st->conf &= ~AD7192_CONF_GAIN(-1); 710 st->conf |= AD7192_CONF_GAIN(i); 711 if (tmp == st->conf) 712 break; 713 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 714 3, st->conf); 715 ad7192_calibrate_all(st); 716 break; 717 } 718 mutex_unlock(&st->lock); 719 break; 720 case IIO_CHAN_INFO_SAMP_FREQ: 721 if (!val) { 722 ret = -EINVAL; 723 break; 724 } 725 726 div = st->fclk / (val * st->f_order * 1024); 727 if (div < 1 || div > 1023) { 728 ret = -EINVAL; 729 break; 730 } 731 732 st->mode &= ~AD7192_MODE_RATE(-1); 733 st->mode |= AD7192_MODE_RATE(div); 734 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 735 break; 736 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 737 ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000); 738 break; 739 default: 740 ret = -EINVAL; 741 } 742 743 iio_device_release_direct_mode(indio_dev); 744 745 return ret; 746 } 747 748 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev, 749 struct iio_chan_spec const *chan, 750 long mask) 751 { 752 switch (mask) { 753 case IIO_CHAN_INFO_SCALE: 754 return IIO_VAL_INT_PLUS_NANO; 755 case IIO_CHAN_INFO_SAMP_FREQ: 756 return IIO_VAL_INT; 757 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 758 return IIO_VAL_INT_PLUS_MICRO; 759 default: 760 return -EINVAL; 761 } 762 } 763 764 static int ad7192_read_avail(struct iio_dev *indio_dev, 765 struct iio_chan_spec const *chan, 766 const int **vals, int *type, int *length, 767 long mask) 768 { 769 struct ad7192_state *st = iio_priv(indio_dev); 770 771 switch (mask) { 772 case IIO_CHAN_INFO_SCALE: 773 *vals = (int *)st->scale_avail; 774 *type = IIO_VAL_INT_PLUS_NANO; 775 /* Values are stored in a 2D matrix */ 776 *length = ARRAY_SIZE(st->scale_avail) * 2; 777 778 return IIO_AVAIL_LIST; 779 } 780 781 return -EINVAL; 782 } 783 784 static const struct iio_info ad7192_info = { 785 .read_raw = ad7192_read_raw, 786 .write_raw = ad7192_write_raw, 787 .write_raw_get_fmt = ad7192_write_raw_get_fmt, 788 .read_avail = ad7192_read_avail, 789 .attrs = &ad7192_attribute_group, 790 .validate_trigger = ad_sd_validate_trigger, 791 }; 792 793 static const struct iio_info ad7195_info = { 794 .read_raw = ad7192_read_raw, 795 .write_raw = ad7192_write_raw, 796 .write_raw_get_fmt = ad7192_write_raw_get_fmt, 797 .read_avail = ad7192_read_avail, 798 .attrs = &ad7195_attribute_group, 799 .validate_trigger = ad_sd_validate_trigger, 800 }; 801 802 #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _extend_name, \ 803 _type, _mask_type_av, _ext_info) \ 804 { \ 805 .type = (_type), \ 806 .differential = ((_channel2) == -1 ? 0 : 1), \ 807 .indexed = 1, \ 808 .channel = (_channel1), \ 809 .channel2 = (_channel2), \ 810 .address = (_address), \ 811 .extend_name = (_extend_name), \ 812 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 813 BIT(IIO_CHAN_INFO_OFFSET), \ 814 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 815 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 816 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 817 .info_mask_shared_by_type_available = (_mask_type_av), \ 818 .ext_info = (_ext_info), \ 819 .scan_index = (_si), \ 820 .scan_type = { \ 821 .sign = 'u', \ 822 .realbits = 24, \ 823 .storagebits = 32, \ 824 .endianness = IIO_BE, \ 825 }, \ 826 } 827 828 #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \ 829 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, NULL, \ 830 IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE), \ 831 ad7192_calibsys_ext_info) 832 833 #define AD719x_CHANNEL(_si, _channel1, _address) \ 834 __AD719x_CHANNEL(_si, _channel1, -1, _address, NULL, IIO_VOLTAGE, \ 835 BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info) 836 837 #define AD719x_SHORTED_CHANNEL(_si, _channel1, _address) \ 838 __AD719x_CHANNEL(_si, _channel1, -1, _address, "shorted", IIO_VOLTAGE, \ 839 BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info) 840 841 #define AD719x_TEMP_CHANNEL(_si, _address) \ 842 __AD719x_CHANNEL(_si, 0, -1, _address, NULL, IIO_TEMP, 0, NULL) 843 844 static const struct iio_chan_spec ad7192_channels[] = { 845 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M), 846 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M), 847 AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP), 848 AD719x_SHORTED_CHANNEL(3, 2, AD7192_CH_AIN2P_AIN2M), 849 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1), 850 AD719x_CHANNEL(5, 2, AD7192_CH_AIN2), 851 AD719x_CHANNEL(6, 3, AD7192_CH_AIN3), 852 AD719x_CHANNEL(7, 4, AD7192_CH_AIN4), 853 IIO_CHAN_SOFT_TIMESTAMP(8), 854 }; 855 856 static const struct iio_chan_spec ad7193_channels[] = { 857 AD719x_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M), 858 AD719x_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M), 859 AD719x_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M), 860 AD719x_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M), 861 AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP), 862 AD719x_SHORTED_CHANNEL(5, 2, AD7193_CH_AIN2P_AIN2M), 863 AD719x_CHANNEL(6, 1, AD7193_CH_AIN1), 864 AD719x_CHANNEL(7, 2, AD7193_CH_AIN2), 865 AD719x_CHANNEL(8, 3, AD7193_CH_AIN3), 866 AD719x_CHANNEL(9, 4, AD7193_CH_AIN4), 867 AD719x_CHANNEL(10, 5, AD7193_CH_AIN5), 868 AD719x_CHANNEL(11, 6, AD7193_CH_AIN6), 869 AD719x_CHANNEL(12, 7, AD7193_CH_AIN7), 870 AD719x_CHANNEL(13, 8, AD7193_CH_AIN8), 871 IIO_CHAN_SOFT_TIMESTAMP(14), 872 }; 873 874 static const struct ad7192_chip_info ad7192_chip_info_tbl[] = { 875 [ID_AD7190] = { 876 .chip_id = CHIPID_AD7190, 877 .name = "ad7190", 878 }, 879 [ID_AD7192] = { 880 .chip_id = CHIPID_AD7192, 881 .name = "ad7192", 882 }, 883 [ID_AD7193] = { 884 .chip_id = CHIPID_AD7193, 885 .name = "ad7193", 886 }, 887 [ID_AD7195] = { 888 .chip_id = CHIPID_AD7195, 889 .name = "ad7195", 890 }, 891 }; 892 893 static int ad7192_channels_config(struct iio_dev *indio_dev) 894 { 895 struct ad7192_state *st = iio_priv(indio_dev); 896 897 switch (st->chip_info->chip_id) { 898 case CHIPID_AD7193: 899 indio_dev->channels = ad7193_channels; 900 indio_dev->num_channels = ARRAY_SIZE(ad7193_channels); 901 break; 902 default: 903 indio_dev->channels = ad7192_channels; 904 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels); 905 break; 906 } 907 908 return 0; 909 } 910 911 static void ad7192_reg_disable(void *reg) 912 { 913 regulator_disable(reg); 914 } 915 916 static void ad7192_clk_disable(void *clk) 917 { 918 clk_disable_unprepare(clk); 919 } 920 921 static int ad7192_probe(struct spi_device *spi) 922 { 923 struct ad7192_state *st; 924 struct iio_dev *indio_dev; 925 int ret; 926 927 if (!spi->irq) { 928 dev_err(&spi->dev, "no IRQ?\n"); 929 return -ENODEV; 930 } 931 932 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 933 if (!indio_dev) 934 return -ENOMEM; 935 936 st = iio_priv(indio_dev); 937 938 mutex_init(&st->lock); 939 940 st->avdd = devm_regulator_get(&spi->dev, "avdd"); 941 if (IS_ERR(st->avdd)) 942 return PTR_ERR(st->avdd); 943 944 ret = regulator_enable(st->avdd); 945 if (ret) { 946 dev_err(&spi->dev, "Failed to enable specified AVdd supply\n"); 947 return ret; 948 } 949 950 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->avdd); 951 if (ret) 952 return ret; 953 954 st->dvdd = devm_regulator_get(&spi->dev, "dvdd"); 955 if (IS_ERR(st->dvdd)) 956 return PTR_ERR(st->dvdd); 957 958 ret = regulator_enable(st->dvdd); 959 if (ret) { 960 dev_err(&spi->dev, "Failed to enable specified DVdd supply\n"); 961 return ret; 962 } 963 964 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->dvdd); 965 if (ret) 966 return ret; 967 968 ret = regulator_get_voltage(st->avdd); 969 if (ret < 0) { 970 dev_err(&spi->dev, "Device tree error, reference voltage undefined\n"); 971 return ret; 972 } 973 st->int_vref_mv = ret / 1000; 974 975 st->chip_info = of_device_get_match_data(&spi->dev); 976 indio_dev->name = st->chip_info->name; 977 indio_dev->modes = INDIO_DIRECT_MODE; 978 979 ret = ad7192_channels_config(indio_dev); 980 if (ret < 0) 981 return ret; 982 983 if (st->chip_info->chip_id == CHIPID_AD7195) 984 indio_dev->info = &ad7195_info; 985 else 986 indio_dev->info = &ad7192_info; 987 988 ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info); 989 990 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev); 991 if (ret) 992 return ret; 993 994 st->fclk = AD7192_INT_FREQ_MHZ; 995 996 st->mclk = devm_clk_get_optional(&spi->dev, "mclk"); 997 if (IS_ERR(st->mclk)) 998 return PTR_ERR(st->mclk); 999 1000 st->clock_sel = ad7192_of_clock_select(st); 1001 1002 if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 || 1003 st->clock_sel == AD7192_CLK_EXT_MCLK2) { 1004 ret = clk_prepare_enable(st->mclk); 1005 if (ret < 0) 1006 return ret; 1007 1008 ret = devm_add_action_or_reset(&spi->dev, ad7192_clk_disable, 1009 st->mclk); 1010 if (ret) 1011 return ret; 1012 1013 st->fclk = clk_get_rate(st->mclk); 1014 if (!ad7192_valid_external_frequency(st->fclk)) { 1015 dev_err(&spi->dev, 1016 "External clock frequency out of bounds\n"); 1017 return -EINVAL; 1018 } 1019 } 1020 1021 ret = ad7192_setup(st, spi->dev.of_node); 1022 if (ret) 1023 return ret; 1024 1025 return devm_iio_device_register(&spi->dev, indio_dev); 1026 } 1027 1028 static const struct of_device_id ad7192_of_match[] = { 1029 { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] }, 1030 { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] }, 1031 { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] }, 1032 { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] }, 1033 {} 1034 }; 1035 MODULE_DEVICE_TABLE(of, ad7192_of_match); 1036 1037 static struct spi_driver ad7192_driver = { 1038 .driver = { 1039 .name = "ad7192", 1040 .of_match_table = ad7192_of_match, 1041 }, 1042 .probe = ad7192_probe, 1043 }; 1044 module_spi_driver(ad7192_driver); 1045 1046 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 1047 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC"); 1048 MODULE_LICENSE("GPL v2"); 1049