1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AD7190 AD7192 AD7193 AD7195 SPI ADC driver 4 * 5 * Copyright 2011-2015 Analog Devices Inc. 6 */ 7 8 #include <linux/interrupt.h> 9 #include <linux/clk.h> 10 #include <linux/device.h> 11 #include <linux/kernel.h> 12 #include <linux/slab.h> 13 #include <linux/sysfs.h> 14 #include <linux/spi/spi.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/err.h> 17 #include <linux/sched.h> 18 #include <linux/delay.h> 19 #include <linux/of.h> 20 21 #include <linux/iio/iio.h> 22 #include <linux/iio/sysfs.h> 23 #include <linux/iio/buffer.h> 24 #include <linux/iio/trigger.h> 25 #include <linux/iio/trigger_consumer.h> 26 #include <linux/iio/triggered_buffer.h> 27 #include <linux/iio/adc/ad_sigma_delta.h> 28 29 /* Registers */ 30 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */ 31 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */ 32 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */ 33 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */ 34 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */ 35 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */ 36 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */ 37 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */ 38 /* (AD7792)/24-bit (AD7192)) */ 39 #define AD7192_REG_FULLSALE 7 /* Full-Scale Register */ 40 /* (RW, 16-bit (AD7792)/24-bit (AD7192)) */ 41 42 /* Communications Register Bit Designations (AD7192_REG_COMM) */ 43 #define AD7192_COMM_WEN BIT(7) /* Write Enable */ 44 #define AD7192_COMM_WRITE 0 /* Write Operation */ 45 #define AD7192_COMM_READ BIT(6) /* Read Operation */ 46 #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */ 47 #define AD7192_COMM_CREAD BIT(2) /* Continuous Read of Data Register */ 48 49 /* Status Register Bit Designations (AD7192_REG_STAT) */ 50 #define AD7192_STAT_RDY BIT(7) /* Ready */ 51 #define AD7192_STAT_ERR BIT(6) /* Error (Overrange, Underrange) */ 52 #define AD7192_STAT_NOREF BIT(5) /* Error no external reference */ 53 #define AD7192_STAT_PARITY BIT(4) /* Parity */ 54 #define AD7192_STAT_CH3 BIT(2) /* Channel 3 */ 55 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */ 56 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */ 57 58 /* Mode Register Bit Designations (AD7192_REG_MODE) */ 59 #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */ 60 #define AD7192_MODE_SEL_MASK (0x7 << 21) /* Operation Mode Select Mask */ 61 #define AD7192_MODE_STA(x) (((x) & 0x1) << 20) /* Status Register transmission */ 62 #define AD7192_MODE_STA_MASK BIT(20) /* Status Register transmission Mask */ 63 #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */ 64 #define AD7192_MODE_SINC3 BIT(15) /* SINC3 Filter Select */ 65 #define AD7192_MODE_ENPAR BIT(13) /* Parity Enable */ 66 #define AD7192_MODE_CLKDIV BIT(12) /* Clock divide by 2 (AD7190/2 only)*/ 67 #define AD7192_MODE_SCYCLE BIT(11) /* Single cycle conversion */ 68 #define AD7192_MODE_REJ60 BIT(10) /* 50/60Hz notch filter */ 69 #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */ 70 71 /* Mode Register: AD7192_MODE_SEL options */ 72 #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */ 73 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */ 74 #define AD7192_MODE_IDLE 2 /* Idle Mode */ 75 #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */ 76 #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */ 77 #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */ 78 #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */ 79 #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */ 80 81 /* Mode Register: AD7192_MODE_CLKSRC options */ 82 #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected*/ 83 /* from MCLK1 to MCLK2 */ 84 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */ 85 #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not */ 86 /* available at the MCLK2 pin */ 87 #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available*/ 88 /* at the MCLK2 pin */ 89 90 /* Configuration Register Bit Designations (AD7192_REG_CONF) */ 91 92 #define AD7192_CONF_CHOP BIT(23) /* CHOP enable */ 93 #define AD7192_CONF_ACX BIT(22) /* AC excitation enable(AD7195 only) */ 94 #define AD7192_CONF_REFSEL BIT(20) /* REFIN1/REFIN2 Reference Select */ 95 #define AD7192_CONF_CHAN(x) ((x) << 8) /* Channel select */ 96 #define AD7192_CONF_CHAN_MASK (0x7FF << 8) /* Channel select mask */ 97 #define AD7192_CONF_BURN BIT(7) /* Burnout current enable */ 98 #define AD7192_CONF_REFDET BIT(6) /* Reference detect enable */ 99 #define AD7192_CONF_BUF BIT(4) /* Buffered Mode Enable */ 100 #define AD7192_CONF_UNIPOLAR BIT(3) /* Unipolar/Bipolar Enable */ 101 #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */ 102 103 #define AD7192_CH_AIN1P_AIN2M BIT(0) /* AIN1(+) - AIN2(-) */ 104 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */ 105 #define AD7192_CH_TEMP BIT(2) /* Temp Sensor */ 106 #define AD7192_CH_AIN2P_AIN2M BIT(3) /* AIN2(+) - AIN2(-) */ 107 #define AD7192_CH_AIN1 BIT(4) /* AIN1 - AINCOM */ 108 #define AD7192_CH_AIN2 BIT(5) /* AIN2 - AINCOM */ 109 #define AD7192_CH_AIN3 BIT(6) /* AIN3 - AINCOM */ 110 #define AD7192_CH_AIN4 BIT(7) /* AIN4 - AINCOM */ 111 112 #define AD7193_CH_AIN1P_AIN2M 0x001 /* AIN1(+) - AIN2(-) */ 113 #define AD7193_CH_AIN3P_AIN4M 0x002 /* AIN3(+) - AIN4(-) */ 114 #define AD7193_CH_AIN5P_AIN6M 0x004 /* AIN5(+) - AIN6(-) */ 115 #define AD7193_CH_AIN7P_AIN8M 0x008 /* AIN7(+) - AIN8(-) */ 116 #define AD7193_CH_TEMP 0x100 /* Temp senseor */ 117 #define AD7193_CH_AIN2P_AIN2M 0x200 /* AIN2(+) - AIN2(-) */ 118 #define AD7193_CH_AIN1 0x401 /* AIN1 - AINCOM */ 119 #define AD7193_CH_AIN2 0x402 /* AIN2 - AINCOM */ 120 #define AD7193_CH_AIN3 0x404 /* AIN3 - AINCOM */ 121 #define AD7193_CH_AIN4 0x408 /* AIN4 - AINCOM */ 122 #define AD7193_CH_AIN5 0x410 /* AIN5 - AINCOM */ 123 #define AD7193_CH_AIN6 0x420 /* AIN6 - AINCOM */ 124 #define AD7193_CH_AIN7 0x440 /* AIN7 - AINCOM */ 125 #define AD7193_CH_AIN8 0x480 /* AIN7 - AINCOM */ 126 #define AD7193_CH_AINCOM 0x600 /* AINCOM - AINCOM */ 127 128 /* ID Register Bit Designations (AD7192_REG_ID) */ 129 #define CHIPID_AD7190 0x4 130 #define CHIPID_AD7192 0x0 131 #define CHIPID_AD7193 0x2 132 #define CHIPID_AD7195 0x6 133 #define AD7192_ID_MASK 0x0F 134 135 /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */ 136 #define AD7192_GPOCON_BPDSW BIT(6) /* Bridge power-down switch enable */ 137 #define AD7192_GPOCON_GP32EN BIT(5) /* Digital Output P3 and P2 enable */ 138 #define AD7192_GPOCON_GP10EN BIT(4) /* Digital Output P1 and P0 enable */ 139 #define AD7192_GPOCON_P3DAT BIT(3) /* P3 state */ 140 #define AD7192_GPOCON_P2DAT BIT(2) /* P2 state */ 141 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */ 142 #define AD7192_GPOCON_P0DAT BIT(0) /* P0 state */ 143 144 #define AD7192_EXT_FREQ_MHZ_MIN 2457600 145 #define AD7192_EXT_FREQ_MHZ_MAX 5120000 146 #define AD7192_INT_FREQ_MHZ 4915200 147 148 #define AD7192_NO_SYNC_FILTER 1 149 #define AD7192_SYNC3_FILTER 3 150 #define AD7192_SYNC4_FILTER 4 151 152 /* NOTE: 153 * The AD7190/2/5 features a dual use data out ready DOUT/RDY output. 154 * In order to avoid contentions on the SPI bus, it's therefore necessary 155 * to use spi bus locking. 156 * 157 * The DOUT/RDY output must also be wired to an interrupt capable GPIO. 158 */ 159 160 enum { 161 AD7192_SYSCALIB_ZERO_SCALE, 162 AD7192_SYSCALIB_FULL_SCALE, 163 }; 164 165 enum { 166 ID_AD7190, 167 ID_AD7192, 168 ID_AD7193, 169 ID_AD7195, 170 }; 171 172 struct ad7192_chip_info { 173 unsigned int chip_id; 174 const char *name; 175 }; 176 177 struct ad7192_state { 178 const struct ad7192_chip_info *chip_info; 179 struct regulator *avdd; 180 struct clk *mclk; 181 u16 int_vref_mv; 182 u32 fclk; 183 u32 f_order; 184 u32 mode; 185 u32 conf; 186 u32 scale_avail[8][2]; 187 u8 gpocon; 188 u8 clock_sel; 189 struct mutex lock; /* protect sensor state */ 190 u8 syscalib_mode[8]; 191 192 struct ad_sigma_delta sd; 193 }; 194 195 static const char * const ad7192_syscalib_modes[] = { 196 [AD7192_SYSCALIB_ZERO_SCALE] = "zero_scale", 197 [AD7192_SYSCALIB_FULL_SCALE] = "full_scale", 198 }; 199 200 static int ad7192_set_syscalib_mode(struct iio_dev *indio_dev, 201 const struct iio_chan_spec *chan, 202 unsigned int mode) 203 { 204 struct ad7192_state *st = iio_priv(indio_dev); 205 206 st->syscalib_mode[chan->channel] = mode; 207 208 return 0; 209 } 210 211 static int ad7192_get_syscalib_mode(struct iio_dev *indio_dev, 212 const struct iio_chan_spec *chan) 213 { 214 struct ad7192_state *st = iio_priv(indio_dev); 215 216 return st->syscalib_mode[chan->channel]; 217 } 218 219 static ssize_t ad7192_write_syscalib(struct iio_dev *indio_dev, 220 uintptr_t private, 221 const struct iio_chan_spec *chan, 222 const char *buf, size_t len) 223 { 224 struct ad7192_state *st = iio_priv(indio_dev); 225 bool sys_calib; 226 int ret, temp; 227 228 ret = kstrtobool(buf, &sys_calib); 229 if (ret) 230 return ret; 231 232 temp = st->syscalib_mode[chan->channel]; 233 if (sys_calib) { 234 if (temp == AD7192_SYSCALIB_ZERO_SCALE) 235 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO, 236 chan->address); 237 else 238 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL, 239 chan->address); 240 } 241 242 return ret ? ret : len; 243 } 244 245 static const struct iio_enum ad7192_syscalib_mode_enum = { 246 .items = ad7192_syscalib_modes, 247 .num_items = ARRAY_SIZE(ad7192_syscalib_modes), 248 .set = ad7192_set_syscalib_mode, 249 .get = ad7192_get_syscalib_mode 250 }; 251 252 static const struct iio_chan_spec_ext_info ad7192_calibsys_ext_info[] = { 253 { 254 .name = "sys_calibration", 255 .write = ad7192_write_syscalib, 256 .shared = IIO_SEPARATE, 257 }, 258 IIO_ENUM("sys_calibration_mode", IIO_SEPARATE, 259 &ad7192_syscalib_mode_enum), 260 IIO_ENUM_AVAILABLE("sys_calibration_mode", IIO_SHARED_BY_TYPE, 261 &ad7192_syscalib_mode_enum), 262 {} 263 }; 264 265 static struct ad7192_state *ad_sigma_delta_to_ad7192(struct ad_sigma_delta *sd) 266 { 267 return container_of(sd, struct ad7192_state, sd); 268 } 269 270 static int ad7192_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 271 { 272 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 273 274 st->conf &= ~AD7192_CONF_CHAN_MASK; 275 st->conf |= AD7192_CONF_CHAN(channel); 276 277 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 278 } 279 280 static int ad7192_set_mode(struct ad_sigma_delta *sd, 281 enum ad_sigma_delta_mode mode) 282 { 283 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 284 285 st->mode &= ~AD7192_MODE_SEL_MASK; 286 st->mode |= AD7192_MODE_SEL(mode); 287 288 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 289 } 290 291 static int ad7192_append_status(struct ad_sigma_delta *sd, bool append) 292 { 293 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 294 unsigned int mode = st->mode; 295 int ret; 296 297 mode &= ~AD7192_MODE_STA_MASK; 298 mode |= AD7192_MODE_STA(append); 299 300 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode); 301 if (ret < 0) 302 return ret; 303 304 st->mode = mode; 305 306 return 0; 307 } 308 309 static int ad7192_disable_all(struct ad_sigma_delta *sd) 310 { 311 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); 312 u32 conf = st->conf; 313 int ret; 314 315 conf &= ~AD7192_CONF_CHAN_MASK; 316 317 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); 318 if (ret < 0) 319 return ret; 320 321 st->conf = conf; 322 323 return 0; 324 } 325 326 static const struct ad_sigma_delta_info ad7192_sigma_delta_info = { 327 .set_channel = ad7192_set_channel, 328 .append_status = ad7192_append_status, 329 .disable_all = ad7192_disable_all, 330 .set_mode = ad7192_set_mode, 331 .has_registers = true, 332 .addr_shift = 3, 333 .read_mask = BIT(6), 334 .status_ch_mask = GENMASK(3, 0), 335 .num_slots = 4, 336 .irq_flags = IRQF_TRIGGER_FALLING, 337 }; 338 339 static const struct ad_sd_calib_data ad7192_calib_arr[8] = { 340 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1}, 341 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1}, 342 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2}, 343 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2}, 344 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3}, 345 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3}, 346 {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4}, 347 {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4} 348 }; 349 350 static int ad7192_calibrate_all(struct ad7192_state *st) 351 { 352 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr, 353 ARRAY_SIZE(ad7192_calib_arr)); 354 } 355 356 static inline bool ad7192_valid_external_frequency(u32 freq) 357 { 358 return (freq >= AD7192_EXT_FREQ_MHZ_MIN && 359 freq <= AD7192_EXT_FREQ_MHZ_MAX); 360 } 361 362 static int ad7192_of_clock_select(struct ad7192_state *st) 363 { 364 struct device_node *np = st->sd.spi->dev.of_node; 365 unsigned int clock_sel; 366 367 clock_sel = AD7192_CLK_INT; 368 369 /* use internal clock */ 370 if (!st->mclk) { 371 if (of_property_read_bool(np, "adi,int-clock-output-enable")) 372 clock_sel = AD7192_CLK_INT_CO; 373 } else { 374 if (of_property_read_bool(np, "adi,clock-xtal")) 375 clock_sel = AD7192_CLK_EXT_MCLK1_2; 376 else 377 clock_sel = AD7192_CLK_EXT_MCLK2; 378 } 379 380 return clock_sel; 381 } 382 383 static int ad7192_setup(struct iio_dev *indio_dev, struct device_node *np) 384 { 385 struct ad7192_state *st = iio_priv(indio_dev); 386 bool rej60_en, refin2_en; 387 bool buf_en, bipolar, burnout_curr_en; 388 unsigned long long scale_uv; 389 int i, ret, id; 390 391 /* reset the serial interface */ 392 ret = ad_sd_reset(&st->sd, 48); 393 if (ret < 0) 394 return ret; 395 usleep_range(500, 1000); /* Wait for at least 500us */ 396 397 /* write/read test for device presence */ 398 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id); 399 if (ret) 400 return ret; 401 402 id &= AD7192_ID_MASK; 403 404 if (id != st->chip_info->chip_id) 405 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X != 0x%X)\n", 406 id, st->chip_info->chip_id); 407 408 st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) | 409 AD7192_MODE_CLKSRC(st->clock_sel) | 410 AD7192_MODE_RATE(480); 411 412 st->conf = AD7192_CONF_GAIN(0); 413 414 rej60_en = of_property_read_bool(np, "adi,rejection-60-Hz-enable"); 415 if (rej60_en) 416 st->mode |= AD7192_MODE_REJ60; 417 418 refin2_en = of_property_read_bool(np, "adi,refin2-pins-enable"); 419 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195) 420 st->conf |= AD7192_CONF_REFSEL; 421 422 st->conf &= ~AD7192_CONF_CHOP; 423 st->f_order = AD7192_NO_SYNC_FILTER; 424 425 buf_en = of_property_read_bool(np, "adi,buffer-enable"); 426 if (buf_en) 427 st->conf |= AD7192_CONF_BUF; 428 429 bipolar = of_property_read_bool(np, "bipolar"); 430 if (!bipolar) 431 st->conf |= AD7192_CONF_UNIPOLAR; 432 433 burnout_curr_en = of_property_read_bool(np, 434 "adi,burnout-currents-enable"); 435 if (burnout_curr_en && buf_en) { 436 st->conf |= AD7192_CONF_BURN; 437 } else if (burnout_curr_en) { 438 dev_warn(&st->sd.spi->dev, 439 "Can't enable burnout currents: see CHOP or buffer\n"); 440 } 441 442 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 443 if (ret) 444 return ret; 445 446 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 447 if (ret) 448 return ret; 449 450 ret = ad7192_calibrate_all(st); 451 if (ret) 452 return ret; 453 454 /* Populate available ADC input ranges */ 455 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { 456 scale_uv = ((u64)st->int_vref_mv * 100000000) 457 >> (indio_dev->channels[0].scan_type.realbits - 458 ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1)); 459 scale_uv >>= i; 460 461 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; 462 st->scale_avail[i][0] = scale_uv; 463 } 464 465 return 0; 466 } 467 468 static ssize_t ad7192_show_ac_excitation(struct device *dev, 469 struct device_attribute *attr, 470 char *buf) 471 { 472 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 473 struct ad7192_state *st = iio_priv(indio_dev); 474 475 return sysfs_emit(buf, "%d\n", !!(st->conf & AD7192_CONF_ACX)); 476 } 477 478 static ssize_t ad7192_show_bridge_switch(struct device *dev, 479 struct device_attribute *attr, 480 char *buf) 481 { 482 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 483 struct ad7192_state *st = iio_priv(indio_dev); 484 485 return sysfs_emit(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW)); 486 } 487 488 static ssize_t ad7192_set(struct device *dev, 489 struct device_attribute *attr, 490 const char *buf, 491 size_t len) 492 { 493 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 494 struct ad7192_state *st = iio_priv(indio_dev); 495 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); 496 int ret; 497 bool val; 498 499 ret = kstrtobool(buf, &val); 500 if (ret < 0) 501 return ret; 502 503 ret = iio_device_claim_direct_mode(indio_dev); 504 if (ret) 505 return ret; 506 507 switch ((u32)this_attr->address) { 508 case AD7192_REG_GPOCON: 509 if (val) 510 st->gpocon |= AD7192_GPOCON_BPDSW; 511 else 512 st->gpocon &= ~AD7192_GPOCON_BPDSW; 513 514 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon); 515 break; 516 case AD7192_REG_CONF: 517 if (val) 518 st->conf |= AD7192_CONF_ACX; 519 else 520 st->conf &= ~AD7192_CONF_ACX; 521 522 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 523 break; 524 default: 525 ret = -EINVAL; 526 } 527 528 iio_device_release_direct_mode(indio_dev); 529 530 return ret ? ret : len; 531 } 532 533 static void ad7192_get_available_filter_freq(struct ad7192_state *st, 534 int *freq) 535 { 536 unsigned int fadc; 537 538 /* Formulas for filter at page 25 of the datasheet */ 539 fadc = DIV_ROUND_CLOSEST(st->fclk, 540 AD7192_SYNC4_FILTER * AD7192_MODE_RATE(st->mode)); 541 freq[0] = DIV_ROUND_CLOSEST(fadc * 240, 1024); 542 543 fadc = DIV_ROUND_CLOSEST(st->fclk, 544 AD7192_SYNC3_FILTER * AD7192_MODE_RATE(st->mode)); 545 freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024); 546 547 fadc = DIV_ROUND_CLOSEST(st->fclk, AD7192_MODE_RATE(st->mode)); 548 freq[2] = DIV_ROUND_CLOSEST(fadc * 230, 1024); 549 freq[3] = DIV_ROUND_CLOSEST(fadc * 272, 1024); 550 } 551 552 static ssize_t ad7192_show_filter_avail(struct device *dev, 553 struct device_attribute *attr, 554 char *buf) 555 { 556 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 557 struct ad7192_state *st = iio_priv(indio_dev); 558 unsigned int freq_avail[4], i; 559 size_t len = 0; 560 561 ad7192_get_available_filter_freq(st, freq_avail); 562 563 for (i = 0; i < ARRAY_SIZE(freq_avail); i++) 564 len += sysfs_emit_at(buf, len, "%d.%03d ", freq_avail[i] / 1000, 565 freq_avail[i] % 1000); 566 567 buf[len - 1] = '\n'; 568 569 return len; 570 } 571 572 static IIO_DEVICE_ATTR(filter_low_pass_3db_frequency_available, 573 0444, ad7192_show_filter_avail, NULL, 0); 574 575 static IIO_DEVICE_ATTR(bridge_switch_en, 0644, 576 ad7192_show_bridge_switch, ad7192_set, 577 AD7192_REG_GPOCON); 578 579 static IIO_DEVICE_ATTR(ac_excitation_en, 0644, 580 ad7192_show_ac_excitation, ad7192_set, 581 AD7192_REG_CONF); 582 583 static struct attribute *ad7192_attributes[] = { 584 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr, 585 &iio_dev_attr_bridge_switch_en.dev_attr.attr, 586 NULL 587 }; 588 589 static const struct attribute_group ad7192_attribute_group = { 590 .attrs = ad7192_attributes, 591 }; 592 593 static struct attribute *ad7195_attributes[] = { 594 &iio_dev_attr_filter_low_pass_3db_frequency_available.dev_attr.attr, 595 &iio_dev_attr_bridge_switch_en.dev_attr.attr, 596 &iio_dev_attr_ac_excitation_en.dev_attr.attr, 597 NULL 598 }; 599 600 static const struct attribute_group ad7195_attribute_group = { 601 .attrs = ad7195_attributes, 602 }; 603 604 static unsigned int ad7192_get_temp_scale(bool unipolar) 605 { 606 return unipolar ? 2815 * 2 : 2815; 607 } 608 609 static int ad7192_set_3db_filter_freq(struct ad7192_state *st, 610 int val, int val2) 611 { 612 int freq_avail[4], i, ret, freq; 613 unsigned int diff_new, diff_old; 614 int idx = 0; 615 616 diff_old = U32_MAX; 617 freq = val * 1000 + val2; 618 619 ad7192_get_available_filter_freq(st, freq_avail); 620 621 for (i = 0; i < ARRAY_SIZE(freq_avail); i++) { 622 diff_new = abs(freq - freq_avail[i]); 623 if (diff_new < diff_old) { 624 diff_old = diff_new; 625 idx = i; 626 } 627 } 628 629 switch (idx) { 630 case 0: 631 st->f_order = AD7192_SYNC4_FILTER; 632 st->mode &= ~AD7192_MODE_SINC3; 633 634 st->conf |= AD7192_CONF_CHOP; 635 break; 636 case 1: 637 st->f_order = AD7192_SYNC3_FILTER; 638 st->mode |= AD7192_MODE_SINC3; 639 640 st->conf |= AD7192_CONF_CHOP; 641 break; 642 case 2: 643 st->f_order = AD7192_NO_SYNC_FILTER; 644 st->mode &= ~AD7192_MODE_SINC3; 645 646 st->conf &= ~AD7192_CONF_CHOP; 647 break; 648 case 3: 649 st->f_order = AD7192_NO_SYNC_FILTER; 650 st->mode |= AD7192_MODE_SINC3; 651 652 st->conf &= ~AD7192_CONF_CHOP; 653 break; 654 } 655 656 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 657 if (ret < 0) 658 return ret; 659 660 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); 661 } 662 663 static int ad7192_get_3db_filter_freq(struct ad7192_state *st) 664 { 665 unsigned int fadc; 666 667 fadc = DIV_ROUND_CLOSEST(st->fclk, 668 st->f_order * AD7192_MODE_RATE(st->mode)); 669 670 if (st->conf & AD7192_CONF_CHOP) 671 return DIV_ROUND_CLOSEST(fadc * 240, 1024); 672 if (st->mode & AD7192_MODE_SINC3) 673 return DIV_ROUND_CLOSEST(fadc * 272, 1024); 674 else 675 return DIV_ROUND_CLOSEST(fadc * 230, 1024); 676 } 677 678 static int ad7192_read_raw(struct iio_dev *indio_dev, 679 struct iio_chan_spec const *chan, 680 int *val, 681 int *val2, 682 long m) 683 { 684 struct ad7192_state *st = iio_priv(indio_dev); 685 bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR); 686 687 switch (m) { 688 case IIO_CHAN_INFO_RAW: 689 return ad_sigma_delta_single_conversion(indio_dev, chan, val); 690 case IIO_CHAN_INFO_SCALE: 691 switch (chan->type) { 692 case IIO_VOLTAGE: 693 mutex_lock(&st->lock); 694 *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0]; 695 *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1]; 696 mutex_unlock(&st->lock); 697 return IIO_VAL_INT_PLUS_NANO; 698 case IIO_TEMP: 699 *val = 0; 700 *val2 = 1000000000 / ad7192_get_temp_scale(unipolar); 701 return IIO_VAL_INT_PLUS_NANO; 702 default: 703 return -EINVAL; 704 } 705 case IIO_CHAN_INFO_OFFSET: 706 if (!unipolar) 707 *val = -(1 << (chan->scan_type.realbits - 1)); 708 else 709 *val = 0; 710 /* Kelvin to Celsius */ 711 if (chan->type == IIO_TEMP) 712 *val -= 273 * ad7192_get_temp_scale(unipolar); 713 return IIO_VAL_INT; 714 case IIO_CHAN_INFO_SAMP_FREQ: 715 *val = st->fclk / 716 (st->f_order * 1024 * AD7192_MODE_RATE(st->mode)); 717 return IIO_VAL_INT; 718 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 719 *val = ad7192_get_3db_filter_freq(st); 720 *val2 = 1000; 721 return IIO_VAL_FRACTIONAL; 722 } 723 724 return -EINVAL; 725 } 726 727 static int ad7192_write_raw(struct iio_dev *indio_dev, 728 struct iio_chan_spec const *chan, 729 int val, 730 int val2, 731 long mask) 732 { 733 struct ad7192_state *st = iio_priv(indio_dev); 734 int ret, i, div; 735 unsigned int tmp; 736 737 ret = iio_device_claim_direct_mode(indio_dev); 738 if (ret) 739 return ret; 740 741 switch (mask) { 742 case IIO_CHAN_INFO_SCALE: 743 ret = -EINVAL; 744 mutex_lock(&st->lock); 745 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) 746 if (val2 == st->scale_avail[i][1]) { 747 ret = 0; 748 tmp = st->conf; 749 st->conf &= ~AD7192_CONF_GAIN(-1); 750 st->conf |= AD7192_CONF_GAIN(i); 751 if (tmp == st->conf) 752 break; 753 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 754 3, st->conf); 755 ad7192_calibrate_all(st); 756 break; 757 } 758 mutex_unlock(&st->lock); 759 break; 760 case IIO_CHAN_INFO_SAMP_FREQ: 761 if (!val) { 762 ret = -EINVAL; 763 break; 764 } 765 766 div = st->fclk / (val * st->f_order * 1024); 767 if (div < 1 || div > 1023) { 768 ret = -EINVAL; 769 break; 770 } 771 772 st->mode &= ~AD7192_MODE_RATE(-1); 773 st->mode |= AD7192_MODE_RATE(div); 774 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); 775 break; 776 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 777 ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000); 778 break; 779 default: 780 ret = -EINVAL; 781 } 782 783 iio_device_release_direct_mode(indio_dev); 784 785 return ret; 786 } 787 788 static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev, 789 struct iio_chan_spec const *chan, 790 long mask) 791 { 792 switch (mask) { 793 case IIO_CHAN_INFO_SCALE: 794 return IIO_VAL_INT_PLUS_NANO; 795 case IIO_CHAN_INFO_SAMP_FREQ: 796 return IIO_VAL_INT; 797 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 798 return IIO_VAL_INT_PLUS_MICRO; 799 default: 800 return -EINVAL; 801 } 802 } 803 804 static int ad7192_read_avail(struct iio_dev *indio_dev, 805 struct iio_chan_spec const *chan, 806 const int **vals, int *type, int *length, 807 long mask) 808 { 809 struct ad7192_state *st = iio_priv(indio_dev); 810 811 switch (mask) { 812 case IIO_CHAN_INFO_SCALE: 813 *vals = (int *)st->scale_avail; 814 *type = IIO_VAL_INT_PLUS_NANO; 815 /* Values are stored in a 2D matrix */ 816 *length = ARRAY_SIZE(st->scale_avail) * 2; 817 818 return IIO_AVAIL_LIST; 819 } 820 821 return -EINVAL; 822 } 823 824 static int ad7192_update_scan_mode(struct iio_dev *indio_dev, const unsigned long *scan_mask) 825 { 826 struct ad7192_state *st = iio_priv(indio_dev); 827 u32 conf = st->conf; 828 int ret; 829 int i; 830 831 conf &= ~AD7192_CONF_CHAN_MASK; 832 for_each_set_bit(i, scan_mask, 8) 833 conf |= AD7192_CONF_CHAN(i); 834 835 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); 836 if (ret < 0) 837 return ret; 838 839 st->conf = conf; 840 841 return 0; 842 } 843 844 static const struct iio_info ad7192_info = { 845 .read_raw = ad7192_read_raw, 846 .write_raw = ad7192_write_raw, 847 .write_raw_get_fmt = ad7192_write_raw_get_fmt, 848 .read_avail = ad7192_read_avail, 849 .attrs = &ad7192_attribute_group, 850 .validate_trigger = ad_sd_validate_trigger, 851 .update_scan_mode = ad7192_update_scan_mode, 852 }; 853 854 static const struct iio_info ad7195_info = { 855 .read_raw = ad7192_read_raw, 856 .write_raw = ad7192_write_raw, 857 .write_raw_get_fmt = ad7192_write_raw_get_fmt, 858 .read_avail = ad7192_read_avail, 859 .attrs = &ad7195_attribute_group, 860 .validate_trigger = ad_sd_validate_trigger, 861 .update_scan_mode = ad7192_update_scan_mode, 862 }; 863 864 #define __AD719x_CHANNEL(_si, _channel1, _channel2, _address, _extend_name, \ 865 _type, _mask_type_av, _ext_info) \ 866 { \ 867 .type = (_type), \ 868 .differential = ((_channel2) == -1 ? 0 : 1), \ 869 .indexed = 1, \ 870 .channel = (_channel1), \ 871 .channel2 = (_channel2), \ 872 .address = (_address), \ 873 .extend_name = (_extend_name), \ 874 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 875 BIT(IIO_CHAN_INFO_OFFSET), \ 876 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 877 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 878 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 879 .info_mask_shared_by_type_available = (_mask_type_av), \ 880 .ext_info = (_ext_info), \ 881 .scan_index = (_si), \ 882 .scan_type = { \ 883 .sign = 'u', \ 884 .realbits = 24, \ 885 .storagebits = 32, \ 886 .endianness = IIO_BE, \ 887 }, \ 888 } 889 890 #define AD719x_DIFF_CHANNEL(_si, _channel1, _channel2, _address) \ 891 __AD719x_CHANNEL(_si, _channel1, _channel2, _address, NULL, \ 892 IIO_VOLTAGE, BIT(IIO_CHAN_INFO_SCALE), \ 893 ad7192_calibsys_ext_info) 894 895 #define AD719x_CHANNEL(_si, _channel1, _address) \ 896 __AD719x_CHANNEL(_si, _channel1, -1, _address, NULL, IIO_VOLTAGE, \ 897 BIT(IIO_CHAN_INFO_SCALE), ad7192_calibsys_ext_info) 898 899 #define AD719x_TEMP_CHANNEL(_si, _address) \ 900 __AD719x_CHANNEL(_si, 0, -1, _address, NULL, IIO_TEMP, 0, NULL) 901 902 static const struct iio_chan_spec ad7192_channels[] = { 903 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M), 904 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M), 905 AD719x_TEMP_CHANNEL(2, AD7192_CH_TEMP), 906 AD719x_DIFF_CHANNEL(3, 2, 2, AD7192_CH_AIN2P_AIN2M), 907 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1), 908 AD719x_CHANNEL(5, 2, AD7192_CH_AIN2), 909 AD719x_CHANNEL(6, 3, AD7192_CH_AIN3), 910 AD719x_CHANNEL(7, 4, AD7192_CH_AIN4), 911 IIO_CHAN_SOFT_TIMESTAMP(8), 912 }; 913 914 static const struct iio_chan_spec ad7193_channels[] = { 915 AD719x_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M), 916 AD719x_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M), 917 AD719x_DIFF_CHANNEL(2, 5, 6, AD7193_CH_AIN5P_AIN6M), 918 AD719x_DIFF_CHANNEL(3, 7, 8, AD7193_CH_AIN7P_AIN8M), 919 AD719x_TEMP_CHANNEL(4, AD7193_CH_TEMP), 920 AD719x_DIFF_CHANNEL(5, 2, 2, AD7193_CH_AIN2P_AIN2M), 921 AD719x_CHANNEL(6, 1, AD7193_CH_AIN1), 922 AD719x_CHANNEL(7, 2, AD7193_CH_AIN2), 923 AD719x_CHANNEL(8, 3, AD7193_CH_AIN3), 924 AD719x_CHANNEL(9, 4, AD7193_CH_AIN4), 925 AD719x_CHANNEL(10, 5, AD7193_CH_AIN5), 926 AD719x_CHANNEL(11, 6, AD7193_CH_AIN6), 927 AD719x_CHANNEL(12, 7, AD7193_CH_AIN7), 928 AD719x_CHANNEL(13, 8, AD7193_CH_AIN8), 929 IIO_CHAN_SOFT_TIMESTAMP(14), 930 }; 931 932 static const struct ad7192_chip_info ad7192_chip_info_tbl[] = { 933 [ID_AD7190] = { 934 .chip_id = CHIPID_AD7190, 935 .name = "ad7190", 936 }, 937 [ID_AD7192] = { 938 .chip_id = CHIPID_AD7192, 939 .name = "ad7192", 940 }, 941 [ID_AD7193] = { 942 .chip_id = CHIPID_AD7193, 943 .name = "ad7193", 944 }, 945 [ID_AD7195] = { 946 .chip_id = CHIPID_AD7195, 947 .name = "ad7195", 948 }, 949 }; 950 951 static int ad7192_channels_config(struct iio_dev *indio_dev) 952 { 953 struct ad7192_state *st = iio_priv(indio_dev); 954 955 switch (st->chip_info->chip_id) { 956 case CHIPID_AD7193: 957 indio_dev->channels = ad7193_channels; 958 indio_dev->num_channels = ARRAY_SIZE(ad7193_channels); 959 break; 960 default: 961 indio_dev->channels = ad7192_channels; 962 indio_dev->num_channels = ARRAY_SIZE(ad7192_channels); 963 break; 964 } 965 966 return 0; 967 } 968 969 static void ad7192_reg_disable(void *reg) 970 { 971 regulator_disable(reg); 972 } 973 974 static int ad7192_probe(struct spi_device *spi) 975 { 976 struct ad7192_state *st; 977 struct iio_dev *indio_dev; 978 int ret; 979 980 if (!spi->irq) { 981 dev_err(&spi->dev, "no IRQ?\n"); 982 return -ENODEV; 983 } 984 985 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 986 if (!indio_dev) 987 return -ENOMEM; 988 989 st = iio_priv(indio_dev); 990 991 mutex_init(&st->lock); 992 993 st->avdd = devm_regulator_get(&spi->dev, "avdd"); 994 if (IS_ERR(st->avdd)) 995 return PTR_ERR(st->avdd); 996 997 ret = regulator_enable(st->avdd); 998 if (ret) { 999 dev_err(&spi->dev, "Failed to enable specified AVdd supply\n"); 1000 return ret; 1001 } 1002 1003 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->avdd); 1004 if (ret) 1005 return ret; 1006 1007 ret = devm_regulator_get_enable(&spi->dev, "dvdd"); 1008 if (ret) 1009 return dev_err_probe(&spi->dev, ret, "Failed to enable specified DVdd supply\n"); 1010 1011 ret = regulator_get_voltage(st->avdd); 1012 if (ret < 0) { 1013 dev_err(&spi->dev, "Device tree error, reference voltage undefined\n"); 1014 return ret; 1015 } 1016 st->int_vref_mv = ret / 1000; 1017 1018 st->chip_info = of_device_get_match_data(&spi->dev); 1019 if (!st->chip_info) 1020 st->chip_info = (void *)spi_get_device_id(spi)->driver_data; 1021 indio_dev->name = st->chip_info->name; 1022 indio_dev->modes = INDIO_DIRECT_MODE; 1023 1024 ret = ad7192_channels_config(indio_dev); 1025 if (ret < 0) 1026 return ret; 1027 1028 if (st->chip_info->chip_id == CHIPID_AD7195) 1029 indio_dev->info = &ad7195_info; 1030 else 1031 indio_dev->info = &ad7192_info; 1032 1033 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info); 1034 if (ret) 1035 return ret; 1036 1037 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev); 1038 if (ret) 1039 return ret; 1040 1041 st->fclk = AD7192_INT_FREQ_MHZ; 1042 1043 st->mclk = devm_clk_get_optional_enabled(&spi->dev, "mclk"); 1044 if (IS_ERR(st->mclk)) 1045 return PTR_ERR(st->mclk); 1046 1047 st->clock_sel = ad7192_of_clock_select(st); 1048 1049 if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 || 1050 st->clock_sel == AD7192_CLK_EXT_MCLK2) { 1051 st->fclk = clk_get_rate(st->mclk); 1052 if (!ad7192_valid_external_frequency(st->fclk)) { 1053 dev_err(&spi->dev, 1054 "External clock frequency out of bounds\n"); 1055 return -EINVAL; 1056 } 1057 } 1058 1059 ret = ad7192_setup(indio_dev, spi->dev.of_node); 1060 if (ret) 1061 return ret; 1062 1063 return devm_iio_device_register(&spi->dev, indio_dev); 1064 } 1065 1066 static const struct of_device_id ad7192_of_match[] = { 1067 { .compatible = "adi,ad7190", .data = &ad7192_chip_info_tbl[ID_AD7190] }, 1068 { .compatible = "adi,ad7192", .data = &ad7192_chip_info_tbl[ID_AD7192] }, 1069 { .compatible = "adi,ad7193", .data = &ad7192_chip_info_tbl[ID_AD7193] }, 1070 { .compatible = "adi,ad7195", .data = &ad7192_chip_info_tbl[ID_AD7195] }, 1071 {} 1072 }; 1073 MODULE_DEVICE_TABLE(of, ad7192_of_match); 1074 1075 static const struct spi_device_id ad7192_ids[] = { 1076 { "ad7190", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7190] }, 1077 { "ad7192", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7192] }, 1078 { "ad7193", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7193] }, 1079 { "ad7195", (kernel_ulong_t)&ad7192_chip_info_tbl[ID_AD7195] }, 1080 {} 1081 }; 1082 MODULE_DEVICE_TABLE(spi, ad7192_ids); 1083 1084 static struct spi_driver ad7192_driver = { 1085 .driver = { 1086 .name = "ad7192", 1087 .of_match_table = ad7192_of_match, 1088 }, 1089 .probe = ad7192_probe, 1090 .id_table = ad7192_ids, 1091 }; 1092 module_spi_driver(ad7192_driver); 1093 1094 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>"); 1095 MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7193, AD7195 ADC"); 1096 MODULE_LICENSE("GPL v2"); 1097 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA); 1098