xref: /openbmc/linux/drivers/iio/adc/ad7124.c (revision 715f23b6)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * AD7124 SPI ADC driver
4  *
5  * Copyright 2018 Analog Devices Inc.
6  */
7 #include <linux/bitfield.h>
8 #include <linux/clk.h>
9 #include <linux/delay.h>
10 #include <linux/device.h>
11 #include <linux/err.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/regulator/consumer.h>
15 #include <linux/spi/spi.h>
16 
17 #include <linux/iio/iio.h>
18 #include <linux/iio/adc/ad_sigma_delta.h>
19 #include <linux/iio/sysfs.h>
20 
21 /* AD7124 registers */
22 #define AD7124_COMMS			0x00
23 #define AD7124_STATUS			0x00
24 #define AD7124_ADC_CONTROL		0x01
25 #define AD7124_DATA			0x02
26 #define AD7124_IO_CONTROL_1		0x03
27 #define AD7124_IO_CONTROL_2		0x04
28 #define AD7124_ID			0x05
29 #define AD7124_ERROR			0x06
30 #define AD7124_ERROR_EN		0x07
31 #define AD7124_MCLK_COUNT		0x08
32 #define AD7124_CHANNEL(x)		(0x09 + (x))
33 #define AD7124_CONFIG(x)		(0x19 + (x))
34 #define AD7124_FILTER(x)		(0x21 + (x))
35 #define AD7124_OFFSET(x)		(0x29 + (x))
36 #define AD7124_GAIN(x)			(0x31 + (x))
37 
38 /* AD7124_STATUS */
39 #define AD7124_STATUS_POR_FLAG_MSK	BIT(4)
40 
41 /* AD7124_ADC_CONTROL */
42 #define AD7124_ADC_CTRL_REF_EN_MSK	BIT(8)
43 #define AD7124_ADC_CTRL_REF_EN(x)	FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x)
44 #define AD7124_ADC_CTRL_PWR_MSK	GENMASK(7, 6)
45 #define AD7124_ADC_CTRL_PWR(x)		FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
46 #define AD7124_ADC_CTRL_MODE_MSK	GENMASK(5, 2)
47 #define AD7124_ADC_CTRL_MODE(x)	FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
48 
49 /* AD7124_CHANNEL_X */
50 #define AD7124_CHANNEL_EN_MSK		BIT(15)
51 #define AD7124_CHANNEL_EN(x)		FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
52 #define AD7124_CHANNEL_SETUP_MSK	GENMASK(14, 12)
53 #define AD7124_CHANNEL_SETUP(x)	FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
54 #define AD7124_CHANNEL_AINP_MSK	GENMASK(9, 5)
55 #define AD7124_CHANNEL_AINP(x)		FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
56 #define AD7124_CHANNEL_AINM_MSK	GENMASK(4, 0)
57 #define AD7124_CHANNEL_AINM(x)		FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
58 
59 /* AD7124_CONFIG_X */
60 #define AD7124_CONFIG_BIPOLAR_MSK	BIT(11)
61 #define AD7124_CONFIG_BIPOLAR(x)	FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
62 #define AD7124_CONFIG_REF_SEL_MSK	GENMASK(4, 3)
63 #define AD7124_CONFIG_REF_SEL(x)	FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
64 #define AD7124_CONFIG_PGA_MSK		GENMASK(2, 0)
65 #define AD7124_CONFIG_PGA(x)		FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
66 #define AD7124_CONFIG_IN_BUFF_MSK	GENMASK(7, 6)
67 #define AD7124_CONFIG_IN_BUFF(x)	FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
68 
69 /* AD7124_FILTER_X */
70 #define AD7124_FILTER_FS_MSK		GENMASK(10, 0)
71 #define AD7124_FILTER_FS(x)		FIELD_PREP(AD7124_FILTER_FS_MSK, x)
72 
73 enum ad7124_ids {
74 	ID_AD7124_4,
75 	ID_AD7124_8,
76 };
77 
78 enum ad7124_ref_sel {
79 	AD7124_REFIN1,
80 	AD7124_REFIN2,
81 	AD7124_INT_REF,
82 	AD7124_AVDD_REF,
83 };
84 
85 enum ad7124_power_mode {
86 	AD7124_LOW_POWER,
87 	AD7124_MID_POWER,
88 	AD7124_FULL_POWER,
89 };
90 
91 static const unsigned int ad7124_gain[8] = {
92 	1, 2, 4, 8, 16, 32, 64, 128
93 };
94 
95 static const int ad7124_master_clk_freq_hz[3] = {
96 	[AD7124_LOW_POWER] = 76800,
97 	[AD7124_MID_POWER] = 153600,
98 	[AD7124_FULL_POWER] = 614400,
99 };
100 
101 static const char * const ad7124_ref_names[] = {
102 	[AD7124_REFIN1] = "refin1",
103 	[AD7124_REFIN2] = "refin2",
104 	[AD7124_INT_REF] = "int",
105 	[AD7124_AVDD_REF] = "avdd",
106 };
107 
108 struct ad7124_chip_info {
109 	unsigned int num_inputs;
110 };
111 
112 struct ad7124_channel_config {
113 	enum ad7124_ref_sel refsel;
114 	bool bipolar;
115 	bool buf_positive;
116 	bool buf_negative;
117 	unsigned int ain;
118 	unsigned int vref_mv;
119 	unsigned int pga_bits;
120 	unsigned int odr;
121 };
122 
123 struct ad7124_state {
124 	const struct ad7124_chip_info *chip_info;
125 	struct ad_sigma_delta sd;
126 	struct ad7124_channel_config *channel_config;
127 	struct regulator *vref[4];
128 	struct clk *mclk;
129 	unsigned int adc_control;
130 	unsigned int num_channels;
131 };
132 
133 static const struct iio_chan_spec ad7124_channel_template = {
134 	.type = IIO_VOLTAGE,
135 	.indexed = 1,
136 	.differential = 1,
137 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
138 		BIT(IIO_CHAN_INFO_SCALE) |
139 		BIT(IIO_CHAN_INFO_OFFSET) |
140 		BIT(IIO_CHAN_INFO_SAMP_FREQ),
141 	.scan_type = {
142 		.sign = 'u',
143 		.realbits = 24,
144 		.storagebits = 32,
145 		.shift = 8,
146 		.endianness = IIO_BE,
147 	},
148 };
149 
150 static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
151 	[ID_AD7124_4] = {
152 		.num_inputs = 8,
153 	},
154 	[ID_AD7124_8] = {
155 		.num_inputs = 16,
156 	},
157 };
158 
159 static int ad7124_find_closest_match(const int *array,
160 				     unsigned int size, int val)
161 {
162 	int i, idx;
163 	unsigned int diff_new, diff_old;
164 
165 	diff_old = U32_MAX;
166 	idx = 0;
167 
168 	for (i = 0; i < size; i++) {
169 		diff_new = abs(val - array[i]);
170 		if (diff_new < diff_old) {
171 			diff_old = diff_new;
172 			idx = i;
173 		}
174 	}
175 
176 	return idx;
177 }
178 
179 static int ad7124_spi_write_mask(struct ad7124_state *st,
180 				 unsigned int addr,
181 				 unsigned long mask,
182 				 unsigned int val,
183 				 unsigned int bytes)
184 {
185 	unsigned int readval;
186 	int ret;
187 
188 	ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
189 	if (ret < 0)
190 		return ret;
191 
192 	readval &= ~mask;
193 	readval |= val;
194 
195 	return ad_sd_write_reg(&st->sd, addr, bytes, readval);
196 }
197 
198 static int ad7124_set_mode(struct ad_sigma_delta *sd,
199 			   enum ad_sigma_delta_mode mode)
200 {
201 	struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
202 
203 	st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
204 	st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
205 
206 	return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
207 }
208 
209 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
210 {
211 	struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
212 	unsigned int val;
213 
214 	val = st->channel_config[channel].ain | AD7124_CHANNEL_EN(1) |
215 	      AD7124_CHANNEL_SETUP(channel);
216 
217 	return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(channel), 2, val);
218 }
219 
220 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
221 	.set_channel = ad7124_set_channel,
222 	.set_mode = ad7124_set_mode,
223 	.has_registers = true,
224 	.addr_shift = 0,
225 	.read_mask = BIT(6),
226 	.data_reg = AD7124_DATA,
227 };
228 
229 static int ad7124_set_channel_odr(struct ad7124_state *st,
230 				  unsigned int channel,
231 				  unsigned int odr)
232 {
233 	unsigned int fclk, odr_sel_bits;
234 	int ret;
235 
236 	fclk = clk_get_rate(st->mclk);
237 	/*
238 	 * FS[10:0] = fCLK / (fADC x 32) where:
239 	 * fADC is the output data rate
240 	 * fCLK is the master clock frequency
241 	 * FS[10:0] are the bits in the filter register
242 	 * FS[10:0] can have a value from 1 to 2047
243 	 */
244 	odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
245 	if (odr_sel_bits < 1)
246 		odr_sel_bits = 1;
247 	else if (odr_sel_bits > 2047)
248 		odr_sel_bits = 2047;
249 
250 	ret = ad7124_spi_write_mask(st, AD7124_FILTER(channel),
251 				    AD7124_FILTER_FS_MSK,
252 				    AD7124_FILTER_FS(odr_sel_bits), 3);
253 	if (ret < 0)
254 		return ret;
255 	/* fADC = fCLK / (FS[10:0] x 32) */
256 	st->channel_config[channel].odr =
257 		DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
258 
259 	return 0;
260 }
261 
262 static int ad7124_set_channel_gain(struct ad7124_state *st,
263 				   unsigned int channel,
264 				   unsigned int gain)
265 {
266 	unsigned int res;
267 	int ret;
268 
269 	res = ad7124_find_closest_match(ad7124_gain,
270 					ARRAY_SIZE(ad7124_gain), gain);
271 	ret = ad7124_spi_write_mask(st, AD7124_CONFIG(channel),
272 				    AD7124_CONFIG_PGA_MSK,
273 				    AD7124_CONFIG_PGA(res), 2);
274 	if (ret < 0)
275 		return ret;
276 
277 	st->channel_config[channel].pga_bits = res;
278 
279 	return 0;
280 }
281 
282 static int ad7124_read_raw(struct iio_dev *indio_dev,
283 			   struct iio_chan_spec const *chan,
284 			   int *val, int *val2, long info)
285 {
286 	struct ad7124_state *st = iio_priv(indio_dev);
287 	int idx, ret;
288 
289 	switch (info) {
290 	case IIO_CHAN_INFO_RAW:
291 		ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
292 		if (ret < 0)
293 			return ret;
294 
295 		/* After the conversion is performed, disable the channel */
296 		ret = ad_sd_write_reg(&st->sd,
297 				      AD7124_CHANNEL(chan->address), 2,
298 				      st->channel_config[chan->address].ain |
299 				      AD7124_CHANNEL_EN(0));
300 		if (ret < 0)
301 			return ret;
302 
303 		return IIO_VAL_INT;
304 	case IIO_CHAN_INFO_SCALE:
305 		idx = st->channel_config[chan->address].pga_bits;
306 		*val = st->channel_config[chan->address].vref_mv;
307 		if (st->channel_config[chan->address].bipolar)
308 			*val2 = chan->scan_type.realbits - 1 + idx;
309 		else
310 			*val2 = chan->scan_type.realbits + idx;
311 
312 		return IIO_VAL_FRACTIONAL_LOG2;
313 	case IIO_CHAN_INFO_OFFSET:
314 		if (st->channel_config[chan->address].bipolar)
315 			*val = -(1 << (chan->scan_type.realbits - 1));
316 		else
317 			*val = 0;
318 
319 		return IIO_VAL_INT;
320 	case IIO_CHAN_INFO_SAMP_FREQ:
321 		*val = st->channel_config[chan->address].odr;
322 
323 		return IIO_VAL_INT;
324 	default:
325 		return -EINVAL;
326 	}
327 }
328 
329 static int ad7124_write_raw(struct iio_dev *indio_dev,
330 			    struct iio_chan_spec const *chan,
331 			    int val, int val2, long info)
332 {
333 	struct ad7124_state *st = iio_priv(indio_dev);
334 	unsigned int res, gain, full_scale, vref;
335 
336 	switch (info) {
337 	case IIO_CHAN_INFO_SAMP_FREQ:
338 		if (val2 != 0)
339 			return -EINVAL;
340 
341 		return ad7124_set_channel_odr(st, chan->address, val);
342 	case IIO_CHAN_INFO_SCALE:
343 		if (val != 0)
344 			return -EINVAL;
345 
346 		if (st->channel_config[chan->address].bipolar)
347 			full_scale = 1 << (chan->scan_type.realbits - 1);
348 		else
349 			full_scale = 1 << chan->scan_type.realbits;
350 
351 		vref = st->channel_config[chan->address].vref_mv * 1000000LL;
352 		res = DIV_ROUND_CLOSEST(vref, full_scale);
353 		gain = DIV_ROUND_CLOSEST(res, val2);
354 
355 		return ad7124_set_channel_gain(st, chan->address, gain);
356 	default:
357 		return -EINVAL;
358 	}
359 }
360 
361 static IIO_CONST_ATTR(in_voltage_scale_available,
362 	"0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
363 
364 static struct attribute *ad7124_attributes[] = {
365 	&iio_const_attr_in_voltage_scale_available.dev_attr.attr,
366 	NULL,
367 };
368 
369 static const struct attribute_group ad7124_attrs_group = {
370 	.attrs = ad7124_attributes,
371 };
372 
373 static const struct iio_info ad7124_info = {
374 	.read_raw = ad7124_read_raw,
375 	.write_raw = ad7124_write_raw,
376 	.validate_trigger = ad_sd_validate_trigger,
377 	.attrs = &ad7124_attrs_group,
378 };
379 
380 static int ad7124_soft_reset(struct ad7124_state *st)
381 {
382 	unsigned int readval, timeout;
383 	int ret;
384 
385 	ret = ad_sd_reset(&st->sd, 64);
386 	if (ret < 0)
387 		return ret;
388 
389 	timeout = 100;
390 	do {
391 		ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
392 		if (ret < 0)
393 			return ret;
394 
395 		if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
396 			return 0;
397 
398 		/* The AD7124 requires typically 2ms to power up and settle */
399 		usleep_range(100, 2000);
400 	} while (--timeout);
401 
402 	dev_err(&st->sd.spi->dev, "Soft reset failed\n");
403 
404 	return -EIO;
405 }
406 
407 static int ad7124_init_channel_vref(struct ad7124_state *st,
408 				    unsigned int channel_number)
409 {
410 	unsigned int refsel = st->channel_config[channel_number].refsel;
411 
412 	switch (refsel) {
413 	case AD7124_REFIN1:
414 	case AD7124_REFIN2:
415 	case AD7124_AVDD_REF:
416 		if (IS_ERR(st->vref[refsel])) {
417 			dev_err(&st->sd.spi->dev,
418 				"Error, trying to use external voltage reference without a %s regulator.\n",
419 				ad7124_ref_names[refsel]);
420 			return PTR_ERR(st->vref[refsel]);
421 		}
422 		st->channel_config[channel_number].vref_mv =
423 			regulator_get_voltage(st->vref[refsel]);
424 		/* Conversion from uV to mV */
425 		st->channel_config[channel_number].vref_mv /= 1000;
426 		break;
427 	case AD7124_INT_REF:
428 		st->channel_config[channel_number].vref_mv = 2500;
429 		st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
430 		st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
431 		return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL,
432 				      2, st->adc_control);
433 	default:
434 		dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
435 		return -EINVAL;
436 	}
437 
438 	return 0;
439 }
440 
441 static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev,
442 					  struct device_node *np)
443 {
444 	struct ad7124_state *st = iio_priv(indio_dev);
445 	struct device_node *child;
446 	struct iio_chan_spec *chan;
447 	struct ad7124_channel_config *chan_config;
448 	unsigned int ain[2], channel = 0, tmp;
449 	int ret;
450 
451 	st->num_channels = of_get_available_child_count(np);
452 	if (!st->num_channels) {
453 		dev_err(indio_dev->dev.parent, "no channel children\n");
454 		return -ENODEV;
455 	}
456 
457 	chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
458 			    sizeof(*chan), GFP_KERNEL);
459 	if (!chan)
460 		return -ENOMEM;
461 
462 	chan_config = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
463 				   sizeof(*chan_config), GFP_KERNEL);
464 	if (!chan_config)
465 		return -ENOMEM;
466 
467 	indio_dev->channels = chan;
468 	indio_dev->num_channels = st->num_channels;
469 	st->channel_config = chan_config;
470 
471 	for_each_available_child_of_node(np, child) {
472 		ret = of_property_read_u32(child, "reg", &channel);
473 		if (ret)
474 			goto err;
475 
476 		ret = of_property_read_u32_array(child, "diff-channels",
477 						 ain, 2);
478 		if (ret)
479 			goto err;
480 
481 		st->channel_config[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
482 						  AD7124_CHANNEL_AINM(ain[1]);
483 		st->channel_config[channel].bipolar =
484 			of_property_read_bool(child, "bipolar");
485 
486 		ret = of_property_read_u32(child, "adi,reference-select", &tmp);
487 		if (ret)
488 			st->channel_config[channel].refsel = AD7124_INT_REF;
489 		else
490 			st->channel_config[channel].refsel = tmp;
491 
492 		st->channel_config[channel].buf_positive =
493 			of_property_read_bool(child, "adi,buffered-positive");
494 		st->channel_config[channel].buf_negative =
495 			of_property_read_bool(child, "adi,buffered-negative");
496 
497 		*chan = ad7124_channel_template;
498 		chan->address = channel;
499 		chan->scan_index = channel;
500 		chan->channel = ain[0];
501 		chan->channel2 = ain[1];
502 
503 		chan++;
504 	}
505 
506 	return 0;
507 err:
508 	of_node_put(child);
509 
510 	return ret;
511 }
512 
513 static int ad7124_setup(struct ad7124_state *st)
514 {
515 	unsigned int val, fclk, power_mode;
516 	int i, ret, tmp;
517 
518 	fclk = clk_get_rate(st->mclk);
519 	if (!fclk)
520 		return -EINVAL;
521 
522 	/* The power mode changes the master clock frequency */
523 	power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
524 					ARRAY_SIZE(ad7124_master_clk_freq_hz),
525 					fclk);
526 	if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
527 		ret = clk_set_rate(st->mclk, fclk);
528 		if (ret)
529 			return ret;
530 	}
531 
532 	/* Set the power mode */
533 	st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
534 	st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
535 	ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
536 	if (ret < 0)
537 		return ret;
538 
539 	for (i = 0; i < st->num_channels; i++) {
540 		val = st->channel_config[i].ain | AD7124_CHANNEL_SETUP(i);
541 		ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, val);
542 		if (ret < 0)
543 			return ret;
544 
545 		ret = ad7124_init_channel_vref(st, i);
546 		if (ret < 0)
547 			return ret;
548 
549 		tmp = (st->channel_config[i].buf_positive << 1)  +
550 			st->channel_config[i].buf_negative;
551 
552 		val = AD7124_CONFIG_BIPOLAR(st->channel_config[i].bipolar) |
553 		      AD7124_CONFIG_REF_SEL(st->channel_config[i].refsel) |
554 		      AD7124_CONFIG_IN_BUFF(tmp);
555 		ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(i), 2, val);
556 		if (ret < 0)
557 			return ret;
558 		/*
559 		 * 9.38 SPS is the minimum output data rate supported
560 		 * regardless of the selected power mode. Round it up to 10 and
561 		 * set all the enabled channels to this default value.
562 		 */
563 		ret = ad7124_set_channel_odr(st, i, 10);
564 	}
565 
566 	return ret;
567 }
568 
569 static int ad7124_probe(struct spi_device *spi)
570 {
571 	const struct spi_device_id *id;
572 	struct ad7124_state *st;
573 	struct iio_dev *indio_dev;
574 	int i, ret;
575 
576 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
577 	if (!indio_dev)
578 		return -ENOMEM;
579 
580 	st = iio_priv(indio_dev);
581 
582 	id = spi_get_device_id(spi);
583 	st->chip_info = &ad7124_chip_info_tbl[id->driver_data];
584 
585 	ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
586 
587 	spi_set_drvdata(spi, indio_dev);
588 
589 	indio_dev->dev.parent = &spi->dev;
590 	indio_dev->name = spi_get_device_id(spi)->name;
591 	indio_dev->modes = INDIO_DIRECT_MODE;
592 	indio_dev->info = &ad7124_info;
593 
594 	ret = ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node);
595 	if (ret < 0)
596 		return ret;
597 
598 	for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
599 		if (i == AD7124_INT_REF)
600 			continue;
601 
602 		st->vref[i] = devm_regulator_get_optional(&spi->dev,
603 						ad7124_ref_names[i]);
604 		if (PTR_ERR(st->vref[i]) == -ENODEV)
605 			continue;
606 		else if (IS_ERR(st->vref[i]))
607 			return PTR_ERR(st->vref[i]);
608 
609 		ret = regulator_enable(st->vref[i]);
610 		if (ret)
611 			return ret;
612 	}
613 
614 	st->mclk = devm_clk_get(&spi->dev, "mclk");
615 	if (IS_ERR(st->mclk)) {
616 		ret = PTR_ERR(st->mclk);
617 		goto error_regulator_disable;
618 	}
619 
620 	ret = clk_prepare_enable(st->mclk);
621 	if (ret < 0)
622 		goto error_regulator_disable;
623 
624 	ret = ad7124_soft_reset(st);
625 	if (ret < 0)
626 		goto error_clk_disable_unprepare;
627 
628 	ret = ad7124_setup(st);
629 	if (ret < 0)
630 		goto error_clk_disable_unprepare;
631 
632 	ret = ad_sd_setup_buffer_and_trigger(indio_dev);
633 	if (ret < 0)
634 		goto error_clk_disable_unprepare;
635 
636 	ret = iio_device_register(indio_dev);
637 	if (ret < 0) {
638 		dev_err(&spi->dev, "Failed to register iio device\n");
639 		goto error_remove_trigger;
640 	}
641 
642 	return 0;
643 
644 error_remove_trigger:
645 	ad_sd_cleanup_buffer_and_trigger(indio_dev);
646 error_clk_disable_unprepare:
647 	clk_disable_unprepare(st->mclk);
648 error_regulator_disable:
649 	for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
650 		if (!IS_ERR_OR_NULL(st->vref[i]))
651 			regulator_disable(st->vref[i]);
652 	}
653 
654 	return ret;
655 }
656 
657 static int ad7124_remove(struct spi_device *spi)
658 {
659 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
660 	struct ad7124_state *st = iio_priv(indio_dev);
661 	int i;
662 
663 	iio_device_unregister(indio_dev);
664 	ad_sd_cleanup_buffer_and_trigger(indio_dev);
665 	clk_disable_unprepare(st->mclk);
666 
667 	for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
668 		if (!IS_ERR_OR_NULL(st->vref[i]))
669 			regulator_disable(st->vref[i]);
670 	}
671 
672 	return 0;
673 }
674 
675 static const struct spi_device_id ad7124_id_table[] = {
676 	{ "ad7124-4", ID_AD7124_4 },
677 	{ "ad7124-8", ID_AD7124_8 },
678 	{}
679 };
680 MODULE_DEVICE_TABLE(spi, ad7124_id_table);
681 
682 static const struct of_device_id ad7124_of_match[] = {
683 	{ .compatible = "adi,ad7124-4" },
684 	{ .compatible = "adi,ad7124-8" },
685 	{ },
686 };
687 MODULE_DEVICE_TABLE(of, ad7124_of_match);
688 
689 static struct spi_driver ad71124_driver = {
690 	.driver = {
691 		.name = "ad7124",
692 		.of_match_table = ad7124_of_match,
693 	},
694 	.probe = ad7124_probe,
695 	.remove	= ad7124_remove,
696 	.id_table = ad7124_id_table,
697 };
698 module_spi_driver(ad71124_driver);
699 
700 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
701 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
702 MODULE_LICENSE("GPL");
703