xref: /openbmc/linux/drivers/iio/adc/ad7124.c (revision 710b797c)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * AD7124 SPI ADC driver
4  *
5  * Copyright 2018 Analog Devices Inc.
6  */
7 #include <linux/bitfield.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/device.h>
12 #include <linux/err.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/kfifo.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/spi/spi.h>
20 
21 #include <linux/iio/iio.h>
22 #include <linux/iio/adc/ad_sigma_delta.h>
23 #include <linux/iio/sysfs.h>
24 
25 /* AD7124 registers */
26 #define AD7124_COMMS			0x00
27 #define AD7124_STATUS			0x00
28 #define AD7124_ADC_CONTROL		0x01
29 #define AD7124_DATA			0x02
30 #define AD7124_IO_CONTROL_1		0x03
31 #define AD7124_IO_CONTROL_2		0x04
32 #define AD7124_ID			0x05
33 #define AD7124_ERROR			0x06
34 #define AD7124_ERROR_EN		0x07
35 #define AD7124_MCLK_COUNT		0x08
36 #define AD7124_CHANNEL(x)		(0x09 + (x))
37 #define AD7124_CONFIG(x)		(0x19 + (x))
38 #define AD7124_FILTER(x)		(0x21 + (x))
39 #define AD7124_OFFSET(x)		(0x29 + (x))
40 #define AD7124_GAIN(x)			(0x31 + (x))
41 
42 /* AD7124_STATUS */
43 #define AD7124_STATUS_POR_FLAG_MSK	BIT(4)
44 
45 /* AD7124_ADC_CONTROL */
46 #define AD7124_ADC_CTRL_REF_EN_MSK	BIT(8)
47 #define AD7124_ADC_CTRL_REF_EN(x)	FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x)
48 #define AD7124_ADC_CTRL_PWR_MSK	GENMASK(7, 6)
49 #define AD7124_ADC_CTRL_PWR(x)		FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
50 #define AD7124_ADC_CTRL_MODE_MSK	GENMASK(5, 2)
51 #define AD7124_ADC_CTRL_MODE(x)	FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
52 
53 /* AD7124 ID */
54 #define AD7124_DEVICE_ID_MSK		GENMASK(7, 4)
55 #define AD7124_DEVICE_ID_GET(x)		FIELD_GET(AD7124_DEVICE_ID_MSK, x)
56 #define AD7124_SILICON_REV_MSK		GENMASK(3, 0)
57 #define AD7124_SILICON_REV_GET(x)	FIELD_GET(AD7124_SILICON_REV_MSK, x)
58 
59 #define CHIPID_AD7124_4			0x0
60 #define CHIPID_AD7124_8			0x1
61 
62 /* AD7124_CHANNEL_X */
63 #define AD7124_CHANNEL_EN_MSK		BIT(15)
64 #define AD7124_CHANNEL_EN(x)		FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
65 #define AD7124_CHANNEL_SETUP_MSK	GENMASK(14, 12)
66 #define AD7124_CHANNEL_SETUP(x)	FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
67 #define AD7124_CHANNEL_AINP_MSK	GENMASK(9, 5)
68 #define AD7124_CHANNEL_AINP(x)		FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
69 #define AD7124_CHANNEL_AINM_MSK	GENMASK(4, 0)
70 #define AD7124_CHANNEL_AINM(x)		FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
71 
72 /* AD7124_CONFIG_X */
73 #define AD7124_CONFIG_BIPOLAR_MSK	BIT(11)
74 #define AD7124_CONFIG_BIPOLAR(x)	FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
75 #define AD7124_CONFIG_REF_SEL_MSK	GENMASK(4, 3)
76 #define AD7124_CONFIG_REF_SEL(x)	FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
77 #define AD7124_CONFIG_PGA_MSK		GENMASK(2, 0)
78 #define AD7124_CONFIG_PGA(x)		FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
79 #define AD7124_CONFIG_IN_BUFF_MSK	GENMASK(7, 6)
80 #define AD7124_CONFIG_IN_BUFF(x)	FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
81 
82 /* AD7124_FILTER_X */
83 #define AD7124_FILTER_FS_MSK		GENMASK(10, 0)
84 #define AD7124_FILTER_FS(x)		FIELD_PREP(AD7124_FILTER_FS_MSK, x)
85 #define AD7124_FILTER_TYPE_MSK		GENMASK(23, 21)
86 #define AD7124_FILTER_TYPE_SEL(x)	FIELD_PREP(AD7124_FILTER_TYPE_MSK, x)
87 
88 #define AD7124_SINC3_FILTER 2
89 #define AD7124_SINC4_FILTER 0
90 
91 #define AD7124_CONF_ADDR_OFFSET	20
92 #define AD7124_MAX_CONFIGS	8
93 #define AD7124_MAX_CHANNELS	16
94 
95 enum ad7124_ids {
96 	ID_AD7124_4,
97 	ID_AD7124_8,
98 };
99 
100 enum ad7124_ref_sel {
101 	AD7124_REFIN1,
102 	AD7124_REFIN2,
103 	AD7124_INT_REF,
104 	AD7124_AVDD_REF,
105 };
106 
107 enum ad7124_power_mode {
108 	AD7124_LOW_POWER,
109 	AD7124_MID_POWER,
110 	AD7124_FULL_POWER,
111 };
112 
113 static const unsigned int ad7124_gain[8] = {
114 	1, 2, 4, 8, 16, 32, 64, 128
115 };
116 
117 static const unsigned int ad7124_reg_size[] = {
118 	1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
119 	2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
120 	2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
121 	3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
122 	3, 3, 3, 3, 3
123 };
124 
125 static const int ad7124_master_clk_freq_hz[3] = {
126 	[AD7124_LOW_POWER] = 76800,
127 	[AD7124_MID_POWER] = 153600,
128 	[AD7124_FULL_POWER] = 614400,
129 };
130 
131 static const char * const ad7124_ref_names[] = {
132 	[AD7124_REFIN1] = "refin1",
133 	[AD7124_REFIN2] = "refin2",
134 	[AD7124_INT_REF] = "int",
135 	[AD7124_AVDD_REF] = "avdd",
136 };
137 
138 struct ad7124_chip_info {
139 	const char *name;
140 	unsigned int chip_id;
141 	unsigned int num_inputs;
142 };
143 
144 struct ad7124_channel_config {
145 	bool live;
146 	unsigned int cfg_slot;
147 	enum ad7124_ref_sel refsel;
148 	bool bipolar;
149 	bool buf_positive;
150 	bool buf_negative;
151 	unsigned int vref_mv;
152 	unsigned int pga_bits;
153 	unsigned int odr;
154 	unsigned int odr_sel_bits;
155 	unsigned int filter_type;
156 };
157 
158 struct ad7124_channel {
159 	unsigned int nr;
160 	struct ad7124_channel_config cfg;
161 	unsigned int ain;
162 	unsigned int slot;
163 };
164 
165 struct ad7124_state {
166 	const struct ad7124_chip_info *chip_info;
167 	struct ad_sigma_delta sd;
168 	struct ad7124_channel *channels;
169 	struct regulator *vref[4];
170 	struct clk *mclk;
171 	unsigned int adc_control;
172 	unsigned int num_channels;
173 	struct mutex cfgs_lock; /* lock for configs access */
174 	unsigned long cfg_slots_status; /* bitmap with slot status (1 means it is used) */
175 	DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS);
176 };
177 
178 static const struct iio_chan_spec ad7124_channel_template = {
179 	.type = IIO_VOLTAGE,
180 	.indexed = 1,
181 	.differential = 1,
182 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
183 		BIT(IIO_CHAN_INFO_SCALE) |
184 		BIT(IIO_CHAN_INFO_OFFSET) |
185 		BIT(IIO_CHAN_INFO_SAMP_FREQ) |
186 		BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
187 	.scan_type = {
188 		.sign = 'u',
189 		.realbits = 24,
190 		.storagebits = 32,
191 		.shift = 8,
192 		.endianness = IIO_BE,
193 	},
194 };
195 
196 static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
197 	[ID_AD7124_4] = {
198 		.name = "ad7124-4",
199 		.chip_id = CHIPID_AD7124_4,
200 		.num_inputs = 8,
201 	},
202 	[ID_AD7124_8] = {
203 		.name = "ad7124-8",
204 		.chip_id = CHIPID_AD7124_8,
205 		.num_inputs = 16,
206 	},
207 };
208 
209 static int ad7124_find_closest_match(const int *array,
210 				     unsigned int size, int val)
211 {
212 	int i, idx;
213 	unsigned int diff_new, diff_old;
214 
215 	diff_old = U32_MAX;
216 	idx = 0;
217 
218 	for (i = 0; i < size; i++) {
219 		diff_new = abs(val - array[i]);
220 		if (diff_new < diff_old) {
221 			diff_old = diff_new;
222 			idx = i;
223 		}
224 	}
225 
226 	return idx;
227 }
228 
229 static int ad7124_spi_write_mask(struct ad7124_state *st,
230 				 unsigned int addr,
231 				 unsigned long mask,
232 				 unsigned int val,
233 				 unsigned int bytes)
234 {
235 	unsigned int readval;
236 	int ret;
237 
238 	ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
239 	if (ret < 0)
240 		return ret;
241 
242 	readval &= ~mask;
243 	readval |= val;
244 
245 	return ad_sd_write_reg(&st->sd, addr, bytes, readval);
246 }
247 
248 static int ad7124_set_mode(struct ad_sigma_delta *sd,
249 			   enum ad_sigma_delta_mode mode)
250 {
251 	struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
252 
253 	st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
254 	st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
255 
256 	return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
257 }
258 
259 static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel, unsigned int odr)
260 {
261 	unsigned int fclk, odr_sel_bits;
262 
263 	fclk = clk_get_rate(st->mclk);
264 	/*
265 	 * FS[10:0] = fCLK / (fADC x 32) where:
266 	 * fADC is the output data rate
267 	 * fCLK is the master clock frequency
268 	 * FS[10:0] are the bits in the filter register
269 	 * FS[10:0] can have a value from 1 to 2047
270 	 */
271 	odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
272 	if (odr_sel_bits < 1)
273 		odr_sel_bits = 1;
274 	else if (odr_sel_bits > 2047)
275 		odr_sel_bits = 2047;
276 
277 	if (odr_sel_bits != st->channels[channel].cfg.odr_sel_bits)
278 		st->channels[channel].cfg.live = false;
279 
280 	/* fADC = fCLK / (FS[10:0] x 32) */
281 	st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
282 	st->channels[channel].cfg.odr_sel_bits = odr_sel_bits;
283 }
284 
285 static int ad7124_get_3db_filter_freq(struct ad7124_state *st,
286 				      unsigned int channel)
287 {
288 	unsigned int fadc;
289 
290 	fadc = st->channels[channel].cfg.odr;
291 
292 	switch (st->channels[channel].cfg.filter_type) {
293 	case AD7124_SINC3_FILTER:
294 		return DIV_ROUND_CLOSEST(fadc * 230, 1000);
295 	case AD7124_SINC4_FILTER:
296 		return DIV_ROUND_CLOSEST(fadc * 262, 1000);
297 	default:
298 		return -EINVAL;
299 	}
300 }
301 
302 static void ad7124_set_3db_filter_freq(struct ad7124_state *st, unsigned int channel,
303 				       unsigned int freq)
304 {
305 	unsigned int sinc4_3db_odr;
306 	unsigned int sinc3_3db_odr;
307 	unsigned int new_filter;
308 	unsigned int new_odr;
309 
310 	sinc4_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 230);
311 	sinc3_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 262);
312 
313 	if (sinc4_3db_odr > sinc3_3db_odr) {
314 		new_filter = AD7124_SINC3_FILTER;
315 		new_odr = sinc4_3db_odr;
316 	} else {
317 		new_filter = AD7124_SINC4_FILTER;
318 		new_odr = sinc3_3db_odr;
319 	}
320 
321 	if (new_odr != st->channels[channel].cfg.odr)
322 		st->channels[channel].cfg.live = false;
323 
324 	st->channels[channel].cfg.filter_type = new_filter;
325 	st->channels[channel].cfg.odr = new_odr;
326 }
327 
328 static struct ad7124_channel_config *ad7124_find_similar_live_cfg(struct ad7124_state *st,
329 								  struct ad7124_channel_config *cfg)
330 {
331 	struct ad7124_channel_config *cfg_aux;
332 	ptrdiff_t cmp_size;
333 	int i;
334 
335 	cmp_size = (u8 *)&cfg->live - (u8 *)cfg;
336 	for (i = 0; i < st->num_channels; i++) {
337 		cfg_aux = &st->channels[i].cfg;
338 
339 		if (cfg_aux->live && !memcmp(cfg, cfg_aux, cmp_size))
340 			return cfg_aux;
341 	}
342 
343 	return NULL;
344 }
345 
346 static int ad7124_find_free_config_slot(struct ad7124_state *st)
347 {
348 	unsigned int free_cfg_slot;
349 
350 	free_cfg_slot = find_next_zero_bit(&st->cfg_slots_status, AD7124_MAX_CONFIGS, 0);
351 	if (free_cfg_slot == AD7124_MAX_CONFIGS)
352 		return -1;
353 
354 	return free_cfg_slot;
355 }
356 
357 static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg)
358 {
359 	unsigned int refsel = cfg->refsel;
360 
361 	switch (refsel) {
362 	case AD7124_REFIN1:
363 	case AD7124_REFIN2:
364 	case AD7124_AVDD_REF:
365 		if (IS_ERR(st->vref[refsel])) {
366 			dev_err(&st->sd.spi->dev,
367 				"Error, trying to use external voltage reference without a %s regulator.\n",
368 				ad7124_ref_names[refsel]);
369 			return PTR_ERR(st->vref[refsel]);
370 		}
371 		cfg->vref_mv = regulator_get_voltage(st->vref[refsel]);
372 		/* Conversion from uV to mV */
373 		cfg->vref_mv /= 1000;
374 		return 0;
375 	case AD7124_INT_REF:
376 		cfg->vref_mv = 2500;
377 		st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
378 		st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
379 		return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL,
380 				      2, st->adc_control);
381 	default:
382 		dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
383 		return -EINVAL;
384 	}
385 }
386 
387 static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg,
388 			       unsigned int cfg_slot)
389 {
390 	unsigned int tmp;
391 	unsigned int val;
392 	int ret;
393 
394 	cfg->cfg_slot = cfg_slot;
395 
396 	tmp = (cfg->buf_positive << 1) + cfg->buf_negative;
397 	val = AD7124_CONFIG_BIPOLAR(cfg->bipolar) | AD7124_CONFIG_REF_SEL(cfg->refsel) |
398 	      AD7124_CONFIG_IN_BUFF(tmp);
399 	ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg->cfg_slot), 2, val);
400 	if (ret < 0)
401 		return ret;
402 
403 	tmp = AD7124_FILTER_TYPE_SEL(cfg->filter_type);
404 	ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_TYPE_MSK,
405 				    tmp, 3);
406 	if (ret < 0)
407 		return ret;
408 
409 	ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_FS_MSK,
410 				    AD7124_FILTER_FS(cfg->odr_sel_bits), 3);
411 	if (ret < 0)
412 		return ret;
413 
414 	return ad7124_spi_write_mask(st, AD7124_CONFIG(cfg->cfg_slot), AD7124_CONFIG_PGA_MSK,
415 				     AD7124_CONFIG_PGA(cfg->pga_bits), 2);
416 }
417 
418 static struct ad7124_channel_config *ad7124_pop_config(struct ad7124_state *st)
419 {
420 	struct ad7124_channel_config *lru_cfg;
421 	struct ad7124_channel_config *cfg;
422 	int ret;
423 	int i;
424 
425 	/*
426 	 * Pop least recently used config from the fifo
427 	 * in order to make room for the new one
428 	 */
429 	ret = kfifo_get(&st->live_cfgs_fifo, &lru_cfg);
430 	if (ret <= 0)
431 		return NULL;
432 
433 	lru_cfg->live = false;
434 
435 	/* mark slot as free */
436 	assign_bit(lru_cfg->cfg_slot, &st->cfg_slots_status, 0);
437 
438 	/* invalidate all other configs that pointed to this one */
439 	for (i = 0; i < st->num_channels; i++) {
440 		cfg = &st->channels[i].cfg;
441 
442 		if (cfg->cfg_slot == lru_cfg->cfg_slot)
443 			cfg->live = false;
444 	}
445 
446 	return lru_cfg;
447 }
448 
449 static int ad7124_push_config(struct ad7124_state *st, struct ad7124_channel_config *cfg)
450 {
451 	struct ad7124_channel_config *lru_cfg;
452 	int free_cfg_slot;
453 
454 	free_cfg_slot = ad7124_find_free_config_slot(st);
455 	if (free_cfg_slot >= 0) {
456 		/* push the new config in configs queue */
457 		kfifo_put(&st->live_cfgs_fifo, cfg);
458 	} else {
459 		/* pop one config to make room for the new one */
460 		lru_cfg = ad7124_pop_config(st);
461 		if (!lru_cfg)
462 			return -EINVAL;
463 
464 		/* push the new config in configs queue */
465 		free_cfg_slot = lru_cfg->cfg_slot;
466 		kfifo_put(&st->live_cfgs_fifo, cfg);
467 	}
468 
469 	/* mark slot as used */
470 	assign_bit(free_cfg_slot, &st->cfg_slots_status, 1);
471 
472 	return ad7124_write_config(st, cfg, free_cfg_slot);
473 }
474 
475 static int ad7124_enable_channel(struct ad7124_state *st, struct ad7124_channel *ch)
476 {
477 	ch->cfg.live = true;
478 	return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(ch->nr), 2, ch->ain |
479 			      AD7124_CHANNEL_SETUP(ch->cfg.cfg_slot) | AD7124_CHANNEL_EN(1));
480 }
481 
482 static int ad7124_prepare_read(struct ad7124_state *st, int address)
483 {
484 	struct ad7124_channel_config *cfg = &st->channels[address].cfg;
485 	struct ad7124_channel_config *live_cfg;
486 
487 	/*
488 	 * Before doing any reads assign the channel a configuration.
489 	 * Check if channel's config is on the device
490 	 */
491 	if (!cfg->live) {
492 		/* check if config matches another one */
493 		live_cfg = ad7124_find_similar_live_cfg(st, cfg);
494 		if (!live_cfg)
495 			ad7124_push_config(st, cfg);
496 		else
497 			cfg->cfg_slot = live_cfg->cfg_slot;
498 	}
499 
500 	/* point channel to the config slot and enable */
501 	return ad7124_enable_channel(st, &st->channels[address]);
502 }
503 
504 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
505 {
506 	struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
507 	int ret;
508 
509 	mutex_lock(&st->cfgs_lock);
510 	ret = ad7124_prepare_read(st, channel);
511 	mutex_unlock(&st->cfgs_lock);
512 
513 	return ret;
514 }
515 
516 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
517 	.set_channel = ad7124_set_channel,
518 	.set_mode = ad7124_set_mode,
519 	.has_registers = true,
520 	.addr_shift = 0,
521 	.read_mask = BIT(6),
522 	.data_reg = AD7124_DATA,
523 	.irq_flags = IRQF_TRIGGER_FALLING
524 };
525 
526 static int ad7124_read_raw(struct iio_dev *indio_dev,
527 			   struct iio_chan_spec const *chan,
528 			   int *val, int *val2, long info)
529 {
530 	struct ad7124_state *st = iio_priv(indio_dev);
531 	int idx, ret;
532 
533 	switch (info) {
534 	case IIO_CHAN_INFO_RAW:
535 		ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
536 		if (ret < 0)
537 			return ret;
538 
539 		/* After the conversion is performed, disable the channel */
540 		ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(chan->address), 2,
541 				      st->channels[chan->address].ain | AD7124_CHANNEL_EN(0));
542 		if (ret < 0)
543 			return ret;
544 
545 		return IIO_VAL_INT;
546 	case IIO_CHAN_INFO_SCALE:
547 		mutex_lock(&st->cfgs_lock);
548 
549 		idx = st->channels[chan->address].cfg.pga_bits;
550 		*val = st->channels[chan->address].cfg.vref_mv;
551 		if (st->channels[chan->address].cfg.bipolar)
552 			*val2 = chan->scan_type.realbits - 1 + idx;
553 		else
554 			*val2 = chan->scan_type.realbits + idx;
555 
556 		mutex_unlock(&st->cfgs_lock);
557 		return IIO_VAL_FRACTIONAL_LOG2;
558 	case IIO_CHAN_INFO_OFFSET:
559 		mutex_lock(&st->cfgs_lock);
560 		if (st->channels[chan->address].cfg.bipolar)
561 			*val = -(1 << (chan->scan_type.realbits - 1));
562 		else
563 			*val = 0;
564 
565 		mutex_unlock(&st->cfgs_lock);
566 		return IIO_VAL_INT;
567 	case IIO_CHAN_INFO_SAMP_FREQ:
568 		mutex_lock(&st->cfgs_lock);
569 		*val = st->channels[chan->address].cfg.odr;
570 		mutex_unlock(&st->cfgs_lock);
571 
572 		return IIO_VAL_INT;
573 	case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
574 		mutex_lock(&st->cfgs_lock);
575 		*val = ad7124_get_3db_filter_freq(st, chan->scan_index);
576 		mutex_unlock(&st->cfgs_lock);
577 
578 		return IIO_VAL_INT;
579 	default:
580 		return -EINVAL;
581 	}
582 }
583 
584 static int ad7124_write_raw(struct iio_dev *indio_dev,
585 			    struct iio_chan_spec const *chan,
586 			    int val, int val2, long info)
587 {
588 	struct ad7124_state *st = iio_priv(indio_dev);
589 	unsigned int res, gain, full_scale, vref;
590 	int ret = 0;
591 
592 	mutex_lock(&st->cfgs_lock);
593 
594 	switch (info) {
595 	case IIO_CHAN_INFO_SAMP_FREQ:
596 		if (val2 != 0) {
597 			ret = -EINVAL;
598 			break;
599 		}
600 
601 		ad7124_set_channel_odr(st, chan->address, val);
602 		break;
603 	case IIO_CHAN_INFO_SCALE:
604 		if (val != 0) {
605 			ret = -EINVAL;
606 			break;
607 		}
608 
609 		if (st->channels[chan->address].cfg.bipolar)
610 			full_scale = 1 << (chan->scan_type.realbits - 1);
611 		else
612 			full_scale = 1 << chan->scan_type.realbits;
613 
614 		vref = st->channels[chan->address].cfg.vref_mv * 1000000LL;
615 		res = DIV_ROUND_CLOSEST(vref, full_scale);
616 		gain = DIV_ROUND_CLOSEST(res, val2);
617 		res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain);
618 
619 		if (st->channels[chan->address].cfg.pga_bits != res)
620 			st->channels[chan->address].cfg.live = false;
621 
622 		st->channels[chan->address].cfg.pga_bits = res;
623 		break;
624 	case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
625 		if (val2 != 0) {
626 			ret = -EINVAL;
627 			break;
628 		}
629 
630 		ad7124_set_3db_filter_freq(st, chan->address, val);
631 		break;
632 	default:
633 		ret =  -EINVAL;
634 	}
635 
636 	mutex_unlock(&st->cfgs_lock);
637 	return ret;
638 }
639 
640 static int ad7124_reg_access(struct iio_dev *indio_dev,
641 			     unsigned int reg,
642 			     unsigned int writeval,
643 			     unsigned int *readval)
644 {
645 	struct ad7124_state *st = iio_priv(indio_dev);
646 	int ret;
647 
648 	if (reg >= ARRAY_SIZE(ad7124_reg_size))
649 		return -EINVAL;
650 
651 	if (readval)
652 		ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
653 				     readval);
654 	else
655 		ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
656 				      writeval);
657 
658 	return ret;
659 }
660 
661 static IIO_CONST_ATTR(in_voltage_scale_available,
662 	"0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
663 
664 static struct attribute *ad7124_attributes[] = {
665 	&iio_const_attr_in_voltage_scale_available.dev_attr.attr,
666 	NULL,
667 };
668 
669 static const struct attribute_group ad7124_attrs_group = {
670 	.attrs = ad7124_attributes,
671 };
672 
673 static const struct iio_info ad7124_info = {
674 	.read_raw = ad7124_read_raw,
675 	.write_raw = ad7124_write_raw,
676 	.debugfs_reg_access = &ad7124_reg_access,
677 	.validate_trigger = ad_sd_validate_trigger,
678 	.attrs = &ad7124_attrs_group,
679 };
680 
681 static int ad7124_soft_reset(struct ad7124_state *st)
682 {
683 	unsigned int readval, timeout;
684 	int ret;
685 
686 	ret = ad_sd_reset(&st->sd, 64);
687 	if (ret < 0)
688 		return ret;
689 
690 	timeout = 100;
691 	do {
692 		ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
693 		if (ret < 0)
694 			return ret;
695 
696 		if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
697 			return 0;
698 
699 		/* The AD7124 requires typically 2ms to power up and settle */
700 		usleep_range(100, 2000);
701 	} while (--timeout);
702 
703 	dev_err(&st->sd.spi->dev, "Soft reset failed\n");
704 
705 	return -EIO;
706 }
707 
708 static int ad7124_check_chip_id(struct ad7124_state *st)
709 {
710 	unsigned int readval, chip_id, silicon_rev;
711 	int ret;
712 
713 	ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval);
714 	if (ret < 0)
715 		return ret;
716 
717 	chip_id = AD7124_DEVICE_ID_GET(readval);
718 	silicon_rev = AD7124_SILICON_REV_GET(readval);
719 
720 	if (chip_id != st->chip_info->chip_id) {
721 		dev_err(&st->sd.spi->dev,
722 			"Chip ID mismatch: expected %u, got %u\n",
723 			st->chip_info->chip_id, chip_id);
724 		return -ENODEV;
725 	}
726 
727 	if (silicon_rev == 0) {
728 		dev_err(&st->sd.spi->dev,
729 			"Silicon revision empty. Chip may not be present\n");
730 		return -ENODEV;
731 	}
732 
733 	return 0;
734 }
735 
736 static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev,
737 					  struct device_node *np)
738 {
739 	struct ad7124_state *st = iio_priv(indio_dev);
740 	struct ad7124_channel_config *cfg;
741 	struct ad7124_channel *channels;
742 	struct device_node *child;
743 	struct iio_chan_spec *chan;
744 	unsigned int ain[2], channel = 0, tmp;
745 	int ret;
746 
747 	st->num_channels = of_get_available_child_count(np);
748 	if (!st->num_channels) {
749 		dev_err(indio_dev->dev.parent, "no channel children\n");
750 		return -ENODEV;
751 	}
752 
753 	chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
754 			    sizeof(*chan), GFP_KERNEL);
755 	if (!chan)
756 		return -ENOMEM;
757 
758 	channels = devm_kcalloc(indio_dev->dev.parent, st->num_channels, sizeof(*channels),
759 				GFP_KERNEL);
760 	if (!channels)
761 		return -ENOMEM;
762 
763 	indio_dev->channels = chan;
764 	indio_dev->num_channels = st->num_channels;
765 	st->channels = channels;
766 
767 	for_each_available_child_of_node(np, child) {
768 		cfg = &st->channels[channel].cfg;
769 
770 		ret = of_property_read_u32(child, "reg", &channel);
771 		if (ret)
772 			goto err;
773 
774 		ret = of_property_read_u32_array(child, "diff-channels",
775 						 ain, 2);
776 		if (ret)
777 			goto err;
778 
779 		st->channels[channel].nr = channel;
780 		st->channels[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
781 						  AD7124_CHANNEL_AINM(ain[1]);
782 
783 		cfg->bipolar = of_property_read_bool(child, "bipolar");
784 
785 		ret = of_property_read_u32(child, "adi,reference-select", &tmp);
786 		if (ret)
787 			cfg->refsel = AD7124_INT_REF;
788 		else
789 			cfg->refsel = tmp;
790 
791 		cfg->buf_positive = of_property_read_bool(child, "adi,buffered-positive");
792 		cfg->buf_negative = of_property_read_bool(child, "adi,buffered-negative");
793 
794 		chan[channel] = ad7124_channel_template;
795 		chan[channel].address = channel;
796 		chan[channel].scan_index = channel;
797 		chan[channel].channel = ain[0];
798 		chan[channel].channel2 = ain[1];
799 	}
800 
801 	return 0;
802 err:
803 	of_node_put(child);
804 
805 	return ret;
806 }
807 
808 static int ad7124_setup(struct ad7124_state *st)
809 {
810 	unsigned int fclk, power_mode;
811 	int i, ret;
812 
813 	fclk = clk_get_rate(st->mclk);
814 	if (!fclk)
815 		return -EINVAL;
816 
817 	/* The power mode changes the master clock frequency */
818 	power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
819 					ARRAY_SIZE(ad7124_master_clk_freq_hz),
820 					fclk);
821 	if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
822 		ret = clk_set_rate(st->mclk, fclk);
823 		if (ret)
824 			return ret;
825 	}
826 
827 	/* Set the power mode */
828 	st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
829 	st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
830 	ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
831 	if (ret < 0)
832 		return ret;
833 
834 	mutex_init(&st->cfgs_lock);
835 	INIT_KFIFO(st->live_cfgs_fifo);
836 	for (i = 0; i < st->num_channels; i++) {
837 
838 		ret = ad7124_init_config_vref(st, &st->channels[i].cfg);
839 		if (ret < 0)
840 			return ret;
841 
842 		/*
843 		 * 9.38 SPS is the minimum output data rate supported
844 		 * regardless of the selected power mode. Round it up to 10 and
845 		 * set all channels to this default value.
846 		 */
847 		ad7124_set_channel_odr(st, i, 10);
848 	}
849 
850 	return ret;
851 }
852 
853 static int ad7124_probe(struct spi_device *spi)
854 {
855 	const struct ad7124_chip_info *info;
856 	struct ad7124_state *st;
857 	struct iio_dev *indio_dev;
858 	int i, ret;
859 
860 	info = of_device_get_match_data(&spi->dev);
861 	if (!info)
862 		return -ENODEV;
863 
864 	indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
865 	if (!indio_dev)
866 		return -ENOMEM;
867 
868 	st = iio_priv(indio_dev);
869 
870 	st->chip_info = info;
871 
872 	ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
873 
874 	spi_set_drvdata(spi, indio_dev);
875 
876 	indio_dev->name = st->chip_info->name;
877 	indio_dev->modes = INDIO_DIRECT_MODE;
878 	indio_dev->info = &ad7124_info;
879 
880 	ret = ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node);
881 	if (ret < 0)
882 		return ret;
883 
884 	for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
885 		if (i == AD7124_INT_REF)
886 			continue;
887 
888 		st->vref[i] = devm_regulator_get_optional(&spi->dev,
889 						ad7124_ref_names[i]);
890 		if (PTR_ERR(st->vref[i]) == -ENODEV)
891 			continue;
892 		else if (IS_ERR(st->vref[i]))
893 			return PTR_ERR(st->vref[i]);
894 
895 		ret = regulator_enable(st->vref[i]);
896 		if (ret)
897 			return ret;
898 	}
899 
900 	st->mclk = devm_clk_get(&spi->dev, "mclk");
901 	if (IS_ERR(st->mclk)) {
902 		ret = PTR_ERR(st->mclk);
903 		goto error_regulator_disable;
904 	}
905 
906 	ret = clk_prepare_enable(st->mclk);
907 	if (ret < 0)
908 		goto error_regulator_disable;
909 
910 	ret = ad7124_soft_reset(st);
911 	if (ret < 0)
912 		goto error_clk_disable_unprepare;
913 
914 	ret = ad7124_check_chip_id(st);
915 	if (ret)
916 		goto error_clk_disable_unprepare;
917 
918 	ret = ad7124_setup(st);
919 	if (ret < 0)
920 		goto error_clk_disable_unprepare;
921 
922 	ret = ad_sd_setup_buffer_and_trigger(indio_dev);
923 	if (ret < 0)
924 		goto error_clk_disable_unprepare;
925 
926 	ret = iio_device_register(indio_dev);
927 	if (ret < 0) {
928 		dev_err(&spi->dev, "Failed to register iio device\n");
929 		goto error_remove_trigger;
930 	}
931 
932 	return 0;
933 
934 error_remove_trigger:
935 	ad_sd_cleanup_buffer_and_trigger(indio_dev);
936 error_clk_disable_unprepare:
937 	clk_disable_unprepare(st->mclk);
938 error_regulator_disable:
939 	for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
940 		if (!IS_ERR_OR_NULL(st->vref[i]))
941 			regulator_disable(st->vref[i]);
942 	}
943 
944 	return ret;
945 }
946 
947 static int ad7124_remove(struct spi_device *spi)
948 {
949 	struct iio_dev *indio_dev = spi_get_drvdata(spi);
950 	struct ad7124_state *st = iio_priv(indio_dev);
951 	int i;
952 
953 	iio_device_unregister(indio_dev);
954 	ad_sd_cleanup_buffer_and_trigger(indio_dev);
955 	clk_disable_unprepare(st->mclk);
956 
957 	for (i = ARRAY_SIZE(st->vref) - 1; i >= 0; i--) {
958 		if (!IS_ERR_OR_NULL(st->vref[i]))
959 			regulator_disable(st->vref[i]);
960 	}
961 
962 	return 0;
963 }
964 
965 static const struct of_device_id ad7124_of_match[] = {
966 	{ .compatible = "adi,ad7124-4",
967 		.data = &ad7124_chip_info_tbl[ID_AD7124_4], },
968 	{ .compatible = "adi,ad7124-8",
969 		.data = &ad7124_chip_info_tbl[ID_AD7124_8], },
970 	{ },
971 };
972 MODULE_DEVICE_TABLE(of, ad7124_of_match);
973 
974 static struct spi_driver ad71124_driver = {
975 	.driver = {
976 		.name = "ad7124",
977 		.of_match_table = ad7124_of_match,
978 	},
979 	.probe = ad7124_probe,
980 	.remove	= ad7124_remove,
981 };
982 module_spi_driver(ad71124_driver);
983 
984 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
985 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
986 MODULE_LICENSE("GPL");
987