1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * AD7124 SPI ADC driver 4 * 5 * Copyright 2018 Analog Devices Inc. 6 */ 7 #include <linux/bitfield.h> 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/device.h> 12 #include <linux/err.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/kfifo.h> 16 #include <linux/module.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/property.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/spi/spi.h> 21 22 #include <linux/iio/iio.h> 23 #include <linux/iio/adc/ad_sigma_delta.h> 24 #include <linux/iio/sysfs.h> 25 26 /* AD7124 registers */ 27 #define AD7124_COMMS 0x00 28 #define AD7124_STATUS 0x00 29 #define AD7124_ADC_CONTROL 0x01 30 #define AD7124_DATA 0x02 31 #define AD7124_IO_CONTROL_1 0x03 32 #define AD7124_IO_CONTROL_2 0x04 33 #define AD7124_ID 0x05 34 #define AD7124_ERROR 0x06 35 #define AD7124_ERROR_EN 0x07 36 #define AD7124_MCLK_COUNT 0x08 37 #define AD7124_CHANNEL(x) (0x09 + (x)) 38 #define AD7124_CONFIG(x) (0x19 + (x)) 39 #define AD7124_FILTER(x) (0x21 + (x)) 40 #define AD7124_OFFSET(x) (0x29 + (x)) 41 #define AD7124_GAIN(x) (0x31 + (x)) 42 43 /* AD7124_STATUS */ 44 #define AD7124_STATUS_POR_FLAG_MSK BIT(4) 45 46 /* AD7124_ADC_CONTROL */ 47 #define AD7124_ADC_STATUS_EN_MSK BIT(10) 48 #define AD7124_ADC_STATUS_EN(x) FIELD_PREP(AD7124_ADC_STATUS_EN_MSK, x) 49 #define AD7124_ADC_CTRL_REF_EN_MSK BIT(8) 50 #define AD7124_ADC_CTRL_REF_EN(x) FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x) 51 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6) 52 #define AD7124_ADC_CTRL_PWR(x) FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x) 53 #define AD7124_ADC_CTRL_MODE_MSK GENMASK(5, 2) 54 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x) 55 56 /* AD7124 ID */ 57 #define AD7124_DEVICE_ID_MSK GENMASK(7, 4) 58 #define AD7124_DEVICE_ID_GET(x) FIELD_GET(AD7124_DEVICE_ID_MSK, x) 59 #define AD7124_SILICON_REV_MSK GENMASK(3, 0) 60 #define AD7124_SILICON_REV_GET(x) FIELD_GET(AD7124_SILICON_REV_MSK, x) 61 62 #define CHIPID_AD7124_4 0x0 63 #define CHIPID_AD7124_8 0x1 64 65 /* AD7124_CHANNEL_X */ 66 #define AD7124_CHANNEL_EN_MSK BIT(15) 67 #define AD7124_CHANNEL_EN(x) FIELD_PREP(AD7124_CHANNEL_EN_MSK, x) 68 #define AD7124_CHANNEL_SETUP_MSK GENMASK(14, 12) 69 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x) 70 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5) 71 #define AD7124_CHANNEL_AINP(x) FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x) 72 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0) 73 #define AD7124_CHANNEL_AINM(x) FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x) 74 75 /* AD7124_CONFIG_X */ 76 #define AD7124_CONFIG_BIPOLAR_MSK BIT(11) 77 #define AD7124_CONFIG_BIPOLAR(x) FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x) 78 #define AD7124_CONFIG_REF_SEL_MSK GENMASK(4, 3) 79 #define AD7124_CONFIG_REF_SEL(x) FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x) 80 #define AD7124_CONFIG_PGA_MSK GENMASK(2, 0) 81 #define AD7124_CONFIG_PGA(x) FIELD_PREP(AD7124_CONFIG_PGA_MSK, x) 82 #define AD7124_CONFIG_IN_BUFF_MSK GENMASK(6, 5) 83 #define AD7124_CONFIG_IN_BUFF(x) FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x) 84 85 /* AD7124_FILTER_X */ 86 #define AD7124_FILTER_FS_MSK GENMASK(10, 0) 87 #define AD7124_FILTER_FS(x) FIELD_PREP(AD7124_FILTER_FS_MSK, x) 88 #define AD7124_FILTER_TYPE_MSK GENMASK(23, 21) 89 #define AD7124_FILTER_TYPE_SEL(x) FIELD_PREP(AD7124_FILTER_TYPE_MSK, x) 90 91 #define AD7124_SINC3_FILTER 2 92 #define AD7124_SINC4_FILTER 0 93 94 #define AD7124_CONF_ADDR_OFFSET 20 95 #define AD7124_MAX_CONFIGS 8 96 #define AD7124_MAX_CHANNELS 16 97 98 enum ad7124_ids { 99 ID_AD7124_4, 100 ID_AD7124_8, 101 }; 102 103 enum ad7124_ref_sel { 104 AD7124_REFIN1, 105 AD7124_REFIN2, 106 AD7124_INT_REF, 107 AD7124_AVDD_REF, 108 }; 109 110 enum ad7124_power_mode { 111 AD7124_LOW_POWER, 112 AD7124_MID_POWER, 113 AD7124_FULL_POWER, 114 }; 115 116 static const unsigned int ad7124_gain[8] = { 117 1, 2, 4, 8, 16, 32, 64, 128 118 }; 119 120 static const unsigned int ad7124_reg_size[] = { 121 1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2, 122 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 123 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 124 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 125 3, 3, 3, 3, 3 126 }; 127 128 static const int ad7124_master_clk_freq_hz[3] = { 129 [AD7124_LOW_POWER] = 76800, 130 [AD7124_MID_POWER] = 153600, 131 [AD7124_FULL_POWER] = 614400, 132 }; 133 134 static const char * const ad7124_ref_names[] = { 135 [AD7124_REFIN1] = "refin1", 136 [AD7124_REFIN2] = "refin2", 137 [AD7124_INT_REF] = "int", 138 [AD7124_AVDD_REF] = "avdd", 139 }; 140 141 struct ad7124_chip_info { 142 const char *name; 143 unsigned int chip_id; 144 unsigned int num_inputs; 145 }; 146 147 struct ad7124_channel_config { 148 bool live; 149 unsigned int cfg_slot; 150 /* 151 * Following fields are used to compare for equality. If you 152 * make adaptations in it, you most likely also have to adapt 153 * ad7124_find_similar_live_cfg(), too. 154 */ 155 struct_group(config_props, 156 enum ad7124_ref_sel refsel; 157 bool bipolar; 158 bool buf_positive; 159 bool buf_negative; 160 unsigned int vref_mv; 161 unsigned int pga_bits; 162 unsigned int odr; 163 unsigned int odr_sel_bits; 164 unsigned int filter_type; 165 ); 166 }; 167 168 struct ad7124_channel { 169 unsigned int nr; 170 struct ad7124_channel_config cfg; 171 unsigned int ain; 172 unsigned int slot; 173 }; 174 175 struct ad7124_state { 176 const struct ad7124_chip_info *chip_info; 177 struct ad_sigma_delta sd; 178 struct ad7124_channel *channels; 179 struct regulator *vref[4]; 180 struct clk *mclk; 181 unsigned int adc_control; 182 unsigned int num_channels; 183 struct mutex cfgs_lock; /* lock for configs access */ 184 unsigned long cfg_slots_status; /* bitmap with slot status (1 means it is used) */ 185 DECLARE_KFIFO(live_cfgs_fifo, struct ad7124_channel_config *, AD7124_MAX_CONFIGS); 186 }; 187 188 static const struct iio_chan_spec ad7124_channel_template = { 189 .type = IIO_VOLTAGE, 190 .indexed = 1, 191 .differential = 1, 192 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 193 BIT(IIO_CHAN_INFO_SCALE) | 194 BIT(IIO_CHAN_INFO_OFFSET) | 195 BIT(IIO_CHAN_INFO_SAMP_FREQ) | 196 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), 197 .scan_type = { 198 .sign = 'u', 199 .realbits = 24, 200 .storagebits = 32, 201 .endianness = IIO_BE, 202 }, 203 }; 204 205 static struct ad7124_chip_info ad7124_chip_info_tbl[] = { 206 [ID_AD7124_4] = { 207 .name = "ad7124-4", 208 .chip_id = CHIPID_AD7124_4, 209 .num_inputs = 8, 210 }, 211 [ID_AD7124_8] = { 212 .name = "ad7124-8", 213 .chip_id = CHIPID_AD7124_8, 214 .num_inputs = 16, 215 }, 216 }; 217 218 static int ad7124_find_closest_match(const int *array, 219 unsigned int size, int val) 220 { 221 int i, idx; 222 unsigned int diff_new, diff_old; 223 224 diff_old = U32_MAX; 225 idx = 0; 226 227 for (i = 0; i < size; i++) { 228 diff_new = abs(val - array[i]); 229 if (diff_new < diff_old) { 230 diff_old = diff_new; 231 idx = i; 232 } 233 } 234 235 return idx; 236 } 237 238 static int ad7124_spi_write_mask(struct ad7124_state *st, 239 unsigned int addr, 240 unsigned long mask, 241 unsigned int val, 242 unsigned int bytes) 243 { 244 unsigned int readval; 245 int ret; 246 247 ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval); 248 if (ret < 0) 249 return ret; 250 251 readval &= ~mask; 252 readval |= val; 253 254 return ad_sd_write_reg(&st->sd, addr, bytes, readval); 255 } 256 257 static int ad7124_set_mode(struct ad_sigma_delta *sd, 258 enum ad_sigma_delta_mode mode) 259 { 260 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 261 262 st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK; 263 st->adc_control |= AD7124_ADC_CTRL_MODE(mode); 264 265 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control); 266 } 267 268 static void ad7124_set_channel_odr(struct ad7124_state *st, unsigned int channel, unsigned int odr) 269 { 270 unsigned int fclk, odr_sel_bits; 271 272 fclk = clk_get_rate(st->mclk); 273 /* 274 * FS[10:0] = fCLK / (fADC x 32) where: 275 * fADC is the output data rate 276 * fCLK is the master clock frequency 277 * FS[10:0] are the bits in the filter register 278 * FS[10:0] can have a value from 1 to 2047 279 */ 280 odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32); 281 if (odr_sel_bits < 1) 282 odr_sel_bits = 1; 283 else if (odr_sel_bits > 2047) 284 odr_sel_bits = 2047; 285 286 if (odr_sel_bits != st->channels[channel].cfg.odr_sel_bits) 287 st->channels[channel].cfg.live = false; 288 289 /* fADC = fCLK / (FS[10:0] x 32) */ 290 st->channels[channel].cfg.odr = DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32); 291 st->channels[channel].cfg.odr_sel_bits = odr_sel_bits; 292 } 293 294 static int ad7124_get_3db_filter_freq(struct ad7124_state *st, 295 unsigned int channel) 296 { 297 unsigned int fadc; 298 299 fadc = st->channels[channel].cfg.odr; 300 301 switch (st->channels[channel].cfg.filter_type) { 302 case AD7124_SINC3_FILTER: 303 return DIV_ROUND_CLOSEST(fadc * 230, 1000); 304 case AD7124_SINC4_FILTER: 305 return DIV_ROUND_CLOSEST(fadc * 262, 1000); 306 default: 307 return -EINVAL; 308 } 309 } 310 311 static void ad7124_set_3db_filter_freq(struct ad7124_state *st, unsigned int channel, 312 unsigned int freq) 313 { 314 unsigned int sinc4_3db_odr; 315 unsigned int sinc3_3db_odr; 316 unsigned int new_filter; 317 unsigned int new_odr; 318 319 sinc4_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 230); 320 sinc3_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 262); 321 322 if (sinc4_3db_odr > sinc3_3db_odr) { 323 new_filter = AD7124_SINC3_FILTER; 324 new_odr = sinc4_3db_odr; 325 } else { 326 new_filter = AD7124_SINC4_FILTER; 327 new_odr = sinc3_3db_odr; 328 } 329 330 if (new_odr != st->channels[channel].cfg.odr) 331 st->channels[channel].cfg.live = false; 332 333 st->channels[channel].cfg.filter_type = new_filter; 334 st->channels[channel].cfg.odr = new_odr; 335 } 336 337 static struct ad7124_channel_config *ad7124_find_similar_live_cfg(struct ad7124_state *st, 338 struct ad7124_channel_config *cfg) 339 { 340 struct ad7124_channel_config *cfg_aux; 341 int i; 342 343 /* 344 * This is just to make sure that the comparison is adapted after 345 * struct ad7124_channel_config was changed. 346 */ 347 static_assert(sizeof_field(struct ad7124_channel_config, config_props) == 348 sizeof(struct { 349 enum ad7124_ref_sel refsel; 350 bool bipolar; 351 bool buf_positive; 352 bool buf_negative; 353 unsigned int vref_mv; 354 unsigned int pga_bits; 355 unsigned int odr; 356 unsigned int odr_sel_bits; 357 unsigned int filter_type; 358 })); 359 360 for (i = 0; i < st->num_channels; i++) { 361 cfg_aux = &st->channels[i].cfg; 362 363 if (cfg_aux->live && 364 cfg->refsel == cfg_aux->refsel && 365 cfg->bipolar == cfg_aux->bipolar && 366 cfg->buf_positive == cfg_aux->buf_positive && 367 cfg->buf_negative == cfg_aux->buf_negative && 368 cfg->vref_mv == cfg_aux->vref_mv && 369 cfg->pga_bits == cfg_aux->pga_bits && 370 cfg->odr == cfg_aux->odr && 371 cfg->odr_sel_bits == cfg_aux->odr_sel_bits && 372 cfg->filter_type == cfg_aux->filter_type) 373 return cfg_aux; 374 } 375 376 return NULL; 377 } 378 379 static int ad7124_find_free_config_slot(struct ad7124_state *st) 380 { 381 unsigned int free_cfg_slot; 382 383 free_cfg_slot = find_first_zero_bit(&st->cfg_slots_status, AD7124_MAX_CONFIGS); 384 if (free_cfg_slot == AD7124_MAX_CONFIGS) 385 return -1; 386 387 return free_cfg_slot; 388 } 389 390 static int ad7124_init_config_vref(struct ad7124_state *st, struct ad7124_channel_config *cfg) 391 { 392 unsigned int refsel = cfg->refsel; 393 394 switch (refsel) { 395 case AD7124_REFIN1: 396 case AD7124_REFIN2: 397 case AD7124_AVDD_REF: 398 if (IS_ERR(st->vref[refsel])) { 399 dev_err(&st->sd.spi->dev, 400 "Error, trying to use external voltage reference without a %s regulator.\n", 401 ad7124_ref_names[refsel]); 402 return PTR_ERR(st->vref[refsel]); 403 } 404 cfg->vref_mv = regulator_get_voltage(st->vref[refsel]); 405 /* Conversion from uV to mV */ 406 cfg->vref_mv /= 1000; 407 return 0; 408 case AD7124_INT_REF: 409 cfg->vref_mv = 2500; 410 st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK; 411 st->adc_control |= AD7124_ADC_CTRL_REF_EN(1); 412 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 413 2, st->adc_control); 414 default: 415 dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel); 416 return -EINVAL; 417 } 418 } 419 420 static int ad7124_write_config(struct ad7124_state *st, struct ad7124_channel_config *cfg, 421 unsigned int cfg_slot) 422 { 423 unsigned int tmp; 424 unsigned int val; 425 int ret; 426 427 cfg->cfg_slot = cfg_slot; 428 429 tmp = (cfg->buf_positive << 1) + cfg->buf_negative; 430 val = AD7124_CONFIG_BIPOLAR(cfg->bipolar) | AD7124_CONFIG_REF_SEL(cfg->refsel) | 431 AD7124_CONFIG_IN_BUFF(tmp); 432 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(cfg->cfg_slot), 2, val); 433 if (ret < 0) 434 return ret; 435 436 tmp = AD7124_FILTER_TYPE_SEL(cfg->filter_type); 437 ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_TYPE_MSK, 438 tmp, 3); 439 if (ret < 0) 440 return ret; 441 442 ret = ad7124_spi_write_mask(st, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_FS_MSK, 443 AD7124_FILTER_FS(cfg->odr_sel_bits), 3); 444 if (ret < 0) 445 return ret; 446 447 return ad7124_spi_write_mask(st, AD7124_CONFIG(cfg->cfg_slot), AD7124_CONFIG_PGA_MSK, 448 AD7124_CONFIG_PGA(cfg->pga_bits), 2); 449 } 450 451 static struct ad7124_channel_config *ad7124_pop_config(struct ad7124_state *st) 452 { 453 struct ad7124_channel_config *lru_cfg; 454 struct ad7124_channel_config *cfg; 455 int ret; 456 int i; 457 458 /* 459 * Pop least recently used config from the fifo 460 * in order to make room for the new one 461 */ 462 ret = kfifo_get(&st->live_cfgs_fifo, &lru_cfg); 463 if (ret <= 0) 464 return NULL; 465 466 lru_cfg->live = false; 467 468 /* mark slot as free */ 469 assign_bit(lru_cfg->cfg_slot, &st->cfg_slots_status, 0); 470 471 /* invalidate all other configs that pointed to this one */ 472 for (i = 0; i < st->num_channels; i++) { 473 cfg = &st->channels[i].cfg; 474 475 if (cfg->cfg_slot == lru_cfg->cfg_slot) 476 cfg->live = false; 477 } 478 479 return lru_cfg; 480 } 481 482 static int ad7124_push_config(struct ad7124_state *st, struct ad7124_channel_config *cfg) 483 { 484 struct ad7124_channel_config *lru_cfg; 485 int free_cfg_slot; 486 487 free_cfg_slot = ad7124_find_free_config_slot(st); 488 if (free_cfg_slot >= 0) { 489 /* push the new config in configs queue */ 490 kfifo_put(&st->live_cfgs_fifo, cfg); 491 } else { 492 /* pop one config to make room for the new one */ 493 lru_cfg = ad7124_pop_config(st); 494 if (!lru_cfg) 495 return -EINVAL; 496 497 /* push the new config in configs queue */ 498 free_cfg_slot = lru_cfg->cfg_slot; 499 kfifo_put(&st->live_cfgs_fifo, cfg); 500 } 501 502 /* mark slot as used */ 503 assign_bit(free_cfg_slot, &st->cfg_slots_status, 1); 504 505 return ad7124_write_config(st, cfg, free_cfg_slot); 506 } 507 508 static int ad7124_enable_channel(struct ad7124_state *st, struct ad7124_channel *ch) 509 { 510 ch->cfg.live = true; 511 return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(ch->nr), 2, ch->ain | 512 AD7124_CHANNEL_SETUP(ch->cfg.cfg_slot) | AD7124_CHANNEL_EN(1)); 513 } 514 515 static int ad7124_prepare_read(struct ad7124_state *st, int address) 516 { 517 struct ad7124_channel_config *cfg = &st->channels[address].cfg; 518 struct ad7124_channel_config *live_cfg; 519 520 /* 521 * Before doing any reads assign the channel a configuration. 522 * Check if channel's config is on the device 523 */ 524 if (!cfg->live) { 525 /* check if config matches another one */ 526 live_cfg = ad7124_find_similar_live_cfg(st, cfg); 527 if (!live_cfg) 528 ad7124_push_config(st, cfg); 529 else 530 cfg->cfg_slot = live_cfg->cfg_slot; 531 } 532 533 /* point channel to the config slot and enable */ 534 return ad7124_enable_channel(st, &st->channels[address]); 535 } 536 537 static int __ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 538 { 539 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 540 541 return ad7124_prepare_read(st, channel); 542 } 543 544 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel) 545 { 546 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 547 int ret; 548 549 mutex_lock(&st->cfgs_lock); 550 ret = __ad7124_set_channel(sd, channel); 551 mutex_unlock(&st->cfgs_lock); 552 553 return ret; 554 } 555 556 static int ad7124_append_status(struct ad_sigma_delta *sd, bool append) 557 { 558 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 559 unsigned int adc_control = st->adc_control; 560 int ret; 561 562 adc_control &= ~AD7124_ADC_STATUS_EN_MSK; 563 adc_control |= AD7124_ADC_STATUS_EN(append); 564 565 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, adc_control); 566 if (ret < 0) 567 return ret; 568 569 st->adc_control = adc_control; 570 571 return 0; 572 } 573 574 static int ad7124_disable_all(struct ad_sigma_delta *sd) 575 { 576 struct ad7124_state *st = container_of(sd, struct ad7124_state, sd); 577 int ret; 578 int i; 579 580 for (i = 0; i < st->num_channels; i++) { 581 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_EN_MSK, 0, 2); 582 if (ret < 0) 583 return ret; 584 } 585 586 return 0; 587 } 588 589 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = { 590 .set_channel = ad7124_set_channel, 591 .append_status = ad7124_append_status, 592 .disable_all = ad7124_disable_all, 593 .set_mode = ad7124_set_mode, 594 .has_registers = true, 595 .addr_shift = 0, 596 .read_mask = BIT(6), 597 .status_ch_mask = GENMASK(3, 0), 598 .data_reg = AD7124_DATA, 599 .num_slots = 8, 600 .irq_flags = IRQF_TRIGGER_FALLING, 601 }; 602 603 static int ad7124_read_raw(struct iio_dev *indio_dev, 604 struct iio_chan_spec const *chan, 605 int *val, int *val2, long info) 606 { 607 struct ad7124_state *st = iio_priv(indio_dev); 608 int idx, ret; 609 610 switch (info) { 611 case IIO_CHAN_INFO_RAW: 612 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val); 613 if (ret < 0) 614 return ret; 615 616 /* After the conversion is performed, disable the channel */ 617 ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(chan->address), 2, 618 st->channels[chan->address].ain | AD7124_CHANNEL_EN(0)); 619 if (ret < 0) 620 return ret; 621 622 return IIO_VAL_INT; 623 case IIO_CHAN_INFO_SCALE: 624 mutex_lock(&st->cfgs_lock); 625 626 idx = st->channels[chan->address].cfg.pga_bits; 627 *val = st->channels[chan->address].cfg.vref_mv; 628 if (st->channels[chan->address].cfg.bipolar) 629 *val2 = chan->scan_type.realbits - 1 + idx; 630 else 631 *val2 = chan->scan_type.realbits + idx; 632 633 mutex_unlock(&st->cfgs_lock); 634 return IIO_VAL_FRACTIONAL_LOG2; 635 case IIO_CHAN_INFO_OFFSET: 636 mutex_lock(&st->cfgs_lock); 637 if (st->channels[chan->address].cfg.bipolar) 638 *val = -(1 << (chan->scan_type.realbits - 1)); 639 else 640 *val = 0; 641 642 mutex_unlock(&st->cfgs_lock); 643 return IIO_VAL_INT; 644 case IIO_CHAN_INFO_SAMP_FREQ: 645 mutex_lock(&st->cfgs_lock); 646 *val = st->channels[chan->address].cfg.odr; 647 mutex_unlock(&st->cfgs_lock); 648 649 return IIO_VAL_INT; 650 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 651 mutex_lock(&st->cfgs_lock); 652 *val = ad7124_get_3db_filter_freq(st, chan->scan_index); 653 mutex_unlock(&st->cfgs_lock); 654 655 return IIO_VAL_INT; 656 default: 657 return -EINVAL; 658 } 659 } 660 661 static int ad7124_write_raw(struct iio_dev *indio_dev, 662 struct iio_chan_spec const *chan, 663 int val, int val2, long info) 664 { 665 struct ad7124_state *st = iio_priv(indio_dev); 666 unsigned int res, gain, full_scale, vref; 667 int ret = 0; 668 669 mutex_lock(&st->cfgs_lock); 670 671 switch (info) { 672 case IIO_CHAN_INFO_SAMP_FREQ: 673 if (val2 != 0 || val == 0) { 674 ret = -EINVAL; 675 break; 676 } 677 678 ad7124_set_channel_odr(st, chan->address, val); 679 break; 680 case IIO_CHAN_INFO_SCALE: 681 if (val != 0) { 682 ret = -EINVAL; 683 break; 684 } 685 686 if (st->channels[chan->address].cfg.bipolar) 687 full_scale = 1 << (chan->scan_type.realbits - 1); 688 else 689 full_scale = 1 << chan->scan_type.realbits; 690 691 vref = st->channels[chan->address].cfg.vref_mv * 1000000LL; 692 res = DIV_ROUND_CLOSEST(vref, full_scale); 693 gain = DIV_ROUND_CLOSEST(res, val2); 694 res = ad7124_find_closest_match(ad7124_gain, ARRAY_SIZE(ad7124_gain), gain); 695 696 if (st->channels[chan->address].cfg.pga_bits != res) 697 st->channels[chan->address].cfg.live = false; 698 699 st->channels[chan->address].cfg.pga_bits = res; 700 break; 701 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 702 if (val2 != 0) { 703 ret = -EINVAL; 704 break; 705 } 706 707 ad7124_set_3db_filter_freq(st, chan->address, val); 708 break; 709 default: 710 ret = -EINVAL; 711 } 712 713 mutex_unlock(&st->cfgs_lock); 714 return ret; 715 } 716 717 static int ad7124_reg_access(struct iio_dev *indio_dev, 718 unsigned int reg, 719 unsigned int writeval, 720 unsigned int *readval) 721 { 722 struct ad7124_state *st = iio_priv(indio_dev); 723 int ret; 724 725 if (reg >= ARRAY_SIZE(ad7124_reg_size)) 726 return -EINVAL; 727 728 if (readval) 729 ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg], 730 readval); 731 else 732 ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg], 733 writeval); 734 735 return ret; 736 } 737 738 static IIO_CONST_ATTR(in_voltage_scale_available, 739 "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023"); 740 741 static struct attribute *ad7124_attributes[] = { 742 &iio_const_attr_in_voltage_scale_available.dev_attr.attr, 743 NULL, 744 }; 745 746 static const struct attribute_group ad7124_attrs_group = { 747 .attrs = ad7124_attributes, 748 }; 749 750 static int ad7124_update_scan_mode(struct iio_dev *indio_dev, 751 const unsigned long *scan_mask) 752 { 753 struct ad7124_state *st = iio_priv(indio_dev); 754 bool bit_set; 755 int ret; 756 int i; 757 758 mutex_lock(&st->cfgs_lock); 759 for (i = 0; i < st->num_channels; i++) { 760 bit_set = test_bit(i, scan_mask); 761 if (bit_set) 762 ret = __ad7124_set_channel(&st->sd, i); 763 else 764 ret = ad7124_spi_write_mask(st, AD7124_CHANNEL(i), AD7124_CHANNEL_EN_MSK, 765 0, 2); 766 if (ret < 0) { 767 mutex_unlock(&st->cfgs_lock); 768 769 return ret; 770 } 771 } 772 773 mutex_unlock(&st->cfgs_lock); 774 775 return 0; 776 } 777 778 static const struct iio_info ad7124_info = { 779 .read_raw = ad7124_read_raw, 780 .write_raw = ad7124_write_raw, 781 .debugfs_reg_access = &ad7124_reg_access, 782 .validate_trigger = ad_sd_validate_trigger, 783 .update_scan_mode = ad7124_update_scan_mode, 784 .attrs = &ad7124_attrs_group, 785 }; 786 787 static int ad7124_soft_reset(struct ad7124_state *st) 788 { 789 unsigned int readval, timeout; 790 int ret; 791 792 ret = ad_sd_reset(&st->sd, 64); 793 if (ret < 0) 794 return ret; 795 796 fsleep(200); 797 timeout = 100; 798 do { 799 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval); 800 if (ret < 0) 801 return ret; 802 803 if (!(readval & AD7124_STATUS_POR_FLAG_MSK)) 804 return 0; 805 806 /* The AD7124 requires typically 2ms to power up and settle */ 807 usleep_range(100, 2000); 808 } while (--timeout); 809 810 dev_err(&st->sd.spi->dev, "Soft reset failed\n"); 811 812 return -EIO; 813 } 814 815 static int ad7124_check_chip_id(struct ad7124_state *st) 816 { 817 unsigned int readval, chip_id, silicon_rev; 818 int ret; 819 820 ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval); 821 if (ret < 0) 822 return ret; 823 824 chip_id = AD7124_DEVICE_ID_GET(readval); 825 silicon_rev = AD7124_SILICON_REV_GET(readval); 826 827 if (chip_id != st->chip_info->chip_id) { 828 dev_err(&st->sd.spi->dev, 829 "Chip ID mismatch: expected %u, got %u\n", 830 st->chip_info->chip_id, chip_id); 831 return -ENODEV; 832 } 833 834 if (silicon_rev == 0) { 835 dev_err(&st->sd.spi->dev, 836 "Silicon revision empty. Chip may not be present\n"); 837 return -ENODEV; 838 } 839 840 return 0; 841 } 842 843 static int ad7124_parse_channel_config(struct iio_dev *indio_dev, 844 struct device *dev) 845 { 846 struct ad7124_state *st = iio_priv(indio_dev); 847 struct ad7124_channel_config *cfg; 848 struct ad7124_channel *channels; 849 struct iio_chan_spec *chan; 850 unsigned int ain[2], channel = 0, tmp; 851 int ret; 852 853 st->num_channels = device_get_child_node_count(dev); 854 if (!st->num_channels) 855 return dev_err_probe(dev, -ENODEV, "no channel children\n"); 856 857 chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels, 858 sizeof(*chan), GFP_KERNEL); 859 if (!chan) 860 return -ENOMEM; 861 862 channels = devm_kcalloc(indio_dev->dev.parent, st->num_channels, sizeof(*channels), 863 GFP_KERNEL); 864 if (!channels) 865 return -ENOMEM; 866 867 indio_dev->channels = chan; 868 indio_dev->num_channels = st->num_channels; 869 st->channels = channels; 870 871 device_for_each_child_node_scoped(dev, child) { 872 ret = fwnode_property_read_u32(child, "reg", &channel); 873 if (ret) 874 return ret; 875 876 if (channel >= indio_dev->num_channels) 877 return dev_err_probe(dev, -EINVAL, 878 "Channel index >= number of channels\n"); 879 880 ret = fwnode_property_read_u32_array(child, "diff-channels", 881 ain, 2); 882 if (ret) 883 return ret; 884 885 st->channels[channel].nr = channel; 886 st->channels[channel].ain = AD7124_CHANNEL_AINP(ain[0]) | 887 AD7124_CHANNEL_AINM(ain[1]); 888 889 cfg = &st->channels[channel].cfg; 890 cfg->bipolar = fwnode_property_read_bool(child, "bipolar"); 891 892 ret = fwnode_property_read_u32(child, "adi,reference-select", &tmp); 893 if (ret) 894 cfg->refsel = AD7124_INT_REF; 895 else 896 cfg->refsel = tmp; 897 898 cfg->buf_positive = 899 fwnode_property_read_bool(child, "adi,buffered-positive"); 900 cfg->buf_negative = 901 fwnode_property_read_bool(child, "adi,buffered-negative"); 902 903 chan[channel] = ad7124_channel_template; 904 chan[channel].address = channel; 905 chan[channel].scan_index = channel; 906 chan[channel].channel = ain[0]; 907 chan[channel].channel2 = ain[1]; 908 } 909 910 return 0; 911 } 912 913 static int ad7124_setup(struct ad7124_state *st) 914 { 915 unsigned int fclk, power_mode; 916 int i, ret; 917 918 fclk = clk_get_rate(st->mclk); 919 if (!fclk) 920 return -EINVAL; 921 922 /* The power mode changes the master clock frequency */ 923 power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz, 924 ARRAY_SIZE(ad7124_master_clk_freq_hz), 925 fclk); 926 if (fclk != ad7124_master_clk_freq_hz[power_mode]) { 927 ret = clk_set_rate(st->mclk, fclk); 928 if (ret) 929 return ret; 930 } 931 932 /* Set the power mode */ 933 st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK; 934 st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode); 935 ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control); 936 if (ret < 0) 937 return ret; 938 939 mutex_init(&st->cfgs_lock); 940 INIT_KFIFO(st->live_cfgs_fifo); 941 for (i = 0; i < st->num_channels; i++) { 942 943 ret = ad7124_init_config_vref(st, &st->channels[i].cfg); 944 if (ret < 0) 945 return ret; 946 947 /* 948 * 9.38 SPS is the minimum output data rate supported 949 * regardless of the selected power mode. Round it up to 10 and 950 * set all channels to this default value. 951 */ 952 ad7124_set_channel_odr(st, i, 10); 953 954 /* Disable all channels to prevent unintended conversions. */ 955 ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, 0); 956 } 957 958 return ret; 959 } 960 961 static void ad7124_reg_disable(void *r) 962 { 963 regulator_disable(r); 964 } 965 966 static int ad7124_probe(struct spi_device *spi) 967 { 968 const struct ad7124_chip_info *info; 969 struct ad7124_state *st; 970 struct iio_dev *indio_dev; 971 int i, ret; 972 973 info = spi_get_device_match_data(spi); 974 if (!info) 975 return -ENODEV; 976 977 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 978 if (!indio_dev) 979 return -ENOMEM; 980 981 st = iio_priv(indio_dev); 982 983 st->chip_info = info; 984 985 indio_dev->name = st->chip_info->name; 986 indio_dev->modes = INDIO_DIRECT_MODE; 987 indio_dev->info = &ad7124_info; 988 989 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info); 990 if (ret < 0) 991 return ret; 992 993 ret = ad7124_parse_channel_config(indio_dev, &spi->dev); 994 if (ret < 0) 995 return ret; 996 997 for (i = 0; i < ARRAY_SIZE(st->vref); i++) { 998 if (i == AD7124_INT_REF) 999 continue; 1000 1001 st->vref[i] = devm_regulator_get_optional(&spi->dev, 1002 ad7124_ref_names[i]); 1003 if (PTR_ERR(st->vref[i]) == -ENODEV) 1004 continue; 1005 else if (IS_ERR(st->vref[i])) 1006 return PTR_ERR(st->vref[i]); 1007 1008 ret = regulator_enable(st->vref[i]); 1009 if (ret) 1010 return ret; 1011 1012 ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable, 1013 st->vref[i]); 1014 if (ret) 1015 return ret; 1016 } 1017 1018 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk"); 1019 if (IS_ERR(st->mclk)) 1020 return PTR_ERR(st->mclk); 1021 1022 ret = ad7124_soft_reset(st); 1023 if (ret < 0) 1024 return ret; 1025 1026 ret = ad7124_check_chip_id(st); 1027 if (ret) 1028 return ret; 1029 1030 ret = ad7124_setup(st); 1031 if (ret < 0) 1032 return ret; 1033 1034 ret = devm_ad_sd_setup_buffer_and_trigger(&spi->dev, indio_dev); 1035 if (ret < 0) 1036 return ret; 1037 1038 return devm_iio_device_register(&spi->dev, indio_dev); 1039 1040 } 1041 1042 static const struct of_device_id ad7124_of_match[] = { 1043 { .compatible = "adi,ad7124-4", 1044 .data = &ad7124_chip_info_tbl[ID_AD7124_4], }, 1045 { .compatible = "adi,ad7124-8", 1046 .data = &ad7124_chip_info_tbl[ID_AD7124_8], }, 1047 { }, 1048 }; 1049 MODULE_DEVICE_TABLE(of, ad7124_of_match); 1050 1051 static const struct spi_device_id ad71124_ids[] = { 1052 { "ad7124-4", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_4] }, 1053 { "ad7124-8", (kernel_ulong_t)&ad7124_chip_info_tbl[ID_AD7124_8] }, 1054 {} 1055 }; 1056 MODULE_DEVICE_TABLE(spi, ad71124_ids); 1057 1058 static struct spi_driver ad71124_driver = { 1059 .driver = { 1060 .name = "ad7124", 1061 .of_match_table = ad7124_of_match, 1062 }, 1063 .probe = ad7124_probe, 1064 .id_table = ad71124_ids, 1065 }; 1066 module_spi_driver(ad71124_driver); 1067 1068 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>"); 1069 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver"); 1070 MODULE_LICENSE("GPL"); 1071 MODULE_IMPORT_NS(IIO_AD_SIGMA_DELTA); 1072