1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2022 Analog Devices, Inc. 4 * Author: Cosmin Tanislav <cosmin.tanislav@analog.com> 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/clk-provider.h> 11 #include <linux/delay.h> 12 #include <linux/device.h> 13 #include <linux/err.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/interrupt.h> 16 #include <linux/irq.h> 17 #include <linux/kernel.h> 18 #include <linux/module.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/spi/spi.h> 23 #include <linux/units.h> 24 25 #include <asm/div64.h> 26 #include <asm/unaligned.h> 27 28 #include <linux/iio/buffer.h> 29 #include <linux/iio/iio.h> 30 #include <linux/iio/kfifo_buf.h> 31 #include <linux/iio/sysfs.h> 32 33 #define AD4130_NAME "ad4130" 34 35 #define AD4130_COMMS_READ_MASK BIT(6) 36 37 #define AD4130_STATUS_REG 0x00 38 39 #define AD4130_ADC_CONTROL_REG 0x01 40 #define AD4130_ADC_CONTROL_BIPOLAR_MASK BIT(14) 41 #define AD4130_ADC_CONTROL_INT_REF_VAL_MASK BIT(13) 42 #define AD4130_INT_REF_2_5V 2500000 43 #define AD4130_INT_REF_1_25V 1250000 44 #define AD4130_ADC_CONTROL_CSB_EN_MASK BIT(9) 45 #define AD4130_ADC_CONTROL_INT_REF_EN_MASK BIT(8) 46 #define AD4130_ADC_CONTROL_MODE_MASK GENMASK(5, 2) 47 #define AD4130_ADC_CONTROL_MCLK_SEL_MASK GENMASK(1, 0) 48 #define AD4130_MCLK_FREQ_76_8KHZ 76800 49 #define AD4130_MCLK_FREQ_153_6KHZ 153600 50 51 #define AD4130_DATA_REG 0x02 52 53 #define AD4130_IO_CONTROL_REG 0x03 54 #define AD4130_IO_CONTROL_INT_PIN_SEL_MASK GENMASK(9, 8) 55 #define AD4130_IO_CONTROL_GPIO_DATA_MASK GENMASK(7, 4) 56 #define AD4130_IO_CONTROL_GPIO_CTRL_MASK GENMASK(3, 0) 57 58 #define AD4130_VBIAS_REG 0x04 59 60 #define AD4130_ID_REG 0x05 61 62 #define AD4130_ERROR_REG 0x06 63 64 #define AD4130_ERROR_EN_REG 0x07 65 66 #define AD4130_MCLK_COUNT_REG 0x08 67 68 #define AD4130_CHANNEL_X_REG(x) (0x09 + (x)) 69 #define AD4130_CHANNEL_EN_MASK BIT(23) 70 #define AD4130_CHANNEL_SETUP_MASK GENMASK(22, 20) 71 #define AD4130_CHANNEL_AINP_MASK GENMASK(17, 13) 72 #define AD4130_CHANNEL_AINM_MASK GENMASK(12, 8) 73 #define AD4130_CHANNEL_IOUT1_MASK GENMASK(7, 4) 74 #define AD4130_CHANNEL_IOUT2_MASK GENMASK(3, 0) 75 76 #define AD4130_CONFIG_X_REG(x) (0x19 + (x)) 77 #define AD4130_CONFIG_IOUT1_VAL_MASK GENMASK(15, 13) 78 #define AD4130_CONFIG_IOUT2_VAL_MASK GENMASK(12, 10) 79 #define AD4130_CONFIG_BURNOUT_MASK GENMASK(9, 8) 80 #define AD4130_CONFIG_REF_BUFP_MASK BIT(7) 81 #define AD4130_CONFIG_REF_BUFM_MASK BIT(6) 82 #define AD4130_CONFIG_REF_SEL_MASK GENMASK(5, 4) 83 #define AD4130_CONFIG_PGA_MASK GENMASK(3, 1) 84 85 #define AD4130_FILTER_X_REG(x) (0x21 + (x)) 86 #define AD4130_FILTER_MODE_MASK GENMASK(15, 12) 87 #define AD4130_FILTER_SELECT_MASK GENMASK(10, 0) 88 #define AD4130_FILTER_SELECT_MIN 1 89 90 #define AD4130_OFFSET_X_REG(x) (0x29 + (x)) 91 92 #define AD4130_GAIN_X_REG(x) (0x31 + (x)) 93 94 #define AD4130_MISC_REG 0x39 95 96 #define AD4130_FIFO_CONTROL_REG 0x3a 97 #define AD4130_FIFO_CONTROL_HEADER_MASK BIT(18) 98 #define AD4130_FIFO_CONTROL_MODE_MASK GENMASK(17, 16) 99 #define AD4130_FIFO_CONTROL_WM_INT_EN_MASK BIT(9) 100 #define AD4130_FIFO_CONTROL_WM_MASK GENMASK(7, 0) 101 #define AD4130_WATERMARK_256 0 102 103 #define AD4130_FIFO_STATUS_REG 0x3b 104 105 #define AD4130_FIFO_THRESHOLD_REG 0x3c 106 107 #define AD4130_FIFO_DATA_REG 0x3d 108 #define AD4130_FIFO_SIZE 256 109 #define AD4130_FIFO_MAX_SAMPLE_SIZE 3 110 111 #define AD4130_MAX_ANALOG_PINS 16 112 #define AD4130_MAX_CHANNELS 16 113 #define AD4130_MAX_DIFF_INPUTS 30 114 #define AD4130_MAX_GPIOS 4 115 #define AD4130_MAX_ODR 2400 116 #define AD4130_MAX_PGA 8 117 #define AD4130_MAX_SETUPS 8 118 119 #define AD4130_AIN2_P1 0x2 120 #define AD4130_AIN3_P2 0x3 121 122 #define AD4130_RESET_BUF_SIZE 8 123 #define AD4130_RESET_SLEEP_US (160 * MICRO / AD4130_MCLK_FREQ_76_8KHZ) 124 125 #define AD4130_INVALID_SLOT -1 126 127 static const unsigned int ad4130_reg_size[] = { 128 [AD4130_STATUS_REG] = 1, 129 [AD4130_ADC_CONTROL_REG] = 2, 130 [AD4130_DATA_REG] = 3, 131 [AD4130_IO_CONTROL_REG] = 2, 132 [AD4130_VBIAS_REG] = 2, 133 [AD4130_ID_REG] = 1, 134 [AD4130_ERROR_REG] = 2, 135 [AD4130_ERROR_EN_REG] = 2, 136 [AD4130_MCLK_COUNT_REG] = 1, 137 [AD4130_CHANNEL_X_REG(0) ... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1)] = 3, 138 [AD4130_CONFIG_X_REG(0) ... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = 2, 139 [AD4130_FILTER_X_REG(0) ... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = 3, 140 [AD4130_OFFSET_X_REG(0) ... AD4130_OFFSET_X_REG(AD4130_MAX_SETUPS - 1)] = 3, 141 [AD4130_GAIN_X_REG(0) ... AD4130_GAIN_X_REG(AD4130_MAX_SETUPS - 1)] = 3, 142 [AD4130_MISC_REG] = 2, 143 [AD4130_FIFO_CONTROL_REG] = 3, 144 [AD4130_FIFO_STATUS_REG] = 1, 145 [AD4130_FIFO_THRESHOLD_REG] = 3, 146 [AD4130_FIFO_DATA_REG] = 3, 147 }; 148 149 enum ad4130_int_ref_val { 150 AD4130_INT_REF_VAL_2_5V, 151 AD4130_INT_REF_VAL_1_25V, 152 }; 153 154 enum ad4130_mclk_sel { 155 AD4130_MCLK_76_8KHZ, 156 AD4130_MCLK_76_8KHZ_OUT, 157 AD4130_MCLK_76_8KHZ_EXT, 158 AD4130_MCLK_153_6KHZ_EXT, 159 }; 160 161 enum ad4130_int_pin_sel { 162 AD4130_INT_PIN_INT, 163 AD4130_INT_PIN_CLK, 164 AD4130_INT_PIN_P2, 165 AD4130_INT_PIN_DOUT, 166 }; 167 168 enum ad4130_iout { 169 AD4130_IOUT_OFF, 170 AD4130_IOUT_10000NA, 171 AD4130_IOUT_20000NA, 172 AD4130_IOUT_50000NA, 173 AD4130_IOUT_100000NA, 174 AD4130_IOUT_150000NA, 175 AD4130_IOUT_200000NA, 176 AD4130_IOUT_100NA, 177 AD4130_IOUT_MAX 178 }; 179 180 enum ad4130_burnout { 181 AD4130_BURNOUT_OFF, 182 AD4130_BURNOUT_500NA, 183 AD4130_BURNOUT_2000NA, 184 AD4130_BURNOUT_4000NA, 185 AD4130_BURNOUT_MAX 186 }; 187 188 enum ad4130_ref_sel { 189 AD4130_REF_REFIN1, 190 AD4130_REF_REFIN2, 191 AD4130_REF_REFOUT_AVSS, 192 AD4130_REF_AVDD_AVSS, 193 AD4130_REF_SEL_MAX 194 }; 195 196 enum ad4130_fifo_mode { 197 AD4130_FIFO_MODE_DISABLED = 0b00, 198 AD4130_FIFO_MODE_WM = 0b01, 199 }; 200 201 enum ad4130_mode { 202 AD4130_MODE_CONTINUOUS = 0b0000, 203 AD4130_MODE_IDLE = 0b0100, 204 }; 205 206 enum ad4130_filter_mode { 207 AD4130_FILTER_SINC4, 208 AD4130_FILTER_SINC4_SINC1, 209 AD4130_FILTER_SINC3, 210 AD4130_FILTER_SINC3_REJ60, 211 AD4130_FILTER_SINC3_SINC1, 212 AD4130_FILTER_SINC3_PF1, 213 AD4130_FILTER_SINC3_PF2, 214 AD4130_FILTER_SINC3_PF3, 215 AD4130_FILTER_SINC3_PF4, 216 }; 217 218 enum ad4130_pin_function { 219 AD4130_PIN_FN_NONE, 220 AD4130_PIN_FN_SPECIAL = BIT(0), 221 AD4130_PIN_FN_DIFF = BIT(1), 222 AD4130_PIN_FN_EXCITATION = BIT(2), 223 AD4130_PIN_FN_VBIAS = BIT(3), 224 }; 225 226 struct ad4130_setup_info { 227 unsigned int iout0_val; 228 unsigned int iout1_val; 229 unsigned int burnout; 230 unsigned int pga; 231 unsigned int fs; 232 u32 ref_sel; 233 enum ad4130_filter_mode filter_mode; 234 bool ref_bufp; 235 bool ref_bufm; 236 }; 237 238 struct ad4130_slot_info { 239 struct ad4130_setup_info setup; 240 unsigned int enabled_channels; 241 unsigned int channels; 242 }; 243 244 struct ad4130_chan_info { 245 struct ad4130_setup_info setup; 246 u32 iout0; 247 u32 iout1; 248 int slot; 249 bool enabled; 250 bool initialized; 251 }; 252 253 struct ad4130_filter_config { 254 enum ad4130_filter_mode filter_mode; 255 unsigned int odr_div; 256 unsigned int fs_max; 257 enum iio_available_type samp_freq_avail_type; 258 int samp_freq_avail_len; 259 int samp_freq_avail[3][2]; 260 }; 261 262 struct ad4130_state { 263 struct regmap *regmap; 264 struct spi_device *spi; 265 struct clk *mclk; 266 struct regulator_bulk_data regulators[4]; 267 u32 irq_trigger; 268 u32 inv_irq_trigger; 269 270 /* 271 * Synchronize access to members the of driver state, and ensure 272 * atomicity of consecutive regmap operations. 273 */ 274 struct mutex lock; 275 struct completion completion; 276 277 struct iio_chan_spec chans[AD4130_MAX_CHANNELS]; 278 struct ad4130_chan_info chans_info[AD4130_MAX_CHANNELS]; 279 struct ad4130_slot_info slots_info[AD4130_MAX_SETUPS]; 280 enum ad4130_pin_function pins_fn[AD4130_MAX_ANALOG_PINS]; 281 u32 vbias_pins[AD4130_MAX_ANALOG_PINS]; 282 u32 num_vbias_pins; 283 int scale_tbls[AD4130_REF_SEL_MAX][AD4130_MAX_PGA][2]; 284 struct gpio_chip gc; 285 struct clk_hw int_clk_hw; 286 287 u32 int_pin_sel; 288 u32 int_ref_uv; 289 u32 mclk_sel; 290 bool int_ref_en; 291 bool bipolar; 292 293 unsigned int num_enabled_channels; 294 unsigned int effective_watermark; 295 unsigned int watermark; 296 297 struct spi_message fifo_msg; 298 struct spi_transfer fifo_xfer[2]; 299 300 /* 301 * DMA (thus cache coherency maintenance) requires any transfer 302 * buffers to live in their own cache lines. As the use of these 303 * buffers is synchronous, all of the buffers used for DMA in this 304 * driver may share a cache line. 305 */ 306 u8 reset_buf[AD4130_RESET_BUF_SIZE] __aligned(IIO_DMA_MINALIGN); 307 u8 reg_write_tx_buf[4]; 308 u8 reg_read_tx_buf[1]; 309 u8 reg_read_rx_buf[3]; 310 u8 fifo_tx_buf[2]; 311 u8 fifo_rx_buf[AD4130_FIFO_SIZE * 312 AD4130_FIFO_MAX_SAMPLE_SIZE]; 313 }; 314 315 static const char * const ad4130_int_pin_names[] = { 316 [AD4130_INT_PIN_INT] = "int", 317 [AD4130_INT_PIN_CLK] = "clk", 318 [AD4130_INT_PIN_P2] = "p2", 319 [AD4130_INT_PIN_DOUT] = "dout", 320 }; 321 322 static const unsigned int ad4130_iout_current_na_tbl[AD4130_IOUT_MAX] = { 323 [AD4130_IOUT_OFF] = 0, 324 [AD4130_IOUT_100NA] = 100, 325 [AD4130_IOUT_10000NA] = 10000, 326 [AD4130_IOUT_20000NA] = 20000, 327 [AD4130_IOUT_50000NA] = 50000, 328 [AD4130_IOUT_100000NA] = 100000, 329 [AD4130_IOUT_150000NA] = 150000, 330 [AD4130_IOUT_200000NA] = 200000, 331 }; 332 333 static const unsigned int ad4130_burnout_current_na_tbl[AD4130_BURNOUT_MAX] = { 334 [AD4130_BURNOUT_OFF] = 0, 335 [AD4130_BURNOUT_500NA] = 500, 336 [AD4130_BURNOUT_2000NA] = 2000, 337 [AD4130_BURNOUT_4000NA] = 4000, 338 }; 339 340 #define AD4130_VARIABLE_ODR_CONFIG(_filter_mode, _odr_div, _fs_max) \ 341 { \ 342 .filter_mode = (_filter_mode), \ 343 .odr_div = (_odr_div), \ 344 .fs_max = (_fs_max), \ 345 .samp_freq_avail_type = IIO_AVAIL_RANGE, \ 346 .samp_freq_avail = { \ 347 { AD4130_MAX_ODR, (_odr_div) * (_fs_max) }, \ 348 { AD4130_MAX_ODR, (_odr_div) * (_fs_max) }, \ 349 { AD4130_MAX_ODR, (_odr_div) }, \ 350 }, \ 351 } 352 353 #define AD4130_FIXED_ODR_CONFIG(_filter_mode, _odr_div) \ 354 { \ 355 .filter_mode = (_filter_mode), \ 356 .odr_div = (_odr_div), \ 357 .fs_max = AD4130_FILTER_SELECT_MIN, \ 358 .samp_freq_avail_type = IIO_AVAIL_LIST, \ 359 .samp_freq_avail_len = 1, \ 360 .samp_freq_avail = { \ 361 { AD4130_MAX_ODR, (_odr_div) }, \ 362 }, \ 363 } 364 365 static const struct ad4130_filter_config ad4130_filter_configs[] = { 366 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC4, 1, 10), 367 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC4_SINC1, 11, 10), 368 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3, 1, 2047), 369 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3_REJ60, 1, 2047), 370 AD4130_VARIABLE_ODR_CONFIG(AD4130_FILTER_SINC3_SINC1, 10, 2047), 371 AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF1, 92), 372 AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF2, 100), 373 AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF3, 124), 374 AD4130_FIXED_ODR_CONFIG(AD4130_FILTER_SINC3_PF4, 148), 375 }; 376 377 static const char * const ad4130_filter_modes_str[] = { 378 [AD4130_FILTER_SINC4] = "sinc4", 379 [AD4130_FILTER_SINC4_SINC1] = "sinc4+sinc1", 380 [AD4130_FILTER_SINC3] = "sinc3", 381 [AD4130_FILTER_SINC3_REJ60] = "sinc3+rej60", 382 [AD4130_FILTER_SINC3_SINC1] = "sinc3+sinc1", 383 [AD4130_FILTER_SINC3_PF1] = "sinc3+pf1", 384 [AD4130_FILTER_SINC3_PF2] = "sinc3+pf2", 385 [AD4130_FILTER_SINC3_PF3] = "sinc3+pf3", 386 [AD4130_FILTER_SINC3_PF4] = "sinc3+pf4", 387 }; 388 389 static int ad4130_get_reg_size(struct ad4130_state *st, unsigned int reg, 390 unsigned int *size) 391 { 392 if (reg >= ARRAY_SIZE(ad4130_reg_size)) 393 return -EINVAL; 394 395 *size = ad4130_reg_size[reg]; 396 397 return 0; 398 } 399 400 static unsigned int ad4130_data_reg_size(struct ad4130_state *st) 401 { 402 unsigned int data_reg_size; 403 int ret; 404 405 ret = ad4130_get_reg_size(st, AD4130_DATA_REG, &data_reg_size); 406 if (ret) 407 return 0; 408 409 return data_reg_size; 410 } 411 412 static unsigned int ad4130_resolution(struct ad4130_state *st) 413 { 414 return ad4130_data_reg_size(st) * BITS_PER_BYTE; 415 } 416 417 static int ad4130_reg_write(void *context, unsigned int reg, unsigned int val) 418 { 419 struct ad4130_state *st = context; 420 unsigned int size; 421 int ret; 422 423 ret = ad4130_get_reg_size(st, reg, &size); 424 if (ret) 425 return ret; 426 427 st->reg_write_tx_buf[0] = reg; 428 429 switch (size) { 430 case 3: 431 put_unaligned_be24(val, &st->reg_write_tx_buf[1]); 432 break; 433 case 2: 434 put_unaligned_be16(val, &st->reg_write_tx_buf[1]); 435 break; 436 case 1: 437 st->reg_write_tx_buf[1] = val; 438 break; 439 default: 440 return -EINVAL; 441 } 442 443 return spi_write(st->spi, st->reg_write_tx_buf, size + 1); 444 } 445 446 static int ad4130_reg_read(void *context, unsigned int reg, unsigned int *val) 447 { 448 struct ad4130_state *st = context; 449 struct spi_transfer t[] = { 450 { 451 .tx_buf = st->reg_read_tx_buf, 452 .len = sizeof(st->reg_read_tx_buf), 453 }, 454 { 455 .rx_buf = st->reg_read_rx_buf, 456 }, 457 }; 458 unsigned int size; 459 int ret; 460 461 ret = ad4130_get_reg_size(st, reg, &size); 462 if (ret) 463 return ret; 464 465 st->reg_read_tx_buf[0] = AD4130_COMMS_READ_MASK | reg; 466 t[1].len = size; 467 468 ret = spi_sync_transfer(st->spi, t, ARRAY_SIZE(t)); 469 if (ret) 470 return ret; 471 472 switch (size) { 473 case 3: 474 *val = get_unaligned_be24(st->reg_read_rx_buf); 475 break; 476 case 2: 477 *val = get_unaligned_be16(st->reg_read_rx_buf); 478 break; 479 case 1: 480 *val = st->reg_read_rx_buf[0]; 481 break; 482 default: 483 return -EINVAL; 484 } 485 486 return 0; 487 } 488 489 static const struct regmap_config ad4130_regmap_config = { 490 .reg_read = ad4130_reg_read, 491 .reg_write = ad4130_reg_write, 492 }; 493 494 static int ad4130_gpio_init_valid_mask(struct gpio_chip *gc, 495 unsigned long *valid_mask, 496 unsigned int ngpios) 497 { 498 struct ad4130_state *st = gpiochip_get_data(gc); 499 unsigned int i; 500 501 /* 502 * Output-only GPIO functionality is available on pins AIN2 through 503 * AIN5. If these pins are used for anything else, do not expose them. 504 */ 505 for (i = 0; i < ngpios; i++) { 506 unsigned int pin = i + AD4130_AIN2_P1; 507 bool valid = st->pins_fn[pin] == AD4130_PIN_FN_NONE; 508 509 __assign_bit(i, valid_mask, valid); 510 } 511 512 return 0; 513 } 514 515 static int ad4130_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 516 { 517 return GPIO_LINE_DIRECTION_OUT; 518 } 519 520 static void ad4130_gpio_set(struct gpio_chip *gc, unsigned int offset, 521 int value) 522 { 523 struct ad4130_state *st = gpiochip_get_data(gc); 524 unsigned int mask = FIELD_PREP(AD4130_IO_CONTROL_GPIO_DATA_MASK, 525 BIT(offset)); 526 527 regmap_update_bits(st->regmap, AD4130_IO_CONTROL_REG, mask, 528 value ? mask : 0); 529 } 530 531 static int ad4130_set_mode(struct ad4130_state *st, enum ad4130_mode mode) 532 { 533 return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG, 534 AD4130_ADC_CONTROL_MODE_MASK, 535 FIELD_PREP(AD4130_ADC_CONTROL_MODE_MASK, mode)); 536 } 537 538 static int ad4130_set_watermark_interrupt_en(struct ad4130_state *st, bool en) 539 { 540 return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, 541 AD4130_FIFO_CONTROL_WM_INT_EN_MASK, 542 FIELD_PREP(AD4130_FIFO_CONTROL_WM_INT_EN_MASK, en)); 543 } 544 545 static unsigned int ad4130_watermark_reg_val(unsigned int val) 546 { 547 if (val == AD4130_FIFO_SIZE) 548 val = AD4130_WATERMARK_256; 549 550 return val; 551 } 552 553 static int ad4130_set_fifo_mode(struct ad4130_state *st, 554 enum ad4130_fifo_mode mode) 555 { 556 return regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, 557 AD4130_FIFO_CONTROL_MODE_MASK, 558 FIELD_PREP(AD4130_FIFO_CONTROL_MODE_MASK, mode)); 559 } 560 561 static void ad4130_push_fifo_data(struct iio_dev *indio_dev) 562 { 563 struct ad4130_state *st = iio_priv(indio_dev); 564 unsigned int data_reg_size = ad4130_data_reg_size(st); 565 unsigned int transfer_len = st->effective_watermark * data_reg_size; 566 unsigned int set_size = st->num_enabled_channels * data_reg_size; 567 unsigned int i; 568 int ret; 569 570 st->fifo_tx_buf[1] = ad4130_watermark_reg_val(st->effective_watermark); 571 st->fifo_xfer[1].len = transfer_len; 572 573 ret = spi_sync(st->spi, &st->fifo_msg); 574 if (ret) 575 return; 576 577 for (i = 0; i < transfer_len; i += set_size) 578 iio_push_to_buffers(indio_dev, &st->fifo_rx_buf[i]); 579 } 580 581 static irqreturn_t ad4130_irq_handler(int irq, void *private) 582 { 583 struct iio_dev *indio_dev = private; 584 struct ad4130_state *st = iio_priv(indio_dev); 585 586 if (iio_buffer_enabled(indio_dev)) 587 ad4130_push_fifo_data(indio_dev); 588 else 589 complete(&st->completion); 590 591 return IRQ_HANDLED; 592 } 593 594 static int ad4130_find_slot(struct ad4130_state *st, 595 struct ad4130_setup_info *target_setup_info, 596 unsigned int *slot, bool *overwrite) 597 { 598 unsigned int i; 599 600 *slot = AD4130_INVALID_SLOT; 601 *overwrite = false; 602 603 for (i = 0; i < AD4130_MAX_SETUPS; i++) { 604 struct ad4130_slot_info *slot_info = &st->slots_info[i]; 605 606 /* Immediately accept a matching setup info. */ 607 if (!memcmp(target_setup_info, &slot_info->setup, 608 sizeof(*target_setup_info))) { 609 *slot = i; 610 return 0; 611 } 612 613 /* Ignore all setups which are used by enabled channels. */ 614 if (slot_info->enabled_channels) 615 continue; 616 617 /* Find the least used slot. */ 618 if (*slot == AD4130_INVALID_SLOT || 619 slot_info->channels < st->slots_info[*slot].channels) 620 *slot = i; 621 } 622 623 if (*slot == AD4130_INVALID_SLOT) 624 return -EINVAL; 625 626 *overwrite = true; 627 628 return 0; 629 } 630 631 static void ad4130_unlink_channel(struct ad4130_state *st, unsigned int channel) 632 { 633 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; 634 struct ad4130_slot_info *slot_info = &st->slots_info[chan_info->slot]; 635 636 chan_info->slot = AD4130_INVALID_SLOT; 637 slot_info->channels--; 638 } 639 640 static int ad4130_unlink_slot(struct ad4130_state *st, unsigned int slot) 641 { 642 unsigned int i; 643 644 for (i = 0; i < AD4130_MAX_CHANNELS; i++) { 645 struct ad4130_chan_info *chan_info = &st->chans_info[i]; 646 647 if (!chan_info->initialized || chan_info->slot != slot) 648 continue; 649 650 ad4130_unlink_channel(st, i); 651 } 652 653 return 0; 654 } 655 656 static int ad4130_link_channel_slot(struct ad4130_state *st, 657 unsigned int channel, unsigned int slot) 658 { 659 struct ad4130_slot_info *slot_info = &st->slots_info[slot]; 660 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; 661 int ret; 662 663 ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel), 664 AD4130_CHANNEL_SETUP_MASK, 665 FIELD_PREP(AD4130_CHANNEL_SETUP_MASK, slot)); 666 if (ret) 667 return ret; 668 669 chan_info->slot = slot; 670 slot_info->channels++; 671 672 return 0; 673 } 674 675 static int ad4130_write_slot_setup(struct ad4130_state *st, 676 unsigned int slot, 677 struct ad4130_setup_info *setup_info) 678 { 679 unsigned int val; 680 int ret; 681 682 val = FIELD_PREP(AD4130_CONFIG_IOUT1_VAL_MASK, setup_info->iout0_val) | 683 FIELD_PREP(AD4130_CONFIG_IOUT1_VAL_MASK, setup_info->iout1_val) | 684 FIELD_PREP(AD4130_CONFIG_BURNOUT_MASK, setup_info->burnout) | 685 FIELD_PREP(AD4130_CONFIG_REF_BUFP_MASK, setup_info->ref_bufp) | 686 FIELD_PREP(AD4130_CONFIG_REF_BUFM_MASK, setup_info->ref_bufm) | 687 FIELD_PREP(AD4130_CONFIG_REF_SEL_MASK, setup_info->ref_sel) | 688 FIELD_PREP(AD4130_CONFIG_PGA_MASK, setup_info->pga); 689 690 ret = regmap_write(st->regmap, AD4130_CONFIG_X_REG(slot), val); 691 if (ret) 692 return ret; 693 694 val = FIELD_PREP(AD4130_FILTER_MODE_MASK, setup_info->filter_mode) | 695 FIELD_PREP(AD4130_FILTER_SELECT_MASK, setup_info->fs); 696 697 ret = regmap_write(st->regmap, AD4130_FILTER_X_REG(slot), val); 698 if (ret) 699 return ret; 700 701 memcpy(&st->slots_info[slot].setup, setup_info, sizeof(*setup_info)); 702 703 return 0; 704 } 705 706 static int ad4130_write_channel_setup(struct ad4130_state *st, 707 unsigned int channel, bool on_enable) 708 { 709 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; 710 struct ad4130_setup_info *setup_info = &chan_info->setup; 711 bool overwrite; 712 int slot; 713 int ret; 714 715 /* 716 * The following cases need to be handled. 717 * 718 * 1. Enabled and linked channel with setup changes: 719 * - Find a slot. If not possible, return error. 720 * - Unlink channel from current slot. 721 * - If the slot has channels linked to it, unlink all channels, and 722 * write the new setup to it. 723 * - Link channel to new slot. 724 * 725 * 2. Soon to be enabled and unlinked channel: 726 * - Find a slot. If not possible, return error. 727 * - If the slot has channels linked to it, unlink all channels, and 728 * write the new setup to it. 729 * - Link channel to the slot. 730 * 731 * 3. Disabled and linked channel with setup changes: 732 * - Unlink channel from current slot. 733 * 734 * 4. Soon to be enabled and linked channel: 735 * 5. Disabled and unlinked channel with setup changes: 736 * - Do nothing. 737 */ 738 739 /* Case 4 */ 740 if (on_enable && chan_info->slot != AD4130_INVALID_SLOT) 741 return 0; 742 743 if (!on_enable && !chan_info->enabled) { 744 if (chan_info->slot != AD4130_INVALID_SLOT) 745 /* Case 3 */ 746 ad4130_unlink_channel(st, channel); 747 748 /* Cases 3 & 5 */ 749 return 0; 750 } 751 752 /* Cases 1 & 2 */ 753 ret = ad4130_find_slot(st, setup_info, &slot, &overwrite); 754 if (ret) 755 return ret; 756 757 if (chan_info->slot != AD4130_INVALID_SLOT) 758 /* Case 1 */ 759 ad4130_unlink_channel(st, channel); 760 761 if (overwrite) { 762 ret = ad4130_unlink_slot(st, slot); 763 if (ret) 764 return ret; 765 766 ret = ad4130_write_slot_setup(st, slot, setup_info); 767 if (ret) 768 return ret; 769 } 770 771 return ad4130_link_channel_slot(st, channel, slot); 772 } 773 774 static int ad4130_set_channel_enable(struct ad4130_state *st, 775 unsigned int channel, bool status) 776 { 777 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; 778 struct ad4130_slot_info *slot_info; 779 int ret; 780 781 if (chan_info->enabled == status) 782 return 0; 783 784 if (status) { 785 ret = ad4130_write_channel_setup(st, channel, true); 786 if (ret) 787 return ret; 788 } 789 790 slot_info = &st->slots_info[chan_info->slot]; 791 792 ret = regmap_update_bits(st->regmap, AD4130_CHANNEL_X_REG(channel), 793 AD4130_CHANNEL_EN_MASK, 794 FIELD_PREP(AD4130_CHANNEL_EN_MASK, status)); 795 if (ret) 796 return ret; 797 798 slot_info->enabled_channels += status ? 1 : -1; 799 chan_info->enabled = status; 800 801 return 0; 802 } 803 804 /* 805 * Table 58. FILTER_MODE_n bits and Filter Types of the datasheet describes 806 * the relation between filter mode, ODR and FS. 807 * 808 * Notice that the max ODR of each filter mode is not necessarily the 809 * absolute max ODR supported by the chip. 810 * 811 * The ODR divider is not explicitly specified, but it can be deduced based 812 * on the ODR range of each filter mode. 813 * 814 * For example, for Sinc4+Sinc1, max ODR is 218.18. That means that the 815 * absolute max ODR is divided by 11 to achieve the max ODR of this filter 816 * mode. 817 * 818 * The formulas for converting between ODR and FS for a specific filter 819 * mode can be deduced from the same table. 820 * 821 * Notice that FS = 1 actually means max ODR, and that ODR decreases by 822 * (maximum ODR / maximum FS) for each increment of FS. 823 * 824 * odr = MAX_ODR / odr_div * (1 - (fs - 1) / fs_max) <=> 825 * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=> 826 * odr = MAX_ODR * (1 - (fs - 1) / fs_max) / odr_div <=> 827 * odr = MAX_ODR * (fs_max - fs + 1) / (fs_max * odr_div) 828 * (used in ad4130_fs_to_freq) 829 * 830 * For the opposite formula, FS can be extracted from the last one. 831 * 832 * MAX_ODR * (fs_max - fs + 1) = fs_max * odr_div * odr <=> 833 * fs_max - fs + 1 = fs_max * odr_div * odr / MAX_ODR <=> 834 * fs = 1 + fs_max - fs_max * odr_div * odr / MAX_ODR 835 * (used in ad4130_fs_to_freq) 836 */ 837 838 static void ad4130_freq_to_fs(enum ad4130_filter_mode filter_mode, 839 int val, int val2, unsigned int *fs) 840 { 841 const struct ad4130_filter_config *filter_config = 842 &ad4130_filter_configs[filter_mode]; 843 u64 dividend, divisor; 844 int temp; 845 846 dividend = filter_config->fs_max * filter_config->odr_div * 847 ((u64)val * NANO + val2); 848 divisor = (u64)AD4130_MAX_ODR * NANO; 849 850 temp = AD4130_FILTER_SELECT_MIN + filter_config->fs_max - 851 DIV64_U64_ROUND_CLOSEST(dividend, divisor); 852 853 if (temp < AD4130_FILTER_SELECT_MIN) 854 temp = AD4130_FILTER_SELECT_MIN; 855 else if (temp > filter_config->fs_max) 856 temp = filter_config->fs_max; 857 858 *fs = temp; 859 } 860 861 static void ad4130_fs_to_freq(enum ad4130_filter_mode filter_mode, 862 unsigned int fs, int *val, int *val2) 863 { 864 const struct ad4130_filter_config *filter_config = 865 &ad4130_filter_configs[filter_mode]; 866 unsigned int dividend, divisor; 867 u64 temp; 868 869 dividend = (filter_config->fs_max - fs + AD4130_FILTER_SELECT_MIN) * 870 AD4130_MAX_ODR; 871 divisor = filter_config->fs_max * filter_config->odr_div; 872 873 temp = div_u64((u64)dividend * NANO, divisor); 874 *val = div_u64_rem(temp, NANO, val2); 875 } 876 877 static int ad4130_set_filter_mode(struct iio_dev *indio_dev, 878 const struct iio_chan_spec *chan, 879 unsigned int val) 880 { 881 struct ad4130_state *st = iio_priv(indio_dev); 882 unsigned int channel = chan->scan_index; 883 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; 884 struct ad4130_setup_info *setup_info = &chan_info->setup; 885 enum ad4130_filter_mode old_filter_mode; 886 int freq_val, freq_val2; 887 unsigned int old_fs; 888 int ret = 0; 889 890 mutex_lock(&st->lock); 891 if (setup_info->filter_mode == val) 892 goto out; 893 894 old_fs = setup_info->fs; 895 old_filter_mode = setup_info->filter_mode; 896 897 /* 898 * When switching between filter modes, try to match the ODR as 899 * close as possible. To do this, convert the current FS into ODR 900 * using the old filter mode, then convert it back into FS using 901 * the new filter mode. 902 */ 903 ad4130_fs_to_freq(setup_info->filter_mode, setup_info->fs, 904 &freq_val, &freq_val2); 905 906 ad4130_freq_to_fs(val, freq_val, freq_val2, &setup_info->fs); 907 908 setup_info->filter_mode = val; 909 910 ret = ad4130_write_channel_setup(st, channel, false); 911 if (ret) { 912 setup_info->fs = old_fs; 913 setup_info->filter_mode = old_filter_mode; 914 } 915 916 out: 917 mutex_unlock(&st->lock); 918 919 return ret; 920 } 921 922 static int ad4130_get_filter_mode(struct iio_dev *indio_dev, 923 const struct iio_chan_spec *chan) 924 { 925 struct ad4130_state *st = iio_priv(indio_dev); 926 unsigned int channel = chan->scan_index; 927 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup; 928 enum ad4130_filter_mode filter_mode; 929 930 mutex_lock(&st->lock); 931 filter_mode = setup_info->filter_mode; 932 mutex_unlock(&st->lock); 933 934 return filter_mode; 935 } 936 937 static const struct iio_enum ad4130_filter_mode_enum = { 938 .items = ad4130_filter_modes_str, 939 .num_items = ARRAY_SIZE(ad4130_filter_modes_str), 940 .set = ad4130_set_filter_mode, 941 .get = ad4130_get_filter_mode, 942 }; 943 944 static const struct iio_chan_spec_ext_info ad4130_filter_mode_ext_info[] = { 945 IIO_ENUM("filter_mode", IIO_SEPARATE, &ad4130_filter_mode_enum), 946 IIO_ENUM_AVAILABLE("filter_mode", IIO_SHARED_BY_TYPE, 947 &ad4130_filter_mode_enum), 948 { } 949 }; 950 951 static const struct iio_chan_spec ad4130_channel_template = { 952 .type = IIO_VOLTAGE, 953 .indexed = 1, 954 .differential = 1, 955 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | 956 BIT(IIO_CHAN_INFO_SCALE) | 957 BIT(IIO_CHAN_INFO_OFFSET) | 958 BIT(IIO_CHAN_INFO_SAMP_FREQ), 959 .info_mask_separate_available = BIT(IIO_CHAN_INFO_SCALE) | 960 BIT(IIO_CHAN_INFO_SAMP_FREQ), 961 .ext_info = ad4130_filter_mode_ext_info, 962 .scan_type = { 963 .sign = 'u', 964 .endianness = IIO_BE, 965 }, 966 }; 967 968 static int ad4130_set_channel_pga(struct ad4130_state *st, unsigned int channel, 969 int val, int val2) 970 { 971 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; 972 struct ad4130_setup_info *setup_info = &chan_info->setup; 973 unsigned int pga, old_pga; 974 int ret = 0; 975 976 for (pga = 0; pga < AD4130_MAX_PGA; pga++) 977 if (val == st->scale_tbls[setup_info->ref_sel][pga][0] && 978 val2 == st->scale_tbls[setup_info->ref_sel][pga][1]) 979 break; 980 981 if (pga == AD4130_MAX_PGA) 982 return -EINVAL; 983 984 mutex_lock(&st->lock); 985 if (pga == setup_info->pga) 986 goto out; 987 988 old_pga = setup_info->pga; 989 setup_info->pga = pga; 990 991 ret = ad4130_write_channel_setup(st, channel, false); 992 if (ret) 993 setup_info->pga = old_pga; 994 995 out: 996 mutex_unlock(&st->lock); 997 998 return ret; 999 } 1000 1001 static int ad4130_set_channel_freq(struct ad4130_state *st, 1002 unsigned int channel, int val, int val2) 1003 { 1004 struct ad4130_chan_info *chan_info = &st->chans_info[channel]; 1005 struct ad4130_setup_info *setup_info = &chan_info->setup; 1006 unsigned int fs, old_fs; 1007 int ret = 0; 1008 1009 mutex_lock(&st->lock); 1010 old_fs = setup_info->fs; 1011 1012 ad4130_freq_to_fs(setup_info->filter_mode, val, val2, &fs); 1013 1014 if (fs == setup_info->fs) 1015 goto out; 1016 1017 setup_info->fs = fs; 1018 1019 ret = ad4130_write_channel_setup(st, channel, false); 1020 if (ret) 1021 setup_info->fs = old_fs; 1022 1023 out: 1024 mutex_unlock(&st->lock); 1025 1026 return ret; 1027 } 1028 1029 static int _ad4130_read_sample(struct iio_dev *indio_dev, unsigned int channel, 1030 int *val) 1031 { 1032 struct ad4130_state *st = iio_priv(indio_dev); 1033 int ret; 1034 1035 ret = ad4130_set_channel_enable(st, channel, true); 1036 if (ret) 1037 return ret; 1038 1039 reinit_completion(&st->completion); 1040 1041 ret = ad4130_set_mode(st, AD4130_MODE_CONTINUOUS); 1042 if (ret) 1043 return ret; 1044 1045 ret = wait_for_completion_timeout(&st->completion, 1046 msecs_to_jiffies(1000)); 1047 if (!ret) 1048 return -ETIMEDOUT; 1049 1050 ret = ad4130_set_mode(st, AD4130_MODE_IDLE); 1051 if (ret) 1052 return ret; 1053 1054 ret = regmap_read(st->regmap, AD4130_DATA_REG, val); 1055 if (ret) 1056 return ret; 1057 1058 ret = ad4130_set_channel_enable(st, channel, false); 1059 if (ret) 1060 return ret; 1061 1062 return IIO_VAL_INT; 1063 } 1064 1065 static int ad4130_read_sample(struct iio_dev *indio_dev, unsigned int channel, 1066 int *val) 1067 { 1068 struct ad4130_state *st = iio_priv(indio_dev); 1069 int ret; 1070 1071 ret = iio_device_claim_direct_mode(indio_dev); 1072 if (ret) 1073 return ret; 1074 1075 mutex_lock(&st->lock); 1076 ret = _ad4130_read_sample(indio_dev, channel, val); 1077 mutex_unlock(&st->lock); 1078 1079 iio_device_release_direct_mode(indio_dev); 1080 1081 return ret; 1082 } 1083 1084 static int ad4130_read_raw(struct iio_dev *indio_dev, 1085 struct iio_chan_spec const *chan, 1086 int *val, int *val2, long info) 1087 { 1088 struct ad4130_state *st = iio_priv(indio_dev); 1089 unsigned int channel = chan->scan_index; 1090 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup; 1091 1092 switch (info) { 1093 case IIO_CHAN_INFO_RAW: 1094 return ad4130_read_sample(indio_dev, channel, val); 1095 case IIO_CHAN_INFO_SCALE: 1096 mutex_lock(&st->lock); 1097 *val = st->scale_tbls[setup_info->ref_sel][setup_info->pga][0]; 1098 *val2 = st->scale_tbls[setup_info->ref_sel][setup_info->pga][1]; 1099 mutex_unlock(&st->lock); 1100 1101 return IIO_VAL_INT_PLUS_NANO; 1102 case IIO_CHAN_INFO_OFFSET: 1103 *val = st->bipolar ? -BIT(chan->scan_type.realbits - 1) : 0; 1104 1105 return IIO_VAL_INT; 1106 case IIO_CHAN_INFO_SAMP_FREQ: 1107 mutex_lock(&st->lock); 1108 ad4130_fs_to_freq(setup_info->filter_mode, setup_info->fs, 1109 val, val2); 1110 mutex_unlock(&st->lock); 1111 1112 return IIO_VAL_INT_PLUS_NANO; 1113 default: 1114 return -EINVAL; 1115 } 1116 } 1117 1118 static int ad4130_read_avail(struct iio_dev *indio_dev, 1119 struct iio_chan_spec const *chan, 1120 const int **vals, int *type, int *length, 1121 long info) 1122 { 1123 struct ad4130_state *st = iio_priv(indio_dev); 1124 unsigned int channel = chan->scan_index; 1125 struct ad4130_setup_info *setup_info = &st->chans_info[channel].setup; 1126 const struct ad4130_filter_config *filter_config; 1127 1128 switch (info) { 1129 case IIO_CHAN_INFO_SCALE: 1130 *vals = (int *)st->scale_tbls[setup_info->ref_sel]; 1131 *length = ARRAY_SIZE(st->scale_tbls[setup_info->ref_sel]) * 2; 1132 1133 *type = IIO_VAL_INT_PLUS_NANO; 1134 1135 return IIO_AVAIL_LIST; 1136 case IIO_CHAN_INFO_SAMP_FREQ: 1137 mutex_lock(&st->lock); 1138 filter_config = &ad4130_filter_configs[setup_info->filter_mode]; 1139 mutex_unlock(&st->lock); 1140 1141 *vals = (int *)filter_config->samp_freq_avail; 1142 *length = filter_config->samp_freq_avail_len * 2; 1143 *type = IIO_VAL_FRACTIONAL; 1144 1145 return filter_config->samp_freq_avail_type; 1146 default: 1147 return -EINVAL; 1148 } 1149 } 1150 1151 static int ad4130_write_raw_get_fmt(struct iio_dev *indio_dev, 1152 struct iio_chan_spec const *chan, 1153 long info) 1154 { 1155 switch (info) { 1156 case IIO_CHAN_INFO_SCALE: 1157 case IIO_CHAN_INFO_SAMP_FREQ: 1158 return IIO_VAL_INT_PLUS_NANO; 1159 default: 1160 return -EINVAL; 1161 } 1162 } 1163 1164 static int ad4130_write_raw(struct iio_dev *indio_dev, 1165 struct iio_chan_spec const *chan, 1166 int val, int val2, long info) 1167 { 1168 struct ad4130_state *st = iio_priv(indio_dev); 1169 unsigned int channel = chan->scan_index; 1170 1171 switch (info) { 1172 case IIO_CHAN_INFO_SCALE: 1173 return ad4130_set_channel_pga(st, channel, val, val2); 1174 case IIO_CHAN_INFO_SAMP_FREQ: 1175 return ad4130_set_channel_freq(st, channel, val, val2); 1176 default: 1177 return -EINVAL; 1178 } 1179 } 1180 1181 static int ad4130_reg_access(struct iio_dev *indio_dev, unsigned int reg, 1182 unsigned int writeval, unsigned int *readval) 1183 { 1184 struct ad4130_state *st = iio_priv(indio_dev); 1185 1186 if (readval) 1187 return regmap_read(st->regmap, reg, readval); 1188 1189 return regmap_write(st->regmap, reg, writeval); 1190 } 1191 1192 static int ad4130_update_scan_mode(struct iio_dev *indio_dev, 1193 const unsigned long *scan_mask) 1194 { 1195 struct ad4130_state *st = iio_priv(indio_dev); 1196 unsigned int channel; 1197 unsigned int val = 0; 1198 int ret; 1199 1200 mutex_lock(&st->lock); 1201 1202 for_each_set_bit(channel, scan_mask, indio_dev->num_channels) { 1203 ret = ad4130_set_channel_enable(st, channel, true); 1204 if (ret) 1205 goto out; 1206 1207 val++; 1208 } 1209 1210 st->num_enabled_channels = val; 1211 1212 out: 1213 mutex_unlock(&st->lock); 1214 1215 return 0; 1216 } 1217 1218 static int ad4130_set_fifo_watermark(struct iio_dev *indio_dev, unsigned int val) 1219 { 1220 struct ad4130_state *st = iio_priv(indio_dev); 1221 unsigned int eff; 1222 int ret; 1223 1224 if (val > AD4130_FIFO_SIZE) 1225 return -EINVAL; 1226 1227 eff = val * st->num_enabled_channels; 1228 if (eff > AD4130_FIFO_SIZE) 1229 /* 1230 * Always set watermark to a multiple of the number of 1231 * enabled channels to avoid making the FIFO unaligned. 1232 */ 1233 eff = rounddown(AD4130_FIFO_SIZE, st->num_enabled_channels); 1234 1235 mutex_lock(&st->lock); 1236 1237 ret = regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, 1238 AD4130_FIFO_CONTROL_WM_MASK, 1239 FIELD_PREP(AD4130_FIFO_CONTROL_WM_MASK, 1240 ad4130_watermark_reg_val(eff))); 1241 if (ret) 1242 goto out; 1243 1244 st->effective_watermark = eff; 1245 st->watermark = val; 1246 1247 out: 1248 mutex_unlock(&st->lock); 1249 1250 return ret; 1251 } 1252 1253 static const struct iio_info ad4130_info = { 1254 .read_raw = ad4130_read_raw, 1255 .read_avail = ad4130_read_avail, 1256 .write_raw_get_fmt = ad4130_write_raw_get_fmt, 1257 .write_raw = ad4130_write_raw, 1258 .update_scan_mode = ad4130_update_scan_mode, 1259 .hwfifo_set_watermark = ad4130_set_fifo_watermark, 1260 .debugfs_reg_access = ad4130_reg_access, 1261 }; 1262 1263 static int ad4130_buffer_postenable(struct iio_dev *indio_dev) 1264 { 1265 struct ad4130_state *st = iio_priv(indio_dev); 1266 int ret; 1267 1268 mutex_lock(&st->lock); 1269 1270 ret = ad4130_set_watermark_interrupt_en(st, true); 1271 if (ret) 1272 goto out; 1273 1274 ret = irq_set_irq_type(st->spi->irq, st->inv_irq_trigger); 1275 if (ret) 1276 goto out; 1277 1278 ret = ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_WM); 1279 if (ret) 1280 goto out; 1281 1282 ret = ad4130_set_mode(st, AD4130_MODE_CONTINUOUS); 1283 1284 out: 1285 mutex_unlock(&st->lock); 1286 1287 return ret; 1288 } 1289 1290 static int ad4130_buffer_predisable(struct iio_dev *indio_dev) 1291 { 1292 struct ad4130_state *st = iio_priv(indio_dev); 1293 unsigned int i; 1294 int ret; 1295 1296 mutex_lock(&st->lock); 1297 1298 ret = ad4130_set_mode(st, AD4130_MODE_IDLE); 1299 if (ret) 1300 goto out; 1301 1302 ret = irq_set_irq_type(st->spi->irq, st->irq_trigger); 1303 if (ret) 1304 goto out; 1305 1306 ret = ad4130_set_fifo_mode(st, AD4130_FIFO_MODE_DISABLED); 1307 if (ret) 1308 goto out; 1309 1310 ret = ad4130_set_watermark_interrupt_en(st, false); 1311 if (ret) 1312 goto out; 1313 1314 /* 1315 * update_scan_mode() is not called in the disable path, disable all 1316 * channels here. 1317 */ 1318 for (i = 0; i < indio_dev->num_channels; i++) { 1319 ret = ad4130_set_channel_enable(st, i, false); 1320 if (ret) 1321 goto out; 1322 } 1323 1324 out: 1325 mutex_unlock(&st->lock); 1326 1327 return ret; 1328 } 1329 1330 static const struct iio_buffer_setup_ops ad4130_buffer_ops = { 1331 .postenable = ad4130_buffer_postenable, 1332 .predisable = ad4130_buffer_predisable, 1333 }; 1334 1335 static ssize_t hwfifo_watermark_show(struct device *dev, 1336 struct device_attribute *attr, char *buf) 1337 { 1338 struct ad4130_state *st = iio_priv(dev_to_iio_dev(dev)); 1339 unsigned int val; 1340 1341 mutex_lock(&st->lock); 1342 val = st->watermark; 1343 mutex_unlock(&st->lock); 1344 1345 return sysfs_emit(buf, "%d\n", val); 1346 } 1347 1348 static ssize_t hwfifo_enabled_show(struct device *dev, 1349 struct device_attribute *attr, char *buf) 1350 { 1351 struct ad4130_state *st = iio_priv(dev_to_iio_dev(dev)); 1352 unsigned int val; 1353 int ret; 1354 1355 ret = regmap_read(st->regmap, AD4130_FIFO_CONTROL_REG, &val); 1356 if (ret) 1357 return ret; 1358 1359 val = FIELD_GET(AD4130_FIFO_CONTROL_MODE_MASK, val); 1360 1361 return sysfs_emit(buf, "%d\n", val != AD4130_FIFO_MODE_DISABLED); 1362 } 1363 1364 static ssize_t hwfifo_watermark_min_show(struct device *dev, 1365 struct device_attribute *attr, 1366 char *buf) 1367 { 1368 return sysfs_emit(buf, "%s\n", "1"); 1369 } 1370 1371 static ssize_t hwfifo_watermark_max_show(struct device *dev, 1372 struct device_attribute *attr, 1373 char *buf) 1374 { 1375 return sysfs_emit(buf, "%s\n", __stringify(AD4130_FIFO_SIZE)); 1376 } 1377 1378 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_min, 0); 1379 static IIO_DEVICE_ATTR_RO(hwfifo_watermark_max, 0); 1380 static IIO_DEVICE_ATTR_RO(hwfifo_watermark, 0); 1381 static IIO_DEVICE_ATTR_RO(hwfifo_enabled, 0); 1382 1383 static const struct iio_dev_attr *ad4130_fifo_attributes[] = { 1384 &iio_dev_attr_hwfifo_watermark_min, 1385 &iio_dev_attr_hwfifo_watermark_max, 1386 &iio_dev_attr_hwfifo_watermark, 1387 &iio_dev_attr_hwfifo_enabled, 1388 NULL 1389 }; 1390 1391 static int _ad4130_find_table_index(const unsigned int *tbl, size_t len, 1392 unsigned int val) 1393 { 1394 unsigned int i; 1395 1396 for (i = 0; i < len; i++) 1397 if (tbl[i] == val) 1398 return i; 1399 1400 return -EINVAL; 1401 } 1402 1403 #define ad4130_find_table_index(table, val) \ 1404 _ad4130_find_table_index(table, ARRAY_SIZE(table), val) 1405 1406 static int ad4130_get_ref_voltage(struct ad4130_state *st, 1407 enum ad4130_ref_sel ref_sel) 1408 { 1409 switch (ref_sel) { 1410 case AD4130_REF_REFIN1: 1411 return regulator_get_voltage(st->regulators[2].consumer); 1412 case AD4130_REF_REFIN2: 1413 return regulator_get_voltage(st->regulators[3].consumer); 1414 case AD4130_REF_AVDD_AVSS: 1415 return regulator_get_voltage(st->regulators[0].consumer); 1416 case AD4130_REF_REFOUT_AVSS: 1417 return st->int_ref_uv; 1418 default: 1419 return -EINVAL; 1420 } 1421 } 1422 1423 static int ad4130_parse_fw_setup(struct ad4130_state *st, 1424 struct fwnode_handle *child, 1425 struct ad4130_setup_info *setup_info) 1426 { 1427 struct device *dev = &st->spi->dev; 1428 u32 tmp; 1429 int ret; 1430 1431 tmp = 0; 1432 fwnode_property_read_u32(child, "adi,excitation-current-0-nanoamp", &tmp); 1433 ret = ad4130_find_table_index(ad4130_iout_current_na_tbl, tmp); 1434 if (ret < 0) 1435 return dev_err_probe(dev, ret, 1436 "Invalid excitation current %unA\n", tmp); 1437 setup_info->iout0_val = ret; 1438 1439 tmp = 0; 1440 fwnode_property_read_u32(child, "adi,excitation-current-1-nanoamp", &tmp); 1441 ret = ad4130_find_table_index(ad4130_iout_current_na_tbl, tmp); 1442 if (ret < 0) 1443 return dev_err_probe(dev, ret, 1444 "Invalid excitation current %unA\n", tmp); 1445 setup_info->iout1_val = ret; 1446 1447 tmp = 0; 1448 fwnode_property_read_u32(child, "adi,burnout-current-nanoamp", &tmp); 1449 ret = ad4130_find_table_index(ad4130_burnout_current_na_tbl, tmp); 1450 if (ret < 0) 1451 return dev_err_probe(dev, ret, 1452 "Invalid burnout current %unA\n", tmp); 1453 setup_info->burnout = ret; 1454 1455 setup_info->ref_bufp = fwnode_property_read_bool(child, "adi,buffered-positive"); 1456 setup_info->ref_bufm = fwnode_property_read_bool(child, "adi,buffered-negative"); 1457 1458 setup_info->ref_sel = AD4130_REF_REFIN1; 1459 fwnode_property_read_u32(child, "adi,reference-select", 1460 &setup_info->ref_sel); 1461 if (setup_info->ref_sel >= AD4130_REF_SEL_MAX) 1462 return dev_err_probe(dev, -EINVAL, 1463 "Invalid reference selected %u\n", 1464 setup_info->ref_sel); 1465 1466 if (setup_info->ref_sel == AD4130_REF_REFOUT_AVSS) 1467 st->int_ref_en = true; 1468 1469 ret = ad4130_get_ref_voltage(st, setup_info->ref_sel); 1470 if (ret < 0) 1471 return dev_err_probe(dev, ret, "Cannot use reference %u\n", 1472 setup_info->ref_sel); 1473 1474 return 0; 1475 } 1476 1477 static int ad4130_validate_diff_channel(struct ad4130_state *st, u32 pin) 1478 { 1479 struct device *dev = &st->spi->dev; 1480 1481 if (pin >= AD4130_MAX_DIFF_INPUTS) 1482 return dev_err_probe(dev, -EINVAL, 1483 "Invalid differential channel %u\n", pin); 1484 1485 if (pin >= AD4130_MAX_ANALOG_PINS) 1486 return 0; 1487 1488 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL) 1489 return dev_err_probe(dev, -EINVAL, 1490 "Pin %u already used with fn %u\n", pin, 1491 st->pins_fn[pin]); 1492 1493 st->pins_fn[pin] |= AD4130_PIN_FN_DIFF; 1494 1495 return 0; 1496 } 1497 1498 static int ad4130_validate_diff_channels(struct ad4130_state *st, 1499 u32 *pins, unsigned int len) 1500 { 1501 unsigned int i; 1502 int ret; 1503 1504 for (i = 0; i < len; i++) { 1505 ret = ad4130_validate_diff_channel(st, pins[i]); 1506 if (ret) 1507 return ret; 1508 } 1509 1510 return 0; 1511 } 1512 1513 static int ad4130_validate_excitation_pin(struct ad4130_state *st, u32 pin) 1514 { 1515 struct device *dev = &st->spi->dev; 1516 1517 if (pin >= AD4130_MAX_ANALOG_PINS) 1518 return dev_err_probe(dev, -EINVAL, 1519 "Invalid excitation pin %u\n", pin); 1520 1521 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL) 1522 return dev_err_probe(dev, -EINVAL, 1523 "Pin %u already used with fn %u\n", pin, 1524 st->pins_fn[pin]); 1525 1526 st->pins_fn[pin] |= AD4130_PIN_FN_EXCITATION; 1527 1528 return 0; 1529 } 1530 1531 static int ad4130_validate_vbias_pin(struct ad4130_state *st, u32 pin) 1532 { 1533 struct device *dev = &st->spi->dev; 1534 1535 if (pin >= AD4130_MAX_ANALOG_PINS) 1536 return dev_err_probe(dev, -EINVAL, "Invalid vbias pin %u\n", 1537 pin); 1538 1539 if (st->pins_fn[pin] == AD4130_PIN_FN_SPECIAL) 1540 return dev_err_probe(dev, -EINVAL, 1541 "Pin %u already used with fn %u\n", pin, 1542 st->pins_fn[pin]); 1543 1544 st->pins_fn[pin] |= AD4130_PIN_FN_VBIAS; 1545 1546 return 0; 1547 } 1548 1549 static int ad4130_validate_vbias_pins(struct ad4130_state *st, 1550 u32 *pins, unsigned int len) 1551 { 1552 unsigned int i; 1553 int ret; 1554 1555 for (i = 0; i < st->num_vbias_pins; i++) { 1556 ret = ad4130_validate_vbias_pin(st, pins[i]); 1557 if (ret) 1558 return ret; 1559 } 1560 1561 return 0; 1562 } 1563 1564 static int ad4130_parse_fw_channel(struct iio_dev *indio_dev, 1565 struct fwnode_handle *child) 1566 { 1567 struct ad4130_state *st = iio_priv(indio_dev); 1568 unsigned int resolution = ad4130_resolution(st); 1569 unsigned int index = indio_dev->num_channels++; 1570 struct device *dev = &st->spi->dev; 1571 struct ad4130_chan_info *chan_info; 1572 struct iio_chan_spec *chan; 1573 u32 pins[2]; 1574 int ret; 1575 1576 if (index >= AD4130_MAX_CHANNELS) 1577 return dev_err_probe(dev, -EINVAL, "Too many channels\n"); 1578 1579 chan = &st->chans[index]; 1580 chan_info = &st->chans_info[index]; 1581 1582 *chan = ad4130_channel_template; 1583 chan->scan_type.realbits = resolution; 1584 chan->scan_type.storagebits = resolution; 1585 chan->scan_index = index; 1586 1587 chan_info->slot = AD4130_INVALID_SLOT; 1588 chan_info->setup.fs = AD4130_FILTER_SELECT_MIN; 1589 chan_info->initialized = true; 1590 1591 ret = fwnode_property_read_u32_array(child, "diff-channels", pins, 1592 ARRAY_SIZE(pins)); 1593 if (ret) 1594 return ret; 1595 1596 ret = ad4130_validate_diff_channels(st, pins, ARRAY_SIZE(pins)); 1597 if (ret) 1598 return ret; 1599 1600 chan->channel = pins[0]; 1601 chan->channel2 = pins[1]; 1602 1603 ret = ad4130_parse_fw_setup(st, child, &chan_info->setup); 1604 if (ret) 1605 return ret; 1606 1607 fwnode_property_read_u32(child, "adi,excitation-pin-0", 1608 &chan_info->iout0); 1609 if (chan_info->setup.iout0_val != AD4130_IOUT_OFF) { 1610 ret = ad4130_validate_excitation_pin(st, chan_info->iout0); 1611 if (ret) 1612 return ret; 1613 } 1614 1615 fwnode_property_read_u32(child, "adi,excitation-pin-1", 1616 &chan_info->iout1); 1617 if (chan_info->setup.iout1_val != AD4130_IOUT_OFF) { 1618 ret = ad4130_validate_excitation_pin(st, chan_info->iout1); 1619 if (ret) 1620 return ret; 1621 } 1622 1623 return 0; 1624 } 1625 1626 static int ad4130_parse_fw_children(struct iio_dev *indio_dev) 1627 { 1628 struct ad4130_state *st = iio_priv(indio_dev); 1629 struct device *dev = &st->spi->dev; 1630 struct fwnode_handle *child; 1631 int ret; 1632 1633 indio_dev->channels = st->chans; 1634 1635 device_for_each_child_node(dev, child) { 1636 ret = ad4130_parse_fw_channel(indio_dev, child); 1637 if (ret) { 1638 fwnode_handle_put(child); 1639 return ret; 1640 } 1641 } 1642 1643 return 0; 1644 } 1645 1646 static int ad4310_parse_fw(struct iio_dev *indio_dev) 1647 { 1648 struct ad4130_state *st = iio_priv(indio_dev); 1649 struct device *dev = &st->spi->dev; 1650 u32 ext_clk_freq = AD4130_MCLK_FREQ_76_8KHZ; 1651 unsigned int i; 1652 int avdd_uv; 1653 int irq; 1654 int ret; 1655 1656 st->mclk = devm_clk_get_optional(dev, "mclk"); 1657 if (IS_ERR(st->mclk)) 1658 return dev_err_probe(dev, PTR_ERR(st->mclk), 1659 "Failed to get mclk\n"); 1660 1661 st->int_pin_sel = AD4130_INT_PIN_INT; 1662 1663 for (i = 0; i < ARRAY_SIZE(ad4130_int_pin_names); i++) { 1664 irq = fwnode_irq_get_byname(dev_fwnode(dev), 1665 ad4130_int_pin_names[i]); 1666 if (irq > 0) { 1667 st->int_pin_sel = i; 1668 break; 1669 } 1670 } 1671 1672 if (st->int_pin_sel == AD4130_INT_PIN_DOUT) 1673 return dev_err_probe(dev, -EINVAL, 1674 "Cannot use DOUT as interrupt pin\n"); 1675 1676 if (st->int_pin_sel == AD4130_INT_PIN_P2) 1677 st->pins_fn[AD4130_AIN3_P2] = AD4130_PIN_FN_SPECIAL; 1678 1679 device_property_read_u32(dev, "adi,ext-clk-freq-hz", &ext_clk_freq); 1680 if (ext_clk_freq != AD4130_MCLK_FREQ_153_6KHZ && 1681 ext_clk_freq != AD4130_MCLK_FREQ_76_8KHZ) 1682 return dev_err_probe(dev, -EINVAL, 1683 "Invalid external clock frequency %u\n", 1684 ext_clk_freq); 1685 1686 if (st->mclk && ext_clk_freq == AD4130_MCLK_FREQ_153_6KHZ) 1687 st->mclk_sel = AD4130_MCLK_153_6KHZ_EXT; 1688 else if (st->mclk) 1689 st->mclk_sel = AD4130_MCLK_76_8KHZ_EXT; 1690 else 1691 st->mclk_sel = AD4130_MCLK_76_8KHZ; 1692 1693 if (st->int_pin_sel == AD4130_INT_PIN_CLK && 1694 st->mclk_sel != AD4130_MCLK_76_8KHZ) 1695 return dev_err_probe(dev, -EINVAL, 1696 "Invalid clock %u for interrupt pin %u\n", 1697 st->mclk_sel, st->int_pin_sel); 1698 1699 st->int_ref_uv = AD4130_INT_REF_2_5V; 1700 1701 /* 1702 * When the AVDD supply is set to below 2.5V the internal reference of 1703 * 1.25V should be selected. 1704 * See datasheet page 37, section ADC REFERENCE. 1705 */ 1706 avdd_uv = regulator_get_voltage(st->regulators[0].consumer); 1707 if (avdd_uv > 0 && avdd_uv < AD4130_INT_REF_2_5V) 1708 st->int_ref_uv = AD4130_INT_REF_1_25V; 1709 1710 st->bipolar = device_property_read_bool(dev, "adi,bipolar"); 1711 1712 ret = device_property_count_u32(dev, "adi,vbias-pins"); 1713 if (ret > 0) { 1714 if (ret > AD4130_MAX_ANALOG_PINS) 1715 return dev_err_probe(dev, -EINVAL, 1716 "Too many vbias pins %u\n", ret); 1717 1718 st->num_vbias_pins = ret; 1719 1720 ret = device_property_read_u32_array(dev, "adi,vbias-pins", 1721 st->vbias_pins, 1722 st->num_vbias_pins); 1723 if (ret) 1724 return dev_err_probe(dev, ret, 1725 "Failed to read vbias pins\n"); 1726 1727 ret = ad4130_validate_vbias_pins(st, st->vbias_pins, 1728 st->num_vbias_pins); 1729 if (ret) 1730 return ret; 1731 } 1732 1733 ret = ad4130_parse_fw_children(indio_dev); 1734 if (ret) 1735 return ret; 1736 1737 return 0; 1738 } 1739 1740 static void ad4130_fill_scale_tbls(struct ad4130_state *st) 1741 { 1742 unsigned int pow = ad4130_resolution(st) - st->bipolar; 1743 unsigned int i, j; 1744 1745 for (i = 0; i < AD4130_REF_SEL_MAX; i++) { 1746 int ret; 1747 u64 nv; 1748 1749 ret = ad4130_get_ref_voltage(st, i); 1750 if (ret < 0) 1751 continue; 1752 1753 nv = (u64)ret * NANO; 1754 1755 for (j = 0; j < AD4130_MAX_PGA; j++) 1756 st->scale_tbls[i][j][1] = div_u64(nv >> (pow + j), MILLI); 1757 } 1758 } 1759 1760 static void ad4130_clk_disable_unprepare(void *clk) 1761 { 1762 clk_disable_unprepare(clk); 1763 } 1764 1765 static int ad4130_set_mclk_sel(struct ad4130_state *st, 1766 enum ad4130_mclk_sel mclk_sel) 1767 { 1768 return regmap_update_bits(st->regmap, AD4130_ADC_CONTROL_REG, 1769 AD4130_ADC_CONTROL_MCLK_SEL_MASK, 1770 FIELD_PREP(AD4130_ADC_CONTROL_MCLK_SEL_MASK, 1771 mclk_sel)); 1772 } 1773 1774 static unsigned long ad4130_int_clk_recalc_rate(struct clk_hw *hw, 1775 unsigned long parent_rate) 1776 { 1777 return AD4130_MCLK_FREQ_76_8KHZ; 1778 } 1779 1780 static int ad4130_int_clk_is_enabled(struct clk_hw *hw) 1781 { 1782 struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw); 1783 1784 return st->mclk_sel == AD4130_MCLK_76_8KHZ_OUT; 1785 } 1786 1787 static int ad4130_int_clk_prepare(struct clk_hw *hw) 1788 { 1789 struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw); 1790 int ret; 1791 1792 ret = ad4130_set_mclk_sel(st, AD4130_MCLK_76_8KHZ_OUT); 1793 if (ret) 1794 return ret; 1795 1796 st->mclk_sel = AD4130_MCLK_76_8KHZ_OUT; 1797 1798 return 0; 1799 } 1800 1801 static void ad4130_int_clk_unprepare(struct clk_hw *hw) 1802 { 1803 struct ad4130_state *st = container_of(hw, struct ad4130_state, int_clk_hw); 1804 int ret; 1805 1806 ret = ad4130_set_mclk_sel(st, AD4130_MCLK_76_8KHZ); 1807 if (ret) 1808 return; 1809 1810 st->mclk_sel = AD4130_MCLK_76_8KHZ; 1811 } 1812 1813 static const struct clk_ops ad4130_int_clk_ops = { 1814 .recalc_rate = ad4130_int_clk_recalc_rate, 1815 .is_enabled = ad4130_int_clk_is_enabled, 1816 .prepare = ad4130_int_clk_prepare, 1817 .unprepare = ad4130_int_clk_unprepare, 1818 }; 1819 1820 static int ad4130_setup_int_clk(struct ad4130_state *st) 1821 { 1822 struct device *dev = &st->spi->dev; 1823 struct device_node *of_node = dev_of_node(dev); 1824 struct clk_init_data init; 1825 const char *clk_name; 1826 struct clk *clk; 1827 1828 if (st->int_pin_sel == AD4130_INT_PIN_CLK || 1829 st->mclk_sel != AD4130_MCLK_76_8KHZ) 1830 return 0; 1831 1832 if (!of_node) 1833 return 0; 1834 1835 clk_name = of_node->name; 1836 of_property_read_string(of_node, "clock-output-names", &clk_name); 1837 1838 init.name = clk_name; 1839 init.ops = &ad4130_int_clk_ops; 1840 1841 st->int_clk_hw.init = &init; 1842 clk = devm_clk_register(dev, &st->int_clk_hw); 1843 if (IS_ERR(clk)) 1844 return PTR_ERR(clk); 1845 1846 return of_clk_add_provider(of_node, of_clk_src_simple_get, clk); 1847 } 1848 1849 static int ad4130_setup(struct iio_dev *indio_dev) 1850 { 1851 struct ad4130_state *st = iio_priv(indio_dev); 1852 struct device *dev = &st->spi->dev; 1853 unsigned int int_ref_val; 1854 unsigned long rate = AD4130_MCLK_FREQ_76_8KHZ; 1855 unsigned int val; 1856 unsigned int i; 1857 int ret; 1858 1859 if (st->mclk_sel == AD4130_MCLK_153_6KHZ_EXT) 1860 rate = AD4130_MCLK_FREQ_153_6KHZ; 1861 1862 ret = clk_set_rate(st->mclk, rate); 1863 if (ret) 1864 return ret; 1865 1866 ret = clk_prepare_enable(st->mclk); 1867 if (ret) 1868 return ret; 1869 1870 ret = devm_add_action_or_reset(dev, ad4130_clk_disable_unprepare, 1871 st->mclk); 1872 if (ret) 1873 return ret; 1874 1875 if (st->int_ref_uv == AD4130_INT_REF_2_5V) 1876 int_ref_val = AD4130_INT_REF_VAL_2_5V; 1877 else 1878 int_ref_val = AD4130_INT_REF_VAL_1_25V; 1879 1880 /* Switch to SPI 4-wire mode. */ 1881 val = FIELD_PREP(AD4130_ADC_CONTROL_CSB_EN_MASK, 1); 1882 val |= FIELD_PREP(AD4130_ADC_CONTROL_BIPOLAR_MASK, st->bipolar); 1883 val |= FIELD_PREP(AD4130_ADC_CONTROL_INT_REF_EN_MASK, st->int_ref_en); 1884 val |= FIELD_PREP(AD4130_ADC_CONTROL_MODE_MASK, AD4130_MODE_IDLE); 1885 val |= FIELD_PREP(AD4130_ADC_CONTROL_MCLK_SEL_MASK, st->mclk_sel); 1886 val |= FIELD_PREP(AD4130_ADC_CONTROL_INT_REF_VAL_MASK, int_ref_val); 1887 1888 ret = regmap_write(st->regmap, AD4130_ADC_CONTROL_REG, val); 1889 if (ret) 1890 return ret; 1891 1892 /* 1893 * Configure all GPIOs for output. If configured, the interrupt function 1894 * of P2 takes priority over the GPIO out function. 1895 */ 1896 val = AD4130_IO_CONTROL_GPIO_CTRL_MASK; 1897 val |= FIELD_PREP(AD4130_IO_CONTROL_INT_PIN_SEL_MASK, st->int_pin_sel); 1898 1899 ret = regmap_write(st->regmap, AD4130_IO_CONTROL_REG, val); 1900 if (ret) 1901 return ret; 1902 1903 val = 0; 1904 for (i = 0; i < st->num_vbias_pins; i++) 1905 val |= BIT(st->vbias_pins[i]); 1906 1907 ret = regmap_write(st->regmap, AD4130_VBIAS_REG, val); 1908 if (ret) 1909 return ret; 1910 1911 ret = regmap_update_bits(st->regmap, AD4130_FIFO_CONTROL_REG, 1912 AD4130_FIFO_CONTROL_HEADER_MASK, 0); 1913 if (ret) 1914 return ret; 1915 1916 /* FIFO watermark interrupt starts out as enabled, disable it. */ 1917 ret = ad4130_set_watermark_interrupt_en(st, false); 1918 if (ret) 1919 return ret; 1920 1921 /* Setup channels. */ 1922 for (i = 0; i < indio_dev->num_channels; i++) { 1923 struct ad4130_chan_info *chan_info = &st->chans_info[i]; 1924 struct iio_chan_spec *chan = &st->chans[i]; 1925 unsigned int val; 1926 1927 val = FIELD_PREP(AD4130_CHANNEL_AINP_MASK, chan->channel) | 1928 FIELD_PREP(AD4130_CHANNEL_AINM_MASK, chan->channel2) | 1929 FIELD_PREP(AD4130_CHANNEL_IOUT1_MASK, chan_info->iout0) | 1930 FIELD_PREP(AD4130_CHANNEL_IOUT2_MASK, chan_info->iout1); 1931 1932 ret = regmap_write(st->regmap, AD4130_CHANNEL_X_REG(i), val); 1933 if (ret) 1934 return ret; 1935 } 1936 1937 return 0; 1938 } 1939 1940 static int ad4130_soft_reset(struct ad4130_state *st) 1941 { 1942 int ret; 1943 1944 ret = spi_write(st->spi, st->reset_buf, sizeof(st->reset_buf)); 1945 if (ret) 1946 return ret; 1947 1948 fsleep(AD4130_RESET_SLEEP_US); 1949 1950 return 0; 1951 } 1952 1953 static void ad4130_disable_regulators(void *data) 1954 { 1955 struct ad4130_state *st = data; 1956 1957 regulator_bulk_disable(ARRAY_SIZE(st->regulators), st->regulators); 1958 } 1959 1960 static int ad4130_probe(struct spi_device *spi) 1961 { 1962 struct device *dev = &spi->dev; 1963 struct iio_dev *indio_dev; 1964 struct ad4130_state *st; 1965 int ret; 1966 1967 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 1968 if (!indio_dev) 1969 return -ENOMEM; 1970 1971 st = iio_priv(indio_dev); 1972 1973 memset(st->reset_buf, 0xff, sizeof(st->reset_buf)); 1974 init_completion(&st->completion); 1975 mutex_init(&st->lock); 1976 st->spi = spi; 1977 1978 /* 1979 * Xfer: [ XFR1 ] [ XFR2 ] 1980 * Master: 0x7D N ...................... 1981 * Slave: ...... DATA1 DATA2 ... DATAN 1982 */ 1983 st->fifo_tx_buf[0] = AD4130_COMMS_READ_MASK | AD4130_FIFO_DATA_REG; 1984 st->fifo_xfer[0].tx_buf = st->fifo_tx_buf; 1985 st->fifo_xfer[0].len = sizeof(st->fifo_tx_buf); 1986 st->fifo_xfer[1].rx_buf = st->fifo_rx_buf; 1987 spi_message_init_with_transfers(&st->fifo_msg, st->fifo_xfer, 1988 ARRAY_SIZE(st->fifo_xfer)); 1989 1990 indio_dev->name = AD4130_NAME; 1991 indio_dev->modes = INDIO_DIRECT_MODE; 1992 indio_dev->info = &ad4130_info; 1993 1994 st->regmap = devm_regmap_init(dev, NULL, st, &ad4130_regmap_config); 1995 if (IS_ERR(st->regmap)) 1996 return PTR_ERR(st->regmap); 1997 1998 st->regulators[0].supply = "avdd"; 1999 st->regulators[1].supply = "iovdd"; 2000 st->regulators[2].supply = "refin1"; 2001 st->regulators[3].supply = "refin2"; 2002 2003 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(st->regulators), 2004 st->regulators); 2005 if (ret) 2006 return dev_err_probe(dev, ret, "Failed to get regulators\n"); 2007 2008 ret = regulator_bulk_enable(ARRAY_SIZE(st->regulators), st->regulators); 2009 if (ret) 2010 return dev_err_probe(dev, ret, "Failed to enable regulators\n"); 2011 2012 ret = devm_add_action_or_reset(dev, ad4130_disable_regulators, st); 2013 if (ret) 2014 return dev_err_probe(dev, ret, 2015 "Failed to add regulators disable action\n"); 2016 2017 ret = ad4130_soft_reset(st); 2018 if (ret) 2019 return ret; 2020 2021 ret = ad4310_parse_fw(indio_dev); 2022 if (ret) 2023 return ret; 2024 2025 ret = ad4130_setup(indio_dev); 2026 if (ret) 2027 return ret; 2028 2029 ret = ad4130_setup_int_clk(st); 2030 if (ret) 2031 return ret; 2032 2033 ad4130_fill_scale_tbls(st); 2034 2035 st->gc.owner = THIS_MODULE; 2036 st->gc.label = AD4130_NAME; 2037 st->gc.base = -1; 2038 st->gc.ngpio = AD4130_MAX_GPIOS; 2039 st->gc.parent = dev; 2040 st->gc.can_sleep = true; 2041 st->gc.init_valid_mask = ad4130_gpio_init_valid_mask; 2042 st->gc.get_direction = ad4130_gpio_get_direction; 2043 st->gc.set = ad4130_gpio_set; 2044 2045 ret = devm_gpiochip_add_data(dev, &st->gc, st); 2046 if (ret) 2047 return ret; 2048 2049 ret = devm_iio_kfifo_buffer_setup_ext(dev, indio_dev, 2050 &ad4130_buffer_ops, 2051 ad4130_fifo_attributes); 2052 if (ret) 2053 return ret; 2054 2055 ret = devm_request_threaded_irq(dev, spi->irq, NULL, 2056 ad4130_irq_handler, IRQF_ONESHOT, 2057 indio_dev->name, indio_dev); 2058 if (ret) 2059 return dev_err_probe(dev, ret, "Failed to request irq\n"); 2060 2061 /* 2062 * When the chip enters FIFO mode, IRQ polarity is inverted. 2063 * When the chip exits FIFO mode, IRQ polarity returns to normal. 2064 * See datasheet pages: 65, FIFO Watermark Interrupt section, 2065 * and 71, Bit Descriptions for STATUS Register, RDYB. 2066 * Cache the normal and inverted IRQ triggers to set them when 2067 * entering and exiting FIFO mode. 2068 */ 2069 st->irq_trigger = irq_get_trigger_type(spi->irq); 2070 if (st->irq_trigger & IRQF_TRIGGER_RISING) 2071 st->inv_irq_trigger = IRQF_TRIGGER_FALLING; 2072 else if (st->irq_trigger & IRQF_TRIGGER_FALLING) 2073 st->inv_irq_trigger = IRQF_TRIGGER_RISING; 2074 else 2075 return dev_err_probe(dev, -EINVAL, "Invalid irq flags: %u\n", 2076 st->irq_trigger); 2077 2078 return devm_iio_device_register(dev, indio_dev); 2079 } 2080 2081 static const struct of_device_id ad4130_of_match[] = { 2082 { 2083 .compatible = "adi,ad4130", 2084 }, 2085 { } 2086 }; 2087 MODULE_DEVICE_TABLE(of, ad4130_of_match); 2088 2089 static struct spi_driver ad4130_driver = { 2090 .driver = { 2091 .name = AD4130_NAME, 2092 .of_match_table = ad4130_of_match, 2093 }, 2094 .probe = ad4130_probe, 2095 }; 2096 module_spi_driver(ad4130_driver); 2097 2098 MODULE_AUTHOR("Cosmin Tanislav <cosmin.tanislav@analog.com>"); 2099 MODULE_DESCRIPTION("Analog Devices AD4130 SPI driver"); 2100 MODULE_LICENSE("GPL"); 2101