1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Murata SCA3300 3-axis industrial accelerometer 4 * 5 * Copyright (c) 2021 Vaisala Oyj. All rights reserved. 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/crc8.h> 10 #include <linux/delay.h> 11 #include <linux/kernel.h> 12 #include <linux/module.h> 13 #include <linux/spi/spi.h> 14 15 #include <asm/unaligned.h> 16 17 #include <linux/iio/buffer.h> 18 #include <linux/iio/iio.h> 19 #include <linux/iio/sysfs.h> 20 #include <linux/iio/trigger_consumer.h> 21 #include <linux/iio/triggered_buffer.h> 22 23 #define SCA3300_ALIAS "sca3300" 24 25 #define SCA3300_CRC8_POLYNOMIAL 0x1d 26 27 /* Device mode register */ 28 #define SCA3300_REG_MODE 0xd 29 #define SCA3300_MODE_SW_RESET 0x20 30 31 /* Last register in map */ 32 #define SCA3300_REG_SELBANK 0x1f 33 34 /* Device status and mask */ 35 #define SCA3300_REG_STATUS 0x6 36 #define SCA3300_STATUS_MASK GENMASK(8, 0) 37 38 /* Device ID */ 39 #define SCA3300_REG_WHOAMI 0x10 40 #define SCA3300_WHOAMI_ID 0x51 41 #define SCL3300_WHOAMI_ID 0xC1 42 43 /* Device return status and mask */ 44 #define SCA3300_VALUE_RS_ERROR 0x3 45 #define SCA3300_MASK_RS_STATUS GENMASK(1, 0) 46 47 #define SCL3300_REG_ANG_CTRL 0x0C 48 #define SCL3300_ANG_ENABLE 0x1F 49 50 enum sca3300_scan_indexes { 51 SCA3300_ACC_X = 0, 52 SCA3300_ACC_Y, 53 SCA3300_ACC_Z, 54 SCA3300_TEMP, 55 SCA3300_TIMESTAMP, 56 SCA3300_INCLI_X, 57 SCA3300_INCLI_Y, 58 SCA3300_INCLI_Z, 59 }; 60 61 #define SCA3300_ACCEL_CHANNEL(index, reg, axis) { \ 62 .type = IIO_ACCEL, \ 63 .address = reg, \ 64 .modified = 1, \ 65 .channel2 = IIO_MOD_##axis, \ 66 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 67 .info_mask_shared_by_type = \ 68 BIT(IIO_CHAN_INFO_SCALE) | \ 69 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 70 .info_mask_shared_by_type_available = \ 71 BIT(IIO_CHAN_INFO_SCALE) | \ 72 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \ 73 .scan_index = index, \ 74 .scan_type = { \ 75 .sign = 's', \ 76 .realbits = 16, \ 77 .storagebits = 16, \ 78 .endianness = IIO_CPU, \ 79 }, \ 80 } 81 82 #define SCA3300_INCLI_CHANNEL(index, reg, axis) { \ 83 .type = IIO_INCLI, \ 84 .address = reg, \ 85 .modified = 1, \ 86 .channel2 = IIO_MOD_##axis, \ 87 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 88 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 89 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \ 90 .scan_index = index, \ 91 .scan_type = { \ 92 .sign = 's', \ 93 .realbits = 16, \ 94 .storagebits = 16, \ 95 .endianness = IIO_CPU, \ 96 }, \ 97 } 98 99 #define SCA3300_TEMP_CHANNEL(index, reg) { \ 100 .type = IIO_TEMP, \ 101 .address = reg, \ 102 .scan_index = index, \ 103 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 104 .scan_type = { \ 105 .sign = 's', \ 106 .realbits = 16, \ 107 .storagebits = 16, \ 108 .endianness = IIO_CPU, \ 109 }, \ 110 } 111 112 static const struct iio_chan_spec sca3300_channels[] = { 113 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_X, 0x1, X), 114 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Y, 0x2, Y), 115 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Z, 0x3, Z), 116 SCA3300_TEMP_CHANNEL(SCA3300_TEMP, 0x05), 117 IIO_CHAN_SOFT_TIMESTAMP(4), 118 }; 119 120 static const int sca3300_lp_freq[] = {70, 10}; 121 static const int sca3300_lp_freq_map[] = {0, 0, 0, 1}; 122 123 static const int scl3300_lp_freq[] = {40, 70, 10}; 124 static const int scl3300_lp_freq_map[] = {0, 1, 2}; 125 126 static const int sca3300_accel_scale[][2] = {{0, 370}, {0, 741}, {0, 185}}; 127 static const int sca3300_accel_scale_map[] = {0, 1, 2, 2}; 128 129 static const int scl3300_accel_scale[][2] = {{0, 167}, {0, 333}, {0, 83}}; 130 static const int scl3300_accel_scale_map[] = {0, 1, 2}; 131 132 static const int scl3300_incli_scale[][2] = {{0, 5495}}; 133 static const int scl3300_incli_scale_map[] = {0, 0, 0}; 134 135 static const int sca3300_avail_modes_map[] = {0, 1, 2, 3}; 136 static const int scl3300_avail_modes_map[] = {0, 1, 3}; 137 138 static const struct iio_chan_spec scl3300_channels[] = { 139 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_X, 0x1, X), 140 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Y, 0x2, Y), 141 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Z, 0x3, Z), 142 SCA3300_TEMP_CHANNEL(SCA3300_TEMP, 0x05), 143 IIO_CHAN_SOFT_TIMESTAMP(4), 144 SCA3300_INCLI_CHANNEL(SCA3300_INCLI_X, 0x09, X), 145 SCA3300_INCLI_CHANNEL(SCA3300_INCLI_Y, 0x0A, Y), 146 SCA3300_INCLI_CHANNEL(SCA3300_INCLI_Z, 0x0B, Z), 147 }; 148 149 static const unsigned long sca3300_scan_masks[] = { 150 BIT(SCA3300_ACC_X) | BIT(SCA3300_ACC_Y) | BIT(SCA3300_ACC_Z) | 151 BIT(SCA3300_TEMP), 152 0 153 }; 154 155 static const unsigned long scl3300_scan_masks[] = { 156 BIT(SCA3300_ACC_X) | BIT(SCA3300_ACC_Y) | BIT(SCA3300_ACC_Z) | 157 BIT(SCA3300_TEMP) | 158 BIT(SCA3300_INCLI_X) | BIT(SCA3300_INCLI_Y) | BIT(SCA3300_INCLI_Z), 159 0 160 }; 161 162 struct sca3300_chip_info { 163 const char *name; 164 const unsigned long *scan_masks; 165 const struct iio_chan_spec *channels; 166 u8 num_channels; 167 u8 num_accel_scales; 168 const int (*accel_scale)[2]; 169 const int *accel_scale_map; 170 const int (*incli_scale)[2]; 171 const int *incli_scale_map; 172 u8 num_incli_scales; 173 u8 num_freqs; 174 const int *freq_table; 175 const int *freq_map; 176 const int *avail_modes_table; 177 u8 num_avail_modes; 178 u8 chip_id; 179 bool angle_supported; 180 }; 181 182 /** 183 * struct sca3300_data - device data 184 * @spi: SPI device structure 185 * @lock: Data buffer lock 186 * @chip: Sensor chip specific information 187 * @scan: Triggered buffer. Four channel 16-bit data + 64-bit timestamp 188 * @txbuf: Transmit buffer 189 * @rxbuf: Receive buffer 190 */ 191 struct sca3300_data { 192 struct spi_device *spi; 193 struct mutex lock; 194 const struct sca3300_chip_info *chip; 195 struct { 196 s16 channels[4]; 197 s64 ts __aligned(sizeof(s64)); 198 } scan; 199 u8 txbuf[4] __aligned(IIO_DMA_MINALIGN); 200 u8 rxbuf[4]; 201 }; 202 203 static const struct sca3300_chip_info sca3300_chip_tbl[] = { 204 { 205 .name = "sca3300", 206 .scan_masks = sca3300_scan_masks, 207 .channels = sca3300_channels, 208 .num_channels = ARRAY_SIZE(sca3300_channels), 209 .num_accel_scales = ARRAY_SIZE(sca3300_accel_scale)*2, 210 .accel_scale = sca3300_accel_scale, 211 .accel_scale_map = sca3300_accel_scale_map, 212 .num_freqs = ARRAY_SIZE(sca3300_lp_freq), 213 .freq_table = sca3300_lp_freq, 214 .freq_map = sca3300_lp_freq_map, 215 .avail_modes_table = sca3300_avail_modes_map, 216 .num_avail_modes = 4, 217 .chip_id = SCA3300_WHOAMI_ID, 218 .angle_supported = false, 219 }, 220 { 221 .name = "scl3300", 222 .scan_masks = scl3300_scan_masks, 223 .channels = scl3300_channels, 224 .num_channels = ARRAY_SIZE(scl3300_channels), 225 .num_accel_scales = ARRAY_SIZE(scl3300_accel_scale)*2, 226 .accel_scale = scl3300_accel_scale, 227 .accel_scale_map = scl3300_accel_scale_map, 228 .incli_scale = scl3300_incli_scale, 229 .incli_scale_map = scl3300_incli_scale_map, 230 .num_incli_scales = ARRAY_SIZE(scl3300_incli_scale)*2, 231 .num_freqs = ARRAY_SIZE(scl3300_lp_freq), 232 .freq_table = scl3300_lp_freq, 233 .freq_map = scl3300_lp_freq_map, 234 .avail_modes_table = scl3300_avail_modes_map, 235 .num_avail_modes = 3, 236 .chip_id = SCL3300_WHOAMI_ID, 237 .angle_supported = true, 238 }, 239 }; 240 241 DECLARE_CRC8_TABLE(sca3300_crc_table); 242 243 static int sca3300_transfer(struct sca3300_data *sca_data, int *val) 244 { 245 /* Consecutive requests min. 10 us delay (Datasheet section 5.1.2) */ 246 struct spi_delay delay = { .value = 10, .unit = SPI_DELAY_UNIT_USECS }; 247 int32_t ret; 248 int rs; 249 u8 crc; 250 struct spi_transfer xfers[2] = { 251 { 252 .tx_buf = sca_data->txbuf, 253 .len = ARRAY_SIZE(sca_data->txbuf), 254 .delay = delay, 255 .cs_change = 1, 256 }, 257 { 258 .rx_buf = sca_data->rxbuf, 259 .len = ARRAY_SIZE(sca_data->rxbuf), 260 .delay = delay, 261 } 262 }; 263 264 /* inverted crc value as described in device data sheet */ 265 crc = ~crc8(sca3300_crc_table, &sca_data->txbuf[0], 3, CRC8_INIT_VALUE); 266 sca_data->txbuf[3] = crc; 267 268 ret = spi_sync_transfer(sca_data->spi, xfers, ARRAY_SIZE(xfers)); 269 if (ret) { 270 dev_err(&sca_data->spi->dev, 271 "transfer error, error: %d\n", ret); 272 return -EIO; 273 } 274 275 crc = ~crc8(sca3300_crc_table, &sca_data->rxbuf[0], 3, CRC8_INIT_VALUE); 276 if (sca_data->rxbuf[3] != crc) { 277 dev_err(&sca_data->spi->dev, "CRC checksum mismatch"); 278 return -EIO; 279 } 280 281 /* get return status */ 282 rs = sca_data->rxbuf[0] & SCA3300_MASK_RS_STATUS; 283 if (rs == SCA3300_VALUE_RS_ERROR) 284 ret = -EINVAL; 285 286 *val = sign_extend32(get_unaligned_be16(&sca_data->rxbuf[1]), 15); 287 288 return ret; 289 } 290 291 static int sca3300_error_handler(struct sca3300_data *sca_data) 292 { 293 int ret; 294 int val; 295 296 mutex_lock(&sca_data->lock); 297 sca_data->txbuf[0] = SCA3300_REG_STATUS << 2; 298 ret = sca3300_transfer(sca_data, &val); 299 mutex_unlock(&sca_data->lock); 300 /* 301 * Return status error is cleared after reading status register once, 302 * expect EINVAL here. 303 */ 304 if (ret != -EINVAL) { 305 dev_err(&sca_data->spi->dev, 306 "error reading device status: %d\n", ret); 307 return ret; 308 } 309 310 dev_err(&sca_data->spi->dev, "device status: 0x%lx\n", 311 val & SCA3300_STATUS_MASK); 312 313 return 0; 314 } 315 316 static int sca3300_read_reg(struct sca3300_data *sca_data, u8 reg, int *val) 317 { 318 int ret; 319 320 mutex_lock(&sca_data->lock); 321 sca_data->txbuf[0] = reg << 2; 322 ret = sca3300_transfer(sca_data, val); 323 mutex_unlock(&sca_data->lock); 324 if (ret != -EINVAL) 325 return ret; 326 327 return sca3300_error_handler(sca_data); 328 } 329 330 static int sca3300_write_reg(struct sca3300_data *sca_data, u8 reg, int val) 331 { 332 int reg_val = 0; 333 int ret; 334 335 mutex_lock(&sca_data->lock); 336 /* BIT(7) for write operation */ 337 sca_data->txbuf[0] = BIT(7) | (reg << 2); 338 put_unaligned_be16(val, &sca_data->txbuf[1]); 339 ret = sca3300_transfer(sca_data, ®_val); 340 mutex_unlock(&sca_data->lock); 341 if (ret != -EINVAL) 342 return ret; 343 344 return sca3300_error_handler(sca_data); 345 } 346 347 static int sca3300_set_op_mode(struct sca3300_data *sca_data, int index) 348 { 349 if ((index < 0) || (index >= sca_data->chip->num_avail_modes)) 350 return -EINVAL; 351 352 return sca3300_write_reg(sca_data, SCA3300_REG_MODE, 353 sca_data->chip->avail_modes_table[index]); 354 } 355 356 static int sca3300_get_op_mode(struct sca3300_data *sca_data, int *index) 357 { 358 int reg_val; 359 int ret; 360 int i; 361 362 ret = sca3300_read_reg(sca_data, SCA3300_REG_MODE, ®_val); 363 if (ret) 364 return ret; 365 366 for (i = 0; i < sca_data->chip->num_avail_modes; i++) { 367 if (sca_data->chip->avail_modes_table[i] == reg_val) 368 break; 369 } 370 if (i == sca_data->chip->num_avail_modes) 371 return -EINVAL; 372 373 *index = i; 374 return 0; 375 } 376 377 static int sca3300_set_frequency(struct sca3300_data *data, int val) 378 { 379 const struct sca3300_chip_info *chip = data->chip; 380 unsigned int index; 381 int *opmode_scale; 382 int *new_scale; 383 unsigned int i; 384 385 if (sca3300_get_op_mode(data, &index)) 386 return -EINVAL; 387 388 /* 389 * Find a mode in which the requested sampling frequency is available 390 * and the scaling currently set is retained. 391 */ 392 opmode_scale = (int *)chip->accel_scale[chip->accel_scale_map[index]]; 393 for (i = 0; i < chip->num_avail_modes; i++) { 394 new_scale = (int *)chip->accel_scale[chip->accel_scale_map[i]]; 395 if ((val == chip->freq_table[chip->freq_map[i]]) && 396 (opmode_scale[1] == new_scale[1]) && 397 (opmode_scale[0] == new_scale[0])) 398 break; 399 } 400 if (i == chip->num_avail_modes) 401 return -EINVAL; 402 403 return sca3300_set_op_mode(data, i); 404 } 405 406 static int sca3300_write_raw(struct iio_dev *indio_dev, 407 struct iio_chan_spec const *chan, 408 int val, int val2, long mask) 409 { 410 struct sca3300_data *data = iio_priv(indio_dev); 411 int index; 412 int i; 413 414 switch (mask) { 415 case IIO_CHAN_INFO_SCALE: 416 if (chan->type != IIO_ACCEL) 417 return -EINVAL; 418 /* 419 * Letting scale take priority over sampling frequency. 420 * That makes sense given we can only ever end up increasing 421 * the sampling frequency which is unlikely to be a problem. 422 */ 423 for (i = 0; i < data->chip->num_avail_modes; i++) { 424 index = data->chip->accel_scale_map[i]; 425 if ((val == data->chip->accel_scale[index][0]) && 426 (val2 == data->chip->accel_scale[index][1])) 427 return sca3300_set_op_mode(data, i); 428 } 429 return -EINVAL; 430 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 431 return sca3300_set_frequency(data, val); 432 default: 433 return -EINVAL; 434 } 435 } 436 437 static int sca3300_read_raw(struct iio_dev *indio_dev, 438 struct iio_chan_spec const *chan, 439 int *val, int *val2, long mask) 440 { 441 struct sca3300_data *data = iio_priv(indio_dev); 442 int index; 443 int ret; 444 445 switch (mask) { 446 case IIO_CHAN_INFO_RAW: 447 ret = sca3300_read_reg(data, chan->address, val); 448 if (ret) 449 return ret; 450 return IIO_VAL_INT; 451 case IIO_CHAN_INFO_SCALE: 452 ret = sca3300_get_op_mode(data, &index); 453 if (ret) 454 return ret; 455 switch (chan->type) { 456 case IIO_INCLI: 457 index = data->chip->incli_scale_map[index]; 458 *val = data->chip->incli_scale[index][0]; 459 *val2 = data->chip->incli_scale[index][1]; 460 return IIO_VAL_INT_PLUS_MICRO; 461 case IIO_ACCEL: 462 index = data->chip->accel_scale_map[index]; 463 *val = data->chip->accel_scale[index][0]; 464 *val2 = data->chip->accel_scale[index][1]; 465 return IIO_VAL_INT_PLUS_MICRO; 466 default: 467 return -EINVAL; 468 } 469 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 470 ret = sca3300_get_op_mode(data, &index); 471 if (ret) 472 return ret; 473 index = data->chip->freq_map[index]; 474 *val = data->chip->freq_table[index]; 475 return IIO_VAL_INT; 476 default: 477 return -EINVAL; 478 } 479 } 480 481 static irqreturn_t sca3300_trigger_handler(int irq, void *p) 482 { 483 struct iio_poll_func *pf = p; 484 struct iio_dev *indio_dev = pf->indio_dev; 485 struct sca3300_data *data = iio_priv(indio_dev); 486 int bit, ret, val, i = 0; 487 488 for_each_set_bit(bit, indio_dev->active_scan_mask, 489 indio_dev->masklength) { 490 ret = sca3300_read_reg(data, sca3300_channels[bit].address, 491 &val); 492 if (ret) { 493 dev_err_ratelimited(&data->spi->dev, 494 "failed to read register, error: %d\n", ret); 495 /* handled, but bailing out due to errors */ 496 goto out; 497 } 498 data->scan.channels[i++] = val; 499 } 500 501 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan, 502 iio_get_time_ns(indio_dev)); 503 out: 504 iio_trigger_notify_done(indio_dev->trig); 505 506 return IRQ_HANDLED; 507 } 508 509 /* 510 * sca3300_init - Device init sequence. See datasheet rev 2 section 511 * 4.2 Start-Up Sequence for details. 512 */ 513 static int sca3300_init(struct sca3300_data *sca_data, 514 struct iio_dev *indio_dev) 515 { 516 int value = 0; 517 int ret; 518 int i; 519 520 ret = sca3300_write_reg(sca_data, SCA3300_REG_MODE, 521 SCA3300_MODE_SW_RESET); 522 if (ret) 523 return ret; 524 525 /* 526 * Wait 1ms after SW-reset command. 527 * Wait for the settling of signal paths, 528 * 15ms for SCA3300 and 25ms for SCL3300, 529 */ 530 usleep_range(26e3, 50e3); 531 532 ret = sca3300_read_reg(sca_data, SCA3300_REG_WHOAMI, &value); 533 if (ret) 534 return ret; 535 536 for (i = 0; i < ARRAY_SIZE(sca3300_chip_tbl); i++) { 537 if (sca3300_chip_tbl[i].chip_id == value) 538 break; 539 } 540 if (i == ARRAY_SIZE(sca3300_chip_tbl)) { 541 dev_err(&sca_data->spi->dev, "unknown chip id %x\n", value); 542 return -ENODEV; 543 } 544 545 sca_data->chip = &sca3300_chip_tbl[i]; 546 547 if (sca_data->chip->angle_supported) { 548 ret = sca3300_write_reg(sca_data, SCL3300_REG_ANG_CTRL, 549 SCL3300_ANG_ENABLE); 550 if (ret) 551 return ret; 552 } 553 554 return 0; 555 } 556 557 static int sca3300_debugfs_reg_access(struct iio_dev *indio_dev, 558 unsigned int reg, unsigned int writeval, 559 unsigned int *readval) 560 { 561 struct sca3300_data *data = iio_priv(indio_dev); 562 int value; 563 int ret; 564 565 if (reg > SCA3300_REG_SELBANK) 566 return -EINVAL; 567 568 if (!readval) 569 return sca3300_write_reg(data, reg, writeval); 570 571 ret = sca3300_read_reg(data, reg, &value); 572 if (ret) 573 return ret; 574 575 *readval = value; 576 577 return 0; 578 } 579 580 static int sca3300_read_avail(struct iio_dev *indio_dev, 581 struct iio_chan_spec const *chan, 582 const int **vals, int *type, int *length, 583 long mask) 584 { 585 struct sca3300_data *data = iio_priv(indio_dev); 586 switch (mask) { 587 case IIO_CHAN_INFO_SCALE: 588 switch (chan->type) { 589 case IIO_INCLI: 590 *vals = (const int *)data->chip->incli_scale; 591 *length = data->chip->num_incli_scales; 592 *type = IIO_VAL_INT_PLUS_MICRO; 593 return IIO_AVAIL_LIST; 594 case IIO_ACCEL: 595 *vals = (const int *)data->chip->accel_scale; 596 *length = data->chip->num_accel_scales; 597 *type = IIO_VAL_INT_PLUS_MICRO; 598 return IIO_AVAIL_LIST; 599 default: 600 return -EINVAL; 601 } 602 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY: 603 *vals = (const int *)data->chip->freq_table; 604 *length = data->chip->num_freqs; 605 *type = IIO_VAL_INT; 606 return IIO_AVAIL_LIST; 607 default: 608 return -EINVAL; 609 } 610 } 611 612 static const struct iio_info sca3300_info = { 613 .read_raw = sca3300_read_raw, 614 .write_raw = sca3300_write_raw, 615 .debugfs_reg_access = &sca3300_debugfs_reg_access, 616 .read_avail = sca3300_read_avail, 617 }; 618 619 static int sca3300_probe(struct spi_device *spi) 620 { 621 struct sca3300_data *sca_data; 622 struct iio_dev *indio_dev; 623 int ret; 624 625 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*sca_data)); 626 if (!indio_dev) 627 return -ENOMEM; 628 629 sca_data = iio_priv(indio_dev); 630 mutex_init(&sca_data->lock); 631 sca_data->spi = spi; 632 633 crc8_populate_msb(sca3300_crc_table, SCA3300_CRC8_POLYNOMIAL); 634 635 indio_dev->info = &sca3300_info; 636 637 ret = sca3300_init(sca_data, indio_dev); 638 if (ret) { 639 dev_err(&spi->dev, "failed to init device, error: %d\n", ret); 640 return ret; 641 } 642 643 indio_dev->name = sca_data->chip->name; 644 indio_dev->modes = INDIO_DIRECT_MODE; 645 indio_dev->channels = sca_data->chip->channels; 646 indio_dev->num_channels = sca_data->chip->num_channels; 647 indio_dev->available_scan_masks = sca_data->chip->scan_masks; 648 649 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev, 650 iio_pollfunc_store_time, 651 sca3300_trigger_handler, NULL); 652 if (ret) { 653 dev_err(&spi->dev, 654 "iio triggered buffer setup failed, error: %d\n", ret); 655 return ret; 656 } 657 658 ret = devm_iio_device_register(&spi->dev, indio_dev); 659 if (ret) { 660 dev_err(&spi->dev, "iio device register failed, error: %d\n", 661 ret); 662 } 663 664 return ret; 665 } 666 667 static const struct of_device_id sca3300_dt_ids[] = { 668 { .compatible = "murata,sca3300"}, 669 { .compatible = "murata,scl3300"}, 670 {} 671 }; 672 MODULE_DEVICE_TABLE(of, sca3300_dt_ids); 673 674 static struct spi_driver sca3300_driver = { 675 .driver = { 676 .name = SCA3300_ALIAS, 677 .of_match_table = sca3300_dt_ids, 678 }, 679 .probe = sca3300_probe, 680 }; 681 module_spi_driver(sca3300_driver); 682 683 MODULE_AUTHOR("Tomas Melin <tomas.melin@vaisala.com>"); 684 MODULE_DESCRIPTION("Murata SCA3300 SPI Accelerometer"); 685 MODULE_LICENSE("GPL v2"); 686