1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * sca3000_core.c -- support VTI sca3000 series accelerometers via SPI
4 *
5 * Copyright (c) 2009 Jonathan Cameron <jic23@kernel.org>
6 *
7 * See industrialio/accels/sca3000.h for comments.
8 */
9
10 #include <linux/interrupt.h>
11 #include <linux/fs.h>
12 #include <linux/device.h>
13 #include <linux/slab.h>
14 #include <linux/kernel.h>
15 #include <linux/spi/spi.h>
16 #include <linux/sysfs.h>
17 #include <linux/module.h>
18 #include <linux/uaccess.h>
19 #include <linux/iio/iio.h>
20 #include <linux/iio/sysfs.h>
21 #include <linux/iio/events.h>
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/kfifo_buf.h>
24
25 #define SCA3000_WRITE_REG(a) (((a) << 2) | 0x02)
26 #define SCA3000_READ_REG(a) ((a) << 2)
27
28 #define SCA3000_REG_REVID_ADDR 0x00
29 #define SCA3000_REG_REVID_MAJOR_MASK GENMASK(8, 4)
30 #define SCA3000_REG_REVID_MINOR_MASK GENMASK(3, 0)
31
32 #define SCA3000_REG_STATUS_ADDR 0x02
33 #define SCA3000_LOCKED BIT(5)
34 #define SCA3000_EEPROM_CS_ERROR BIT(1)
35 #define SCA3000_SPI_FRAME_ERROR BIT(0)
36
37 /* All reads done using register decrement so no need to directly access LSBs */
38 #define SCA3000_REG_X_MSB_ADDR 0x05
39 #define SCA3000_REG_Y_MSB_ADDR 0x07
40 #define SCA3000_REG_Z_MSB_ADDR 0x09
41
42 #define SCA3000_REG_RING_OUT_ADDR 0x0f
43
44 /* Temp read untested - the e05 doesn't have the sensor */
45 #define SCA3000_REG_TEMP_MSB_ADDR 0x13
46
47 #define SCA3000_REG_MODE_ADDR 0x14
48 #define SCA3000_MODE_PROT_MASK 0x28
49 #define SCA3000_REG_MODE_RING_BUF_ENABLE BIT(7)
50 #define SCA3000_REG_MODE_RING_BUF_8BIT BIT(6)
51
52 /*
53 * Free fall detection triggers an interrupt if the acceleration
54 * is below a threshold for equivalent of 25cm drop
55 */
56 #define SCA3000_REG_MODE_FREE_FALL_DETECT BIT(4)
57 #define SCA3000_REG_MODE_MEAS_MODE_NORMAL 0x00
58 #define SCA3000_REG_MODE_MEAS_MODE_OP_1 0x01
59 #define SCA3000_REG_MODE_MEAS_MODE_OP_2 0x02
60
61 /*
62 * In motion detection mode the accelerations are band pass filtered
63 * (approx 1 - 25Hz) and then a programmable threshold used to trigger
64 * and interrupt.
65 */
66 #define SCA3000_REG_MODE_MEAS_MODE_MOT_DET 0x03
67 #define SCA3000_REG_MODE_MODE_MASK 0x03
68
69 #define SCA3000_REG_BUF_COUNT_ADDR 0x15
70
71 #define SCA3000_REG_INT_STATUS_ADDR 0x16
72 #define SCA3000_REG_INT_STATUS_THREE_QUARTERS BIT(7)
73 #define SCA3000_REG_INT_STATUS_HALF BIT(6)
74
75 #define SCA3000_INT_STATUS_FREE_FALL BIT(3)
76 #define SCA3000_INT_STATUS_Y_TRIGGER BIT(2)
77 #define SCA3000_INT_STATUS_X_TRIGGER BIT(1)
78 #define SCA3000_INT_STATUS_Z_TRIGGER BIT(0)
79
80 /* Used to allow access to multiplexed registers */
81 #define SCA3000_REG_CTRL_SEL_ADDR 0x18
82 /* Only available for SCA3000-D03 and SCA3000-D01 */
83 #define SCA3000_REG_CTRL_SEL_I2C_DISABLE 0x01
84 #define SCA3000_REG_CTRL_SEL_MD_CTRL 0x02
85 #define SCA3000_REG_CTRL_SEL_MD_Y_TH 0x03
86 #define SCA3000_REG_CTRL_SEL_MD_X_TH 0x04
87 #define SCA3000_REG_CTRL_SEL_MD_Z_TH 0x05
88 /*
89 * BE VERY CAREFUL WITH THIS, IF 3 BITS ARE NOT SET the device
90 * will not function
91 */
92 #define SCA3000_REG_CTRL_SEL_OUT_CTRL 0x0B
93
94 #define SCA3000_REG_OUT_CTRL_PROT_MASK 0xE0
95 #define SCA3000_REG_OUT_CTRL_BUF_X_EN 0x10
96 #define SCA3000_REG_OUT_CTRL_BUF_Y_EN 0x08
97 #define SCA3000_REG_OUT_CTRL_BUF_Z_EN 0x04
98 #define SCA3000_REG_OUT_CTRL_BUF_DIV_MASK 0x03
99 #define SCA3000_REG_OUT_CTRL_BUF_DIV_4 0x02
100 #define SCA3000_REG_OUT_CTRL_BUF_DIV_2 0x01
101
102
103 /*
104 * Control which motion detector interrupts are on.
105 * For now only OR combinations are supported.
106 */
107 #define SCA3000_MD_CTRL_PROT_MASK 0xC0
108 #define SCA3000_MD_CTRL_OR_Y BIT(0)
109 #define SCA3000_MD_CTRL_OR_X BIT(1)
110 #define SCA3000_MD_CTRL_OR_Z BIT(2)
111 /* Currently unsupported */
112 #define SCA3000_MD_CTRL_AND_Y BIT(3)
113 #define SCA3000_MD_CTRL_AND_X BIT(4)
114 #define SCA3000_MD_CTRL_AND_Z BIT(5)
115
116 /*
117 * Some control registers of complex access methods requiring this register to
118 * be used to remove a lock.
119 */
120 #define SCA3000_REG_UNLOCK_ADDR 0x1e
121
122 #define SCA3000_REG_INT_MASK_ADDR 0x21
123 #define SCA3000_REG_INT_MASK_PROT_MASK 0x1C
124
125 #define SCA3000_REG_INT_MASK_RING_THREE_QUARTER BIT(7)
126 #define SCA3000_REG_INT_MASK_RING_HALF BIT(6)
127
128 #define SCA3000_REG_INT_MASK_ALL_INTS 0x02
129 #define SCA3000_REG_INT_MASK_ACTIVE_HIGH 0x01
130 #define SCA3000_REG_INT_MASK_ACTIVE_LOW 0x00
131 /* Values of multiplexed registers (write to ctrl_data after select) */
132 #define SCA3000_REG_CTRL_DATA_ADDR 0x22
133
134 /*
135 * Measurement modes available on some sca3000 series chips. Code assumes others
136 * may become available in the future.
137 *
138 * Bypass - Bypass the low-pass filter in the signal channel so as to increase
139 * signal bandwidth.
140 *
141 * Narrow - Narrow low-pass filtering of the signal channel and half output
142 * data rate by decimation.
143 *
144 * Wide - Widen low-pass filtering of signal channel to increase bandwidth
145 */
146 #define SCA3000_OP_MODE_BYPASS 0x01
147 #define SCA3000_OP_MODE_NARROW 0x02
148 #define SCA3000_OP_MODE_WIDE 0x04
149 #define SCA3000_MAX_TX 6
150 #define SCA3000_MAX_RX 2
151
152 /**
153 * struct sca3000_state - device instance state information
154 * @us: the associated spi device
155 * @info: chip variant information
156 * @last_timestamp: the timestamp of the last event
157 * @mo_det_use_count: reference counter for the motion detection unit
158 * @lock: lock used to protect elements of sca3000_state
159 * and the underlying device state.
160 * @tx: dma-able transmit buffer
161 * @rx: dma-able receive buffer
162 **/
163 struct sca3000_state {
164 struct spi_device *us;
165 const struct sca3000_chip_info *info;
166 s64 last_timestamp;
167 int mo_det_use_count;
168 struct mutex lock;
169 /* Can these share a cacheline ? */
170 u8 rx[384] __aligned(IIO_DMA_MINALIGN);
171 u8 tx[6] __aligned(IIO_DMA_MINALIGN);
172 };
173
174 /**
175 * struct sca3000_chip_info - model dependent parameters
176 * @scale: scale * 10^-6
177 * @temp_output: some devices have temperature sensors.
178 * @measurement_mode_freq: normal mode sampling frequency
179 * @measurement_mode_3db_freq: 3db cutoff frequency of the low pass filter for
180 * the normal measurement mode.
181 * @option_mode_1: first optional mode. Not all models have one
182 * @option_mode_1_freq: option mode 1 sampling frequency
183 * @option_mode_1_3db_freq: 3db cutoff frequency of the low pass filter for
184 * the first option mode.
185 * @option_mode_2: second optional mode. Not all chips have one
186 * @option_mode_2_freq: option mode 2 sampling frequency
187 * @option_mode_2_3db_freq: 3db cutoff frequency of the low pass filter for
188 * the second option mode.
189 * @mot_det_mult_xz: Bit wise multipliers to calculate the threshold
190 * for motion detection in the x and z axis.
191 * @mot_det_mult_y: Bit wise multipliers to calculate the threshold
192 * for motion detection in the y axis.
193 *
194 * This structure is used to hold information about the functionality of a given
195 * sca3000 variant.
196 **/
197 struct sca3000_chip_info {
198 unsigned int scale;
199 bool temp_output;
200 int measurement_mode_freq;
201 int measurement_mode_3db_freq;
202 int option_mode_1;
203 int option_mode_1_freq;
204 int option_mode_1_3db_freq;
205 int option_mode_2;
206 int option_mode_2_freq;
207 int option_mode_2_3db_freq;
208 int mot_det_mult_xz[6];
209 int mot_det_mult_y[7];
210 };
211
212 enum sca3000_variant {
213 d01,
214 e02,
215 e04,
216 e05,
217 };
218
219 /*
220 * Note where option modes are not defined, the chip simply does not
221 * support any.
222 * Other chips in the sca3000 series use i2c and are not included here.
223 *
224 * Some of these devices are only listed in the family data sheet and
225 * do not actually appear to be available.
226 */
227 static const struct sca3000_chip_info sca3000_spi_chip_info_tbl[] = {
228 [d01] = {
229 .scale = 7357,
230 .temp_output = true,
231 .measurement_mode_freq = 250,
232 .measurement_mode_3db_freq = 45,
233 .option_mode_1 = SCA3000_OP_MODE_BYPASS,
234 .option_mode_1_freq = 250,
235 .option_mode_1_3db_freq = 70,
236 .mot_det_mult_xz = {50, 100, 200, 350, 650, 1300},
237 .mot_det_mult_y = {50, 100, 150, 250, 450, 850, 1750},
238 },
239 [e02] = {
240 .scale = 9810,
241 .measurement_mode_freq = 125,
242 .measurement_mode_3db_freq = 40,
243 .option_mode_1 = SCA3000_OP_MODE_NARROW,
244 .option_mode_1_freq = 63,
245 .option_mode_1_3db_freq = 11,
246 .mot_det_mult_xz = {100, 150, 300, 550, 1050, 2050},
247 .mot_det_mult_y = {50, 100, 200, 350, 700, 1350, 2700},
248 },
249 [e04] = {
250 .scale = 19620,
251 .measurement_mode_freq = 100,
252 .measurement_mode_3db_freq = 38,
253 .option_mode_1 = SCA3000_OP_MODE_NARROW,
254 .option_mode_1_freq = 50,
255 .option_mode_1_3db_freq = 9,
256 .option_mode_2 = SCA3000_OP_MODE_WIDE,
257 .option_mode_2_freq = 400,
258 .option_mode_2_3db_freq = 70,
259 .mot_det_mult_xz = {200, 300, 600, 1100, 2100, 4100},
260 .mot_det_mult_y = {100, 200, 400, 7000, 1400, 2700, 54000},
261 },
262 [e05] = {
263 .scale = 61313,
264 .measurement_mode_freq = 200,
265 .measurement_mode_3db_freq = 60,
266 .option_mode_1 = SCA3000_OP_MODE_NARROW,
267 .option_mode_1_freq = 50,
268 .option_mode_1_3db_freq = 9,
269 .option_mode_2 = SCA3000_OP_MODE_WIDE,
270 .option_mode_2_freq = 400,
271 .option_mode_2_3db_freq = 75,
272 .mot_det_mult_xz = {600, 900, 1700, 3200, 6100, 11900},
273 .mot_det_mult_y = {300, 600, 1200, 2000, 4100, 7800, 15600},
274 },
275 };
276
sca3000_write_reg(struct sca3000_state * st,u8 address,u8 val)277 static int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val)
278 {
279 st->tx[0] = SCA3000_WRITE_REG(address);
280 st->tx[1] = val;
281 return spi_write(st->us, st->tx, 2);
282 }
283
sca3000_read_data_short(struct sca3000_state * st,u8 reg_address_high,int len)284 static int sca3000_read_data_short(struct sca3000_state *st,
285 u8 reg_address_high,
286 int len)
287 {
288 struct spi_transfer xfer[2] = {
289 {
290 .len = 1,
291 .tx_buf = st->tx,
292 }, {
293 .len = len,
294 .rx_buf = st->rx,
295 }
296 };
297 st->tx[0] = SCA3000_READ_REG(reg_address_high);
298
299 return spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
300 }
301
302 /**
303 * sca3000_reg_lock_on() - test if the ctrl register lock is on
304 * @st: Driver specific device instance data.
305 *
306 * Lock must be held.
307 **/
sca3000_reg_lock_on(struct sca3000_state * st)308 static int sca3000_reg_lock_on(struct sca3000_state *st)
309 {
310 int ret;
311
312 ret = sca3000_read_data_short(st, SCA3000_REG_STATUS_ADDR, 1);
313 if (ret < 0)
314 return ret;
315
316 return !(st->rx[0] & SCA3000_LOCKED);
317 }
318
319 /**
320 * __sca3000_unlock_reg_lock() - unlock the control registers
321 * @st: Driver specific device instance data.
322 *
323 * Note the device does not appear to support doing this in a single transfer.
324 * This should only ever be used as part of ctrl reg read.
325 * Lock must be held before calling this
326 */
__sca3000_unlock_reg_lock(struct sca3000_state * st)327 static int __sca3000_unlock_reg_lock(struct sca3000_state *st)
328 {
329 struct spi_transfer xfer[3] = {
330 {
331 .len = 2,
332 .cs_change = 1,
333 .tx_buf = st->tx,
334 }, {
335 .len = 2,
336 .cs_change = 1,
337 .tx_buf = st->tx + 2,
338 }, {
339 .len = 2,
340 .tx_buf = st->tx + 4,
341 },
342 };
343 st->tx[0] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
344 st->tx[1] = 0x00;
345 st->tx[2] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
346 st->tx[3] = 0x50;
347 st->tx[4] = SCA3000_WRITE_REG(SCA3000_REG_UNLOCK_ADDR);
348 st->tx[5] = 0xA0;
349
350 return spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
351 }
352
353 /**
354 * sca3000_write_ctrl_reg() - write to a lock protect ctrl register
355 * @st: Driver specific device instance data.
356 * @sel: selects which registers we wish to write to
357 * @val: the value to be written
358 *
359 * Certain control registers are protected against overwriting by the lock
360 * register and use a shared write address. This function allows writing of
361 * these registers.
362 * Lock must be held.
363 */
sca3000_write_ctrl_reg(struct sca3000_state * st,u8 sel,uint8_t val)364 static int sca3000_write_ctrl_reg(struct sca3000_state *st,
365 u8 sel,
366 uint8_t val)
367 {
368 int ret;
369
370 ret = sca3000_reg_lock_on(st);
371 if (ret < 0)
372 goto error_ret;
373 if (ret) {
374 ret = __sca3000_unlock_reg_lock(st);
375 if (ret)
376 goto error_ret;
377 }
378
379 /* Set the control select register */
380 ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, sel);
381 if (ret)
382 goto error_ret;
383
384 /* Write the actual value into the register */
385 ret = sca3000_write_reg(st, SCA3000_REG_CTRL_DATA_ADDR, val);
386
387 error_ret:
388 return ret;
389 }
390
391 /**
392 * sca3000_read_ctrl_reg() - read from lock protected control register.
393 * @st: Driver specific device instance data.
394 * @ctrl_reg: Which ctrl register do we want to read.
395 *
396 * Lock must be held.
397 */
sca3000_read_ctrl_reg(struct sca3000_state * st,u8 ctrl_reg)398 static int sca3000_read_ctrl_reg(struct sca3000_state *st,
399 u8 ctrl_reg)
400 {
401 int ret;
402
403 ret = sca3000_reg_lock_on(st);
404 if (ret < 0)
405 goto error_ret;
406 if (ret) {
407 ret = __sca3000_unlock_reg_lock(st);
408 if (ret)
409 goto error_ret;
410 }
411 /* Set the control select register */
412 ret = sca3000_write_reg(st, SCA3000_REG_CTRL_SEL_ADDR, ctrl_reg);
413 if (ret)
414 goto error_ret;
415 ret = sca3000_read_data_short(st, SCA3000_REG_CTRL_DATA_ADDR, 1);
416 if (ret)
417 goto error_ret;
418 return st->rx[0];
419 error_ret:
420 return ret;
421 }
422
423 /**
424 * sca3000_print_rev() - sysfs interface to read the chip revision number
425 * @indio_dev: Device instance specific generic IIO data.
426 * Driver specific device instance data can be obtained via
427 * iio_priv(indio_dev)
428 */
sca3000_print_rev(struct iio_dev * indio_dev)429 static int sca3000_print_rev(struct iio_dev *indio_dev)
430 {
431 int ret;
432 struct sca3000_state *st = iio_priv(indio_dev);
433
434 mutex_lock(&st->lock);
435 ret = sca3000_read_data_short(st, SCA3000_REG_REVID_ADDR, 1);
436 if (ret < 0)
437 goto error_ret;
438 dev_info(&indio_dev->dev,
439 "sca3000 revision major=%lu, minor=%lu\n",
440 st->rx[0] & SCA3000_REG_REVID_MAJOR_MASK,
441 st->rx[0] & SCA3000_REG_REVID_MINOR_MASK);
442 error_ret:
443 mutex_unlock(&st->lock);
444
445 return ret;
446 }
447
448 static ssize_t
sca3000_show_available_3db_freqs(struct device * dev,struct device_attribute * attr,char * buf)449 sca3000_show_available_3db_freqs(struct device *dev,
450 struct device_attribute *attr,
451 char *buf)
452 {
453 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
454 struct sca3000_state *st = iio_priv(indio_dev);
455 int len;
456
457 len = sprintf(buf, "%d", st->info->measurement_mode_3db_freq);
458 if (st->info->option_mode_1)
459 len += sprintf(buf + len, " %d",
460 st->info->option_mode_1_3db_freq);
461 if (st->info->option_mode_2)
462 len += sprintf(buf + len, " %d",
463 st->info->option_mode_2_3db_freq);
464 len += sprintf(buf + len, "\n");
465
466 return len;
467 }
468
469 static IIO_DEVICE_ATTR(in_accel_filter_low_pass_3db_frequency_available,
470 S_IRUGO, sca3000_show_available_3db_freqs,
471 NULL, 0);
472
473 static const struct iio_event_spec sca3000_event = {
474 .type = IIO_EV_TYPE_MAG,
475 .dir = IIO_EV_DIR_RISING,
476 .mask_separate = BIT(IIO_EV_INFO_VALUE) | BIT(IIO_EV_INFO_ENABLE),
477 };
478
479 /*
480 * Note the hack in the number of bits to pretend we have 2 more than
481 * we do in the fifo.
482 */
483 #define SCA3000_CHAN(index, mod) \
484 { \
485 .type = IIO_ACCEL, \
486 .modified = 1, \
487 .channel2 = mod, \
488 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
489 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |\
490 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),\
491 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
492 .address = index, \
493 .scan_index = index, \
494 .scan_type = { \
495 .sign = 's', \
496 .realbits = 13, \
497 .storagebits = 16, \
498 .shift = 3, \
499 .endianness = IIO_BE, \
500 }, \
501 .event_spec = &sca3000_event, \
502 .num_event_specs = 1, \
503 }
504
505 static const struct iio_event_spec sca3000_freefall_event_spec = {
506 .type = IIO_EV_TYPE_MAG,
507 .dir = IIO_EV_DIR_FALLING,
508 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
509 BIT(IIO_EV_INFO_PERIOD),
510 };
511
512 static const struct iio_chan_spec sca3000_channels[] = {
513 SCA3000_CHAN(0, IIO_MOD_X),
514 SCA3000_CHAN(1, IIO_MOD_Y),
515 SCA3000_CHAN(2, IIO_MOD_Z),
516 {
517 .type = IIO_ACCEL,
518 .modified = 1,
519 .channel2 = IIO_MOD_X_AND_Y_AND_Z,
520 .scan_index = -1, /* Fake channel */
521 .event_spec = &sca3000_freefall_event_spec,
522 .num_event_specs = 1,
523 },
524 };
525
526 static const struct iio_chan_spec sca3000_channels_with_temp[] = {
527 SCA3000_CHAN(0, IIO_MOD_X),
528 SCA3000_CHAN(1, IIO_MOD_Y),
529 SCA3000_CHAN(2, IIO_MOD_Z),
530 {
531 .type = IIO_TEMP,
532 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
533 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |
534 BIT(IIO_CHAN_INFO_OFFSET),
535 /* No buffer support */
536 .scan_index = -1,
537 .scan_type = {
538 .sign = 'u',
539 .realbits = 9,
540 .storagebits = 16,
541 .shift = 5,
542 .endianness = IIO_BE,
543 },
544 },
545 {
546 .type = IIO_ACCEL,
547 .modified = 1,
548 .channel2 = IIO_MOD_X_AND_Y_AND_Z,
549 .scan_index = -1, /* Fake channel */
550 .event_spec = &sca3000_freefall_event_spec,
551 .num_event_specs = 1,
552 },
553 };
554
555 static u8 sca3000_addresses[3][3] = {
556 [0] = {SCA3000_REG_X_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_X_TH,
557 SCA3000_MD_CTRL_OR_X},
558 [1] = {SCA3000_REG_Y_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_Y_TH,
559 SCA3000_MD_CTRL_OR_Y},
560 [2] = {SCA3000_REG_Z_MSB_ADDR, SCA3000_REG_CTRL_SEL_MD_Z_TH,
561 SCA3000_MD_CTRL_OR_Z},
562 };
563
564 /**
565 * __sca3000_get_base_freq() - obtain mode specific base frequency
566 * @st: Private driver specific device instance specific state.
567 * @info: chip type specific information.
568 * @base_freq: Base frequency for the current measurement mode.
569 *
570 * lock must be held
571 */
__sca3000_get_base_freq(struct sca3000_state * st,const struct sca3000_chip_info * info,int * base_freq)572 static inline int __sca3000_get_base_freq(struct sca3000_state *st,
573 const struct sca3000_chip_info *info,
574 int *base_freq)
575 {
576 int ret;
577
578 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
579 if (ret)
580 goto error_ret;
581 switch (SCA3000_REG_MODE_MODE_MASK & st->rx[0]) {
582 case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
583 *base_freq = info->measurement_mode_freq;
584 break;
585 case SCA3000_REG_MODE_MEAS_MODE_OP_1:
586 *base_freq = info->option_mode_1_freq;
587 break;
588 case SCA3000_REG_MODE_MEAS_MODE_OP_2:
589 *base_freq = info->option_mode_2_freq;
590 break;
591 default:
592 ret = -EINVAL;
593 }
594 error_ret:
595 return ret;
596 }
597
598 /**
599 * sca3000_read_raw_samp_freq() - read_raw handler for IIO_CHAN_INFO_SAMP_FREQ
600 * @st: Private driver specific device instance specific state.
601 * @val: The frequency read back.
602 *
603 * lock must be held
604 **/
sca3000_read_raw_samp_freq(struct sca3000_state * st,int * val)605 static int sca3000_read_raw_samp_freq(struct sca3000_state *st, int *val)
606 {
607 int ret;
608
609 ret = __sca3000_get_base_freq(st, st->info, val);
610 if (ret)
611 return ret;
612
613 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
614 if (ret < 0)
615 return ret;
616
617 if (*val > 0) {
618 ret &= SCA3000_REG_OUT_CTRL_BUF_DIV_MASK;
619 switch (ret) {
620 case SCA3000_REG_OUT_CTRL_BUF_DIV_2:
621 *val /= 2;
622 break;
623 case SCA3000_REG_OUT_CTRL_BUF_DIV_4:
624 *val /= 4;
625 break;
626 }
627 }
628
629 return 0;
630 }
631
632 /**
633 * sca3000_write_raw_samp_freq() - write_raw handler for IIO_CHAN_INFO_SAMP_FREQ
634 * @st: Private driver specific device instance specific state.
635 * @val: The frequency desired.
636 *
637 * lock must be held
638 */
sca3000_write_raw_samp_freq(struct sca3000_state * st,int val)639 static int sca3000_write_raw_samp_freq(struct sca3000_state *st, int val)
640 {
641 int ret, base_freq, ctrlval;
642
643 ret = __sca3000_get_base_freq(st, st->info, &base_freq);
644 if (ret)
645 return ret;
646
647 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
648 if (ret < 0)
649 return ret;
650
651 ctrlval = ret & ~SCA3000_REG_OUT_CTRL_BUF_DIV_MASK;
652
653 if (val == base_freq / 2)
654 ctrlval |= SCA3000_REG_OUT_CTRL_BUF_DIV_2;
655 if (val == base_freq / 4)
656 ctrlval |= SCA3000_REG_OUT_CTRL_BUF_DIV_4;
657 else if (val != base_freq)
658 return -EINVAL;
659
660 return sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL,
661 ctrlval);
662 }
663
sca3000_read_3db_freq(struct sca3000_state * st,int * val)664 static int sca3000_read_3db_freq(struct sca3000_state *st, int *val)
665 {
666 int ret;
667
668 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
669 if (ret)
670 return ret;
671
672 /* mask bottom 2 bits - only ones that are relevant */
673 st->rx[0] &= SCA3000_REG_MODE_MODE_MASK;
674 switch (st->rx[0]) {
675 case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
676 *val = st->info->measurement_mode_3db_freq;
677 return IIO_VAL_INT;
678 case SCA3000_REG_MODE_MEAS_MODE_MOT_DET:
679 return -EBUSY;
680 case SCA3000_REG_MODE_MEAS_MODE_OP_1:
681 *val = st->info->option_mode_1_3db_freq;
682 return IIO_VAL_INT;
683 case SCA3000_REG_MODE_MEAS_MODE_OP_2:
684 *val = st->info->option_mode_2_3db_freq;
685 return IIO_VAL_INT;
686 default:
687 return -EINVAL;
688 }
689 }
690
sca3000_write_3db_freq(struct sca3000_state * st,int val)691 static int sca3000_write_3db_freq(struct sca3000_state *st, int val)
692 {
693 int ret;
694 int mode;
695
696 if (val == st->info->measurement_mode_3db_freq)
697 mode = SCA3000_REG_MODE_MEAS_MODE_NORMAL;
698 else if (st->info->option_mode_1 &&
699 (val == st->info->option_mode_1_3db_freq))
700 mode = SCA3000_REG_MODE_MEAS_MODE_OP_1;
701 else if (st->info->option_mode_2 &&
702 (val == st->info->option_mode_2_3db_freq))
703 mode = SCA3000_REG_MODE_MEAS_MODE_OP_2;
704 else
705 return -EINVAL;
706 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
707 if (ret)
708 return ret;
709
710 st->rx[0] &= ~SCA3000_REG_MODE_MODE_MASK;
711 st->rx[0] |= (mode & SCA3000_REG_MODE_MODE_MASK);
712
713 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR, st->rx[0]);
714 }
715
sca3000_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)716 static int sca3000_read_raw(struct iio_dev *indio_dev,
717 struct iio_chan_spec const *chan,
718 int *val,
719 int *val2,
720 long mask)
721 {
722 struct sca3000_state *st = iio_priv(indio_dev);
723 int ret;
724 u8 address;
725
726 switch (mask) {
727 case IIO_CHAN_INFO_RAW:
728 mutex_lock(&st->lock);
729 if (chan->type == IIO_ACCEL) {
730 if (st->mo_det_use_count) {
731 mutex_unlock(&st->lock);
732 return -EBUSY;
733 }
734 address = sca3000_addresses[chan->address][0];
735 ret = sca3000_read_data_short(st, address, 2);
736 if (ret < 0) {
737 mutex_unlock(&st->lock);
738 return ret;
739 }
740 *val = sign_extend32(be16_to_cpup((__be16 *)st->rx) >>
741 chan->scan_type.shift,
742 chan->scan_type.realbits - 1);
743 } else {
744 /* get the temperature when available */
745 ret = sca3000_read_data_short(st,
746 SCA3000_REG_TEMP_MSB_ADDR,
747 2);
748 if (ret < 0) {
749 mutex_unlock(&st->lock);
750 return ret;
751 }
752 *val = (be16_to_cpup((__be16 *)st->rx) >>
753 chan->scan_type.shift) &
754 GENMASK(chan->scan_type.realbits - 1, 0);
755 }
756 mutex_unlock(&st->lock);
757 return IIO_VAL_INT;
758 case IIO_CHAN_INFO_SCALE:
759 *val = 0;
760 if (chan->type == IIO_ACCEL)
761 *val2 = st->info->scale;
762 else /* temperature */
763 *val2 = 555556;
764 return IIO_VAL_INT_PLUS_MICRO;
765 case IIO_CHAN_INFO_OFFSET:
766 *val = -214;
767 *val2 = 600000;
768 return IIO_VAL_INT_PLUS_MICRO;
769 case IIO_CHAN_INFO_SAMP_FREQ:
770 mutex_lock(&st->lock);
771 ret = sca3000_read_raw_samp_freq(st, val);
772 mutex_unlock(&st->lock);
773 return ret ? ret : IIO_VAL_INT;
774 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
775 mutex_lock(&st->lock);
776 ret = sca3000_read_3db_freq(st, val);
777 mutex_unlock(&st->lock);
778 return ret;
779 default:
780 return -EINVAL;
781 }
782 }
783
sca3000_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)784 static int sca3000_write_raw(struct iio_dev *indio_dev,
785 struct iio_chan_spec const *chan,
786 int val, int val2, long mask)
787 {
788 struct sca3000_state *st = iio_priv(indio_dev);
789 int ret;
790
791 switch (mask) {
792 case IIO_CHAN_INFO_SAMP_FREQ:
793 if (val2)
794 return -EINVAL;
795 mutex_lock(&st->lock);
796 ret = sca3000_write_raw_samp_freq(st, val);
797 mutex_unlock(&st->lock);
798 return ret;
799 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
800 if (val2)
801 return -EINVAL;
802 mutex_lock(&st->lock);
803 ret = sca3000_write_3db_freq(st, val);
804 mutex_unlock(&st->lock);
805 return ret;
806 default:
807 return -EINVAL;
808 }
809
810 return ret;
811 }
812
813 /**
814 * sca3000_read_av_freq() - sysfs function to get available frequencies
815 * @dev: Device structure for this device.
816 * @attr: Description of the attribute.
817 * @buf: Incoming string
818 *
819 * The later modes are only relevant to the ring buffer - and depend on current
820 * mode. Note that data sheet gives rather wide tolerances for these so integer
821 * division will give good enough answer and not all chips have them specified
822 * at all.
823 **/
sca3000_read_av_freq(struct device * dev,struct device_attribute * attr,char * buf)824 static ssize_t sca3000_read_av_freq(struct device *dev,
825 struct device_attribute *attr,
826 char *buf)
827 {
828 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
829 struct sca3000_state *st = iio_priv(indio_dev);
830 int len = 0, ret, val;
831
832 mutex_lock(&st->lock);
833 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
834 val = st->rx[0];
835 mutex_unlock(&st->lock);
836 if (ret)
837 goto error_ret;
838
839 switch (val & SCA3000_REG_MODE_MODE_MASK) {
840 case SCA3000_REG_MODE_MEAS_MODE_NORMAL:
841 len += sprintf(buf + len, "%d %d %d\n",
842 st->info->measurement_mode_freq,
843 st->info->measurement_mode_freq / 2,
844 st->info->measurement_mode_freq / 4);
845 break;
846 case SCA3000_REG_MODE_MEAS_MODE_OP_1:
847 len += sprintf(buf + len, "%d %d %d\n",
848 st->info->option_mode_1_freq,
849 st->info->option_mode_1_freq / 2,
850 st->info->option_mode_1_freq / 4);
851 break;
852 case SCA3000_REG_MODE_MEAS_MODE_OP_2:
853 len += sprintf(buf + len, "%d %d %d\n",
854 st->info->option_mode_2_freq,
855 st->info->option_mode_2_freq / 2,
856 st->info->option_mode_2_freq / 4);
857 break;
858 }
859 return len;
860 error_ret:
861 return ret;
862 }
863
864 /*
865 * Should only really be registered if ring buffer support is compiled in.
866 * Does no harm however and doing it right would add a fair bit of complexity
867 */
868 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(sca3000_read_av_freq);
869
870 /*
871 * sca3000_read_event_value() - query of a threshold or period
872 */
sca3000_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)873 static int sca3000_read_event_value(struct iio_dev *indio_dev,
874 const struct iio_chan_spec *chan,
875 enum iio_event_type type,
876 enum iio_event_direction dir,
877 enum iio_event_info info,
878 int *val, int *val2)
879 {
880 struct sca3000_state *st = iio_priv(indio_dev);
881 long ret;
882 int i;
883
884 switch (info) {
885 case IIO_EV_INFO_VALUE:
886 mutex_lock(&st->lock);
887 ret = sca3000_read_ctrl_reg(st,
888 sca3000_addresses[chan->address][1]);
889 mutex_unlock(&st->lock);
890 if (ret < 0)
891 return ret;
892 *val = 0;
893 if (chan->channel2 == IIO_MOD_Y)
894 for_each_set_bit(i, &ret,
895 ARRAY_SIZE(st->info->mot_det_mult_y))
896 *val += st->info->mot_det_mult_y[i];
897 else
898 for_each_set_bit(i, &ret,
899 ARRAY_SIZE(st->info->mot_det_mult_xz))
900 *val += st->info->mot_det_mult_xz[i];
901
902 return IIO_VAL_INT;
903 case IIO_EV_INFO_PERIOD:
904 *val = 0;
905 *val2 = 226000;
906 return IIO_VAL_INT_PLUS_MICRO;
907 default:
908 return -EINVAL;
909 }
910 }
911
912 /**
913 * sca3000_write_event_value() - control of threshold and period
914 * @indio_dev: Device instance specific IIO information.
915 * @chan: Description of the channel for which the event is being
916 * configured.
917 * @type: The type of event being configured, here magnitude rising
918 * as everything else is read only.
919 * @dir: Direction of the event (here rising)
920 * @info: What information about the event are we configuring.
921 * Here the threshold only.
922 * @val: Integer part of the value being written..
923 * @val2: Non integer part of the value being written. Here always 0.
924 */
sca3000_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)925 static int sca3000_write_event_value(struct iio_dev *indio_dev,
926 const struct iio_chan_spec *chan,
927 enum iio_event_type type,
928 enum iio_event_direction dir,
929 enum iio_event_info info,
930 int val, int val2)
931 {
932 struct sca3000_state *st = iio_priv(indio_dev);
933 int ret;
934 int i;
935 u8 nonlinear = 0;
936
937 if (chan->channel2 == IIO_MOD_Y) {
938 i = ARRAY_SIZE(st->info->mot_det_mult_y);
939 while (i > 0)
940 if (val >= st->info->mot_det_mult_y[--i]) {
941 nonlinear |= (1 << i);
942 val -= st->info->mot_det_mult_y[i];
943 }
944 } else {
945 i = ARRAY_SIZE(st->info->mot_det_mult_xz);
946 while (i > 0)
947 if (val >= st->info->mot_det_mult_xz[--i]) {
948 nonlinear |= (1 << i);
949 val -= st->info->mot_det_mult_xz[i];
950 }
951 }
952
953 mutex_lock(&st->lock);
954 ret = sca3000_write_ctrl_reg(st,
955 sca3000_addresses[chan->address][1],
956 nonlinear);
957 mutex_unlock(&st->lock);
958
959 return ret;
960 }
961
962 static struct attribute *sca3000_attributes[] = {
963 &iio_dev_attr_in_accel_filter_low_pass_3db_frequency_available.dev_attr.attr,
964 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
965 NULL,
966 };
967
968 static const struct attribute_group sca3000_attribute_group = {
969 .attrs = sca3000_attributes,
970 };
971
sca3000_read_data(struct sca3000_state * st,u8 reg_address_high,u8 * rx,int len)972 static int sca3000_read_data(struct sca3000_state *st,
973 u8 reg_address_high,
974 u8 *rx,
975 int len)
976 {
977 int ret;
978 struct spi_transfer xfer[2] = {
979 {
980 .len = 1,
981 .tx_buf = st->tx,
982 }, {
983 .len = len,
984 .rx_buf = rx,
985 }
986 };
987
988 st->tx[0] = SCA3000_READ_REG(reg_address_high);
989 ret = spi_sync_transfer(st->us, xfer, ARRAY_SIZE(xfer));
990 if (ret) {
991 dev_err(&st->us->dev, "problem reading register\n");
992 return ret;
993 }
994
995 return 0;
996 }
997
998 /**
999 * sca3000_ring_int_process() - ring specific interrupt handling.
1000 * @val: Value of the interrupt status register.
1001 * @indio_dev: Device instance specific IIO device structure.
1002 */
sca3000_ring_int_process(u8 val,struct iio_dev * indio_dev)1003 static void sca3000_ring_int_process(u8 val, struct iio_dev *indio_dev)
1004 {
1005 struct sca3000_state *st = iio_priv(indio_dev);
1006 int ret, i, num_available;
1007
1008 mutex_lock(&st->lock);
1009
1010 if (val & SCA3000_REG_INT_STATUS_HALF) {
1011 ret = sca3000_read_data_short(st, SCA3000_REG_BUF_COUNT_ADDR,
1012 1);
1013 if (ret)
1014 goto error_ret;
1015 num_available = st->rx[0];
1016 /*
1017 * num_available is the total number of samples available
1018 * i.e. number of time points * number of channels.
1019 */
1020 ret = sca3000_read_data(st, SCA3000_REG_RING_OUT_ADDR, st->rx,
1021 num_available * 2);
1022 if (ret)
1023 goto error_ret;
1024 for (i = 0; i < num_available / 3; i++) {
1025 /*
1026 * Dirty hack to cover for 11 bit in fifo, 13 bit
1027 * direct reading.
1028 *
1029 * In theory the bottom two bits are undefined.
1030 * In reality they appear to always be 0.
1031 */
1032 iio_push_to_buffers(indio_dev, st->rx + i * 3 * 2);
1033 }
1034 }
1035 error_ret:
1036 mutex_unlock(&st->lock);
1037 }
1038
1039 /**
1040 * sca3000_event_handler() - handling ring and non ring events
1041 * @irq: The irq being handled.
1042 * @private: struct iio_device pointer for the device.
1043 *
1044 * Ring related interrupt handler. Depending on event, push to
1045 * the ring buffer event chrdev or the event one.
1046 *
1047 * This function is complicated by the fact that the devices can signify ring
1048 * and non ring events via the same interrupt line and they can only
1049 * be distinguished via a read of the relevant status register.
1050 */
sca3000_event_handler(int irq,void * private)1051 static irqreturn_t sca3000_event_handler(int irq, void *private)
1052 {
1053 struct iio_dev *indio_dev = private;
1054 struct sca3000_state *st = iio_priv(indio_dev);
1055 int ret, val;
1056 s64 last_timestamp = iio_get_time_ns(indio_dev);
1057
1058 /*
1059 * Could lead if badly timed to an extra read of status reg,
1060 * but ensures no interrupt is missed.
1061 */
1062 mutex_lock(&st->lock);
1063 ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1);
1064 val = st->rx[0];
1065 mutex_unlock(&st->lock);
1066 if (ret)
1067 goto done;
1068
1069 sca3000_ring_int_process(val, indio_dev);
1070
1071 if (val & SCA3000_INT_STATUS_FREE_FALL)
1072 iio_push_event(indio_dev,
1073 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1074 0,
1075 IIO_MOD_X_AND_Y_AND_Z,
1076 IIO_EV_TYPE_MAG,
1077 IIO_EV_DIR_FALLING),
1078 last_timestamp);
1079
1080 if (val & SCA3000_INT_STATUS_Y_TRIGGER)
1081 iio_push_event(indio_dev,
1082 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1083 0,
1084 IIO_MOD_Y,
1085 IIO_EV_TYPE_MAG,
1086 IIO_EV_DIR_RISING),
1087 last_timestamp);
1088
1089 if (val & SCA3000_INT_STATUS_X_TRIGGER)
1090 iio_push_event(indio_dev,
1091 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1092 0,
1093 IIO_MOD_X,
1094 IIO_EV_TYPE_MAG,
1095 IIO_EV_DIR_RISING),
1096 last_timestamp);
1097
1098 if (val & SCA3000_INT_STATUS_Z_TRIGGER)
1099 iio_push_event(indio_dev,
1100 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1101 0,
1102 IIO_MOD_Z,
1103 IIO_EV_TYPE_MAG,
1104 IIO_EV_DIR_RISING),
1105 last_timestamp);
1106
1107 done:
1108 return IRQ_HANDLED;
1109 }
1110
1111 /*
1112 * sca3000_read_event_config() what events are enabled
1113 */
sca3000_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)1114 static int sca3000_read_event_config(struct iio_dev *indio_dev,
1115 const struct iio_chan_spec *chan,
1116 enum iio_event_type type,
1117 enum iio_event_direction dir)
1118 {
1119 struct sca3000_state *st = iio_priv(indio_dev);
1120 int ret;
1121 /* read current value of mode register */
1122 mutex_lock(&st->lock);
1123
1124 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1125 if (ret)
1126 goto error_ret;
1127
1128 switch (chan->channel2) {
1129 case IIO_MOD_X_AND_Y_AND_Z:
1130 ret = !!(st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT);
1131 break;
1132 case IIO_MOD_X:
1133 case IIO_MOD_Y:
1134 case IIO_MOD_Z:
1135 /*
1136 * Motion detection mode cannot run at the same time as
1137 * acceleration data being read.
1138 */
1139 if ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
1140 != SCA3000_REG_MODE_MEAS_MODE_MOT_DET) {
1141 ret = 0;
1142 } else {
1143 ret = sca3000_read_ctrl_reg(st,
1144 SCA3000_REG_CTRL_SEL_MD_CTRL);
1145 if (ret < 0)
1146 goto error_ret;
1147 /* only supporting logical or's for now */
1148 ret = !!(ret & sca3000_addresses[chan->address][2]);
1149 }
1150 break;
1151 default:
1152 ret = -EINVAL;
1153 }
1154
1155 error_ret:
1156 mutex_unlock(&st->lock);
1157
1158 return ret;
1159 }
1160
sca3000_freefall_set_state(struct iio_dev * indio_dev,int state)1161 static int sca3000_freefall_set_state(struct iio_dev *indio_dev, int state)
1162 {
1163 struct sca3000_state *st = iio_priv(indio_dev);
1164 int ret;
1165
1166 /* read current value of mode register */
1167 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1168 if (ret)
1169 return ret;
1170
1171 /* if off and should be on */
1172 if (state && !(st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT))
1173 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1174 st->rx[0] | SCA3000_REG_MODE_FREE_FALL_DETECT);
1175 /* if on and should be off */
1176 else if (!state && (st->rx[0] & SCA3000_REG_MODE_FREE_FALL_DETECT))
1177 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1178 st->rx[0] & ~SCA3000_REG_MODE_FREE_FALL_DETECT);
1179 else
1180 return 0;
1181 }
1182
sca3000_motion_detect_set_state(struct iio_dev * indio_dev,int axis,int state)1183 static int sca3000_motion_detect_set_state(struct iio_dev *indio_dev, int axis,
1184 int state)
1185 {
1186 struct sca3000_state *st = iio_priv(indio_dev);
1187 int ret, ctrlval;
1188
1189 /*
1190 * First read the motion detector config to find out if
1191 * this axis is on
1192 */
1193 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
1194 if (ret < 0)
1195 return ret;
1196 ctrlval = ret;
1197 /* if off and should be on */
1198 if (state && !(ctrlval & sca3000_addresses[axis][2])) {
1199 ret = sca3000_write_ctrl_reg(st,
1200 SCA3000_REG_CTRL_SEL_MD_CTRL,
1201 ctrlval |
1202 sca3000_addresses[axis][2]);
1203 if (ret)
1204 return ret;
1205 st->mo_det_use_count++;
1206 } else if (!state && (ctrlval & sca3000_addresses[axis][2])) {
1207 ret = sca3000_write_ctrl_reg(st,
1208 SCA3000_REG_CTRL_SEL_MD_CTRL,
1209 ctrlval &
1210 ~(sca3000_addresses[axis][2]));
1211 if (ret)
1212 return ret;
1213 st->mo_det_use_count--;
1214 }
1215
1216 /* read current value of mode register */
1217 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1218 if (ret)
1219 return ret;
1220 /* if off and should be on */
1221 if ((st->mo_det_use_count) &&
1222 ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
1223 != SCA3000_REG_MODE_MEAS_MODE_MOT_DET))
1224 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1225 (st->rx[0] & ~SCA3000_REG_MODE_MODE_MASK)
1226 | SCA3000_REG_MODE_MEAS_MODE_MOT_DET);
1227 /* if on and should be off */
1228 else if (!(st->mo_det_use_count) &&
1229 ((st->rx[0] & SCA3000_REG_MODE_MODE_MASK)
1230 == SCA3000_REG_MODE_MEAS_MODE_MOT_DET))
1231 return sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1232 st->rx[0] & SCA3000_REG_MODE_MODE_MASK);
1233 else
1234 return 0;
1235 }
1236
1237 /**
1238 * sca3000_write_event_config() - simple on off control for motion detector
1239 * @indio_dev: IIO device instance specific structure. Data specific to this
1240 * particular driver may be accessed via iio_priv(indio_dev).
1241 * @chan: Description of the channel whose event we are configuring.
1242 * @type: The type of event.
1243 * @dir: The direction of the event.
1244 * @state: Desired state of event being configured.
1245 *
1246 * This is a per axis control, but enabling any will result in the
1247 * motion detector unit being enabled.
1248 * N.B. enabling motion detector stops normal data acquisition.
1249 * There is a complexity in knowing which mode to return to when
1250 * this mode is disabled. Currently normal mode is assumed.
1251 **/
sca3000_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)1252 static int sca3000_write_event_config(struct iio_dev *indio_dev,
1253 const struct iio_chan_spec *chan,
1254 enum iio_event_type type,
1255 enum iio_event_direction dir,
1256 int state)
1257 {
1258 struct sca3000_state *st = iio_priv(indio_dev);
1259 int ret;
1260
1261 mutex_lock(&st->lock);
1262 switch (chan->channel2) {
1263 case IIO_MOD_X_AND_Y_AND_Z:
1264 ret = sca3000_freefall_set_state(indio_dev, state);
1265 break;
1266
1267 case IIO_MOD_X:
1268 case IIO_MOD_Y:
1269 case IIO_MOD_Z:
1270 ret = sca3000_motion_detect_set_state(indio_dev,
1271 chan->address,
1272 state);
1273 break;
1274 default:
1275 ret = -EINVAL;
1276 break;
1277 }
1278 mutex_unlock(&st->lock);
1279
1280 return ret;
1281 }
1282
1283 static inline
__sca3000_hw_ring_state_set(struct iio_dev * indio_dev,bool state)1284 int __sca3000_hw_ring_state_set(struct iio_dev *indio_dev, bool state)
1285 {
1286 struct sca3000_state *st = iio_priv(indio_dev);
1287 int ret;
1288
1289 mutex_lock(&st->lock);
1290 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1291 if (ret)
1292 goto error_ret;
1293 if (state) {
1294 dev_info(&indio_dev->dev, "supposedly enabling ring buffer\n");
1295 ret = sca3000_write_reg(st,
1296 SCA3000_REG_MODE_ADDR,
1297 (st->rx[0] | SCA3000_REG_MODE_RING_BUF_ENABLE));
1298 } else
1299 ret = sca3000_write_reg(st,
1300 SCA3000_REG_MODE_ADDR,
1301 (st->rx[0] & ~SCA3000_REG_MODE_RING_BUF_ENABLE));
1302 error_ret:
1303 mutex_unlock(&st->lock);
1304
1305 return ret;
1306 }
1307
1308 /**
1309 * sca3000_hw_ring_preenable() - hw ring buffer preenable function
1310 * @indio_dev: structure representing the IIO device. Device instance
1311 * specific state can be accessed via iio_priv(indio_dev).
1312 *
1313 * Very simple enable function as the chip will allows normal reads
1314 * during ring buffer operation so as long as it is indeed running
1315 * before we notify the core, the precise ordering does not matter.
1316 */
sca3000_hw_ring_preenable(struct iio_dev * indio_dev)1317 static int sca3000_hw_ring_preenable(struct iio_dev *indio_dev)
1318 {
1319 int ret;
1320 struct sca3000_state *st = iio_priv(indio_dev);
1321
1322 mutex_lock(&st->lock);
1323
1324 /* Enable the 50% full interrupt */
1325 ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1326 if (ret)
1327 goto error_unlock;
1328 ret = sca3000_write_reg(st,
1329 SCA3000_REG_INT_MASK_ADDR,
1330 st->rx[0] | SCA3000_REG_INT_MASK_RING_HALF);
1331 if (ret)
1332 goto error_unlock;
1333
1334 mutex_unlock(&st->lock);
1335
1336 return __sca3000_hw_ring_state_set(indio_dev, 1);
1337
1338 error_unlock:
1339 mutex_unlock(&st->lock);
1340
1341 return ret;
1342 }
1343
sca3000_hw_ring_postdisable(struct iio_dev * indio_dev)1344 static int sca3000_hw_ring_postdisable(struct iio_dev *indio_dev)
1345 {
1346 int ret;
1347 struct sca3000_state *st = iio_priv(indio_dev);
1348
1349 ret = __sca3000_hw_ring_state_set(indio_dev, 0);
1350 if (ret)
1351 return ret;
1352
1353 /* Disable the 50% full interrupt */
1354 mutex_lock(&st->lock);
1355
1356 ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1357 if (ret)
1358 goto unlock;
1359 ret = sca3000_write_reg(st,
1360 SCA3000_REG_INT_MASK_ADDR,
1361 st->rx[0] & ~SCA3000_REG_INT_MASK_RING_HALF);
1362 unlock:
1363 mutex_unlock(&st->lock);
1364 return ret;
1365 }
1366
1367 static const struct iio_buffer_setup_ops sca3000_ring_setup_ops = {
1368 .preenable = &sca3000_hw_ring_preenable,
1369 .postdisable = &sca3000_hw_ring_postdisable,
1370 };
1371
1372 /**
1373 * sca3000_clean_setup() - get the device into a predictable state
1374 * @st: Device instance specific private data structure
1375 *
1376 * Devices use flash memory to store many of the register values
1377 * and hence can come up in somewhat unpredictable states.
1378 * Hence reset everything on driver load.
1379 */
sca3000_clean_setup(struct sca3000_state * st)1380 static int sca3000_clean_setup(struct sca3000_state *st)
1381 {
1382 int ret;
1383
1384 mutex_lock(&st->lock);
1385 /* Ensure all interrupts have been acknowledged */
1386 ret = sca3000_read_data_short(st, SCA3000_REG_INT_STATUS_ADDR, 1);
1387 if (ret)
1388 goto error_ret;
1389
1390 /* Turn off all motion detection channels */
1391 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
1392 if (ret < 0)
1393 goto error_ret;
1394 ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL,
1395 ret & SCA3000_MD_CTRL_PROT_MASK);
1396 if (ret)
1397 goto error_ret;
1398
1399 /* Disable ring buffer */
1400 ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
1401 if (ret < 0)
1402 goto error_ret;
1403 ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL,
1404 (ret & SCA3000_REG_OUT_CTRL_PROT_MASK)
1405 | SCA3000_REG_OUT_CTRL_BUF_X_EN
1406 | SCA3000_REG_OUT_CTRL_BUF_Y_EN
1407 | SCA3000_REG_OUT_CTRL_BUF_Z_EN
1408 | SCA3000_REG_OUT_CTRL_BUF_DIV_4);
1409 if (ret)
1410 goto error_ret;
1411 /* Enable interrupts, relevant to mode and set up as active low */
1412 ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1413 if (ret)
1414 goto error_ret;
1415 ret = sca3000_write_reg(st,
1416 SCA3000_REG_INT_MASK_ADDR,
1417 (ret & SCA3000_REG_INT_MASK_PROT_MASK)
1418 | SCA3000_REG_INT_MASK_ACTIVE_LOW);
1419 if (ret)
1420 goto error_ret;
1421 /*
1422 * Select normal measurement mode, free fall off, ring off
1423 * Ring in 12 bit mode - it is fine to overwrite reserved bits 3,5
1424 * as that occurs in one of the example on the datasheet
1425 */
1426 ret = sca3000_read_data_short(st, SCA3000_REG_MODE_ADDR, 1);
1427 if (ret)
1428 goto error_ret;
1429 ret = sca3000_write_reg(st, SCA3000_REG_MODE_ADDR,
1430 (st->rx[0] & SCA3000_MODE_PROT_MASK));
1431
1432 error_ret:
1433 mutex_unlock(&st->lock);
1434 return ret;
1435 }
1436
1437 static const struct iio_info sca3000_info = {
1438 .attrs = &sca3000_attribute_group,
1439 .read_raw = &sca3000_read_raw,
1440 .write_raw = &sca3000_write_raw,
1441 .read_event_value = &sca3000_read_event_value,
1442 .write_event_value = &sca3000_write_event_value,
1443 .read_event_config = &sca3000_read_event_config,
1444 .write_event_config = &sca3000_write_event_config,
1445 };
1446
sca3000_probe(struct spi_device * spi)1447 static int sca3000_probe(struct spi_device *spi)
1448 {
1449 int ret;
1450 struct sca3000_state *st;
1451 struct iio_dev *indio_dev;
1452
1453 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
1454 if (!indio_dev)
1455 return -ENOMEM;
1456
1457 st = iio_priv(indio_dev);
1458 spi_set_drvdata(spi, indio_dev);
1459 st->us = spi;
1460 mutex_init(&st->lock);
1461 st->info = &sca3000_spi_chip_info_tbl[spi_get_device_id(spi)
1462 ->driver_data];
1463
1464 indio_dev->name = spi_get_device_id(spi)->name;
1465 indio_dev->info = &sca3000_info;
1466 if (st->info->temp_output) {
1467 indio_dev->channels = sca3000_channels_with_temp;
1468 indio_dev->num_channels =
1469 ARRAY_SIZE(sca3000_channels_with_temp);
1470 } else {
1471 indio_dev->channels = sca3000_channels;
1472 indio_dev->num_channels = ARRAY_SIZE(sca3000_channels);
1473 }
1474 indio_dev->modes = INDIO_DIRECT_MODE;
1475
1476 ret = devm_iio_kfifo_buffer_setup(&spi->dev, indio_dev,
1477 &sca3000_ring_setup_ops);
1478 if (ret)
1479 return ret;
1480
1481 if (spi->irq) {
1482 ret = request_threaded_irq(spi->irq,
1483 NULL,
1484 &sca3000_event_handler,
1485 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1486 "sca3000",
1487 indio_dev);
1488 if (ret)
1489 return ret;
1490 }
1491 ret = sca3000_clean_setup(st);
1492 if (ret)
1493 goto error_free_irq;
1494
1495 ret = sca3000_print_rev(indio_dev);
1496 if (ret)
1497 goto error_free_irq;
1498
1499 return iio_device_register(indio_dev);
1500
1501 error_free_irq:
1502 if (spi->irq)
1503 free_irq(spi->irq, indio_dev);
1504
1505 return ret;
1506 }
1507
sca3000_stop_all_interrupts(struct sca3000_state * st)1508 static int sca3000_stop_all_interrupts(struct sca3000_state *st)
1509 {
1510 int ret;
1511
1512 mutex_lock(&st->lock);
1513 ret = sca3000_read_data_short(st, SCA3000_REG_INT_MASK_ADDR, 1);
1514 if (ret)
1515 goto error_ret;
1516 ret = sca3000_write_reg(st, SCA3000_REG_INT_MASK_ADDR,
1517 (st->rx[0] &
1518 ~(SCA3000_REG_INT_MASK_RING_THREE_QUARTER |
1519 SCA3000_REG_INT_MASK_RING_HALF |
1520 SCA3000_REG_INT_MASK_ALL_INTS)));
1521 error_ret:
1522 mutex_unlock(&st->lock);
1523 return ret;
1524 }
1525
sca3000_remove(struct spi_device * spi)1526 static void sca3000_remove(struct spi_device *spi)
1527 {
1528 struct iio_dev *indio_dev = spi_get_drvdata(spi);
1529 struct sca3000_state *st = iio_priv(indio_dev);
1530
1531 iio_device_unregister(indio_dev);
1532
1533 /* Must ensure no interrupts can be generated after this! */
1534 sca3000_stop_all_interrupts(st);
1535 if (spi->irq)
1536 free_irq(spi->irq, indio_dev);
1537 }
1538
1539 static const struct spi_device_id sca3000_id[] = {
1540 {"sca3000_d01", d01},
1541 {"sca3000_e02", e02},
1542 {"sca3000_e04", e04},
1543 {"sca3000_e05", e05},
1544 {}
1545 };
1546 MODULE_DEVICE_TABLE(spi, sca3000_id);
1547
1548 static struct spi_driver sca3000_driver = {
1549 .driver = {
1550 .name = "sca3000",
1551 },
1552 .probe = sca3000_probe,
1553 .remove = sca3000_remove,
1554 .id_table = sca3000_id,
1555 };
1556 module_spi_driver(sca3000_driver);
1557
1558 MODULE_AUTHOR("Jonathan Cameron <jic23@kernel.org>");
1559 MODULE_DESCRIPTION("VTI SCA3000 Series Accelerometers SPI driver");
1560 MODULE_LICENSE("GPL v2");
1561