1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 3-axis accelerometer driver for MXC4005XC Memsic sensor 4 * 5 * Copyright (c) 2014, Intel Corporation. 6 */ 7 8 #include <linux/module.h> 9 #include <linux/i2c.h> 10 #include <linux/iio/iio.h> 11 #include <linux/acpi.h> 12 #include <linux/regmap.h> 13 #include <linux/iio/sysfs.h> 14 #include <linux/iio/trigger.h> 15 #include <linux/iio/buffer.h> 16 #include <linux/iio/triggered_buffer.h> 17 #include <linux/iio/trigger_consumer.h> 18 19 #define MXC4005_DRV_NAME "mxc4005" 20 #define MXC4005_IRQ_NAME "mxc4005_event" 21 #define MXC4005_REGMAP_NAME "mxc4005_regmap" 22 23 #define MXC4005_REG_XOUT_UPPER 0x03 24 #define MXC4005_REG_XOUT_LOWER 0x04 25 #define MXC4005_REG_YOUT_UPPER 0x05 26 #define MXC4005_REG_YOUT_LOWER 0x06 27 #define MXC4005_REG_ZOUT_UPPER 0x07 28 #define MXC4005_REG_ZOUT_LOWER 0x08 29 30 #define MXC4005_REG_INT_MASK1 0x0B 31 #define MXC4005_REG_INT_MASK1_BIT_DRDYE 0x01 32 33 #define MXC4005_REG_INT_CLR1 0x01 34 #define MXC4005_REG_INT_CLR1_BIT_DRDYC 0x01 35 36 #define MXC4005_REG_CONTROL 0x0D 37 #define MXC4005_REG_CONTROL_MASK_FSR GENMASK(6, 5) 38 #define MXC4005_CONTROL_FSR_SHIFT 5 39 40 #define MXC4005_REG_DEVICE_ID 0x0E 41 42 enum mxc4005_axis { 43 AXIS_X, 44 AXIS_Y, 45 AXIS_Z, 46 }; 47 48 enum mxc4005_range { 49 MXC4005_RANGE_2G, 50 MXC4005_RANGE_4G, 51 MXC4005_RANGE_8G, 52 }; 53 54 struct mxc4005_data { 55 struct device *dev; 56 struct mutex mutex; 57 struct regmap *regmap; 58 struct iio_trigger *dready_trig; 59 __be16 buffer[8]; 60 bool trigger_enabled; 61 }; 62 63 /* 64 * MXC4005 can operate in the following ranges: 65 * +/- 2G, 4G, 8G (the default +/-2G) 66 * 67 * (2 + 2) * 9.81 / (2^12 - 1) = 0.009582 68 * (4 + 4) * 9.81 / (2^12 - 1) = 0.019164 69 * (8 + 8) * 9.81 / (2^12 - 1) = 0.038329 70 */ 71 static const struct { 72 u8 range; 73 int scale; 74 } mxc4005_scale_table[] = { 75 {MXC4005_RANGE_2G, 9582}, 76 {MXC4005_RANGE_4G, 19164}, 77 {MXC4005_RANGE_8G, 38329}, 78 }; 79 80 81 static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019164 0.038329"); 82 83 static struct attribute *mxc4005_attributes[] = { 84 &iio_const_attr_in_accel_scale_available.dev_attr.attr, 85 NULL, 86 }; 87 88 static const struct attribute_group mxc4005_attrs_group = { 89 .attrs = mxc4005_attributes, 90 }; 91 92 static bool mxc4005_is_readable_reg(struct device *dev, unsigned int reg) 93 { 94 switch (reg) { 95 case MXC4005_REG_XOUT_UPPER: 96 case MXC4005_REG_XOUT_LOWER: 97 case MXC4005_REG_YOUT_UPPER: 98 case MXC4005_REG_YOUT_LOWER: 99 case MXC4005_REG_ZOUT_UPPER: 100 case MXC4005_REG_ZOUT_LOWER: 101 case MXC4005_REG_DEVICE_ID: 102 case MXC4005_REG_CONTROL: 103 return true; 104 default: 105 return false; 106 } 107 } 108 109 static bool mxc4005_is_writeable_reg(struct device *dev, unsigned int reg) 110 { 111 switch (reg) { 112 case MXC4005_REG_INT_CLR1: 113 case MXC4005_REG_INT_MASK1: 114 case MXC4005_REG_CONTROL: 115 return true; 116 default: 117 return false; 118 } 119 } 120 121 static const struct regmap_config mxc4005_regmap_config = { 122 .name = MXC4005_REGMAP_NAME, 123 124 .reg_bits = 8, 125 .val_bits = 8, 126 127 .max_register = MXC4005_REG_DEVICE_ID, 128 129 .readable_reg = mxc4005_is_readable_reg, 130 .writeable_reg = mxc4005_is_writeable_reg, 131 }; 132 133 static int mxc4005_read_xyz(struct mxc4005_data *data) 134 { 135 int ret; 136 137 ret = regmap_bulk_read(data->regmap, MXC4005_REG_XOUT_UPPER, 138 data->buffer, sizeof(data->buffer)); 139 if (ret < 0) { 140 dev_err(data->dev, "failed to read axes\n"); 141 return ret; 142 } 143 144 return 0; 145 } 146 147 static int mxc4005_read_axis(struct mxc4005_data *data, 148 unsigned int addr) 149 { 150 __be16 reg; 151 int ret; 152 153 ret = regmap_bulk_read(data->regmap, addr, ®, sizeof(reg)); 154 if (ret < 0) { 155 dev_err(data->dev, "failed to read reg %02x\n", addr); 156 return ret; 157 } 158 159 return be16_to_cpu(reg); 160 } 161 162 static int mxc4005_read_scale(struct mxc4005_data *data) 163 { 164 unsigned int reg; 165 int ret; 166 int i; 167 168 ret = regmap_read(data->regmap, MXC4005_REG_CONTROL, ®); 169 if (ret < 0) { 170 dev_err(data->dev, "failed to read reg_control\n"); 171 return ret; 172 } 173 174 i = reg >> MXC4005_CONTROL_FSR_SHIFT; 175 176 if (i < 0 || i >= ARRAY_SIZE(mxc4005_scale_table)) 177 return -EINVAL; 178 179 return mxc4005_scale_table[i].scale; 180 } 181 182 static int mxc4005_set_scale(struct mxc4005_data *data, int val) 183 { 184 unsigned int reg; 185 int i; 186 int ret; 187 188 for (i = 0; i < ARRAY_SIZE(mxc4005_scale_table); i++) { 189 if (mxc4005_scale_table[i].scale == val) { 190 reg = i << MXC4005_CONTROL_FSR_SHIFT; 191 ret = regmap_update_bits(data->regmap, 192 MXC4005_REG_CONTROL, 193 MXC4005_REG_CONTROL_MASK_FSR, 194 reg); 195 if (ret < 0) 196 dev_err(data->dev, 197 "failed to write reg_control\n"); 198 return ret; 199 } 200 } 201 202 return -EINVAL; 203 } 204 205 static int mxc4005_read_raw(struct iio_dev *indio_dev, 206 struct iio_chan_spec const *chan, 207 int *val, int *val2, long mask) 208 { 209 struct mxc4005_data *data = iio_priv(indio_dev); 210 int ret; 211 212 switch (mask) { 213 case IIO_CHAN_INFO_RAW: 214 switch (chan->type) { 215 case IIO_ACCEL: 216 if (iio_buffer_enabled(indio_dev)) 217 return -EBUSY; 218 219 ret = mxc4005_read_axis(data, chan->address); 220 if (ret < 0) 221 return ret; 222 *val = sign_extend32(ret >> chan->scan_type.shift, 223 chan->scan_type.realbits - 1); 224 return IIO_VAL_INT; 225 default: 226 return -EINVAL; 227 } 228 case IIO_CHAN_INFO_SCALE: 229 ret = mxc4005_read_scale(data); 230 if (ret < 0) 231 return ret; 232 233 *val = 0; 234 *val2 = ret; 235 return IIO_VAL_INT_PLUS_MICRO; 236 default: 237 return -EINVAL; 238 } 239 } 240 241 static int mxc4005_write_raw(struct iio_dev *indio_dev, 242 struct iio_chan_spec const *chan, 243 int val, int val2, long mask) 244 { 245 struct mxc4005_data *data = iio_priv(indio_dev); 246 247 switch (mask) { 248 case IIO_CHAN_INFO_SCALE: 249 if (val != 0) 250 return -EINVAL; 251 252 return mxc4005_set_scale(data, val2); 253 default: 254 return -EINVAL; 255 } 256 } 257 258 static const struct iio_info mxc4005_info = { 259 .read_raw = mxc4005_read_raw, 260 .write_raw = mxc4005_write_raw, 261 .attrs = &mxc4005_attrs_group, 262 }; 263 264 static const unsigned long mxc4005_scan_masks[] = { 265 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 266 0 267 }; 268 269 #define MXC4005_CHANNEL(_axis, _addr) { \ 270 .type = IIO_ACCEL, \ 271 .modified = 1, \ 272 .channel2 = IIO_MOD_##_axis, \ 273 .address = _addr, \ 274 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 275 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 276 .scan_index = AXIS_##_axis, \ 277 .scan_type = { \ 278 .sign = 's', \ 279 .realbits = 12, \ 280 .storagebits = 16, \ 281 .shift = 4, \ 282 .endianness = IIO_BE, \ 283 }, \ 284 } 285 286 static const struct iio_chan_spec mxc4005_channels[] = { 287 MXC4005_CHANNEL(X, MXC4005_REG_XOUT_UPPER), 288 MXC4005_CHANNEL(Y, MXC4005_REG_YOUT_UPPER), 289 MXC4005_CHANNEL(Z, MXC4005_REG_ZOUT_UPPER), 290 IIO_CHAN_SOFT_TIMESTAMP(3), 291 }; 292 293 static irqreturn_t mxc4005_trigger_handler(int irq, void *private) 294 { 295 struct iio_poll_func *pf = private; 296 struct iio_dev *indio_dev = pf->indio_dev; 297 struct mxc4005_data *data = iio_priv(indio_dev); 298 int ret; 299 300 ret = mxc4005_read_xyz(data); 301 if (ret < 0) 302 goto err; 303 304 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, 305 pf->timestamp); 306 307 err: 308 iio_trigger_notify_done(indio_dev->trig); 309 310 return IRQ_HANDLED; 311 } 312 313 static void mxc4005_clr_intr(struct mxc4005_data *data) 314 { 315 int ret; 316 317 /* clear interrupt */ 318 ret = regmap_write(data->regmap, MXC4005_REG_INT_CLR1, 319 MXC4005_REG_INT_CLR1_BIT_DRDYC); 320 if (ret < 0) 321 dev_err(data->dev, "failed to write to reg_int_clr1\n"); 322 } 323 324 static int mxc4005_set_trigger_state(struct iio_trigger *trig, 325 bool state) 326 { 327 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 328 struct mxc4005_data *data = iio_priv(indio_dev); 329 int ret; 330 331 mutex_lock(&data->mutex); 332 if (state) { 333 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1, 334 MXC4005_REG_INT_MASK1_BIT_DRDYE); 335 } else { 336 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1, 337 ~MXC4005_REG_INT_MASK1_BIT_DRDYE); 338 } 339 340 if (ret < 0) { 341 mutex_unlock(&data->mutex); 342 dev_err(data->dev, "failed to update reg_int_mask1"); 343 return ret; 344 } 345 346 data->trigger_enabled = state; 347 mutex_unlock(&data->mutex); 348 349 return 0; 350 } 351 352 static void mxc4005_trigger_reen(struct iio_trigger *trig) 353 { 354 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 355 struct mxc4005_data *data = iio_priv(indio_dev); 356 357 if (!data->dready_trig) 358 return; 359 360 mxc4005_clr_intr(data); 361 } 362 363 static const struct iio_trigger_ops mxc4005_trigger_ops = { 364 .set_trigger_state = mxc4005_set_trigger_state, 365 .reenable = mxc4005_trigger_reen, 366 }; 367 368 static int mxc4005_chip_init(struct mxc4005_data *data) 369 { 370 int ret; 371 unsigned int reg; 372 373 ret = regmap_read(data->regmap, MXC4005_REG_DEVICE_ID, ®); 374 if (ret < 0) { 375 dev_err(data->dev, "failed to read chip id\n"); 376 return ret; 377 } 378 379 dev_dbg(data->dev, "MXC4005 chip id %02x\n", reg); 380 381 return 0; 382 } 383 384 static int mxc4005_probe(struct i2c_client *client, 385 const struct i2c_device_id *id) 386 { 387 struct mxc4005_data *data; 388 struct iio_dev *indio_dev; 389 struct regmap *regmap; 390 int ret; 391 392 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 393 if (!indio_dev) 394 return -ENOMEM; 395 396 regmap = devm_regmap_init_i2c(client, &mxc4005_regmap_config); 397 if (IS_ERR(regmap)) { 398 dev_err(&client->dev, "failed to initialize regmap\n"); 399 return PTR_ERR(regmap); 400 } 401 402 data = iio_priv(indio_dev); 403 i2c_set_clientdata(client, indio_dev); 404 data->dev = &client->dev; 405 data->regmap = regmap; 406 407 ret = mxc4005_chip_init(data); 408 if (ret < 0) { 409 dev_err(&client->dev, "failed to initialize chip\n"); 410 return ret; 411 } 412 413 mutex_init(&data->mutex); 414 415 indio_dev->channels = mxc4005_channels; 416 indio_dev->num_channels = ARRAY_SIZE(mxc4005_channels); 417 indio_dev->available_scan_masks = mxc4005_scan_masks; 418 indio_dev->name = MXC4005_DRV_NAME; 419 indio_dev->modes = INDIO_DIRECT_MODE; 420 indio_dev->info = &mxc4005_info; 421 422 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, 423 iio_pollfunc_store_time, 424 mxc4005_trigger_handler, 425 NULL); 426 if (ret < 0) { 427 dev_err(&client->dev, 428 "failed to setup iio triggered buffer\n"); 429 return ret; 430 } 431 432 if (client->irq > 0) { 433 data->dready_trig = devm_iio_trigger_alloc(&client->dev, 434 "%s-dev%d", 435 indio_dev->name, 436 indio_dev->id); 437 if (!data->dready_trig) 438 return -ENOMEM; 439 440 ret = devm_request_threaded_irq(&client->dev, client->irq, 441 iio_trigger_generic_data_rdy_poll, 442 NULL, 443 IRQF_TRIGGER_FALLING | 444 IRQF_ONESHOT, 445 MXC4005_IRQ_NAME, 446 data->dready_trig); 447 if (ret) { 448 dev_err(&client->dev, 449 "failed to init threaded irq\n"); 450 return ret; 451 } 452 453 data->dready_trig->ops = &mxc4005_trigger_ops; 454 iio_trigger_set_drvdata(data->dready_trig, indio_dev); 455 indio_dev->trig = data->dready_trig; 456 iio_trigger_get(indio_dev->trig); 457 ret = devm_iio_trigger_register(&client->dev, 458 data->dready_trig); 459 if (ret) { 460 dev_err(&client->dev, 461 "failed to register trigger\n"); 462 return ret; 463 } 464 } 465 466 return devm_iio_device_register(&client->dev, indio_dev); 467 } 468 469 static const struct acpi_device_id mxc4005_acpi_match[] = { 470 {"MXC4005", 0}, 471 {"MXC6655", 0}, 472 { }, 473 }; 474 MODULE_DEVICE_TABLE(acpi, mxc4005_acpi_match); 475 476 static const struct i2c_device_id mxc4005_id[] = { 477 {"mxc4005", 0}, 478 {"mxc6655", 0}, 479 { }, 480 }; 481 MODULE_DEVICE_TABLE(i2c, mxc4005_id); 482 483 static struct i2c_driver mxc4005_driver = { 484 .driver = { 485 .name = MXC4005_DRV_NAME, 486 .acpi_match_table = ACPI_PTR(mxc4005_acpi_match), 487 }, 488 .probe = mxc4005_probe, 489 .id_table = mxc4005_id, 490 }; 491 492 module_i2c_driver(mxc4005_driver); 493 494 MODULE_AUTHOR("Teodora Baluta <teodora.baluta@intel.com>"); 495 MODULE_LICENSE("GPL v2"); 496 MODULE_DESCRIPTION("MXC4005 3-axis accelerometer driver"); 497