1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 3-axis accelerometer driver for MXC4005XC Memsic sensor 4 * 5 * Copyright (c) 2014, Intel Corporation. 6 */ 7 8 #include <linux/module.h> 9 #include <linux/i2c.h> 10 #include <linux/iio/iio.h> 11 #include <linux/acpi.h> 12 #include <linux/regmap.h> 13 #include <linux/iio/sysfs.h> 14 #include <linux/iio/trigger.h> 15 #include <linux/iio/buffer.h> 16 #include <linux/iio/triggered_buffer.h> 17 #include <linux/iio/trigger_consumer.h> 18 19 #define MXC4005_DRV_NAME "mxc4005" 20 #define MXC4005_IRQ_NAME "mxc4005_event" 21 #define MXC4005_REGMAP_NAME "mxc4005_regmap" 22 23 #define MXC4005_REG_XOUT_UPPER 0x03 24 #define MXC4005_REG_XOUT_LOWER 0x04 25 #define MXC4005_REG_YOUT_UPPER 0x05 26 #define MXC4005_REG_YOUT_LOWER 0x06 27 #define MXC4005_REG_ZOUT_UPPER 0x07 28 #define MXC4005_REG_ZOUT_LOWER 0x08 29 30 #define MXC4005_REG_INT_MASK0 0x0A 31 32 #define MXC4005_REG_INT_MASK1 0x0B 33 #define MXC4005_REG_INT_MASK1_BIT_DRDYE 0x01 34 35 #define MXC4005_REG_INT_CLR0 0x00 36 37 #define MXC4005_REG_INT_CLR1 0x01 38 #define MXC4005_REG_INT_CLR1_BIT_DRDYC 0x01 39 40 #define MXC4005_REG_CONTROL 0x0D 41 #define MXC4005_REG_CONTROL_MASK_FSR GENMASK(6, 5) 42 #define MXC4005_CONTROL_FSR_SHIFT 5 43 44 #define MXC4005_REG_DEVICE_ID 0x0E 45 46 enum mxc4005_axis { 47 AXIS_X, 48 AXIS_Y, 49 AXIS_Z, 50 }; 51 52 enum mxc4005_range { 53 MXC4005_RANGE_2G, 54 MXC4005_RANGE_4G, 55 MXC4005_RANGE_8G, 56 }; 57 58 struct mxc4005_data { 59 struct device *dev; 60 struct mutex mutex; 61 struct regmap *regmap; 62 struct iio_trigger *dready_trig; 63 /* Ensure timestamp is naturally aligned */ 64 struct { 65 __be16 chans[3]; 66 s64 timestamp __aligned(8); 67 } scan; 68 bool trigger_enabled; 69 }; 70 71 /* 72 * MXC4005 can operate in the following ranges: 73 * +/- 2G, 4G, 8G (the default +/-2G) 74 * 75 * (2 + 2) * 9.81 / (2^12 - 1) = 0.009582 76 * (4 + 4) * 9.81 / (2^12 - 1) = 0.019164 77 * (8 + 8) * 9.81 / (2^12 - 1) = 0.038329 78 */ 79 static const struct { 80 u8 range; 81 int scale; 82 } mxc4005_scale_table[] = { 83 {MXC4005_RANGE_2G, 9582}, 84 {MXC4005_RANGE_4G, 19164}, 85 {MXC4005_RANGE_8G, 38329}, 86 }; 87 88 89 static IIO_CONST_ATTR(in_accel_scale_available, "0.009582 0.019164 0.038329"); 90 91 static struct attribute *mxc4005_attributes[] = { 92 &iio_const_attr_in_accel_scale_available.dev_attr.attr, 93 NULL, 94 }; 95 96 static const struct attribute_group mxc4005_attrs_group = { 97 .attrs = mxc4005_attributes, 98 }; 99 100 static bool mxc4005_is_readable_reg(struct device *dev, unsigned int reg) 101 { 102 switch (reg) { 103 case MXC4005_REG_XOUT_UPPER: 104 case MXC4005_REG_XOUT_LOWER: 105 case MXC4005_REG_YOUT_UPPER: 106 case MXC4005_REG_YOUT_LOWER: 107 case MXC4005_REG_ZOUT_UPPER: 108 case MXC4005_REG_ZOUT_LOWER: 109 case MXC4005_REG_DEVICE_ID: 110 case MXC4005_REG_CONTROL: 111 return true; 112 default: 113 return false; 114 } 115 } 116 117 static bool mxc4005_is_writeable_reg(struct device *dev, unsigned int reg) 118 { 119 switch (reg) { 120 case MXC4005_REG_INT_CLR0: 121 case MXC4005_REG_INT_CLR1: 122 case MXC4005_REG_INT_MASK0: 123 case MXC4005_REG_INT_MASK1: 124 case MXC4005_REG_CONTROL: 125 return true; 126 default: 127 return false; 128 } 129 } 130 131 static const struct regmap_config mxc4005_regmap_config = { 132 .name = MXC4005_REGMAP_NAME, 133 134 .reg_bits = 8, 135 .val_bits = 8, 136 137 .max_register = MXC4005_REG_DEVICE_ID, 138 139 .readable_reg = mxc4005_is_readable_reg, 140 .writeable_reg = mxc4005_is_writeable_reg, 141 }; 142 143 static int mxc4005_read_xyz(struct mxc4005_data *data) 144 { 145 int ret; 146 147 ret = regmap_bulk_read(data->regmap, MXC4005_REG_XOUT_UPPER, 148 data->scan.chans, sizeof(data->scan.chans)); 149 if (ret < 0) { 150 dev_err(data->dev, "failed to read axes\n"); 151 return ret; 152 } 153 154 return 0; 155 } 156 157 static int mxc4005_read_axis(struct mxc4005_data *data, 158 unsigned int addr) 159 { 160 __be16 reg; 161 int ret; 162 163 ret = regmap_bulk_read(data->regmap, addr, ®, sizeof(reg)); 164 if (ret < 0) { 165 dev_err(data->dev, "failed to read reg %02x\n", addr); 166 return ret; 167 } 168 169 return be16_to_cpu(reg); 170 } 171 172 static int mxc4005_read_scale(struct mxc4005_data *data) 173 { 174 unsigned int reg; 175 int ret; 176 int i; 177 178 ret = regmap_read(data->regmap, MXC4005_REG_CONTROL, ®); 179 if (ret < 0) { 180 dev_err(data->dev, "failed to read reg_control\n"); 181 return ret; 182 } 183 184 i = reg >> MXC4005_CONTROL_FSR_SHIFT; 185 186 if (i < 0 || i >= ARRAY_SIZE(mxc4005_scale_table)) 187 return -EINVAL; 188 189 return mxc4005_scale_table[i].scale; 190 } 191 192 static int mxc4005_set_scale(struct mxc4005_data *data, int val) 193 { 194 unsigned int reg; 195 int i; 196 int ret; 197 198 for (i = 0; i < ARRAY_SIZE(mxc4005_scale_table); i++) { 199 if (mxc4005_scale_table[i].scale == val) { 200 reg = i << MXC4005_CONTROL_FSR_SHIFT; 201 ret = regmap_update_bits(data->regmap, 202 MXC4005_REG_CONTROL, 203 MXC4005_REG_CONTROL_MASK_FSR, 204 reg); 205 if (ret < 0) 206 dev_err(data->dev, 207 "failed to write reg_control\n"); 208 return ret; 209 } 210 } 211 212 return -EINVAL; 213 } 214 215 static int mxc4005_read_raw(struct iio_dev *indio_dev, 216 struct iio_chan_spec const *chan, 217 int *val, int *val2, long mask) 218 { 219 struct mxc4005_data *data = iio_priv(indio_dev); 220 int ret; 221 222 switch (mask) { 223 case IIO_CHAN_INFO_RAW: 224 switch (chan->type) { 225 case IIO_ACCEL: 226 if (iio_buffer_enabled(indio_dev)) 227 return -EBUSY; 228 229 ret = mxc4005_read_axis(data, chan->address); 230 if (ret < 0) 231 return ret; 232 *val = sign_extend32(ret >> chan->scan_type.shift, 233 chan->scan_type.realbits - 1); 234 return IIO_VAL_INT; 235 default: 236 return -EINVAL; 237 } 238 case IIO_CHAN_INFO_SCALE: 239 ret = mxc4005_read_scale(data); 240 if (ret < 0) 241 return ret; 242 243 *val = 0; 244 *val2 = ret; 245 return IIO_VAL_INT_PLUS_MICRO; 246 default: 247 return -EINVAL; 248 } 249 } 250 251 static int mxc4005_write_raw(struct iio_dev *indio_dev, 252 struct iio_chan_spec const *chan, 253 int val, int val2, long mask) 254 { 255 struct mxc4005_data *data = iio_priv(indio_dev); 256 257 switch (mask) { 258 case IIO_CHAN_INFO_SCALE: 259 if (val != 0) 260 return -EINVAL; 261 262 return mxc4005_set_scale(data, val2); 263 default: 264 return -EINVAL; 265 } 266 } 267 268 static const struct iio_info mxc4005_info = { 269 .read_raw = mxc4005_read_raw, 270 .write_raw = mxc4005_write_raw, 271 .attrs = &mxc4005_attrs_group, 272 }; 273 274 static const unsigned long mxc4005_scan_masks[] = { 275 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 276 0 277 }; 278 279 #define MXC4005_CHANNEL(_axis, _addr) { \ 280 .type = IIO_ACCEL, \ 281 .modified = 1, \ 282 .channel2 = IIO_MOD_##_axis, \ 283 .address = _addr, \ 284 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 285 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \ 286 .scan_index = AXIS_##_axis, \ 287 .scan_type = { \ 288 .sign = 's', \ 289 .realbits = 12, \ 290 .storagebits = 16, \ 291 .shift = 4, \ 292 .endianness = IIO_BE, \ 293 }, \ 294 } 295 296 static const struct iio_chan_spec mxc4005_channels[] = { 297 MXC4005_CHANNEL(X, MXC4005_REG_XOUT_UPPER), 298 MXC4005_CHANNEL(Y, MXC4005_REG_YOUT_UPPER), 299 MXC4005_CHANNEL(Z, MXC4005_REG_ZOUT_UPPER), 300 IIO_CHAN_SOFT_TIMESTAMP(3), 301 }; 302 303 static irqreturn_t mxc4005_trigger_handler(int irq, void *private) 304 { 305 struct iio_poll_func *pf = private; 306 struct iio_dev *indio_dev = pf->indio_dev; 307 struct mxc4005_data *data = iio_priv(indio_dev); 308 int ret; 309 310 ret = mxc4005_read_xyz(data); 311 if (ret < 0) 312 goto err; 313 314 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan, 315 pf->timestamp); 316 317 err: 318 iio_trigger_notify_done(indio_dev->trig); 319 320 return IRQ_HANDLED; 321 } 322 323 static void mxc4005_clr_intr(struct mxc4005_data *data) 324 { 325 int ret; 326 327 /* clear interrupt */ 328 ret = regmap_write(data->regmap, MXC4005_REG_INT_CLR1, 329 MXC4005_REG_INT_CLR1_BIT_DRDYC); 330 if (ret < 0) 331 dev_err(data->dev, "failed to write to reg_int_clr1\n"); 332 } 333 334 static int mxc4005_set_trigger_state(struct iio_trigger *trig, 335 bool state) 336 { 337 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 338 struct mxc4005_data *data = iio_priv(indio_dev); 339 unsigned int val; 340 int ret; 341 342 mutex_lock(&data->mutex); 343 344 val = state ? MXC4005_REG_INT_MASK1_BIT_DRDYE : 0; 345 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1, val); 346 if (ret < 0) { 347 mutex_unlock(&data->mutex); 348 dev_err(data->dev, "failed to update reg_int_mask1"); 349 return ret; 350 } 351 352 data->trigger_enabled = state; 353 mutex_unlock(&data->mutex); 354 355 return 0; 356 } 357 358 static void mxc4005_trigger_reen(struct iio_trigger *trig) 359 { 360 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 361 struct mxc4005_data *data = iio_priv(indio_dev); 362 363 if (!data->dready_trig) 364 return; 365 366 mxc4005_clr_intr(data); 367 } 368 369 static const struct iio_trigger_ops mxc4005_trigger_ops = { 370 .set_trigger_state = mxc4005_set_trigger_state, 371 .reenable = mxc4005_trigger_reen, 372 }; 373 374 static int mxc4005_chip_init(struct mxc4005_data *data) 375 { 376 int ret; 377 unsigned int reg; 378 379 ret = regmap_read(data->regmap, MXC4005_REG_DEVICE_ID, ®); 380 if (ret < 0) { 381 dev_err(data->dev, "failed to read chip id\n"); 382 return ret; 383 } 384 385 dev_dbg(data->dev, "MXC4005 chip id %02x\n", reg); 386 387 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK0, 0); 388 if (ret < 0) 389 return dev_err_probe(data->dev, ret, "writing INT_MASK0\n"); 390 391 ret = regmap_write(data->regmap, MXC4005_REG_INT_MASK1, 0); 392 if (ret < 0) 393 return dev_err_probe(data->dev, ret, "writing INT_MASK1\n"); 394 395 return 0; 396 } 397 398 static int mxc4005_probe(struct i2c_client *client) 399 { 400 struct mxc4005_data *data; 401 struct iio_dev *indio_dev; 402 struct regmap *regmap; 403 int ret; 404 405 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 406 if (!indio_dev) 407 return -ENOMEM; 408 409 regmap = devm_regmap_init_i2c(client, &mxc4005_regmap_config); 410 if (IS_ERR(regmap)) { 411 dev_err(&client->dev, "failed to initialize regmap\n"); 412 return PTR_ERR(regmap); 413 } 414 415 data = iio_priv(indio_dev); 416 i2c_set_clientdata(client, indio_dev); 417 data->dev = &client->dev; 418 data->regmap = regmap; 419 420 ret = mxc4005_chip_init(data); 421 if (ret < 0) { 422 dev_err(&client->dev, "failed to initialize chip\n"); 423 return ret; 424 } 425 426 mutex_init(&data->mutex); 427 428 indio_dev->channels = mxc4005_channels; 429 indio_dev->num_channels = ARRAY_SIZE(mxc4005_channels); 430 indio_dev->available_scan_masks = mxc4005_scan_masks; 431 indio_dev->name = MXC4005_DRV_NAME; 432 indio_dev->modes = INDIO_DIRECT_MODE; 433 indio_dev->info = &mxc4005_info; 434 435 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, 436 iio_pollfunc_store_time, 437 mxc4005_trigger_handler, 438 NULL); 439 if (ret < 0) { 440 dev_err(&client->dev, 441 "failed to setup iio triggered buffer\n"); 442 return ret; 443 } 444 445 if (client->irq > 0) { 446 data->dready_trig = devm_iio_trigger_alloc(&client->dev, 447 "%s-dev%d", 448 indio_dev->name, 449 iio_device_id(indio_dev)); 450 if (!data->dready_trig) 451 return -ENOMEM; 452 453 ret = devm_request_threaded_irq(&client->dev, client->irq, 454 iio_trigger_generic_data_rdy_poll, 455 NULL, 456 IRQF_TRIGGER_FALLING | 457 IRQF_ONESHOT, 458 MXC4005_IRQ_NAME, 459 data->dready_trig); 460 if (ret) { 461 dev_err(&client->dev, 462 "failed to init threaded irq\n"); 463 return ret; 464 } 465 466 data->dready_trig->ops = &mxc4005_trigger_ops; 467 iio_trigger_set_drvdata(data->dready_trig, indio_dev); 468 ret = devm_iio_trigger_register(&client->dev, 469 data->dready_trig); 470 if (ret) { 471 dev_err(&client->dev, 472 "failed to register trigger\n"); 473 return ret; 474 } 475 476 indio_dev->trig = iio_trigger_get(data->dready_trig); 477 } 478 479 return devm_iio_device_register(&client->dev, indio_dev); 480 } 481 482 static const struct acpi_device_id mxc4005_acpi_match[] = { 483 {"MXC4005", 0}, 484 {"MXC6655", 0}, 485 { }, 486 }; 487 MODULE_DEVICE_TABLE(acpi, mxc4005_acpi_match); 488 489 static const struct i2c_device_id mxc4005_id[] = { 490 {"mxc4005", 0}, 491 {"mxc6655", 0}, 492 { }, 493 }; 494 MODULE_DEVICE_TABLE(i2c, mxc4005_id); 495 496 static struct i2c_driver mxc4005_driver = { 497 .driver = { 498 .name = MXC4005_DRV_NAME, 499 .acpi_match_table = ACPI_PTR(mxc4005_acpi_match), 500 }, 501 .probe = mxc4005_probe, 502 .id_table = mxc4005_id, 503 }; 504 505 module_i2c_driver(mxc4005_driver); 506 507 MODULE_AUTHOR("Teodora Baluta <teodora.baluta@intel.com>"); 508 MODULE_LICENSE("GPL v2"); 509 MODULE_DESCRIPTION("MXC4005 3-axis accelerometer driver"); 510