1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers: 4 * 5 * device name digital output 7-bit I2C slave address (pin selectable) 6 * --------------------------------------------------------------------- 7 * MMA8451Q 14 bit 0x1c / 0x1d 8 * MMA8452Q 12 bit 0x1c / 0x1d 9 * MMA8453Q 10 bit 0x1c / 0x1d 10 * MMA8652FC 12 bit 0x1d 11 * MMA8653FC 10 bit 0x1d 12 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f 13 * 14 * Copyright 2015 Martin Kepplinger <martink@posteo.de> 15 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net> 16 * 17 * 18 * TODO: orientation events 19 */ 20 21 #include <linux/module.h> 22 #include <linux/i2c.h> 23 #include <linux/iio/iio.h> 24 #include <linux/iio/sysfs.h> 25 #include <linux/iio/buffer.h> 26 #include <linux/iio/trigger.h> 27 #include <linux/iio/trigger_consumer.h> 28 #include <linux/iio/triggered_buffer.h> 29 #include <linux/iio/events.h> 30 #include <linux/delay.h> 31 #include <linux/of_device.h> 32 #include <linux/of_irq.h> 33 #include <linux/pm_runtime.h> 34 35 #define MMA8452_STATUS 0x00 36 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0)) 37 #define MMA8452_OUT_X 0x01 /* MSB first */ 38 #define MMA8452_OUT_Y 0x03 39 #define MMA8452_OUT_Z 0x05 40 #define MMA8452_INT_SRC 0x0c 41 #define MMA8452_WHO_AM_I 0x0d 42 #define MMA8452_DATA_CFG 0x0e 43 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0) 44 #define MMA8452_DATA_CFG_FS_2G 0 45 #define MMA8452_DATA_CFG_FS_4G 1 46 #define MMA8452_DATA_CFG_FS_8G 2 47 #define MMA8452_DATA_CFG_HPF_MASK BIT(4) 48 #define MMA8452_HP_FILTER_CUTOFF 0x0f 49 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0) 50 #define MMA8452_FF_MT_CFG 0x15 51 #define MMA8452_FF_MT_CFG_OAE BIT(6) 52 #define MMA8452_FF_MT_CFG_ELE BIT(7) 53 #define MMA8452_FF_MT_SRC 0x16 54 #define MMA8452_FF_MT_SRC_XHE BIT(1) 55 #define MMA8452_FF_MT_SRC_YHE BIT(3) 56 #define MMA8452_FF_MT_SRC_ZHE BIT(5) 57 #define MMA8452_FF_MT_THS 0x17 58 #define MMA8452_FF_MT_THS_MASK 0x7f 59 #define MMA8452_FF_MT_COUNT 0x18 60 #define MMA8452_FF_MT_CHAN_SHIFT 3 61 #define MMA8452_TRANSIENT_CFG 0x1d 62 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1) 63 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0) 64 #define MMA8452_TRANSIENT_CFG_ELE BIT(4) 65 #define MMA8452_TRANSIENT_SRC 0x1e 66 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1) 67 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3) 68 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5) 69 #define MMA8452_TRANSIENT_THS 0x1f 70 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0) 71 #define MMA8452_TRANSIENT_COUNT 0x20 72 #define MMA8452_TRANSIENT_CHAN_SHIFT 1 73 #define MMA8452_CTRL_REG1 0x2a 74 #define MMA8452_CTRL_ACTIVE BIT(0) 75 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3) 76 #define MMA8452_CTRL_DR_SHIFT 3 77 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */ 78 #define MMA8452_CTRL_REG2 0x2b 79 #define MMA8452_CTRL_REG2_RST BIT(6) 80 #define MMA8452_CTRL_REG2_MODS_SHIFT 3 81 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b 82 #define MMA8452_CTRL_REG4 0x2d 83 #define MMA8452_CTRL_REG5 0x2e 84 #define MMA8452_OFF_X 0x2f 85 #define MMA8452_OFF_Y 0x30 86 #define MMA8452_OFF_Z 0x31 87 88 #define MMA8452_MAX_REG 0x31 89 90 #define MMA8452_INT_DRDY BIT(0) 91 #define MMA8452_INT_FF_MT BIT(2) 92 #define MMA8452_INT_TRANS BIT(5) 93 94 #define MMA8451_DEVICE_ID 0x1a 95 #define MMA8452_DEVICE_ID 0x2a 96 #define MMA8453_DEVICE_ID 0x3a 97 #define MMA8652_DEVICE_ID 0x4a 98 #define MMA8653_DEVICE_ID 0x5a 99 #define FXLS8471_DEVICE_ID 0x6a 100 101 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000 102 103 struct mma8452_data { 104 struct i2c_client *client; 105 struct mutex lock; 106 u8 ctrl_reg1; 107 u8 data_cfg; 108 const struct mma_chip_info *chip_info; 109 }; 110 111 /** 112 * struct mma8452_event_regs - chip specific data related to events 113 * @ev_cfg: event config register address 114 * @ev_cfg_ele: latch bit in event config register 115 * @ev_cfg_chan_shift: number of the bit to enable events in X 116 * direction; in event config register 117 * @ev_src: event source register address 118 * @ev_ths: event threshold register address 119 * @ev_ths_mask: mask for the threshold value 120 * @ev_count: event count (period) register address 121 * 122 * Since not all chips supported by the driver support comparing high pass 123 * filtered data for events (interrupts), different interrupt sources are 124 * used for different chips and the relevant registers are included here. 125 */ 126 struct mma8452_event_regs { 127 u8 ev_cfg; 128 u8 ev_cfg_ele; 129 u8 ev_cfg_chan_shift; 130 u8 ev_src; 131 u8 ev_ths; 132 u8 ev_ths_mask; 133 u8 ev_count; 134 }; 135 136 static const struct mma8452_event_regs ff_mt_ev_regs = { 137 .ev_cfg = MMA8452_FF_MT_CFG, 138 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE, 139 .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT, 140 .ev_src = MMA8452_FF_MT_SRC, 141 .ev_ths = MMA8452_FF_MT_THS, 142 .ev_ths_mask = MMA8452_FF_MT_THS_MASK, 143 .ev_count = MMA8452_FF_MT_COUNT 144 }; 145 146 static const struct mma8452_event_regs trans_ev_regs = { 147 .ev_cfg = MMA8452_TRANSIENT_CFG, 148 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE, 149 .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT, 150 .ev_src = MMA8452_TRANSIENT_SRC, 151 .ev_ths = MMA8452_TRANSIENT_THS, 152 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK, 153 .ev_count = MMA8452_TRANSIENT_COUNT, 154 }; 155 156 /** 157 * struct mma_chip_info - chip specific data 158 * @chip_id: WHO_AM_I register's value 159 * @channels: struct iio_chan_spec matching the device's 160 * capabilities 161 * @num_channels: number of channels 162 * @mma_scales: scale factors for converting register values 163 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers 164 * per mode: m/s^2 and micro m/s^2 165 * @all_events: all events supported by this chip 166 * @enabled_events: event flags enabled and handled by this driver 167 */ 168 struct mma_chip_info { 169 u8 chip_id; 170 const struct iio_chan_spec *channels; 171 int num_channels; 172 const int mma_scales[3][2]; 173 int all_events; 174 int enabled_events; 175 }; 176 177 enum { 178 idx_x, 179 idx_y, 180 idx_z, 181 idx_ts, 182 }; 183 184 static int mma8452_drdy(struct mma8452_data *data) 185 { 186 int tries = 150; 187 188 while (tries-- > 0) { 189 int ret = i2c_smbus_read_byte_data(data->client, 190 MMA8452_STATUS); 191 if (ret < 0) 192 return ret; 193 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY) 194 return 0; 195 196 msleep(20); 197 } 198 199 dev_err(&data->client->dev, "data not ready\n"); 200 201 return -EIO; 202 } 203 204 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on) 205 { 206 #ifdef CONFIG_PM 207 int ret; 208 209 if (on) { 210 ret = pm_runtime_get_sync(&client->dev); 211 } else { 212 pm_runtime_mark_last_busy(&client->dev); 213 ret = pm_runtime_put_autosuspend(&client->dev); 214 } 215 216 if (ret < 0) { 217 dev_err(&client->dev, 218 "failed to change power state to %d\n", on); 219 if (on) 220 pm_runtime_put_noidle(&client->dev); 221 222 return ret; 223 } 224 #endif 225 226 return 0; 227 } 228 229 static int mma8452_read(struct mma8452_data *data, __be16 buf[3]) 230 { 231 int ret = mma8452_drdy(data); 232 233 if (ret < 0) 234 return ret; 235 236 ret = mma8452_set_runtime_pm_state(data->client, true); 237 if (ret) 238 return ret; 239 240 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X, 241 3 * sizeof(__be16), (u8 *)buf); 242 243 ret = mma8452_set_runtime_pm_state(data->client, false); 244 245 return ret; 246 } 247 248 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2], 249 int n) 250 { 251 size_t len = 0; 252 253 while (n-- > 0) 254 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ", 255 vals[n][0], vals[n][1]); 256 257 /* replace trailing space by newline */ 258 buf[len - 1] = '\n'; 259 260 return len; 261 } 262 263 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n, 264 int val, int val2) 265 { 266 while (n-- > 0) 267 if (val == vals[n][0] && val2 == vals[n][1]) 268 return n; 269 270 return -EINVAL; 271 } 272 273 static unsigned int mma8452_get_odr_index(struct mma8452_data *data) 274 { 275 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >> 276 MMA8452_CTRL_DR_SHIFT; 277 } 278 279 static const int mma8452_samp_freq[8][2] = { 280 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000}, 281 {6, 250000}, {1, 560000} 282 }; 283 284 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */ 285 static const unsigned int mma8452_time_step_us[4][8] = { 286 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */ 287 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */ 288 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/ 289 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */ 290 }; 291 292 /* Datasheet table "High-Pass Filter Cutoff Options" */ 293 static const int mma8452_hp_filter_cutoff[4][8][4][2] = { 294 { /* normal */ 295 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */ 296 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */ 297 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */ 298 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */ 299 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */ 300 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */ 301 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */ 302 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */ 303 }, 304 { /* low noise low power */ 305 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 306 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 307 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 308 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 309 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 310 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 311 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 312 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} } 313 }, 314 { /* high resolution */ 315 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 316 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 317 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 318 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 319 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 320 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 321 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 322 { {16, 0}, {8, 0}, {4, 0}, {2, 0} } 323 }, 324 { /* low power */ 325 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 326 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 327 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 328 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 329 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} }, 330 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 331 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 332 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} } 333 } 334 }; 335 336 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */ 337 static const u16 mma8452_os_ratio[4][8] = { 338 /* 800 Hz, 400 Hz, ... , 1.56 Hz */ 339 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */ 340 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */ 341 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */ 342 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */ 343 }; 344 345 static int mma8452_get_power_mode(struct mma8452_data *data) 346 { 347 int reg; 348 349 reg = i2c_smbus_read_byte_data(data->client, 350 MMA8452_CTRL_REG2); 351 if (reg < 0) 352 return reg; 353 354 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >> 355 MMA8452_CTRL_REG2_MODS_SHIFT); 356 } 357 358 static ssize_t mma8452_show_samp_freq_avail(struct device *dev, 359 struct device_attribute *attr, 360 char *buf) 361 { 362 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq, 363 ARRAY_SIZE(mma8452_samp_freq)); 364 } 365 366 static ssize_t mma8452_show_scale_avail(struct device *dev, 367 struct device_attribute *attr, 368 char *buf) 369 { 370 struct mma8452_data *data = iio_priv(i2c_get_clientdata( 371 to_i2c_client(dev))); 372 373 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales, 374 ARRAY_SIZE(data->chip_info->mma_scales)); 375 } 376 377 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev, 378 struct device_attribute *attr, 379 char *buf) 380 { 381 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 382 struct mma8452_data *data = iio_priv(indio_dev); 383 int i, j; 384 385 i = mma8452_get_odr_index(data); 386 j = mma8452_get_power_mode(data); 387 if (j < 0) 388 return j; 389 390 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i], 391 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0])); 392 } 393 394 static ssize_t mma8452_show_os_ratio_avail(struct device *dev, 395 struct device_attribute *attr, 396 char *buf) 397 { 398 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 399 struct mma8452_data *data = iio_priv(indio_dev); 400 int i = mma8452_get_odr_index(data); 401 int j; 402 u16 val = 0; 403 size_t len = 0; 404 405 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) { 406 if (val == mma8452_os_ratio[j][i]) 407 continue; 408 409 val = mma8452_os_ratio[j][i]; 410 411 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val); 412 } 413 buf[len - 1] = '\n'; 414 415 return len; 416 } 417 418 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail); 419 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444, 420 mma8452_show_scale_avail, NULL, 0); 421 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available, 422 0444, mma8452_show_hp_cutoff_avail, NULL, 0); 423 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444, 424 mma8452_show_os_ratio_avail, NULL, 0); 425 426 static int mma8452_get_samp_freq_index(struct mma8452_data *data, 427 int val, int val2) 428 { 429 return mma8452_get_int_plus_micros_index(mma8452_samp_freq, 430 ARRAY_SIZE(mma8452_samp_freq), 431 val, val2); 432 } 433 434 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2) 435 { 436 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales, 437 ARRAY_SIZE(data->chip_info->mma_scales), val, val2); 438 } 439 440 static int mma8452_get_hp_filter_index(struct mma8452_data *data, 441 int val, int val2) 442 { 443 int i, j; 444 445 i = mma8452_get_odr_index(data); 446 j = mma8452_get_power_mode(data); 447 if (j < 0) 448 return j; 449 450 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i], 451 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2); 452 } 453 454 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz) 455 { 456 int j, i, ret; 457 458 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF); 459 if (ret < 0) 460 return ret; 461 462 i = mma8452_get_odr_index(data); 463 j = mma8452_get_power_mode(data); 464 if (j < 0) 465 return j; 466 467 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 468 *hz = mma8452_hp_filter_cutoff[j][i][ret][0]; 469 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1]; 470 471 return 0; 472 } 473 474 static int mma8452_read_raw(struct iio_dev *indio_dev, 475 struct iio_chan_spec const *chan, 476 int *val, int *val2, long mask) 477 { 478 struct mma8452_data *data = iio_priv(indio_dev); 479 __be16 buffer[3]; 480 int i, ret; 481 482 switch (mask) { 483 case IIO_CHAN_INFO_RAW: 484 ret = iio_device_claim_direct_mode(indio_dev); 485 if (ret) 486 return ret; 487 488 mutex_lock(&data->lock); 489 ret = mma8452_read(data, buffer); 490 mutex_unlock(&data->lock); 491 iio_device_release_direct_mode(indio_dev); 492 if (ret < 0) 493 return ret; 494 495 *val = sign_extend32(be16_to_cpu( 496 buffer[chan->scan_index]) >> chan->scan_type.shift, 497 chan->scan_type.realbits - 1); 498 499 return IIO_VAL_INT; 500 case IIO_CHAN_INFO_SCALE: 501 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK; 502 *val = data->chip_info->mma_scales[i][0]; 503 *val2 = data->chip_info->mma_scales[i][1]; 504 505 return IIO_VAL_INT_PLUS_MICRO; 506 case IIO_CHAN_INFO_SAMP_FREQ: 507 i = mma8452_get_odr_index(data); 508 *val = mma8452_samp_freq[i][0]; 509 *val2 = mma8452_samp_freq[i][1]; 510 511 return IIO_VAL_INT_PLUS_MICRO; 512 case IIO_CHAN_INFO_CALIBBIAS: 513 ret = i2c_smbus_read_byte_data(data->client, 514 MMA8452_OFF_X + 515 chan->scan_index); 516 if (ret < 0) 517 return ret; 518 519 *val = sign_extend32(ret, 7); 520 521 return IIO_VAL_INT; 522 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 523 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) { 524 ret = mma8452_read_hp_filter(data, val, val2); 525 if (ret < 0) 526 return ret; 527 } else { 528 *val = 0; 529 *val2 = 0; 530 } 531 532 return IIO_VAL_INT_PLUS_MICRO; 533 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 534 ret = mma8452_get_power_mode(data); 535 if (ret < 0) 536 return ret; 537 538 i = mma8452_get_odr_index(data); 539 540 *val = mma8452_os_ratio[ret][i]; 541 return IIO_VAL_INT; 542 } 543 544 return -EINVAL; 545 } 546 547 static int mma8452_standby(struct mma8452_data *data) 548 { 549 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 550 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE); 551 } 552 553 static int mma8452_active(struct mma8452_data *data) 554 { 555 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 556 data->ctrl_reg1); 557 } 558 559 /* returns >0 if active, 0 if in standby and <0 on error */ 560 static int mma8452_is_active(struct mma8452_data *data) 561 { 562 int reg; 563 564 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1); 565 if (reg < 0) 566 return reg; 567 568 return reg & MMA8452_CTRL_ACTIVE; 569 } 570 571 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val) 572 { 573 int ret; 574 int is_active; 575 576 mutex_lock(&data->lock); 577 578 is_active = mma8452_is_active(data); 579 if (is_active < 0) { 580 ret = is_active; 581 goto fail; 582 } 583 584 /* config can only be changed when in standby */ 585 if (is_active > 0) { 586 ret = mma8452_standby(data); 587 if (ret < 0) 588 goto fail; 589 } 590 591 ret = i2c_smbus_write_byte_data(data->client, reg, val); 592 if (ret < 0) 593 goto fail; 594 595 if (is_active > 0) { 596 ret = mma8452_active(data); 597 if (ret < 0) 598 goto fail; 599 } 600 601 ret = 0; 602 fail: 603 mutex_unlock(&data->lock); 604 605 return ret; 606 } 607 608 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode) 609 { 610 int reg; 611 612 reg = i2c_smbus_read_byte_data(data->client, 613 MMA8452_CTRL_REG2); 614 if (reg < 0) 615 return reg; 616 617 reg &= ~MMA8452_CTRL_REG2_MODS_MASK; 618 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT; 619 620 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg); 621 } 622 623 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */ 624 static int mma8452_freefall_mode_enabled(struct mma8452_data *data) 625 { 626 int val; 627 628 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); 629 if (val < 0) 630 return val; 631 632 return !(val & MMA8452_FF_MT_CFG_OAE); 633 } 634 635 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state) 636 { 637 int val; 638 639 if ((state && mma8452_freefall_mode_enabled(data)) || 640 (!state && !(mma8452_freefall_mode_enabled(data)))) 641 return 0; 642 643 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); 644 if (val < 0) 645 return val; 646 647 if (state) { 648 val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); 649 val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); 650 val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); 651 val &= ~MMA8452_FF_MT_CFG_OAE; 652 } else { 653 val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); 654 val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); 655 val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); 656 val |= MMA8452_FF_MT_CFG_OAE; 657 } 658 659 return mma8452_change_config(data, MMA8452_FF_MT_CFG, val); 660 } 661 662 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data, 663 int val, int val2) 664 { 665 int i, reg; 666 667 i = mma8452_get_hp_filter_index(data, val, val2); 668 if (i < 0) 669 return i; 670 671 reg = i2c_smbus_read_byte_data(data->client, 672 MMA8452_HP_FILTER_CUTOFF); 673 if (reg < 0) 674 return reg; 675 676 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 677 reg |= i; 678 679 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg); 680 } 681 682 static int mma8452_write_raw(struct iio_dev *indio_dev, 683 struct iio_chan_spec const *chan, 684 int val, int val2, long mask) 685 { 686 struct mma8452_data *data = iio_priv(indio_dev); 687 int i, ret; 688 689 ret = iio_device_claim_direct_mode(indio_dev); 690 if (ret) 691 return ret; 692 693 switch (mask) { 694 case IIO_CHAN_INFO_SAMP_FREQ: 695 i = mma8452_get_samp_freq_index(data, val, val2); 696 if (i < 0) { 697 ret = i; 698 break; 699 } 700 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK; 701 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT; 702 703 ret = mma8452_change_config(data, MMA8452_CTRL_REG1, 704 data->ctrl_reg1); 705 break; 706 case IIO_CHAN_INFO_SCALE: 707 i = mma8452_get_scale_index(data, val, val2); 708 if (i < 0) { 709 ret = i; 710 break; 711 } 712 713 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK; 714 data->data_cfg |= i; 715 716 ret = mma8452_change_config(data, MMA8452_DATA_CFG, 717 data->data_cfg); 718 break; 719 case IIO_CHAN_INFO_CALIBBIAS: 720 if (val < -128 || val > 127) { 721 ret = -EINVAL; 722 break; 723 } 724 725 ret = mma8452_change_config(data, 726 MMA8452_OFF_X + chan->scan_index, 727 val); 728 break; 729 730 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 731 if (val == 0 && val2 == 0) { 732 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK; 733 } else { 734 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK; 735 ret = mma8452_set_hp_filter_frequency(data, val, val2); 736 if (ret < 0) 737 break; 738 } 739 740 ret = mma8452_change_config(data, MMA8452_DATA_CFG, 741 data->data_cfg); 742 break; 743 744 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 745 ret = mma8452_get_odr_index(data); 746 747 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) { 748 if (mma8452_os_ratio[i][ret] == val) { 749 ret = mma8452_set_power_mode(data, i); 750 break; 751 } 752 } 753 break; 754 default: 755 ret = -EINVAL; 756 break; 757 } 758 759 iio_device_release_direct_mode(indio_dev); 760 return ret; 761 } 762 763 static int mma8452_get_event_regs(struct mma8452_data *data, 764 const struct iio_chan_spec *chan, enum iio_event_direction dir, 765 const struct mma8452_event_regs **ev_reg) 766 { 767 if (!chan) 768 return -EINVAL; 769 770 switch (chan->type) { 771 case IIO_ACCEL: 772 switch (dir) { 773 case IIO_EV_DIR_RISING: 774 if ((data->chip_info->all_events 775 & MMA8452_INT_TRANS) && 776 (data->chip_info->enabled_events 777 & MMA8452_INT_TRANS)) 778 *ev_reg = &trans_ev_regs; 779 else 780 *ev_reg = &ff_mt_ev_regs; 781 return 0; 782 case IIO_EV_DIR_FALLING: 783 *ev_reg = &ff_mt_ev_regs; 784 return 0; 785 default: 786 return -EINVAL; 787 } 788 default: 789 return -EINVAL; 790 } 791 } 792 793 static int mma8452_read_event_value(struct iio_dev *indio_dev, 794 const struct iio_chan_spec *chan, 795 enum iio_event_type type, 796 enum iio_event_direction dir, 797 enum iio_event_info info, 798 int *val, int *val2) 799 { 800 struct mma8452_data *data = iio_priv(indio_dev); 801 int ret, us, power_mode; 802 const struct mma8452_event_regs *ev_regs; 803 804 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 805 if (ret) 806 return ret; 807 808 switch (info) { 809 case IIO_EV_INFO_VALUE: 810 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths); 811 if (ret < 0) 812 return ret; 813 814 *val = ret & ev_regs->ev_ths_mask; 815 816 return IIO_VAL_INT; 817 818 case IIO_EV_INFO_PERIOD: 819 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count); 820 if (ret < 0) 821 return ret; 822 823 power_mode = mma8452_get_power_mode(data); 824 if (power_mode < 0) 825 return power_mode; 826 827 us = ret * mma8452_time_step_us[power_mode][ 828 mma8452_get_odr_index(data)]; 829 *val = us / USEC_PER_SEC; 830 *val2 = us % USEC_PER_SEC; 831 832 return IIO_VAL_INT_PLUS_MICRO; 833 834 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 835 ret = i2c_smbus_read_byte_data(data->client, 836 MMA8452_TRANSIENT_CFG); 837 if (ret < 0) 838 return ret; 839 840 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) { 841 *val = 0; 842 *val2 = 0; 843 } else { 844 ret = mma8452_read_hp_filter(data, val, val2); 845 if (ret < 0) 846 return ret; 847 } 848 849 return IIO_VAL_INT_PLUS_MICRO; 850 851 default: 852 return -EINVAL; 853 } 854 } 855 856 static int mma8452_write_event_value(struct iio_dev *indio_dev, 857 const struct iio_chan_spec *chan, 858 enum iio_event_type type, 859 enum iio_event_direction dir, 860 enum iio_event_info info, 861 int val, int val2) 862 { 863 struct mma8452_data *data = iio_priv(indio_dev); 864 int ret, reg, steps; 865 const struct mma8452_event_regs *ev_regs; 866 867 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 868 if (ret) 869 return ret; 870 871 switch (info) { 872 case IIO_EV_INFO_VALUE: 873 if (val < 0 || val > ev_regs->ev_ths_mask) 874 return -EINVAL; 875 876 return mma8452_change_config(data, ev_regs->ev_ths, val); 877 878 case IIO_EV_INFO_PERIOD: 879 ret = mma8452_get_power_mode(data); 880 if (ret < 0) 881 return ret; 882 883 steps = (val * USEC_PER_SEC + val2) / 884 mma8452_time_step_us[ret][ 885 mma8452_get_odr_index(data)]; 886 887 if (steps < 0 || steps > 0xff) 888 return -EINVAL; 889 890 return mma8452_change_config(data, ev_regs->ev_count, steps); 891 892 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 893 reg = i2c_smbus_read_byte_data(data->client, 894 MMA8452_TRANSIENT_CFG); 895 if (reg < 0) 896 return reg; 897 898 if (val == 0 && val2 == 0) { 899 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP; 900 } else { 901 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP; 902 ret = mma8452_set_hp_filter_frequency(data, val, val2); 903 if (ret < 0) 904 return ret; 905 } 906 907 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg); 908 909 default: 910 return -EINVAL; 911 } 912 } 913 914 static int mma8452_read_event_config(struct iio_dev *indio_dev, 915 const struct iio_chan_spec *chan, 916 enum iio_event_type type, 917 enum iio_event_direction dir) 918 { 919 struct mma8452_data *data = iio_priv(indio_dev); 920 int ret; 921 const struct mma8452_event_regs *ev_regs; 922 923 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 924 if (ret) 925 return ret; 926 927 switch (dir) { 928 case IIO_EV_DIR_FALLING: 929 return mma8452_freefall_mode_enabled(data); 930 case IIO_EV_DIR_RISING: 931 ret = i2c_smbus_read_byte_data(data->client, 932 ev_regs->ev_cfg); 933 if (ret < 0) 934 return ret; 935 936 return !!(ret & BIT(chan->scan_index + 937 ev_regs->ev_cfg_chan_shift)); 938 default: 939 return -EINVAL; 940 } 941 } 942 943 static int mma8452_write_event_config(struct iio_dev *indio_dev, 944 const struct iio_chan_spec *chan, 945 enum iio_event_type type, 946 enum iio_event_direction dir, 947 int state) 948 { 949 struct mma8452_data *data = iio_priv(indio_dev); 950 int val, ret; 951 const struct mma8452_event_regs *ev_regs; 952 953 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 954 if (ret) 955 return ret; 956 957 ret = mma8452_set_runtime_pm_state(data->client, state); 958 if (ret) 959 return ret; 960 961 switch (dir) { 962 case IIO_EV_DIR_FALLING: 963 return mma8452_set_freefall_mode(data, state); 964 case IIO_EV_DIR_RISING: 965 val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg); 966 if (val < 0) 967 return val; 968 969 if (state) { 970 if (mma8452_freefall_mode_enabled(data)) { 971 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift); 972 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift); 973 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift); 974 val |= MMA8452_FF_MT_CFG_OAE; 975 } 976 val |= BIT(chan->scan_index + 977 ev_regs->ev_cfg_chan_shift); 978 } else { 979 if (mma8452_freefall_mode_enabled(data)) 980 return 0; 981 982 val &= ~BIT(chan->scan_index + 983 ev_regs->ev_cfg_chan_shift); 984 } 985 986 val |= ev_regs->ev_cfg_ele; 987 988 return mma8452_change_config(data, ev_regs->ev_cfg, val); 989 default: 990 return -EINVAL; 991 } 992 } 993 994 static void mma8452_transient_interrupt(struct iio_dev *indio_dev) 995 { 996 struct mma8452_data *data = iio_priv(indio_dev); 997 s64 ts = iio_get_time_ns(indio_dev); 998 int src; 999 1000 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC); 1001 if (src < 0) 1002 return; 1003 1004 if (src & MMA8452_TRANSIENT_SRC_XTRANSE) 1005 iio_push_event(indio_dev, 1006 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1007 IIO_EV_TYPE_MAG, 1008 IIO_EV_DIR_RISING), 1009 ts); 1010 1011 if (src & MMA8452_TRANSIENT_SRC_YTRANSE) 1012 iio_push_event(indio_dev, 1013 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y, 1014 IIO_EV_TYPE_MAG, 1015 IIO_EV_DIR_RISING), 1016 ts); 1017 1018 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE) 1019 iio_push_event(indio_dev, 1020 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z, 1021 IIO_EV_TYPE_MAG, 1022 IIO_EV_DIR_RISING), 1023 ts); 1024 } 1025 1026 static irqreturn_t mma8452_interrupt(int irq, void *p) 1027 { 1028 struct iio_dev *indio_dev = p; 1029 struct mma8452_data *data = iio_priv(indio_dev); 1030 int ret = IRQ_NONE; 1031 int src; 1032 1033 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC); 1034 if (src < 0) 1035 return IRQ_NONE; 1036 1037 if (!(src & data->chip_info->enabled_events)) 1038 return IRQ_NONE; 1039 1040 if (src & MMA8452_INT_DRDY) { 1041 iio_trigger_poll_chained(indio_dev->trig); 1042 ret = IRQ_HANDLED; 1043 } 1044 1045 if (src & MMA8452_INT_FF_MT) { 1046 if (mma8452_freefall_mode_enabled(data)) { 1047 s64 ts = iio_get_time_ns(indio_dev); 1048 1049 iio_push_event(indio_dev, 1050 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 1051 IIO_MOD_X_AND_Y_AND_Z, 1052 IIO_EV_TYPE_MAG, 1053 IIO_EV_DIR_FALLING), 1054 ts); 1055 } 1056 ret = IRQ_HANDLED; 1057 } 1058 1059 if (src & MMA8452_INT_TRANS) { 1060 mma8452_transient_interrupt(indio_dev); 1061 ret = IRQ_HANDLED; 1062 } 1063 1064 return ret; 1065 } 1066 1067 static irqreturn_t mma8452_trigger_handler(int irq, void *p) 1068 { 1069 struct iio_poll_func *pf = p; 1070 struct iio_dev *indio_dev = pf->indio_dev; 1071 struct mma8452_data *data = iio_priv(indio_dev); 1072 u8 buffer[16]; /* 3 16-bit channels + padding + ts */ 1073 int ret; 1074 1075 ret = mma8452_read(data, (__be16 *)buffer); 1076 if (ret < 0) 1077 goto done; 1078 1079 iio_push_to_buffers_with_timestamp(indio_dev, buffer, 1080 iio_get_time_ns(indio_dev)); 1081 1082 done: 1083 iio_trigger_notify_done(indio_dev->trig); 1084 1085 return IRQ_HANDLED; 1086 } 1087 1088 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev, 1089 unsigned int reg, unsigned int writeval, 1090 unsigned int *readval) 1091 { 1092 int ret; 1093 struct mma8452_data *data = iio_priv(indio_dev); 1094 1095 if (reg > MMA8452_MAX_REG) 1096 return -EINVAL; 1097 1098 if (!readval) 1099 return mma8452_change_config(data, reg, writeval); 1100 1101 ret = i2c_smbus_read_byte_data(data->client, reg); 1102 if (ret < 0) 1103 return ret; 1104 1105 *readval = ret; 1106 1107 return 0; 1108 } 1109 1110 static const struct iio_event_spec mma8452_freefall_event[] = { 1111 { 1112 .type = IIO_EV_TYPE_MAG, 1113 .dir = IIO_EV_DIR_FALLING, 1114 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1115 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1116 BIT(IIO_EV_INFO_PERIOD) | 1117 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1118 }, 1119 }; 1120 1121 static const struct iio_event_spec mma8652_freefall_event[] = { 1122 { 1123 .type = IIO_EV_TYPE_MAG, 1124 .dir = IIO_EV_DIR_FALLING, 1125 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1126 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1127 BIT(IIO_EV_INFO_PERIOD) 1128 }, 1129 }; 1130 1131 static const struct iio_event_spec mma8452_transient_event[] = { 1132 { 1133 .type = IIO_EV_TYPE_MAG, 1134 .dir = IIO_EV_DIR_RISING, 1135 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1136 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1137 BIT(IIO_EV_INFO_PERIOD) | 1138 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1139 }, 1140 }; 1141 1142 static const struct iio_event_spec mma8452_motion_event[] = { 1143 { 1144 .type = IIO_EV_TYPE_MAG, 1145 .dir = IIO_EV_DIR_RISING, 1146 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1147 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1148 BIT(IIO_EV_INFO_PERIOD) 1149 }, 1150 }; 1151 1152 /* 1153 * Threshold is configured in fixed 8G/127 steps regardless of 1154 * currently selected scale for measurement. 1155 */ 1156 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742"); 1157 1158 static struct attribute *mma8452_event_attributes[] = { 1159 &iio_const_attr_accel_transient_scale.dev_attr.attr, 1160 NULL, 1161 }; 1162 1163 static struct attribute_group mma8452_event_attribute_group = { 1164 .attrs = mma8452_event_attributes, 1165 }; 1166 1167 #define MMA8452_FREEFALL_CHANNEL(modifier) { \ 1168 .type = IIO_ACCEL, \ 1169 .modified = 1, \ 1170 .channel2 = modifier, \ 1171 .scan_index = -1, \ 1172 .event_spec = mma8452_freefall_event, \ 1173 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \ 1174 } 1175 1176 #define MMA8652_FREEFALL_CHANNEL(modifier) { \ 1177 .type = IIO_ACCEL, \ 1178 .modified = 1, \ 1179 .channel2 = modifier, \ 1180 .scan_index = -1, \ 1181 .event_spec = mma8652_freefall_event, \ 1182 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \ 1183 } 1184 1185 #define MMA8452_CHANNEL(axis, idx, bits) { \ 1186 .type = IIO_ACCEL, \ 1187 .modified = 1, \ 1188 .channel2 = IIO_MOD_##axis, \ 1189 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1190 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1191 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1192 BIT(IIO_CHAN_INFO_SCALE) | \ 1193 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \ 1194 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1195 .scan_index = idx, \ 1196 .scan_type = { \ 1197 .sign = 's', \ 1198 .realbits = (bits), \ 1199 .storagebits = 16, \ 1200 .shift = 16 - (bits), \ 1201 .endianness = IIO_BE, \ 1202 }, \ 1203 .event_spec = mma8452_transient_event, \ 1204 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \ 1205 } 1206 1207 #define MMA8652_CHANNEL(axis, idx, bits) { \ 1208 .type = IIO_ACCEL, \ 1209 .modified = 1, \ 1210 .channel2 = IIO_MOD_##axis, \ 1211 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1212 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1213 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1214 BIT(IIO_CHAN_INFO_SCALE) | \ 1215 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1216 .scan_index = idx, \ 1217 .scan_type = { \ 1218 .sign = 's', \ 1219 .realbits = (bits), \ 1220 .storagebits = 16, \ 1221 .shift = 16 - (bits), \ 1222 .endianness = IIO_BE, \ 1223 }, \ 1224 .event_spec = mma8452_motion_event, \ 1225 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \ 1226 } 1227 1228 static const struct iio_chan_spec mma8451_channels[] = { 1229 MMA8452_CHANNEL(X, idx_x, 14), 1230 MMA8452_CHANNEL(Y, idx_y, 14), 1231 MMA8452_CHANNEL(Z, idx_z, 14), 1232 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1233 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1234 }; 1235 1236 static const struct iio_chan_spec mma8452_channels[] = { 1237 MMA8452_CHANNEL(X, idx_x, 12), 1238 MMA8452_CHANNEL(Y, idx_y, 12), 1239 MMA8452_CHANNEL(Z, idx_z, 12), 1240 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1241 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1242 }; 1243 1244 static const struct iio_chan_spec mma8453_channels[] = { 1245 MMA8452_CHANNEL(X, idx_x, 10), 1246 MMA8452_CHANNEL(Y, idx_y, 10), 1247 MMA8452_CHANNEL(Z, idx_z, 10), 1248 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1249 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1250 }; 1251 1252 static const struct iio_chan_spec mma8652_channels[] = { 1253 MMA8652_CHANNEL(X, idx_x, 12), 1254 MMA8652_CHANNEL(Y, idx_y, 12), 1255 MMA8652_CHANNEL(Z, idx_z, 12), 1256 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1257 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1258 }; 1259 1260 static const struct iio_chan_spec mma8653_channels[] = { 1261 MMA8652_CHANNEL(X, idx_x, 10), 1262 MMA8652_CHANNEL(Y, idx_y, 10), 1263 MMA8652_CHANNEL(Z, idx_z, 10), 1264 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1265 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1266 }; 1267 1268 enum { 1269 mma8451, 1270 mma8452, 1271 mma8453, 1272 mma8652, 1273 mma8653, 1274 fxls8471, 1275 }; 1276 1277 static const struct mma_chip_info mma_chip_info_table[] = { 1278 [mma8451] = { 1279 .chip_id = MMA8451_DEVICE_ID, 1280 .channels = mma8451_channels, 1281 .num_channels = ARRAY_SIZE(mma8451_channels), 1282 /* 1283 * Hardware has fullscale of -2G, -4G, -8G corresponding to 1284 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10 1285 * bit. 1286 * The userspace interface uses m/s^2 and we declare micro units 1287 * So scale factor for 12 bit here is given by: 1288 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665 1289 */ 1290 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1291 /* 1292 * Although we enable the interrupt sources once and for 1293 * all here the event detection itself is not enabled until 1294 * userspace asks for it by mma8452_write_event_config() 1295 */ 1296 .all_events = MMA8452_INT_DRDY | 1297 MMA8452_INT_TRANS | 1298 MMA8452_INT_FF_MT, 1299 .enabled_events = MMA8452_INT_TRANS | 1300 MMA8452_INT_FF_MT, 1301 }, 1302 [mma8452] = { 1303 .chip_id = MMA8452_DEVICE_ID, 1304 .channels = mma8452_channels, 1305 .num_channels = ARRAY_SIZE(mma8452_channels), 1306 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1307 /* 1308 * Although we enable the interrupt sources once and for 1309 * all here the event detection itself is not enabled until 1310 * userspace asks for it by mma8452_write_event_config() 1311 */ 1312 .all_events = MMA8452_INT_DRDY | 1313 MMA8452_INT_TRANS | 1314 MMA8452_INT_FF_MT, 1315 .enabled_events = MMA8452_INT_TRANS | 1316 MMA8452_INT_FF_MT, 1317 }, 1318 [mma8453] = { 1319 .chip_id = MMA8453_DEVICE_ID, 1320 .channels = mma8453_channels, 1321 .num_channels = ARRAY_SIZE(mma8453_channels), 1322 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1323 /* 1324 * Although we enable the interrupt sources once and for 1325 * all here the event detection itself is not enabled until 1326 * userspace asks for it by mma8452_write_event_config() 1327 */ 1328 .all_events = MMA8452_INT_DRDY | 1329 MMA8452_INT_TRANS | 1330 MMA8452_INT_FF_MT, 1331 .enabled_events = MMA8452_INT_TRANS | 1332 MMA8452_INT_FF_MT, 1333 }, 1334 [mma8652] = { 1335 .chip_id = MMA8652_DEVICE_ID, 1336 .channels = mma8652_channels, 1337 .num_channels = ARRAY_SIZE(mma8652_channels), 1338 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1339 .all_events = MMA8452_INT_DRDY | 1340 MMA8452_INT_FF_MT, 1341 .enabled_events = MMA8452_INT_FF_MT, 1342 }, 1343 [mma8653] = { 1344 .chip_id = MMA8653_DEVICE_ID, 1345 .channels = mma8653_channels, 1346 .num_channels = ARRAY_SIZE(mma8653_channels), 1347 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1348 /* 1349 * Although we enable the interrupt sources once and for 1350 * all here the event detection itself is not enabled until 1351 * userspace asks for it by mma8452_write_event_config() 1352 */ 1353 .all_events = MMA8452_INT_DRDY | 1354 MMA8452_INT_FF_MT, 1355 .enabled_events = MMA8452_INT_FF_MT, 1356 }, 1357 [fxls8471] = { 1358 .chip_id = FXLS8471_DEVICE_ID, 1359 .channels = mma8451_channels, 1360 .num_channels = ARRAY_SIZE(mma8451_channels), 1361 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1362 /* 1363 * Although we enable the interrupt sources once and for 1364 * all here the event detection itself is not enabled until 1365 * userspace asks for it by mma8452_write_event_config() 1366 */ 1367 .all_events = MMA8452_INT_DRDY | 1368 MMA8452_INT_TRANS | 1369 MMA8452_INT_FF_MT, 1370 .enabled_events = MMA8452_INT_TRANS | 1371 MMA8452_INT_FF_MT, 1372 }, 1373 }; 1374 1375 static struct attribute *mma8452_attributes[] = { 1376 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1377 &iio_dev_attr_in_accel_scale_available.dev_attr.attr, 1378 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr, 1379 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr, 1380 NULL 1381 }; 1382 1383 static const struct attribute_group mma8452_group = { 1384 .attrs = mma8452_attributes, 1385 }; 1386 1387 static const struct iio_info mma8452_info = { 1388 .attrs = &mma8452_group, 1389 .read_raw = &mma8452_read_raw, 1390 .write_raw = &mma8452_write_raw, 1391 .event_attrs = &mma8452_event_attribute_group, 1392 .read_event_value = &mma8452_read_event_value, 1393 .write_event_value = &mma8452_write_event_value, 1394 .read_event_config = &mma8452_read_event_config, 1395 .write_event_config = &mma8452_write_event_config, 1396 .debugfs_reg_access = &mma8452_reg_access_dbg, 1397 }; 1398 1399 static const unsigned long mma8452_scan_masks[] = {0x7, 0}; 1400 1401 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig, 1402 bool state) 1403 { 1404 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1405 struct mma8452_data *data = iio_priv(indio_dev); 1406 int reg, ret; 1407 1408 ret = mma8452_set_runtime_pm_state(data->client, state); 1409 if (ret) 1410 return ret; 1411 1412 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4); 1413 if (reg < 0) 1414 return reg; 1415 1416 if (state) 1417 reg |= MMA8452_INT_DRDY; 1418 else 1419 reg &= ~MMA8452_INT_DRDY; 1420 1421 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg); 1422 } 1423 1424 static const struct iio_trigger_ops mma8452_trigger_ops = { 1425 .set_trigger_state = mma8452_data_rdy_trigger_set_state, 1426 .validate_device = iio_trigger_validate_own_device, 1427 }; 1428 1429 static int mma8452_trigger_setup(struct iio_dev *indio_dev) 1430 { 1431 struct mma8452_data *data = iio_priv(indio_dev); 1432 struct iio_trigger *trig; 1433 int ret; 1434 1435 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d", 1436 indio_dev->name, 1437 indio_dev->id); 1438 if (!trig) 1439 return -ENOMEM; 1440 1441 trig->dev.parent = &data->client->dev; 1442 trig->ops = &mma8452_trigger_ops; 1443 iio_trigger_set_drvdata(trig, indio_dev); 1444 1445 ret = iio_trigger_register(trig); 1446 if (ret) 1447 return ret; 1448 1449 indio_dev->trig = trig; 1450 1451 return 0; 1452 } 1453 1454 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev) 1455 { 1456 if (indio_dev->trig) 1457 iio_trigger_unregister(indio_dev->trig); 1458 } 1459 1460 static int mma8452_reset(struct i2c_client *client) 1461 { 1462 int i; 1463 int ret; 1464 1465 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2, 1466 MMA8452_CTRL_REG2_RST); 1467 if (ret < 0) 1468 return ret; 1469 1470 for (i = 0; i < 10; i++) { 1471 usleep_range(100, 200); 1472 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2); 1473 if (ret == -EIO) 1474 continue; /* I2C comm reset */ 1475 if (ret < 0) 1476 return ret; 1477 if (!(ret & MMA8452_CTRL_REG2_RST)) 1478 return 0; 1479 } 1480 1481 return -ETIMEDOUT; 1482 } 1483 1484 static const struct of_device_id mma8452_dt_ids[] = { 1485 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] }, 1486 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] }, 1487 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] }, 1488 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] }, 1489 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] }, 1490 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] }, 1491 { } 1492 }; 1493 MODULE_DEVICE_TABLE(of, mma8452_dt_ids); 1494 1495 static int mma8452_probe(struct i2c_client *client, 1496 const struct i2c_device_id *id) 1497 { 1498 struct mma8452_data *data; 1499 struct iio_dev *indio_dev; 1500 int ret; 1501 const struct of_device_id *match; 1502 1503 match = of_match_device(mma8452_dt_ids, &client->dev); 1504 if (!match) { 1505 dev_err(&client->dev, "unknown device model\n"); 1506 return -ENODEV; 1507 } 1508 1509 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 1510 if (!indio_dev) 1511 return -ENOMEM; 1512 1513 data = iio_priv(indio_dev); 1514 data->client = client; 1515 mutex_init(&data->lock); 1516 data->chip_info = match->data; 1517 1518 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I); 1519 if (ret < 0) 1520 return ret; 1521 1522 switch (ret) { 1523 case MMA8451_DEVICE_ID: 1524 case MMA8452_DEVICE_ID: 1525 case MMA8453_DEVICE_ID: 1526 case MMA8652_DEVICE_ID: 1527 case MMA8653_DEVICE_ID: 1528 case FXLS8471_DEVICE_ID: 1529 if (ret == data->chip_info->chip_id) 1530 break; 1531 default: 1532 return -ENODEV; 1533 } 1534 1535 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n", 1536 match->compatible, data->chip_info->chip_id); 1537 1538 i2c_set_clientdata(client, indio_dev); 1539 indio_dev->info = &mma8452_info; 1540 indio_dev->name = id->name; 1541 indio_dev->dev.parent = &client->dev; 1542 indio_dev->modes = INDIO_DIRECT_MODE; 1543 indio_dev->channels = data->chip_info->channels; 1544 indio_dev->num_channels = data->chip_info->num_channels; 1545 indio_dev->available_scan_masks = mma8452_scan_masks; 1546 1547 ret = mma8452_reset(client); 1548 if (ret < 0) 1549 return ret; 1550 1551 data->data_cfg = MMA8452_DATA_CFG_FS_2G; 1552 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG, 1553 data->data_cfg); 1554 if (ret < 0) 1555 return ret; 1556 1557 /* 1558 * By default set transient threshold to max to avoid events if 1559 * enabling without configuring threshold. 1560 */ 1561 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS, 1562 MMA8452_TRANSIENT_THS_MASK); 1563 if (ret < 0) 1564 return ret; 1565 1566 if (client->irq) { 1567 int irq2; 1568 1569 irq2 = of_irq_get_byname(client->dev.of_node, "INT2"); 1570 1571 if (irq2 == client->irq) { 1572 dev_dbg(&client->dev, "using interrupt line INT2\n"); 1573 } else { 1574 ret = i2c_smbus_write_byte_data(client, 1575 MMA8452_CTRL_REG5, 1576 data->chip_info->all_events); 1577 if (ret < 0) 1578 return ret; 1579 1580 dev_dbg(&client->dev, "using interrupt line INT1\n"); 1581 } 1582 1583 ret = i2c_smbus_write_byte_data(client, 1584 MMA8452_CTRL_REG4, 1585 data->chip_info->enabled_events); 1586 if (ret < 0) 1587 return ret; 1588 1589 ret = mma8452_trigger_setup(indio_dev); 1590 if (ret < 0) 1591 return ret; 1592 } 1593 1594 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE | 1595 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT); 1596 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1, 1597 data->ctrl_reg1); 1598 if (ret < 0) 1599 goto trigger_cleanup; 1600 1601 ret = iio_triggered_buffer_setup(indio_dev, NULL, 1602 mma8452_trigger_handler, NULL); 1603 if (ret < 0) 1604 goto trigger_cleanup; 1605 1606 if (client->irq) { 1607 ret = devm_request_threaded_irq(&client->dev, 1608 client->irq, 1609 NULL, mma8452_interrupt, 1610 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1611 client->name, indio_dev); 1612 if (ret) 1613 goto buffer_cleanup; 1614 } 1615 1616 ret = pm_runtime_set_active(&client->dev); 1617 if (ret < 0) 1618 goto buffer_cleanup; 1619 1620 pm_runtime_enable(&client->dev); 1621 pm_runtime_set_autosuspend_delay(&client->dev, 1622 MMA8452_AUTO_SUSPEND_DELAY_MS); 1623 pm_runtime_use_autosuspend(&client->dev); 1624 1625 ret = iio_device_register(indio_dev); 1626 if (ret < 0) 1627 goto buffer_cleanup; 1628 1629 ret = mma8452_set_freefall_mode(data, false); 1630 if (ret < 0) 1631 goto buffer_cleanup; 1632 1633 return 0; 1634 1635 buffer_cleanup: 1636 iio_triggered_buffer_cleanup(indio_dev); 1637 1638 trigger_cleanup: 1639 mma8452_trigger_cleanup(indio_dev); 1640 1641 return ret; 1642 } 1643 1644 static int mma8452_remove(struct i2c_client *client) 1645 { 1646 struct iio_dev *indio_dev = i2c_get_clientdata(client); 1647 1648 iio_device_unregister(indio_dev); 1649 1650 pm_runtime_disable(&client->dev); 1651 pm_runtime_set_suspended(&client->dev); 1652 pm_runtime_put_noidle(&client->dev); 1653 1654 iio_triggered_buffer_cleanup(indio_dev); 1655 mma8452_trigger_cleanup(indio_dev); 1656 mma8452_standby(iio_priv(indio_dev)); 1657 1658 return 0; 1659 } 1660 1661 #ifdef CONFIG_PM 1662 static int mma8452_runtime_suspend(struct device *dev) 1663 { 1664 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1665 struct mma8452_data *data = iio_priv(indio_dev); 1666 int ret; 1667 1668 mutex_lock(&data->lock); 1669 ret = mma8452_standby(data); 1670 mutex_unlock(&data->lock); 1671 if (ret < 0) { 1672 dev_err(&data->client->dev, "powering off device failed\n"); 1673 return -EAGAIN; 1674 } 1675 1676 return 0; 1677 } 1678 1679 static int mma8452_runtime_resume(struct device *dev) 1680 { 1681 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1682 struct mma8452_data *data = iio_priv(indio_dev); 1683 int ret, sleep_val; 1684 1685 ret = mma8452_active(data); 1686 if (ret < 0) 1687 return ret; 1688 1689 ret = mma8452_get_odr_index(data); 1690 sleep_val = 1000 / mma8452_samp_freq[ret][0]; 1691 if (sleep_val < 20) 1692 usleep_range(sleep_val * 1000, 20000); 1693 else 1694 msleep_interruptible(sleep_val); 1695 1696 return 0; 1697 } 1698 #endif 1699 1700 #ifdef CONFIG_PM_SLEEP 1701 static int mma8452_suspend(struct device *dev) 1702 { 1703 return mma8452_standby(iio_priv(i2c_get_clientdata( 1704 to_i2c_client(dev)))); 1705 } 1706 1707 static int mma8452_resume(struct device *dev) 1708 { 1709 return mma8452_active(iio_priv(i2c_get_clientdata( 1710 to_i2c_client(dev)))); 1711 } 1712 #endif 1713 1714 static const struct dev_pm_ops mma8452_pm_ops = { 1715 SET_SYSTEM_SLEEP_PM_OPS(mma8452_suspend, mma8452_resume) 1716 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend, 1717 mma8452_runtime_resume, NULL) 1718 }; 1719 1720 static const struct i2c_device_id mma8452_id[] = { 1721 { "mma8451", mma8451 }, 1722 { "mma8452", mma8452 }, 1723 { "mma8453", mma8453 }, 1724 { "mma8652", mma8652 }, 1725 { "mma8653", mma8653 }, 1726 { "fxls8471", fxls8471 }, 1727 { } 1728 }; 1729 MODULE_DEVICE_TABLE(i2c, mma8452_id); 1730 1731 static struct i2c_driver mma8452_driver = { 1732 .driver = { 1733 .name = "mma8452", 1734 .of_match_table = of_match_ptr(mma8452_dt_ids), 1735 .pm = &mma8452_pm_ops, 1736 }, 1737 .probe = mma8452_probe, 1738 .remove = mma8452_remove, 1739 .id_table = mma8452_id, 1740 }; 1741 module_i2c_driver(mma8452_driver); 1742 1743 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>"); 1744 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver"); 1745 MODULE_LICENSE("GPL"); 1746