1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers: 4 * 5 * device name digital output 7-bit I2C slave address (pin selectable) 6 * --------------------------------------------------------------------- 7 * MMA8451Q 14 bit 0x1c / 0x1d 8 * MMA8452Q 12 bit 0x1c / 0x1d 9 * MMA8453Q 10 bit 0x1c / 0x1d 10 * MMA8652FC 12 bit 0x1d 11 * MMA8653FC 10 bit 0x1d 12 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f 13 * 14 * Copyright 2015 Martin Kepplinger <martink@posteo.de> 15 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net> 16 * 17 * 18 * TODO: orientation events 19 */ 20 21 #include <linux/module.h> 22 #include <linux/i2c.h> 23 #include <linux/iio/iio.h> 24 #include <linux/iio/sysfs.h> 25 #include <linux/iio/buffer.h> 26 #include <linux/iio/trigger.h> 27 #include <linux/iio/trigger_consumer.h> 28 #include <linux/iio/triggered_buffer.h> 29 #include <linux/iio/events.h> 30 #include <linux/delay.h> 31 #include <linux/of_device.h> 32 #include <linux/of_irq.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/regulator/consumer.h> 35 36 #define MMA8452_STATUS 0x00 37 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0)) 38 #define MMA8452_OUT_X 0x01 /* MSB first */ 39 #define MMA8452_OUT_Y 0x03 40 #define MMA8452_OUT_Z 0x05 41 #define MMA8452_INT_SRC 0x0c 42 #define MMA8452_WHO_AM_I 0x0d 43 #define MMA8452_DATA_CFG 0x0e 44 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0) 45 #define MMA8452_DATA_CFG_FS_2G 0 46 #define MMA8452_DATA_CFG_FS_4G 1 47 #define MMA8452_DATA_CFG_FS_8G 2 48 #define MMA8452_DATA_CFG_HPF_MASK BIT(4) 49 #define MMA8452_HP_FILTER_CUTOFF 0x0f 50 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0) 51 #define MMA8452_FF_MT_CFG 0x15 52 #define MMA8452_FF_MT_CFG_OAE BIT(6) 53 #define MMA8452_FF_MT_CFG_ELE BIT(7) 54 #define MMA8452_FF_MT_SRC 0x16 55 #define MMA8452_FF_MT_SRC_XHE BIT(1) 56 #define MMA8452_FF_MT_SRC_YHE BIT(3) 57 #define MMA8452_FF_MT_SRC_ZHE BIT(5) 58 #define MMA8452_FF_MT_THS 0x17 59 #define MMA8452_FF_MT_THS_MASK 0x7f 60 #define MMA8452_FF_MT_COUNT 0x18 61 #define MMA8452_FF_MT_CHAN_SHIFT 3 62 #define MMA8452_TRANSIENT_CFG 0x1d 63 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1) 64 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0) 65 #define MMA8452_TRANSIENT_CFG_ELE BIT(4) 66 #define MMA8452_TRANSIENT_SRC 0x1e 67 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1) 68 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3) 69 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5) 70 #define MMA8452_TRANSIENT_THS 0x1f 71 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0) 72 #define MMA8452_TRANSIENT_COUNT 0x20 73 #define MMA8452_TRANSIENT_CHAN_SHIFT 1 74 #define MMA8452_CTRL_REG1 0x2a 75 #define MMA8452_CTRL_ACTIVE BIT(0) 76 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3) 77 #define MMA8452_CTRL_DR_SHIFT 3 78 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */ 79 #define MMA8452_CTRL_REG2 0x2b 80 #define MMA8452_CTRL_REG2_RST BIT(6) 81 #define MMA8452_CTRL_REG2_MODS_SHIFT 3 82 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b 83 #define MMA8452_CTRL_REG4 0x2d 84 #define MMA8452_CTRL_REG5 0x2e 85 #define MMA8452_OFF_X 0x2f 86 #define MMA8452_OFF_Y 0x30 87 #define MMA8452_OFF_Z 0x31 88 89 #define MMA8452_MAX_REG 0x31 90 91 #define MMA8452_INT_DRDY BIT(0) 92 #define MMA8452_INT_FF_MT BIT(2) 93 #define MMA8452_INT_TRANS BIT(5) 94 95 #define MMA8451_DEVICE_ID 0x1a 96 #define MMA8452_DEVICE_ID 0x2a 97 #define MMA8453_DEVICE_ID 0x3a 98 #define MMA8652_DEVICE_ID 0x4a 99 #define MMA8653_DEVICE_ID 0x5a 100 #define FXLS8471_DEVICE_ID 0x6a 101 102 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000 103 104 struct mma8452_data { 105 struct i2c_client *client; 106 struct mutex lock; 107 u8 ctrl_reg1; 108 u8 data_cfg; 109 const struct mma_chip_info *chip_info; 110 int sleep_val; 111 struct regulator *vdd_reg; 112 struct regulator *vddio_reg; 113 }; 114 115 /** 116 * struct mma8452_event_regs - chip specific data related to events 117 * @ev_cfg: event config register address 118 * @ev_cfg_ele: latch bit in event config register 119 * @ev_cfg_chan_shift: number of the bit to enable events in X 120 * direction; in event config register 121 * @ev_src: event source register address 122 * @ev_ths: event threshold register address 123 * @ev_ths_mask: mask for the threshold value 124 * @ev_count: event count (period) register address 125 * 126 * Since not all chips supported by the driver support comparing high pass 127 * filtered data for events (interrupts), different interrupt sources are 128 * used for different chips and the relevant registers are included here. 129 */ 130 struct mma8452_event_regs { 131 u8 ev_cfg; 132 u8 ev_cfg_ele; 133 u8 ev_cfg_chan_shift; 134 u8 ev_src; 135 u8 ev_ths; 136 u8 ev_ths_mask; 137 u8 ev_count; 138 }; 139 140 static const struct mma8452_event_regs ff_mt_ev_regs = { 141 .ev_cfg = MMA8452_FF_MT_CFG, 142 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE, 143 .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT, 144 .ev_src = MMA8452_FF_MT_SRC, 145 .ev_ths = MMA8452_FF_MT_THS, 146 .ev_ths_mask = MMA8452_FF_MT_THS_MASK, 147 .ev_count = MMA8452_FF_MT_COUNT 148 }; 149 150 static const struct mma8452_event_regs trans_ev_regs = { 151 .ev_cfg = MMA8452_TRANSIENT_CFG, 152 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE, 153 .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT, 154 .ev_src = MMA8452_TRANSIENT_SRC, 155 .ev_ths = MMA8452_TRANSIENT_THS, 156 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK, 157 .ev_count = MMA8452_TRANSIENT_COUNT, 158 }; 159 160 /** 161 * struct mma_chip_info - chip specific data 162 * @chip_id: WHO_AM_I register's value 163 * @channels: struct iio_chan_spec matching the device's 164 * capabilities 165 * @num_channels: number of channels 166 * @mma_scales: scale factors for converting register values 167 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers 168 * per mode: m/s^2 and micro m/s^2 169 * @all_events: all events supported by this chip 170 * @enabled_events: event flags enabled and handled by this driver 171 */ 172 struct mma_chip_info { 173 u8 chip_id; 174 const struct iio_chan_spec *channels; 175 int num_channels; 176 const int mma_scales[3][2]; 177 int all_events; 178 int enabled_events; 179 }; 180 181 enum { 182 idx_x, 183 idx_y, 184 idx_z, 185 idx_ts, 186 }; 187 188 static int mma8452_drdy(struct mma8452_data *data) 189 { 190 int tries = 150; 191 192 while (tries-- > 0) { 193 int ret = i2c_smbus_read_byte_data(data->client, 194 MMA8452_STATUS); 195 if (ret < 0) 196 return ret; 197 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY) 198 return 0; 199 200 if (data->sleep_val <= 20) 201 usleep_range(data->sleep_val * 250, 202 data->sleep_val * 500); 203 else 204 msleep(20); 205 } 206 207 dev_err(&data->client->dev, "data not ready\n"); 208 209 return -EIO; 210 } 211 212 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on) 213 { 214 #ifdef CONFIG_PM 215 int ret; 216 217 if (on) { 218 ret = pm_runtime_get_sync(&client->dev); 219 } else { 220 pm_runtime_mark_last_busy(&client->dev); 221 ret = pm_runtime_put_autosuspend(&client->dev); 222 } 223 224 if (ret < 0) { 225 dev_err(&client->dev, 226 "failed to change power state to %d\n", on); 227 if (on) 228 pm_runtime_put_noidle(&client->dev); 229 230 return ret; 231 } 232 #endif 233 234 return 0; 235 } 236 237 static int mma8452_read(struct mma8452_data *data, __be16 buf[3]) 238 { 239 int ret = mma8452_drdy(data); 240 241 if (ret < 0) 242 return ret; 243 244 ret = mma8452_set_runtime_pm_state(data->client, true); 245 if (ret) 246 return ret; 247 248 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X, 249 3 * sizeof(__be16), (u8 *)buf); 250 251 ret = mma8452_set_runtime_pm_state(data->client, false); 252 253 return ret; 254 } 255 256 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2], 257 int n) 258 { 259 size_t len = 0; 260 261 while (n-- > 0) 262 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ", 263 vals[n][0], vals[n][1]); 264 265 /* replace trailing space by newline */ 266 buf[len - 1] = '\n'; 267 268 return len; 269 } 270 271 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n, 272 int val, int val2) 273 { 274 while (n-- > 0) 275 if (val == vals[n][0] && val2 == vals[n][1]) 276 return n; 277 278 return -EINVAL; 279 } 280 281 static unsigned int mma8452_get_odr_index(struct mma8452_data *data) 282 { 283 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >> 284 MMA8452_CTRL_DR_SHIFT; 285 } 286 287 static const int mma8452_samp_freq[8][2] = { 288 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000}, 289 {6, 250000}, {1, 560000} 290 }; 291 292 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */ 293 static const unsigned int mma8452_time_step_us[4][8] = { 294 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */ 295 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */ 296 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/ 297 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */ 298 }; 299 300 /* Datasheet table "High-Pass Filter Cutoff Options" */ 301 static const int mma8452_hp_filter_cutoff[4][8][4][2] = { 302 { /* normal */ 303 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */ 304 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */ 305 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */ 306 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */ 307 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */ 308 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */ 309 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */ 310 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */ 311 }, 312 { /* low noise low power */ 313 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 314 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 315 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 316 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 317 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 318 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 319 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 320 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} } 321 }, 322 { /* high resolution */ 323 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 324 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 325 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 326 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 327 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 328 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 329 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 330 { {16, 0}, {8, 0}, {4, 0}, {2, 0} } 331 }, 332 { /* low power */ 333 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 334 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 335 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 336 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 337 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} }, 338 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 339 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 340 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} } 341 } 342 }; 343 344 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */ 345 static const u16 mma8452_os_ratio[4][8] = { 346 /* 800 Hz, 400 Hz, ... , 1.56 Hz */ 347 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */ 348 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */ 349 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */ 350 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */ 351 }; 352 353 static int mma8452_get_power_mode(struct mma8452_data *data) 354 { 355 int reg; 356 357 reg = i2c_smbus_read_byte_data(data->client, 358 MMA8452_CTRL_REG2); 359 if (reg < 0) 360 return reg; 361 362 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >> 363 MMA8452_CTRL_REG2_MODS_SHIFT); 364 } 365 366 static ssize_t mma8452_show_samp_freq_avail(struct device *dev, 367 struct device_attribute *attr, 368 char *buf) 369 { 370 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq, 371 ARRAY_SIZE(mma8452_samp_freq)); 372 } 373 374 static ssize_t mma8452_show_scale_avail(struct device *dev, 375 struct device_attribute *attr, 376 char *buf) 377 { 378 struct mma8452_data *data = iio_priv(i2c_get_clientdata( 379 to_i2c_client(dev))); 380 381 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales, 382 ARRAY_SIZE(data->chip_info->mma_scales)); 383 } 384 385 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev, 386 struct device_attribute *attr, 387 char *buf) 388 { 389 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 390 struct mma8452_data *data = iio_priv(indio_dev); 391 int i, j; 392 393 i = mma8452_get_odr_index(data); 394 j = mma8452_get_power_mode(data); 395 if (j < 0) 396 return j; 397 398 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i], 399 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0])); 400 } 401 402 static ssize_t mma8452_show_os_ratio_avail(struct device *dev, 403 struct device_attribute *attr, 404 char *buf) 405 { 406 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 407 struct mma8452_data *data = iio_priv(indio_dev); 408 int i = mma8452_get_odr_index(data); 409 int j; 410 u16 val = 0; 411 size_t len = 0; 412 413 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) { 414 if (val == mma8452_os_ratio[j][i]) 415 continue; 416 417 val = mma8452_os_ratio[j][i]; 418 419 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val); 420 } 421 buf[len - 1] = '\n'; 422 423 return len; 424 } 425 426 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail); 427 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444, 428 mma8452_show_scale_avail, NULL, 0); 429 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available, 430 0444, mma8452_show_hp_cutoff_avail, NULL, 0); 431 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444, 432 mma8452_show_os_ratio_avail, NULL, 0); 433 434 static int mma8452_get_samp_freq_index(struct mma8452_data *data, 435 int val, int val2) 436 { 437 return mma8452_get_int_plus_micros_index(mma8452_samp_freq, 438 ARRAY_SIZE(mma8452_samp_freq), 439 val, val2); 440 } 441 442 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2) 443 { 444 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales, 445 ARRAY_SIZE(data->chip_info->mma_scales), val, val2); 446 } 447 448 static int mma8452_get_hp_filter_index(struct mma8452_data *data, 449 int val, int val2) 450 { 451 int i, j; 452 453 i = mma8452_get_odr_index(data); 454 j = mma8452_get_power_mode(data); 455 if (j < 0) 456 return j; 457 458 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i], 459 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2); 460 } 461 462 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz) 463 { 464 int j, i, ret; 465 466 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF); 467 if (ret < 0) 468 return ret; 469 470 i = mma8452_get_odr_index(data); 471 j = mma8452_get_power_mode(data); 472 if (j < 0) 473 return j; 474 475 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 476 *hz = mma8452_hp_filter_cutoff[j][i][ret][0]; 477 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1]; 478 479 return 0; 480 } 481 482 static int mma8452_read_raw(struct iio_dev *indio_dev, 483 struct iio_chan_spec const *chan, 484 int *val, int *val2, long mask) 485 { 486 struct mma8452_data *data = iio_priv(indio_dev); 487 __be16 buffer[3]; 488 int i, ret; 489 490 switch (mask) { 491 case IIO_CHAN_INFO_RAW: 492 ret = iio_device_claim_direct_mode(indio_dev); 493 if (ret) 494 return ret; 495 496 mutex_lock(&data->lock); 497 ret = mma8452_read(data, buffer); 498 mutex_unlock(&data->lock); 499 iio_device_release_direct_mode(indio_dev); 500 if (ret < 0) 501 return ret; 502 503 *val = sign_extend32(be16_to_cpu( 504 buffer[chan->scan_index]) >> chan->scan_type.shift, 505 chan->scan_type.realbits - 1); 506 507 return IIO_VAL_INT; 508 case IIO_CHAN_INFO_SCALE: 509 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK; 510 *val = data->chip_info->mma_scales[i][0]; 511 *val2 = data->chip_info->mma_scales[i][1]; 512 513 return IIO_VAL_INT_PLUS_MICRO; 514 case IIO_CHAN_INFO_SAMP_FREQ: 515 i = mma8452_get_odr_index(data); 516 *val = mma8452_samp_freq[i][0]; 517 *val2 = mma8452_samp_freq[i][1]; 518 519 return IIO_VAL_INT_PLUS_MICRO; 520 case IIO_CHAN_INFO_CALIBBIAS: 521 ret = i2c_smbus_read_byte_data(data->client, 522 MMA8452_OFF_X + 523 chan->scan_index); 524 if (ret < 0) 525 return ret; 526 527 *val = sign_extend32(ret, 7); 528 529 return IIO_VAL_INT; 530 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 531 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) { 532 ret = mma8452_read_hp_filter(data, val, val2); 533 if (ret < 0) 534 return ret; 535 } else { 536 *val = 0; 537 *val2 = 0; 538 } 539 540 return IIO_VAL_INT_PLUS_MICRO; 541 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 542 ret = mma8452_get_power_mode(data); 543 if (ret < 0) 544 return ret; 545 546 i = mma8452_get_odr_index(data); 547 548 *val = mma8452_os_ratio[ret][i]; 549 return IIO_VAL_INT; 550 } 551 552 return -EINVAL; 553 } 554 555 static int mma8452_calculate_sleep(struct mma8452_data *data) 556 { 557 int ret, i = mma8452_get_odr_index(data); 558 559 if (mma8452_samp_freq[i][0] > 0) 560 ret = 1000 / mma8452_samp_freq[i][0]; 561 else 562 ret = 1000; 563 564 return ret == 0 ? 1 : ret; 565 } 566 567 static int mma8452_standby(struct mma8452_data *data) 568 { 569 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 570 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE); 571 } 572 573 static int mma8452_active(struct mma8452_data *data) 574 { 575 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 576 data->ctrl_reg1); 577 } 578 579 /* returns >0 if active, 0 if in standby and <0 on error */ 580 static int mma8452_is_active(struct mma8452_data *data) 581 { 582 int reg; 583 584 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1); 585 if (reg < 0) 586 return reg; 587 588 return reg & MMA8452_CTRL_ACTIVE; 589 } 590 591 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val) 592 { 593 int ret; 594 int is_active; 595 596 mutex_lock(&data->lock); 597 598 is_active = mma8452_is_active(data); 599 if (is_active < 0) { 600 ret = is_active; 601 goto fail; 602 } 603 604 /* config can only be changed when in standby */ 605 if (is_active > 0) { 606 ret = mma8452_standby(data); 607 if (ret < 0) 608 goto fail; 609 } 610 611 ret = i2c_smbus_write_byte_data(data->client, reg, val); 612 if (ret < 0) 613 goto fail; 614 615 if (is_active > 0) { 616 ret = mma8452_active(data); 617 if (ret < 0) 618 goto fail; 619 } 620 621 ret = 0; 622 fail: 623 mutex_unlock(&data->lock); 624 625 return ret; 626 } 627 628 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode) 629 { 630 int reg; 631 632 reg = i2c_smbus_read_byte_data(data->client, 633 MMA8452_CTRL_REG2); 634 if (reg < 0) 635 return reg; 636 637 reg &= ~MMA8452_CTRL_REG2_MODS_MASK; 638 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT; 639 640 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg); 641 } 642 643 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */ 644 static int mma8452_freefall_mode_enabled(struct mma8452_data *data) 645 { 646 int val; 647 648 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); 649 if (val < 0) 650 return val; 651 652 return !(val & MMA8452_FF_MT_CFG_OAE); 653 } 654 655 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state) 656 { 657 int val; 658 659 if ((state && mma8452_freefall_mode_enabled(data)) || 660 (!state && !(mma8452_freefall_mode_enabled(data)))) 661 return 0; 662 663 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); 664 if (val < 0) 665 return val; 666 667 if (state) { 668 val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); 669 val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); 670 val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); 671 val &= ~MMA8452_FF_MT_CFG_OAE; 672 } else { 673 val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); 674 val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); 675 val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); 676 val |= MMA8452_FF_MT_CFG_OAE; 677 } 678 679 return mma8452_change_config(data, MMA8452_FF_MT_CFG, val); 680 } 681 682 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data, 683 int val, int val2) 684 { 685 int i, reg; 686 687 i = mma8452_get_hp_filter_index(data, val, val2); 688 if (i < 0) 689 return i; 690 691 reg = i2c_smbus_read_byte_data(data->client, 692 MMA8452_HP_FILTER_CUTOFF); 693 if (reg < 0) 694 return reg; 695 696 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 697 reg |= i; 698 699 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg); 700 } 701 702 static int mma8452_write_raw(struct iio_dev *indio_dev, 703 struct iio_chan_spec const *chan, 704 int val, int val2, long mask) 705 { 706 struct mma8452_data *data = iio_priv(indio_dev); 707 int i, ret; 708 709 ret = iio_device_claim_direct_mode(indio_dev); 710 if (ret) 711 return ret; 712 713 switch (mask) { 714 case IIO_CHAN_INFO_SAMP_FREQ: 715 i = mma8452_get_samp_freq_index(data, val, val2); 716 if (i < 0) { 717 ret = i; 718 break; 719 } 720 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK; 721 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT; 722 723 data->sleep_val = mma8452_calculate_sleep(data); 724 725 ret = mma8452_change_config(data, MMA8452_CTRL_REG1, 726 data->ctrl_reg1); 727 break; 728 case IIO_CHAN_INFO_SCALE: 729 i = mma8452_get_scale_index(data, val, val2); 730 if (i < 0) { 731 ret = i; 732 break; 733 } 734 735 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK; 736 data->data_cfg |= i; 737 738 ret = mma8452_change_config(data, MMA8452_DATA_CFG, 739 data->data_cfg); 740 break; 741 case IIO_CHAN_INFO_CALIBBIAS: 742 if (val < -128 || val > 127) { 743 ret = -EINVAL; 744 break; 745 } 746 747 ret = mma8452_change_config(data, 748 MMA8452_OFF_X + chan->scan_index, 749 val); 750 break; 751 752 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 753 if (val == 0 && val2 == 0) { 754 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK; 755 } else { 756 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK; 757 ret = mma8452_set_hp_filter_frequency(data, val, val2); 758 if (ret < 0) 759 break; 760 } 761 762 ret = mma8452_change_config(data, MMA8452_DATA_CFG, 763 data->data_cfg); 764 break; 765 766 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 767 ret = mma8452_get_odr_index(data); 768 769 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) { 770 if (mma8452_os_ratio[i][ret] == val) { 771 ret = mma8452_set_power_mode(data, i); 772 break; 773 } 774 } 775 break; 776 default: 777 ret = -EINVAL; 778 break; 779 } 780 781 iio_device_release_direct_mode(indio_dev); 782 return ret; 783 } 784 785 static int mma8452_get_event_regs(struct mma8452_data *data, 786 const struct iio_chan_spec *chan, enum iio_event_direction dir, 787 const struct mma8452_event_regs **ev_reg) 788 { 789 if (!chan) 790 return -EINVAL; 791 792 switch (chan->type) { 793 case IIO_ACCEL: 794 switch (dir) { 795 case IIO_EV_DIR_RISING: 796 if ((data->chip_info->all_events 797 & MMA8452_INT_TRANS) && 798 (data->chip_info->enabled_events 799 & MMA8452_INT_TRANS)) 800 *ev_reg = &trans_ev_regs; 801 else 802 *ev_reg = &ff_mt_ev_regs; 803 return 0; 804 case IIO_EV_DIR_FALLING: 805 *ev_reg = &ff_mt_ev_regs; 806 return 0; 807 default: 808 return -EINVAL; 809 } 810 default: 811 return -EINVAL; 812 } 813 } 814 815 static int mma8452_read_event_value(struct iio_dev *indio_dev, 816 const struct iio_chan_spec *chan, 817 enum iio_event_type type, 818 enum iio_event_direction dir, 819 enum iio_event_info info, 820 int *val, int *val2) 821 { 822 struct mma8452_data *data = iio_priv(indio_dev); 823 int ret, us, power_mode; 824 const struct mma8452_event_regs *ev_regs; 825 826 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 827 if (ret) 828 return ret; 829 830 switch (info) { 831 case IIO_EV_INFO_VALUE: 832 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths); 833 if (ret < 0) 834 return ret; 835 836 *val = ret & ev_regs->ev_ths_mask; 837 838 return IIO_VAL_INT; 839 840 case IIO_EV_INFO_PERIOD: 841 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count); 842 if (ret < 0) 843 return ret; 844 845 power_mode = mma8452_get_power_mode(data); 846 if (power_mode < 0) 847 return power_mode; 848 849 us = ret * mma8452_time_step_us[power_mode][ 850 mma8452_get_odr_index(data)]; 851 *val = us / USEC_PER_SEC; 852 *val2 = us % USEC_PER_SEC; 853 854 return IIO_VAL_INT_PLUS_MICRO; 855 856 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 857 ret = i2c_smbus_read_byte_data(data->client, 858 MMA8452_TRANSIENT_CFG); 859 if (ret < 0) 860 return ret; 861 862 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) { 863 *val = 0; 864 *val2 = 0; 865 } else { 866 ret = mma8452_read_hp_filter(data, val, val2); 867 if (ret < 0) 868 return ret; 869 } 870 871 return IIO_VAL_INT_PLUS_MICRO; 872 873 default: 874 return -EINVAL; 875 } 876 } 877 878 static int mma8452_write_event_value(struct iio_dev *indio_dev, 879 const struct iio_chan_spec *chan, 880 enum iio_event_type type, 881 enum iio_event_direction dir, 882 enum iio_event_info info, 883 int val, int val2) 884 { 885 struct mma8452_data *data = iio_priv(indio_dev); 886 int ret, reg, steps; 887 const struct mma8452_event_regs *ev_regs; 888 889 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 890 if (ret) 891 return ret; 892 893 switch (info) { 894 case IIO_EV_INFO_VALUE: 895 if (val < 0 || val > ev_regs->ev_ths_mask) 896 return -EINVAL; 897 898 return mma8452_change_config(data, ev_regs->ev_ths, val); 899 900 case IIO_EV_INFO_PERIOD: 901 ret = mma8452_get_power_mode(data); 902 if (ret < 0) 903 return ret; 904 905 steps = (val * USEC_PER_SEC + val2) / 906 mma8452_time_step_us[ret][ 907 mma8452_get_odr_index(data)]; 908 909 if (steps < 0 || steps > 0xff) 910 return -EINVAL; 911 912 return mma8452_change_config(data, ev_regs->ev_count, steps); 913 914 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 915 reg = i2c_smbus_read_byte_data(data->client, 916 MMA8452_TRANSIENT_CFG); 917 if (reg < 0) 918 return reg; 919 920 if (val == 0 && val2 == 0) { 921 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP; 922 } else { 923 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP; 924 ret = mma8452_set_hp_filter_frequency(data, val, val2); 925 if (ret < 0) 926 return ret; 927 } 928 929 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg); 930 931 default: 932 return -EINVAL; 933 } 934 } 935 936 static int mma8452_read_event_config(struct iio_dev *indio_dev, 937 const struct iio_chan_spec *chan, 938 enum iio_event_type type, 939 enum iio_event_direction dir) 940 { 941 struct mma8452_data *data = iio_priv(indio_dev); 942 int ret; 943 const struct mma8452_event_regs *ev_regs; 944 945 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 946 if (ret) 947 return ret; 948 949 switch (dir) { 950 case IIO_EV_DIR_FALLING: 951 return mma8452_freefall_mode_enabled(data); 952 case IIO_EV_DIR_RISING: 953 ret = i2c_smbus_read_byte_data(data->client, 954 ev_regs->ev_cfg); 955 if (ret < 0) 956 return ret; 957 958 return !!(ret & BIT(chan->scan_index + 959 ev_regs->ev_cfg_chan_shift)); 960 default: 961 return -EINVAL; 962 } 963 } 964 965 static int mma8452_write_event_config(struct iio_dev *indio_dev, 966 const struct iio_chan_spec *chan, 967 enum iio_event_type type, 968 enum iio_event_direction dir, 969 int state) 970 { 971 struct mma8452_data *data = iio_priv(indio_dev); 972 int val, ret; 973 const struct mma8452_event_regs *ev_regs; 974 975 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 976 if (ret) 977 return ret; 978 979 ret = mma8452_set_runtime_pm_state(data->client, state); 980 if (ret) 981 return ret; 982 983 switch (dir) { 984 case IIO_EV_DIR_FALLING: 985 return mma8452_set_freefall_mode(data, state); 986 case IIO_EV_DIR_RISING: 987 val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg); 988 if (val < 0) 989 return val; 990 991 if (state) { 992 if (mma8452_freefall_mode_enabled(data)) { 993 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift); 994 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift); 995 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift); 996 val |= MMA8452_FF_MT_CFG_OAE; 997 } 998 val |= BIT(chan->scan_index + 999 ev_regs->ev_cfg_chan_shift); 1000 } else { 1001 if (mma8452_freefall_mode_enabled(data)) 1002 return 0; 1003 1004 val &= ~BIT(chan->scan_index + 1005 ev_regs->ev_cfg_chan_shift); 1006 } 1007 1008 val |= ev_regs->ev_cfg_ele; 1009 1010 return mma8452_change_config(data, ev_regs->ev_cfg, val); 1011 default: 1012 return -EINVAL; 1013 } 1014 } 1015 1016 static void mma8452_transient_interrupt(struct iio_dev *indio_dev) 1017 { 1018 struct mma8452_data *data = iio_priv(indio_dev); 1019 s64 ts = iio_get_time_ns(indio_dev); 1020 int src; 1021 1022 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC); 1023 if (src < 0) 1024 return; 1025 1026 if (src & MMA8452_TRANSIENT_SRC_XTRANSE) 1027 iio_push_event(indio_dev, 1028 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1029 IIO_EV_TYPE_MAG, 1030 IIO_EV_DIR_RISING), 1031 ts); 1032 1033 if (src & MMA8452_TRANSIENT_SRC_YTRANSE) 1034 iio_push_event(indio_dev, 1035 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y, 1036 IIO_EV_TYPE_MAG, 1037 IIO_EV_DIR_RISING), 1038 ts); 1039 1040 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE) 1041 iio_push_event(indio_dev, 1042 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z, 1043 IIO_EV_TYPE_MAG, 1044 IIO_EV_DIR_RISING), 1045 ts); 1046 } 1047 1048 static irqreturn_t mma8452_interrupt(int irq, void *p) 1049 { 1050 struct iio_dev *indio_dev = p; 1051 struct mma8452_data *data = iio_priv(indio_dev); 1052 int ret = IRQ_NONE; 1053 int src; 1054 1055 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC); 1056 if (src < 0) 1057 return IRQ_NONE; 1058 1059 if (!(src & (data->chip_info->enabled_events | MMA8452_INT_DRDY))) 1060 return IRQ_NONE; 1061 1062 if (src & MMA8452_INT_DRDY) { 1063 iio_trigger_poll_chained(indio_dev->trig); 1064 ret = IRQ_HANDLED; 1065 } 1066 1067 if (src & MMA8452_INT_FF_MT) { 1068 if (mma8452_freefall_mode_enabled(data)) { 1069 s64 ts = iio_get_time_ns(indio_dev); 1070 1071 iio_push_event(indio_dev, 1072 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 1073 IIO_MOD_X_AND_Y_AND_Z, 1074 IIO_EV_TYPE_MAG, 1075 IIO_EV_DIR_FALLING), 1076 ts); 1077 } 1078 ret = IRQ_HANDLED; 1079 } 1080 1081 if (src & MMA8452_INT_TRANS) { 1082 mma8452_transient_interrupt(indio_dev); 1083 ret = IRQ_HANDLED; 1084 } 1085 1086 return ret; 1087 } 1088 1089 static irqreturn_t mma8452_trigger_handler(int irq, void *p) 1090 { 1091 struct iio_poll_func *pf = p; 1092 struct iio_dev *indio_dev = pf->indio_dev; 1093 struct mma8452_data *data = iio_priv(indio_dev); 1094 u8 buffer[16]; /* 3 16-bit channels + padding + ts */ 1095 int ret; 1096 1097 ret = mma8452_read(data, (__be16 *)buffer); 1098 if (ret < 0) 1099 goto done; 1100 1101 iio_push_to_buffers_with_timestamp(indio_dev, buffer, 1102 iio_get_time_ns(indio_dev)); 1103 1104 done: 1105 iio_trigger_notify_done(indio_dev->trig); 1106 1107 return IRQ_HANDLED; 1108 } 1109 1110 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev, 1111 unsigned int reg, unsigned int writeval, 1112 unsigned int *readval) 1113 { 1114 int ret; 1115 struct mma8452_data *data = iio_priv(indio_dev); 1116 1117 if (reg > MMA8452_MAX_REG) 1118 return -EINVAL; 1119 1120 if (!readval) 1121 return mma8452_change_config(data, reg, writeval); 1122 1123 ret = i2c_smbus_read_byte_data(data->client, reg); 1124 if (ret < 0) 1125 return ret; 1126 1127 *readval = ret; 1128 1129 return 0; 1130 } 1131 1132 static const struct iio_event_spec mma8452_freefall_event[] = { 1133 { 1134 .type = IIO_EV_TYPE_MAG, 1135 .dir = IIO_EV_DIR_FALLING, 1136 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1137 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1138 BIT(IIO_EV_INFO_PERIOD) | 1139 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1140 }, 1141 }; 1142 1143 static const struct iio_event_spec mma8652_freefall_event[] = { 1144 { 1145 .type = IIO_EV_TYPE_MAG, 1146 .dir = IIO_EV_DIR_FALLING, 1147 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1148 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1149 BIT(IIO_EV_INFO_PERIOD) 1150 }, 1151 }; 1152 1153 static const struct iio_event_spec mma8452_transient_event[] = { 1154 { 1155 .type = IIO_EV_TYPE_MAG, 1156 .dir = IIO_EV_DIR_RISING, 1157 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1158 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1159 BIT(IIO_EV_INFO_PERIOD) | 1160 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1161 }, 1162 }; 1163 1164 static const struct iio_event_spec mma8452_motion_event[] = { 1165 { 1166 .type = IIO_EV_TYPE_MAG, 1167 .dir = IIO_EV_DIR_RISING, 1168 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1169 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1170 BIT(IIO_EV_INFO_PERIOD) 1171 }, 1172 }; 1173 1174 /* 1175 * Threshold is configured in fixed 8G/127 steps regardless of 1176 * currently selected scale for measurement. 1177 */ 1178 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742"); 1179 1180 static struct attribute *mma8452_event_attributes[] = { 1181 &iio_const_attr_accel_transient_scale.dev_attr.attr, 1182 NULL, 1183 }; 1184 1185 static struct attribute_group mma8452_event_attribute_group = { 1186 .attrs = mma8452_event_attributes, 1187 }; 1188 1189 #define MMA8452_FREEFALL_CHANNEL(modifier) { \ 1190 .type = IIO_ACCEL, \ 1191 .modified = 1, \ 1192 .channel2 = modifier, \ 1193 .scan_index = -1, \ 1194 .event_spec = mma8452_freefall_event, \ 1195 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \ 1196 } 1197 1198 #define MMA8652_FREEFALL_CHANNEL(modifier) { \ 1199 .type = IIO_ACCEL, \ 1200 .modified = 1, \ 1201 .channel2 = modifier, \ 1202 .scan_index = -1, \ 1203 .event_spec = mma8652_freefall_event, \ 1204 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \ 1205 } 1206 1207 #define MMA8452_CHANNEL(axis, idx, bits) { \ 1208 .type = IIO_ACCEL, \ 1209 .modified = 1, \ 1210 .channel2 = IIO_MOD_##axis, \ 1211 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1212 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1213 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1214 BIT(IIO_CHAN_INFO_SCALE) | \ 1215 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \ 1216 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1217 .scan_index = idx, \ 1218 .scan_type = { \ 1219 .sign = 's', \ 1220 .realbits = (bits), \ 1221 .storagebits = 16, \ 1222 .shift = 16 - (bits), \ 1223 .endianness = IIO_BE, \ 1224 }, \ 1225 .event_spec = mma8452_transient_event, \ 1226 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \ 1227 } 1228 1229 #define MMA8652_CHANNEL(axis, idx, bits) { \ 1230 .type = IIO_ACCEL, \ 1231 .modified = 1, \ 1232 .channel2 = IIO_MOD_##axis, \ 1233 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1234 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1235 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1236 BIT(IIO_CHAN_INFO_SCALE) | \ 1237 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1238 .scan_index = idx, \ 1239 .scan_type = { \ 1240 .sign = 's', \ 1241 .realbits = (bits), \ 1242 .storagebits = 16, \ 1243 .shift = 16 - (bits), \ 1244 .endianness = IIO_BE, \ 1245 }, \ 1246 .event_spec = mma8452_motion_event, \ 1247 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \ 1248 } 1249 1250 static const struct iio_chan_spec mma8451_channels[] = { 1251 MMA8452_CHANNEL(X, idx_x, 14), 1252 MMA8452_CHANNEL(Y, idx_y, 14), 1253 MMA8452_CHANNEL(Z, idx_z, 14), 1254 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1255 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1256 }; 1257 1258 static const struct iio_chan_spec mma8452_channels[] = { 1259 MMA8452_CHANNEL(X, idx_x, 12), 1260 MMA8452_CHANNEL(Y, idx_y, 12), 1261 MMA8452_CHANNEL(Z, idx_z, 12), 1262 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1263 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1264 }; 1265 1266 static const struct iio_chan_spec mma8453_channels[] = { 1267 MMA8452_CHANNEL(X, idx_x, 10), 1268 MMA8452_CHANNEL(Y, idx_y, 10), 1269 MMA8452_CHANNEL(Z, idx_z, 10), 1270 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1271 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1272 }; 1273 1274 static const struct iio_chan_spec mma8652_channels[] = { 1275 MMA8652_CHANNEL(X, idx_x, 12), 1276 MMA8652_CHANNEL(Y, idx_y, 12), 1277 MMA8652_CHANNEL(Z, idx_z, 12), 1278 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1279 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1280 }; 1281 1282 static const struct iio_chan_spec mma8653_channels[] = { 1283 MMA8652_CHANNEL(X, idx_x, 10), 1284 MMA8652_CHANNEL(Y, idx_y, 10), 1285 MMA8652_CHANNEL(Z, idx_z, 10), 1286 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1287 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1288 }; 1289 1290 enum { 1291 mma8451, 1292 mma8452, 1293 mma8453, 1294 mma8652, 1295 mma8653, 1296 fxls8471, 1297 }; 1298 1299 static const struct mma_chip_info mma_chip_info_table[] = { 1300 [mma8451] = { 1301 .chip_id = MMA8451_DEVICE_ID, 1302 .channels = mma8451_channels, 1303 .num_channels = ARRAY_SIZE(mma8451_channels), 1304 /* 1305 * Hardware has fullscale of -2G, -4G, -8G corresponding to 1306 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10 1307 * bit. 1308 * The userspace interface uses m/s^2 and we declare micro units 1309 * So scale factor for 12 bit here is given by: 1310 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665 1311 */ 1312 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1313 /* 1314 * Although we enable the interrupt sources once and for 1315 * all here the event detection itself is not enabled until 1316 * userspace asks for it by mma8452_write_event_config() 1317 */ 1318 .all_events = MMA8452_INT_DRDY | 1319 MMA8452_INT_TRANS | 1320 MMA8452_INT_FF_MT, 1321 .enabled_events = MMA8452_INT_TRANS | 1322 MMA8452_INT_FF_MT, 1323 }, 1324 [mma8452] = { 1325 .chip_id = MMA8452_DEVICE_ID, 1326 .channels = mma8452_channels, 1327 .num_channels = ARRAY_SIZE(mma8452_channels), 1328 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1329 /* 1330 * Although we enable the interrupt sources once and for 1331 * all here the event detection itself is not enabled until 1332 * userspace asks for it by mma8452_write_event_config() 1333 */ 1334 .all_events = MMA8452_INT_DRDY | 1335 MMA8452_INT_TRANS | 1336 MMA8452_INT_FF_MT, 1337 .enabled_events = MMA8452_INT_TRANS | 1338 MMA8452_INT_FF_MT, 1339 }, 1340 [mma8453] = { 1341 .chip_id = MMA8453_DEVICE_ID, 1342 .channels = mma8453_channels, 1343 .num_channels = ARRAY_SIZE(mma8453_channels), 1344 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1345 /* 1346 * Although we enable the interrupt sources once and for 1347 * all here the event detection itself is not enabled until 1348 * userspace asks for it by mma8452_write_event_config() 1349 */ 1350 .all_events = MMA8452_INT_DRDY | 1351 MMA8452_INT_TRANS | 1352 MMA8452_INT_FF_MT, 1353 .enabled_events = MMA8452_INT_TRANS | 1354 MMA8452_INT_FF_MT, 1355 }, 1356 [mma8652] = { 1357 .chip_id = MMA8652_DEVICE_ID, 1358 .channels = mma8652_channels, 1359 .num_channels = ARRAY_SIZE(mma8652_channels), 1360 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1361 .all_events = MMA8452_INT_DRDY | 1362 MMA8452_INT_FF_MT, 1363 .enabled_events = MMA8452_INT_FF_MT, 1364 }, 1365 [mma8653] = { 1366 .chip_id = MMA8653_DEVICE_ID, 1367 .channels = mma8653_channels, 1368 .num_channels = ARRAY_SIZE(mma8653_channels), 1369 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1370 /* 1371 * Although we enable the interrupt sources once and for 1372 * all here the event detection itself is not enabled until 1373 * userspace asks for it by mma8452_write_event_config() 1374 */ 1375 .all_events = MMA8452_INT_DRDY | 1376 MMA8452_INT_FF_MT, 1377 .enabled_events = MMA8452_INT_FF_MT, 1378 }, 1379 [fxls8471] = { 1380 .chip_id = FXLS8471_DEVICE_ID, 1381 .channels = mma8451_channels, 1382 .num_channels = ARRAY_SIZE(mma8451_channels), 1383 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1384 /* 1385 * Although we enable the interrupt sources once and for 1386 * all here the event detection itself is not enabled until 1387 * userspace asks for it by mma8452_write_event_config() 1388 */ 1389 .all_events = MMA8452_INT_DRDY | 1390 MMA8452_INT_TRANS | 1391 MMA8452_INT_FF_MT, 1392 .enabled_events = MMA8452_INT_TRANS | 1393 MMA8452_INT_FF_MT, 1394 }, 1395 }; 1396 1397 static struct attribute *mma8452_attributes[] = { 1398 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1399 &iio_dev_attr_in_accel_scale_available.dev_attr.attr, 1400 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr, 1401 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr, 1402 NULL 1403 }; 1404 1405 static const struct attribute_group mma8452_group = { 1406 .attrs = mma8452_attributes, 1407 }; 1408 1409 static const struct iio_info mma8452_info = { 1410 .attrs = &mma8452_group, 1411 .read_raw = &mma8452_read_raw, 1412 .write_raw = &mma8452_write_raw, 1413 .event_attrs = &mma8452_event_attribute_group, 1414 .read_event_value = &mma8452_read_event_value, 1415 .write_event_value = &mma8452_write_event_value, 1416 .read_event_config = &mma8452_read_event_config, 1417 .write_event_config = &mma8452_write_event_config, 1418 .debugfs_reg_access = &mma8452_reg_access_dbg, 1419 }; 1420 1421 static const unsigned long mma8452_scan_masks[] = {0x7, 0}; 1422 1423 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig, 1424 bool state) 1425 { 1426 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1427 struct mma8452_data *data = iio_priv(indio_dev); 1428 int reg, ret; 1429 1430 ret = mma8452_set_runtime_pm_state(data->client, state); 1431 if (ret) 1432 return ret; 1433 1434 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4); 1435 if (reg < 0) 1436 return reg; 1437 1438 if (state) 1439 reg |= MMA8452_INT_DRDY; 1440 else 1441 reg &= ~MMA8452_INT_DRDY; 1442 1443 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg); 1444 } 1445 1446 static const struct iio_trigger_ops mma8452_trigger_ops = { 1447 .set_trigger_state = mma8452_data_rdy_trigger_set_state, 1448 .validate_device = iio_trigger_validate_own_device, 1449 }; 1450 1451 static int mma8452_trigger_setup(struct iio_dev *indio_dev) 1452 { 1453 struct mma8452_data *data = iio_priv(indio_dev); 1454 struct iio_trigger *trig; 1455 int ret; 1456 1457 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d", 1458 indio_dev->name, 1459 indio_dev->id); 1460 if (!trig) 1461 return -ENOMEM; 1462 1463 trig->dev.parent = &data->client->dev; 1464 trig->ops = &mma8452_trigger_ops; 1465 iio_trigger_set_drvdata(trig, indio_dev); 1466 1467 ret = iio_trigger_register(trig); 1468 if (ret) 1469 return ret; 1470 1471 indio_dev->trig = trig; 1472 1473 return 0; 1474 } 1475 1476 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev) 1477 { 1478 if (indio_dev->trig) 1479 iio_trigger_unregister(indio_dev->trig); 1480 } 1481 1482 static int mma8452_reset(struct i2c_client *client) 1483 { 1484 int i; 1485 int ret; 1486 1487 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2, 1488 MMA8452_CTRL_REG2_RST); 1489 if (ret < 0) 1490 return ret; 1491 1492 for (i = 0; i < 10; i++) { 1493 usleep_range(100, 200); 1494 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2); 1495 if (ret == -EIO) 1496 continue; /* I2C comm reset */ 1497 if (ret < 0) 1498 return ret; 1499 if (!(ret & MMA8452_CTRL_REG2_RST)) 1500 return 0; 1501 } 1502 1503 return -ETIMEDOUT; 1504 } 1505 1506 static const struct of_device_id mma8452_dt_ids[] = { 1507 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] }, 1508 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] }, 1509 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] }, 1510 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] }, 1511 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] }, 1512 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] }, 1513 { } 1514 }; 1515 MODULE_DEVICE_TABLE(of, mma8452_dt_ids); 1516 1517 static int mma8452_probe(struct i2c_client *client, 1518 const struct i2c_device_id *id) 1519 { 1520 struct mma8452_data *data; 1521 struct iio_dev *indio_dev; 1522 int ret; 1523 const struct of_device_id *match; 1524 1525 match = of_match_device(mma8452_dt_ids, &client->dev); 1526 if (!match) { 1527 dev_err(&client->dev, "unknown device model\n"); 1528 return -ENODEV; 1529 } 1530 1531 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 1532 if (!indio_dev) 1533 return -ENOMEM; 1534 1535 data = iio_priv(indio_dev); 1536 data->client = client; 1537 mutex_init(&data->lock); 1538 data->chip_info = match->data; 1539 1540 data->vdd_reg = devm_regulator_get(&client->dev, "vdd"); 1541 if (IS_ERR(data->vdd_reg)) { 1542 if (PTR_ERR(data->vdd_reg) == -EPROBE_DEFER) 1543 return -EPROBE_DEFER; 1544 1545 dev_err(&client->dev, "failed to get VDD regulator!\n"); 1546 return PTR_ERR(data->vdd_reg); 1547 } 1548 1549 data->vddio_reg = devm_regulator_get(&client->dev, "vddio"); 1550 if (IS_ERR(data->vddio_reg)) { 1551 if (PTR_ERR(data->vddio_reg) == -EPROBE_DEFER) 1552 return -EPROBE_DEFER; 1553 1554 dev_err(&client->dev, "failed to get VDDIO regulator!\n"); 1555 return PTR_ERR(data->vddio_reg); 1556 } 1557 1558 ret = regulator_enable(data->vdd_reg); 1559 if (ret) { 1560 dev_err(&client->dev, "failed to enable VDD regulator!\n"); 1561 return ret; 1562 } 1563 1564 ret = regulator_enable(data->vddio_reg); 1565 if (ret) { 1566 dev_err(&client->dev, "failed to enable VDDIO regulator!\n"); 1567 goto disable_regulator_vdd; 1568 } 1569 1570 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I); 1571 if (ret < 0) 1572 goto disable_regulators; 1573 1574 switch (ret) { 1575 case MMA8451_DEVICE_ID: 1576 case MMA8452_DEVICE_ID: 1577 case MMA8453_DEVICE_ID: 1578 case MMA8652_DEVICE_ID: 1579 case MMA8653_DEVICE_ID: 1580 case FXLS8471_DEVICE_ID: 1581 if (ret == data->chip_info->chip_id) 1582 break; 1583 fallthrough; 1584 default: 1585 ret = -ENODEV; 1586 goto disable_regulators; 1587 } 1588 1589 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n", 1590 match->compatible, data->chip_info->chip_id); 1591 1592 i2c_set_clientdata(client, indio_dev); 1593 indio_dev->info = &mma8452_info; 1594 indio_dev->name = id->name; 1595 indio_dev->modes = INDIO_DIRECT_MODE; 1596 indio_dev->channels = data->chip_info->channels; 1597 indio_dev->num_channels = data->chip_info->num_channels; 1598 indio_dev->available_scan_masks = mma8452_scan_masks; 1599 1600 ret = mma8452_reset(client); 1601 if (ret < 0) 1602 goto disable_regulators; 1603 1604 data->data_cfg = MMA8452_DATA_CFG_FS_2G; 1605 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG, 1606 data->data_cfg); 1607 if (ret < 0) 1608 goto disable_regulators; 1609 1610 /* 1611 * By default set transient threshold to max to avoid events if 1612 * enabling without configuring threshold. 1613 */ 1614 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS, 1615 MMA8452_TRANSIENT_THS_MASK); 1616 if (ret < 0) 1617 goto disable_regulators; 1618 1619 if (client->irq) { 1620 int irq2; 1621 1622 irq2 = of_irq_get_byname(client->dev.of_node, "INT2"); 1623 1624 if (irq2 == client->irq) { 1625 dev_dbg(&client->dev, "using interrupt line INT2\n"); 1626 } else { 1627 ret = i2c_smbus_write_byte_data(client, 1628 MMA8452_CTRL_REG5, 1629 data->chip_info->all_events); 1630 if (ret < 0) 1631 goto disable_regulators; 1632 1633 dev_dbg(&client->dev, "using interrupt line INT1\n"); 1634 } 1635 1636 ret = i2c_smbus_write_byte_data(client, 1637 MMA8452_CTRL_REG4, 1638 data->chip_info->enabled_events); 1639 if (ret < 0) 1640 goto disable_regulators; 1641 1642 ret = mma8452_trigger_setup(indio_dev); 1643 if (ret < 0) 1644 goto disable_regulators; 1645 } 1646 1647 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE | 1648 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT); 1649 1650 data->sleep_val = mma8452_calculate_sleep(data); 1651 1652 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1, 1653 data->ctrl_reg1); 1654 if (ret < 0) 1655 goto trigger_cleanup; 1656 1657 ret = iio_triggered_buffer_setup(indio_dev, NULL, 1658 mma8452_trigger_handler, NULL); 1659 if (ret < 0) 1660 goto trigger_cleanup; 1661 1662 if (client->irq) { 1663 ret = devm_request_threaded_irq(&client->dev, 1664 client->irq, 1665 NULL, mma8452_interrupt, 1666 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1667 client->name, indio_dev); 1668 if (ret) 1669 goto buffer_cleanup; 1670 } 1671 1672 ret = pm_runtime_set_active(&client->dev); 1673 if (ret < 0) 1674 goto buffer_cleanup; 1675 1676 pm_runtime_enable(&client->dev); 1677 pm_runtime_set_autosuspend_delay(&client->dev, 1678 MMA8452_AUTO_SUSPEND_DELAY_MS); 1679 pm_runtime_use_autosuspend(&client->dev); 1680 1681 ret = iio_device_register(indio_dev); 1682 if (ret < 0) 1683 goto buffer_cleanup; 1684 1685 ret = mma8452_set_freefall_mode(data, false); 1686 if (ret < 0) 1687 goto unregister_device; 1688 1689 return 0; 1690 1691 unregister_device: 1692 iio_device_unregister(indio_dev); 1693 1694 buffer_cleanup: 1695 iio_triggered_buffer_cleanup(indio_dev); 1696 1697 trigger_cleanup: 1698 mma8452_trigger_cleanup(indio_dev); 1699 1700 disable_regulators: 1701 regulator_disable(data->vddio_reg); 1702 1703 disable_regulator_vdd: 1704 regulator_disable(data->vdd_reg); 1705 1706 return ret; 1707 } 1708 1709 static int mma8452_remove(struct i2c_client *client) 1710 { 1711 struct iio_dev *indio_dev = i2c_get_clientdata(client); 1712 struct mma8452_data *data = iio_priv(indio_dev); 1713 1714 iio_device_unregister(indio_dev); 1715 1716 pm_runtime_disable(&client->dev); 1717 pm_runtime_set_suspended(&client->dev); 1718 pm_runtime_put_noidle(&client->dev); 1719 1720 iio_triggered_buffer_cleanup(indio_dev); 1721 mma8452_trigger_cleanup(indio_dev); 1722 mma8452_standby(iio_priv(indio_dev)); 1723 1724 regulator_disable(data->vddio_reg); 1725 regulator_disable(data->vdd_reg); 1726 1727 return 0; 1728 } 1729 1730 #ifdef CONFIG_PM 1731 static int mma8452_runtime_suspend(struct device *dev) 1732 { 1733 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1734 struct mma8452_data *data = iio_priv(indio_dev); 1735 int ret; 1736 1737 mutex_lock(&data->lock); 1738 ret = mma8452_standby(data); 1739 mutex_unlock(&data->lock); 1740 if (ret < 0) { 1741 dev_err(&data->client->dev, "powering off device failed\n"); 1742 return -EAGAIN; 1743 } 1744 1745 ret = regulator_disable(data->vddio_reg); 1746 if (ret) { 1747 dev_err(dev, "failed to disable VDDIO regulator\n"); 1748 return ret; 1749 } 1750 1751 ret = regulator_disable(data->vdd_reg); 1752 if (ret) { 1753 dev_err(dev, "failed to disable VDD regulator\n"); 1754 return ret; 1755 } 1756 1757 return 0; 1758 } 1759 1760 static int mma8452_runtime_resume(struct device *dev) 1761 { 1762 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1763 struct mma8452_data *data = iio_priv(indio_dev); 1764 int ret, sleep_val; 1765 1766 ret = regulator_enable(data->vdd_reg); 1767 if (ret) { 1768 dev_err(dev, "failed to enable VDD regulator\n"); 1769 return ret; 1770 } 1771 1772 ret = regulator_enable(data->vddio_reg); 1773 if (ret) { 1774 dev_err(dev, "failed to enable VDDIO regulator\n"); 1775 regulator_disable(data->vdd_reg); 1776 return ret; 1777 } 1778 1779 ret = mma8452_active(data); 1780 if (ret < 0) 1781 goto runtime_resume_failed; 1782 1783 ret = mma8452_get_odr_index(data); 1784 sleep_val = 1000 / mma8452_samp_freq[ret][0]; 1785 if (sleep_val < 20) 1786 usleep_range(sleep_val * 1000, 20000); 1787 else 1788 msleep_interruptible(sleep_val); 1789 1790 return 0; 1791 1792 runtime_resume_failed: 1793 regulator_disable(data->vddio_reg); 1794 regulator_disable(data->vdd_reg); 1795 1796 return ret; 1797 } 1798 #endif 1799 1800 static const struct dev_pm_ops mma8452_pm_ops = { 1801 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1802 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend, 1803 mma8452_runtime_resume, NULL) 1804 }; 1805 1806 static const struct i2c_device_id mma8452_id[] = { 1807 { "mma8451", mma8451 }, 1808 { "mma8452", mma8452 }, 1809 { "mma8453", mma8453 }, 1810 { "mma8652", mma8652 }, 1811 { "mma8653", mma8653 }, 1812 { "fxls8471", fxls8471 }, 1813 { } 1814 }; 1815 MODULE_DEVICE_TABLE(i2c, mma8452_id); 1816 1817 static struct i2c_driver mma8452_driver = { 1818 .driver = { 1819 .name = "mma8452", 1820 .of_match_table = of_match_ptr(mma8452_dt_ids), 1821 .pm = &mma8452_pm_ops, 1822 }, 1823 .probe = mma8452_probe, 1824 .remove = mma8452_remove, 1825 .id_table = mma8452_id, 1826 }; 1827 module_i2c_driver(mma8452_driver); 1828 1829 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>"); 1830 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver"); 1831 MODULE_LICENSE("GPL"); 1832