1 /* 2 * mma8452.c - Support for Freescale MMA8452Q 3-axis 12-bit accelerometer 3 * 4 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net> 5 * 6 * This file is subject to the terms and conditions of version 2 of 7 * the GNU General Public License. See the file COPYING in the main 8 * directory of this archive for more details. 9 * 10 * 7-bit I2C slave address 0x1c/0x1d (pin selectable) 11 * 12 * TODO: orientation / freefall events, autosleep 13 */ 14 15 #include <linux/module.h> 16 #include <linux/i2c.h> 17 #include <linux/iio/iio.h> 18 #include <linux/iio/sysfs.h> 19 #include <linux/iio/buffer.h> 20 #include <linux/iio/trigger.h> 21 #include <linux/iio/trigger_consumer.h> 22 #include <linux/iio/triggered_buffer.h> 23 #include <linux/iio/events.h> 24 #include <linux/delay.h> 25 26 #define MMA8452_STATUS 0x00 27 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0)) 28 #define MMA8452_OUT_X 0x01 /* MSB first, 12-bit */ 29 #define MMA8452_OUT_Y 0x03 30 #define MMA8452_OUT_Z 0x05 31 #define MMA8452_INT_SRC 0x0c 32 #define MMA8452_WHO_AM_I 0x0d 33 #define MMA8452_DATA_CFG 0x0e 34 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0) 35 #define MMA8452_DATA_CFG_FS_2G 0 36 #define MMA8452_DATA_CFG_FS_4G 1 37 #define MMA8452_DATA_CFG_FS_8G 2 38 #define MMA8452_DATA_CFG_HPF_MASK BIT(4) 39 #define MMA8452_HP_FILTER_CUTOFF 0x0f 40 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0) 41 #define MMA8452_TRANSIENT_CFG 0x1d 42 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0) 43 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1) 44 #define MMA8452_TRANSIENT_CFG_ELE BIT(4) 45 #define MMA8452_TRANSIENT_SRC 0x1e 46 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1) 47 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3) 48 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5) 49 #define MMA8452_TRANSIENT_THS 0x1f 50 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0) 51 #define MMA8452_TRANSIENT_COUNT 0x20 52 #define MMA8452_CTRL_REG1 0x2a 53 #define MMA8452_CTRL_ACTIVE BIT(0) 54 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3) 55 #define MMA8452_CTRL_DR_SHIFT 3 56 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */ 57 #define MMA8452_CTRL_REG2 0x2b 58 #define MMA8452_CTRL_REG2_RST BIT(6) 59 #define MMA8452_CTRL_REG4 0x2d 60 #define MMA8452_CTRL_REG5 0x2e 61 #define MMA8452_OFF_X 0x2f 62 #define MMA8452_OFF_Y 0x30 63 #define MMA8452_OFF_Z 0x31 64 65 #define MMA8452_MAX_REG 0x31 66 67 #define MMA8452_INT_DRDY BIT(0) 68 #define MMA8452_INT_TRANS BIT(5) 69 70 #define MMA8452_DEVICE_ID 0x2a 71 72 struct mma8452_data { 73 struct i2c_client *client; 74 struct mutex lock; 75 u8 ctrl_reg1; 76 u8 data_cfg; 77 }; 78 79 static int mma8452_drdy(struct mma8452_data *data) 80 { 81 int tries = 150; 82 83 while (tries-- > 0) { 84 int ret = i2c_smbus_read_byte_data(data->client, 85 MMA8452_STATUS); 86 if (ret < 0) 87 return ret; 88 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY) 89 return 0; 90 91 msleep(20); 92 } 93 94 dev_err(&data->client->dev, "data not ready\n"); 95 96 return -EIO; 97 } 98 99 static int mma8452_read(struct mma8452_data *data, __be16 buf[3]) 100 { 101 int ret = mma8452_drdy(data); 102 103 if (ret < 0) 104 return ret; 105 106 return i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X, 107 3 * sizeof(__be16), (u8 *)buf); 108 } 109 110 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2], 111 int n) 112 { 113 size_t len = 0; 114 115 while (n-- > 0) 116 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ", 117 vals[n][0], vals[n][1]); 118 119 /* replace trailing space by newline */ 120 buf[len - 1] = '\n'; 121 122 return len; 123 } 124 125 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n, 126 int val, int val2) 127 { 128 while (n-- > 0) 129 if (val == vals[n][0] && val2 == vals[n][1]) 130 return n; 131 132 return -EINVAL; 133 } 134 135 static int mma8452_get_odr_index(struct mma8452_data *data) 136 { 137 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >> 138 MMA8452_CTRL_DR_SHIFT; 139 } 140 141 static const int mma8452_samp_freq[8][2] = { 142 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000}, 143 {6, 250000}, {1, 560000} 144 }; 145 146 /* 147 * Hardware has fullscale of -2G, -4G, -8G corresponding to raw value -2048 148 * The userspace interface uses m/s^2 and we declare micro units 149 * So scale factor is given by: 150 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g = 9.80665 151 */ 152 static const int mma8452_scales[3][2] = { 153 {0, 9577}, {0, 19154}, {0, 38307} 154 }; 155 156 /* Datasheet table 35 (step time vs sample frequency) */ 157 static const int mma8452_transient_time_step_us[8] = { 158 1250, 159 2500, 160 5000, 161 10000, 162 20000, 163 20000, 164 20000, 165 20000 166 }; 167 168 /* Datasheet table 18 (normal mode) */ 169 static const int mma8452_hp_filter_cutoff[8][4][2] = { 170 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */ 171 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */ 172 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */ 173 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */ 174 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */ 175 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */ 176 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */ 177 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */ 178 }; 179 180 static ssize_t mma8452_show_samp_freq_avail(struct device *dev, 181 struct device_attribute *attr, 182 char *buf) 183 { 184 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq, 185 ARRAY_SIZE(mma8452_samp_freq)); 186 } 187 188 static ssize_t mma8452_show_scale_avail(struct device *dev, 189 struct device_attribute *attr, 190 char *buf) 191 { 192 return mma8452_show_int_plus_micros(buf, mma8452_scales, 193 ARRAY_SIZE(mma8452_scales)); 194 } 195 196 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev, 197 struct device_attribute *attr, 198 char *buf) 199 { 200 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 201 struct mma8452_data *data = iio_priv(indio_dev); 202 int i = mma8452_get_odr_index(data); 203 204 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[i], 205 ARRAY_SIZE(mma8452_hp_filter_cutoff[0])); 206 } 207 208 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail); 209 static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO, 210 mma8452_show_scale_avail, NULL, 0); 211 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available, 212 S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0); 213 214 static int mma8452_get_samp_freq_index(struct mma8452_data *data, 215 int val, int val2) 216 { 217 return mma8452_get_int_plus_micros_index(mma8452_samp_freq, 218 ARRAY_SIZE(mma8452_samp_freq), 219 val, val2); 220 } 221 222 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2) 223 { 224 return mma8452_get_int_plus_micros_index(mma8452_scales, 225 ARRAY_SIZE(mma8452_scales), 226 val, val2); 227 } 228 229 static int mma8452_get_hp_filter_index(struct mma8452_data *data, 230 int val, int val2) 231 { 232 int i = mma8452_get_odr_index(data); 233 234 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[i], 235 ARRAY_SIZE(mma8452_hp_filter_cutoff[0]), val, val2); 236 } 237 238 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz) 239 { 240 int i, ret; 241 242 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF); 243 if (ret < 0) 244 return ret; 245 246 i = mma8452_get_odr_index(data); 247 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 248 *hz = mma8452_hp_filter_cutoff[i][ret][0]; 249 *uHz = mma8452_hp_filter_cutoff[i][ret][1]; 250 251 return 0; 252 } 253 254 static int mma8452_read_raw(struct iio_dev *indio_dev, 255 struct iio_chan_spec const *chan, 256 int *val, int *val2, long mask) 257 { 258 struct mma8452_data *data = iio_priv(indio_dev); 259 __be16 buffer[3]; 260 int i, ret; 261 262 switch (mask) { 263 case IIO_CHAN_INFO_RAW: 264 if (iio_buffer_enabled(indio_dev)) 265 return -EBUSY; 266 267 mutex_lock(&data->lock); 268 ret = mma8452_read(data, buffer); 269 mutex_unlock(&data->lock); 270 if (ret < 0) 271 return ret; 272 273 *val = sign_extend32(be16_to_cpu(buffer[chan->scan_index]) >> 4, 274 11); 275 276 return IIO_VAL_INT; 277 case IIO_CHAN_INFO_SCALE: 278 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK; 279 *val = mma8452_scales[i][0]; 280 *val2 = mma8452_scales[i][1]; 281 282 return IIO_VAL_INT_PLUS_MICRO; 283 case IIO_CHAN_INFO_SAMP_FREQ: 284 i = mma8452_get_odr_index(data); 285 *val = mma8452_samp_freq[i][0]; 286 *val2 = mma8452_samp_freq[i][1]; 287 288 return IIO_VAL_INT_PLUS_MICRO; 289 case IIO_CHAN_INFO_CALIBBIAS: 290 ret = i2c_smbus_read_byte_data(data->client, 291 MMA8452_OFF_X + chan->scan_index); 292 if (ret < 0) 293 return ret; 294 295 *val = sign_extend32(ret, 7); 296 297 return IIO_VAL_INT; 298 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 299 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) { 300 ret = mma8452_read_hp_filter(data, val, val2); 301 if (ret < 0) 302 return ret; 303 } else { 304 *val = 0; 305 *val2 = 0; 306 } 307 308 return IIO_VAL_INT_PLUS_MICRO; 309 } 310 311 return -EINVAL; 312 } 313 314 static int mma8452_standby(struct mma8452_data *data) 315 { 316 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 317 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE); 318 } 319 320 static int mma8452_active(struct mma8452_data *data) 321 { 322 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 323 data->ctrl_reg1); 324 } 325 326 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val) 327 { 328 int ret; 329 330 mutex_lock(&data->lock); 331 332 /* config can only be changed when in standby */ 333 ret = mma8452_standby(data); 334 if (ret < 0) 335 goto fail; 336 337 ret = i2c_smbus_write_byte_data(data->client, reg, val); 338 if (ret < 0) 339 goto fail; 340 341 ret = mma8452_active(data); 342 if (ret < 0) 343 goto fail; 344 345 ret = 0; 346 fail: 347 mutex_unlock(&data->lock); 348 349 return ret; 350 } 351 352 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data, 353 int val, int val2) 354 { 355 int i, reg; 356 357 i = mma8452_get_hp_filter_index(data, val, val2); 358 if (i < 0) 359 return i; 360 361 reg = i2c_smbus_read_byte_data(data->client, 362 MMA8452_HP_FILTER_CUTOFF); 363 if (reg < 0) 364 return reg; 365 366 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 367 reg |= i; 368 369 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg); 370 } 371 372 static int mma8452_write_raw(struct iio_dev *indio_dev, 373 struct iio_chan_spec const *chan, 374 int val, int val2, long mask) 375 { 376 struct mma8452_data *data = iio_priv(indio_dev); 377 int i, ret; 378 379 if (iio_buffer_enabled(indio_dev)) 380 return -EBUSY; 381 382 switch (mask) { 383 case IIO_CHAN_INFO_SAMP_FREQ: 384 i = mma8452_get_samp_freq_index(data, val, val2); 385 if (i < 0) 386 return i; 387 388 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK; 389 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT; 390 391 return mma8452_change_config(data, MMA8452_CTRL_REG1, 392 data->ctrl_reg1); 393 case IIO_CHAN_INFO_SCALE: 394 i = mma8452_get_scale_index(data, val, val2); 395 if (i < 0) 396 return i; 397 398 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK; 399 data->data_cfg |= i; 400 401 return mma8452_change_config(data, MMA8452_DATA_CFG, 402 data->data_cfg); 403 case IIO_CHAN_INFO_CALIBBIAS: 404 if (val < -128 || val > 127) 405 return -EINVAL; 406 407 return mma8452_change_config(data, 408 MMA8452_OFF_X + chan->scan_index, 409 val); 410 411 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 412 if (val == 0 && val2 == 0) { 413 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK; 414 } else { 415 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK; 416 ret = mma8452_set_hp_filter_frequency(data, val, val2); 417 if (ret < 0) 418 return ret; 419 } 420 421 return mma8452_change_config(data, MMA8452_DATA_CFG, 422 data->data_cfg); 423 424 default: 425 return -EINVAL; 426 } 427 } 428 429 static int mma8452_read_thresh(struct iio_dev *indio_dev, 430 const struct iio_chan_spec *chan, 431 enum iio_event_type type, 432 enum iio_event_direction dir, 433 enum iio_event_info info, 434 int *val, int *val2) 435 { 436 struct mma8452_data *data = iio_priv(indio_dev); 437 int ret, us; 438 439 switch (info) { 440 case IIO_EV_INFO_VALUE: 441 ret = i2c_smbus_read_byte_data(data->client, 442 MMA8452_TRANSIENT_THS); 443 if (ret < 0) 444 return ret; 445 446 *val = ret & MMA8452_TRANSIENT_THS_MASK; 447 448 return IIO_VAL_INT; 449 450 case IIO_EV_INFO_PERIOD: 451 ret = i2c_smbus_read_byte_data(data->client, 452 MMA8452_TRANSIENT_COUNT); 453 if (ret < 0) 454 return ret; 455 456 us = ret * mma8452_transient_time_step_us[ 457 mma8452_get_odr_index(data)]; 458 *val = us / USEC_PER_SEC; 459 *val2 = us % USEC_PER_SEC; 460 461 return IIO_VAL_INT_PLUS_MICRO; 462 463 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 464 ret = i2c_smbus_read_byte_data(data->client, 465 MMA8452_TRANSIENT_CFG); 466 if (ret < 0) 467 return ret; 468 469 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) { 470 *val = 0; 471 *val2 = 0; 472 } else { 473 ret = mma8452_read_hp_filter(data, val, val2); 474 if (ret < 0) 475 return ret; 476 } 477 478 return IIO_VAL_INT_PLUS_MICRO; 479 480 default: 481 return -EINVAL; 482 } 483 } 484 485 static int mma8452_write_thresh(struct iio_dev *indio_dev, 486 const struct iio_chan_spec *chan, 487 enum iio_event_type type, 488 enum iio_event_direction dir, 489 enum iio_event_info info, 490 int val, int val2) 491 { 492 struct mma8452_data *data = iio_priv(indio_dev); 493 int ret, reg, steps; 494 495 switch (info) { 496 case IIO_EV_INFO_VALUE: 497 if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK) 498 return -EINVAL; 499 500 return mma8452_change_config(data, MMA8452_TRANSIENT_THS, val); 501 502 case IIO_EV_INFO_PERIOD: 503 steps = (val * USEC_PER_SEC + val2) / 504 mma8452_transient_time_step_us[ 505 mma8452_get_odr_index(data)]; 506 507 if (steps < 0 || steps > 0xff) 508 return -EINVAL; 509 510 return mma8452_change_config(data, MMA8452_TRANSIENT_COUNT, 511 steps); 512 513 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 514 reg = i2c_smbus_read_byte_data(data->client, 515 MMA8452_TRANSIENT_CFG); 516 if (reg < 0) 517 return reg; 518 519 if (val == 0 && val2 == 0) { 520 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP; 521 } else { 522 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP; 523 ret = mma8452_set_hp_filter_frequency(data, val, val2); 524 if (ret < 0) 525 return ret; 526 } 527 528 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg); 529 530 default: 531 return -EINVAL; 532 } 533 } 534 535 static int mma8452_read_event_config(struct iio_dev *indio_dev, 536 const struct iio_chan_spec *chan, 537 enum iio_event_type type, 538 enum iio_event_direction dir) 539 { 540 struct mma8452_data *data = iio_priv(indio_dev); 541 int ret; 542 543 ret = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_CFG); 544 if (ret < 0) 545 return ret; 546 547 return ret & MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index) ? 1 : 0; 548 } 549 550 static int mma8452_write_event_config(struct iio_dev *indio_dev, 551 const struct iio_chan_spec *chan, 552 enum iio_event_type type, 553 enum iio_event_direction dir, 554 int state) 555 { 556 struct mma8452_data *data = iio_priv(indio_dev); 557 int val; 558 559 val = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_CFG); 560 if (val < 0) 561 return val; 562 563 if (state) 564 val |= MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index); 565 else 566 val &= ~MMA8452_TRANSIENT_CFG_CHAN(chan->scan_index); 567 568 val |= MMA8452_TRANSIENT_CFG_ELE; 569 570 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, val); 571 } 572 573 static void mma8452_transient_interrupt(struct iio_dev *indio_dev) 574 { 575 struct mma8452_data *data = iio_priv(indio_dev); 576 s64 ts = iio_get_time_ns(); 577 int src; 578 579 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC); 580 if (src < 0) 581 return; 582 583 if (src & MMA8452_TRANSIENT_SRC_XTRANSE) 584 iio_push_event(indio_dev, 585 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 586 IIO_EV_TYPE_MAG, 587 IIO_EV_DIR_RISING), 588 ts); 589 590 if (src & MMA8452_TRANSIENT_SRC_YTRANSE) 591 iio_push_event(indio_dev, 592 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y, 593 IIO_EV_TYPE_MAG, 594 IIO_EV_DIR_RISING), 595 ts); 596 597 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE) 598 iio_push_event(indio_dev, 599 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z, 600 IIO_EV_TYPE_MAG, 601 IIO_EV_DIR_RISING), 602 ts); 603 } 604 605 static irqreturn_t mma8452_interrupt(int irq, void *p) 606 { 607 struct iio_dev *indio_dev = p; 608 struct mma8452_data *data = iio_priv(indio_dev); 609 int ret = IRQ_NONE; 610 int src; 611 612 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC); 613 if (src < 0) 614 return IRQ_NONE; 615 616 if (src & MMA8452_INT_DRDY) { 617 iio_trigger_poll_chained(indio_dev->trig); 618 ret = IRQ_HANDLED; 619 } 620 621 if (src & MMA8452_INT_TRANS) { 622 mma8452_transient_interrupt(indio_dev); 623 ret = IRQ_HANDLED; 624 } 625 626 return ret; 627 } 628 629 static irqreturn_t mma8452_trigger_handler(int irq, void *p) 630 { 631 struct iio_poll_func *pf = p; 632 struct iio_dev *indio_dev = pf->indio_dev; 633 struct mma8452_data *data = iio_priv(indio_dev); 634 u8 buffer[16]; /* 3 16-bit channels + padding + ts */ 635 int ret; 636 637 ret = mma8452_read(data, (__be16 *)buffer); 638 if (ret < 0) 639 goto done; 640 641 iio_push_to_buffers_with_timestamp(indio_dev, buffer, 642 iio_get_time_ns()); 643 644 done: 645 iio_trigger_notify_done(indio_dev->trig); 646 647 return IRQ_HANDLED; 648 } 649 650 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev, 651 unsigned reg, unsigned writeval, 652 unsigned *readval) 653 { 654 int ret; 655 struct mma8452_data *data = iio_priv(indio_dev); 656 657 if (reg > MMA8452_MAX_REG) 658 return -EINVAL; 659 660 if (!readval) 661 return mma8452_change_config(data, reg, writeval); 662 663 ret = i2c_smbus_read_byte_data(data->client, reg); 664 if (ret < 0) 665 return ret; 666 667 *readval = ret; 668 669 return 0; 670 } 671 672 static const struct iio_event_spec mma8452_transient_event[] = { 673 { 674 .type = IIO_EV_TYPE_MAG, 675 .dir = IIO_EV_DIR_RISING, 676 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 677 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 678 BIT(IIO_EV_INFO_PERIOD) | 679 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 680 }, 681 }; 682 683 /* 684 * Threshold is configured in fixed 8G/127 steps regardless of 685 * currently selected scale for measurement. 686 */ 687 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742"); 688 689 static struct attribute *mma8452_event_attributes[] = { 690 &iio_const_attr_accel_transient_scale.dev_attr.attr, 691 NULL, 692 }; 693 694 static struct attribute_group mma8452_event_attribute_group = { 695 .attrs = mma8452_event_attributes, 696 .name = "events", 697 }; 698 699 #define MMA8452_CHANNEL(axis, idx) { \ 700 .type = IIO_ACCEL, \ 701 .modified = 1, \ 702 .channel2 = IIO_MOD_##axis, \ 703 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 704 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 705 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 706 BIT(IIO_CHAN_INFO_SCALE) | \ 707 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY), \ 708 .scan_index = idx, \ 709 .scan_type = { \ 710 .sign = 's', \ 711 .realbits = 12, \ 712 .storagebits = 16, \ 713 .shift = 4, \ 714 .endianness = IIO_BE, \ 715 }, \ 716 .event_spec = mma8452_transient_event, \ 717 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \ 718 } 719 720 static const struct iio_chan_spec mma8452_channels[] = { 721 MMA8452_CHANNEL(X, 0), 722 MMA8452_CHANNEL(Y, 1), 723 MMA8452_CHANNEL(Z, 2), 724 IIO_CHAN_SOFT_TIMESTAMP(3), 725 }; 726 727 static struct attribute *mma8452_attributes[] = { 728 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 729 &iio_dev_attr_in_accel_scale_available.dev_attr.attr, 730 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr, 731 NULL 732 }; 733 734 static const struct attribute_group mma8452_group = { 735 .attrs = mma8452_attributes, 736 }; 737 738 static const struct iio_info mma8452_info = { 739 .attrs = &mma8452_group, 740 .read_raw = &mma8452_read_raw, 741 .write_raw = &mma8452_write_raw, 742 .event_attrs = &mma8452_event_attribute_group, 743 .read_event_value = &mma8452_read_thresh, 744 .write_event_value = &mma8452_write_thresh, 745 .read_event_config = &mma8452_read_event_config, 746 .write_event_config = &mma8452_write_event_config, 747 .debugfs_reg_access = &mma8452_reg_access_dbg, 748 .driver_module = THIS_MODULE, 749 }; 750 751 static const unsigned long mma8452_scan_masks[] = {0x7, 0}; 752 753 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig, 754 bool state) 755 { 756 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 757 struct mma8452_data *data = iio_priv(indio_dev); 758 int reg; 759 760 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4); 761 if (reg < 0) 762 return reg; 763 764 if (state) 765 reg |= MMA8452_INT_DRDY; 766 else 767 reg &= ~MMA8452_INT_DRDY; 768 769 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg); 770 } 771 772 static int mma8452_validate_device(struct iio_trigger *trig, 773 struct iio_dev *indio_dev) 774 { 775 struct iio_dev *indio = iio_trigger_get_drvdata(trig); 776 777 if (indio != indio_dev) 778 return -EINVAL; 779 780 return 0; 781 } 782 783 static const struct iio_trigger_ops mma8452_trigger_ops = { 784 .set_trigger_state = mma8452_data_rdy_trigger_set_state, 785 .validate_device = mma8452_validate_device, 786 .owner = THIS_MODULE, 787 }; 788 789 static int mma8452_trigger_setup(struct iio_dev *indio_dev) 790 { 791 struct mma8452_data *data = iio_priv(indio_dev); 792 struct iio_trigger *trig; 793 int ret; 794 795 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d", 796 indio_dev->name, 797 indio_dev->id); 798 if (!trig) 799 return -ENOMEM; 800 801 trig->dev.parent = &data->client->dev; 802 trig->ops = &mma8452_trigger_ops; 803 iio_trigger_set_drvdata(trig, indio_dev); 804 805 ret = iio_trigger_register(trig); 806 if (ret) 807 return ret; 808 809 indio_dev->trig = trig; 810 811 return 0; 812 } 813 814 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev) 815 { 816 if (indio_dev->trig) 817 iio_trigger_unregister(indio_dev->trig); 818 } 819 820 static int mma8452_reset(struct i2c_client *client) 821 { 822 int i; 823 int ret; 824 825 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2, 826 MMA8452_CTRL_REG2_RST); 827 if (ret < 0) 828 return ret; 829 830 for (i = 0; i < 10; i++) { 831 usleep_range(100, 200); 832 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2); 833 if (ret == -EIO) 834 continue; /* I2C comm reset */ 835 if (ret < 0) 836 return ret; 837 if (!(ret & MMA8452_CTRL_REG2_RST)) 838 return 0; 839 } 840 841 return -ETIMEDOUT; 842 } 843 844 static int mma8452_probe(struct i2c_client *client, 845 const struct i2c_device_id *id) 846 { 847 struct mma8452_data *data; 848 struct iio_dev *indio_dev; 849 int ret; 850 851 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I); 852 if (ret < 0) 853 return ret; 854 if (ret != MMA8452_DEVICE_ID) 855 return -ENODEV; 856 857 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 858 if (!indio_dev) 859 return -ENOMEM; 860 861 data = iio_priv(indio_dev); 862 data->client = client; 863 mutex_init(&data->lock); 864 865 i2c_set_clientdata(client, indio_dev); 866 indio_dev->info = &mma8452_info; 867 indio_dev->name = id->name; 868 indio_dev->dev.parent = &client->dev; 869 indio_dev->modes = INDIO_DIRECT_MODE; 870 indio_dev->channels = mma8452_channels; 871 indio_dev->num_channels = ARRAY_SIZE(mma8452_channels); 872 indio_dev->available_scan_masks = mma8452_scan_masks; 873 874 ret = mma8452_reset(client); 875 if (ret < 0) 876 return ret; 877 878 data->data_cfg = MMA8452_DATA_CFG_FS_2G; 879 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG, 880 data->data_cfg); 881 if (ret < 0) 882 return ret; 883 884 /* 885 * By default set transient threshold to max to avoid events if 886 * enabling without configuring threshold. 887 */ 888 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS, 889 MMA8452_TRANSIENT_THS_MASK); 890 if (ret < 0) 891 return ret; 892 893 if (client->irq) { 894 /* 895 * Although we enable the transient interrupt source once and 896 * for all here the transient event detection itself is not 897 * enabled until userspace asks for it by 898 * mma8452_write_event_config() 899 */ 900 int supported_interrupts = MMA8452_INT_DRDY | MMA8452_INT_TRANS; 901 int enabled_interrupts = MMA8452_INT_TRANS; 902 903 /* Assume wired to INT1 pin */ 904 ret = i2c_smbus_write_byte_data(client, 905 MMA8452_CTRL_REG5, 906 supported_interrupts); 907 if (ret < 0) 908 return ret; 909 910 ret = i2c_smbus_write_byte_data(client, 911 MMA8452_CTRL_REG4, 912 enabled_interrupts); 913 if (ret < 0) 914 return ret; 915 916 ret = mma8452_trigger_setup(indio_dev); 917 if (ret < 0) 918 return ret; 919 } 920 921 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE | 922 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT); 923 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1, 924 data->ctrl_reg1); 925 if (ret < 0) 926 goto trigger_cleanup; 927 928 ret = iio_triggered_buffer_setup(indio_dev, NULL, 929 mma8452_trigger_handler, NULL); 930 if (ret < 0) 931 goto trigger_cleanup; 932 933 if (client->irq) { 934 ret = devm_request_threaded_irq(&client->dev, 935 client->irq, 936 NULL, mma8452_interrupt, 937 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 938 client->name, indio_dev); 939 if (ret) 940 goto buffer_cleanup; 941 } 942 943 ret = iio_device_register(indio_dev); 944 if (ret < 0) 945 goto buffer_cleanup; 946 947 return 0; 948 949 buffer_cleanup: 950 iio_triggered_buffer_cleanup(indio_dev); 951 952 trigger_cleanup: 953 mma8452_trigger_cleanup(indio_dev); 954 955 return ret; 956 } 957 958 static int mma8452_remove(struct i2c_client *client) 959 { 960 struct iio_dev *indio_dev = i2c_get_clientdata(client); 961 962 iio_device_unregister(indio_dev); 963 iio_triggered_buffer_cleanup(indio_dev); 964 mma8452_trigger_cleanup(indio_dev); 965 mma8452_standby(iio_priv(indio_dev)); 966 967 return 0; 968 } 969 970 #ifdef CONFIG_PM_SLEEP 971 static int mma8452_suspend(struct device *dev) 972 { 973 return mma8452_standby(iio_priv(i2c_get_clientdata( 974 to_i2c_client(dev)))); 975 } 976 977 static int mma8452_resume(struct device *dev) 978 { 979 return mma8452_active(iio_priv(i2c_get_clientdata( 980 to_i2c_client(dev)))); 981 } 982 983 static SIMPLE_DEV_PM_OPS(mma8452_pm_ops, mma8452_suspend, mma8452_resume); 984 #define MMA8452_PM_OPS (&mma8452_pm_ops) 985 #else 986 #define MMA8452_PM_OPS NULL 987 #endif 988 989 static const struct i2c_device_id mma8452_id[] = { 990 { "mma8452", 0 }, 991 { } 992 }; 993 MODULE_DEVICE_TABLE(i2c, mma8452_id); 994 995 static const struct of_device_id mma8452_dt_ids[] = { 996 { .compatible = "fsl,mma8452" }, 997 { } 998 }; 999 MODULE_DEVICE_TABLE(of, mma8452_dt_ids); 1000 1001 static struct i2c_driver mma8452_driver = { 1002 .driver = { 1003 .name = "mma8452", 1004 .of_match_table = of_match_ptr(mma8452_dt_ids), 1005 .pm = MMA8452_PM_OPS, 1006 }, 1007 .probe = mma8452_probe, 1008 .remove = mma8452_remove, 1009 .id_table = mma8452_id, 1010 }; 1011 module_i2c_driver(mma8452_driver); 1012 1013 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>"); 1014 MODULE_DESCRIPTION("Freescale MMA8452 accelerometer driver"); 1015 MODULE_LICENSE("GPL"); 1016