1 /* 2 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers: 3 * 4 * device name digital output 7-bit I2C slave address (pin selectable) 5 * --------------------------------------------------------------------- 6 * MMA8451Q 14 bit 0x1c / 0x1d 7 * MMA8452Q 12 bit 0x1c / 0x1d 8 * MMA8453Q 10 bit 0x1c / 0x1d 9 * MMA8652FC 12 bit 0x1d 10 * MMA8653FC 10 bit 0x1d 11 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f 12 * 13 * Copyright 2015 Martin Kepplinger <martink@posteo.de> 14 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net> 15 * 16 * This file is subject to the terms and conditions of version 2 of 17 * the GNU General Public License. See the file COPYING in the main 18 * directory of this archive for more details. 19 * 20 * TODO: orientation events 21 */ 22 23 #include <linux/module.h> 24 #include <linux/i2c.h> 25 #include <linux/iio/iio.h> 26 #include <linux/iio/sysfs.h> 27 #include <linux/iio/buffer.h> 28 #include <linux/iio/trigger.h> 29 #include <linux/iio/trigger_consumer.h> 30 #include <linux/iio/triggered_buffer.h> 31 #include <linux/iio/events.h> 32 #include <linux/delay.h> 33 #include <linux/of_device.h> 34 #include <linux/of_irq.h> 35 #include <linux/pm_runtime.h> 36 37 #define MMA8452_STATUS 0x00 38 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0)) 39 #define MMA8452_OUT_X 0x01 /* MSB first */ 40 #define MMA8452_OUT_Y 0x03 41 #define MMA8452_OUT_Z 0x05 42 #define MMA8452_INT_SRC 0x0c 43 #define MMA8452_WHO_AM_I 0x0d 44 #define MMA8452_DATA_CFG 0x0e 45 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0) 46 #define MMA8452_DATA_CFG_FS_2G 0 47 #define MMA8452_DATA_CFG_FS_4G 1 48 #define MMA8452_DATA_CFG_FS_8G 2 49 #define MMA8452_DATA_CFG_HPF_MASK BIT(4) 50 #define MMA8452_HP_FILTER_CUTOFF 0x0f 51 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0) 52 #define MMA8452_FF_MT_CFG 0x15 53 #define MMA8452_FF_MT_CFG_OAE BIT(6) 54 #define MMA8452_FF_MT_CFG_ELE BIT(7) 55 #define MMA8452_FF_MT_SRC 0x16 56 #define MMA8452_FF_MT_SRC_XHE BIT(1) 57 #define MMA8452_FF_MT_SRC_YHE BIT(3) 58 #define MMA8452_FF_MT_SRC_ZHE BIT(5) 59 #define MMA8452_FF_MT_THS 0x17 60 #define MMA8452_FF_MT_THS_MASK 0x7f 61 #define MMA8452_FF_MT_COUNT 0x18 62 #define MMA8452_FF_MT_CHAN_SHIFT 3 63 #define MMA8452_TRANSIENT_CFG 0x1d 64 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1) 65 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0) 66 #define MMA8452_TRANSIENT_CFG_ELE BIT(4) 67 #define MMA8452_TRANSIENT_SRC 0x1e 68 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1) 69 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3) 70 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5) 71 #define MMA8452_TRANSIENT_THS 0x1f 72 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0) 73 #define MMA8452_TRANSIENT_COUNT 0x20 74 #define MMA8452_TRANSIENT_CHAN_SHIFT 1 75 #define MMA8452_CTRL_REG1 0x2a 76 #define MMA8452_CTRL_ACTIVE BIT(0) 77 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3) 78 #define MMA8452_CTRL_DR_SHIFT 3 79 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */ 80 #define MMA8452_CTRL_REG2 0x2b 81 #define MMA8452_CTRL_REG2_RST BIT(6) 82 #define MMA8452_CTRL_REG2_MODS_SHIFT 3 83 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b 84 #define MMA8452_CTRL_REG4 0x2d 85 #define MMA8452_CTRL_REG5 0x2e 86 #define MMA8452_OFF_X 0x2f 87 #define MMA8452_OFF_Y 0x30 88 #define MMA8452_OFF_Z 0x31 89 90 #define MMA8452_MAX_REG 0x31 91 92 #define MMA8452_INT_DRDY BIT(0) 93 #define MMA8452_INT_FF_MT BIT(2) 94 #define MMA8452_INT_TRANS BIT(5) 95 96 #define MMA8451_DEVICE_ID 0x1a 97 #define MMA8452_DEVICE_ID 0x2a 98 #define MMA8453_DEVICE_ID 0x3a 99 #define MMA8652_DEVICE_ID 0x4a 100 #define MMA8653_DEVICE_ID 0x5a 101 #define FXLS8471_DEVICE_ID 0x6a 102 103 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000 104 105 struct mma8452_data { 106 struct i2c_client *client; 107 struct mutex lock; 108 u8 ctrl_reg1; 109 u8 data_cfg; 110 const struct mma_chip_info *chip_info; 111 }; 112 113 /** 114 * struct mma8452_event_regs - chip specific data related to events 115 * @ev_cfg: event config register address 116 * @ev_cfg_ele: latch bit in event config register 117 * @ev_cfg_chan_shift: number of the bit to enable events in X 118 * direction; in event config register 119 * @ev_src: event source register address 120 * @ev_ths: event threshold register address 121 * @ev_ths_mask: mask for the threshold value 122 * @ev_count: event count (period) register address 123 * 124 * Since not all chips supported by the driver support comparing high pass 125 * filtered data for events (interrupts), different interrupt sources are 126 * used for different chips and the relevant registers are included here. 127 */ 128 struct mma8452_event_regs { 129 u8 ev_cfg; 130 u8 ev_cfg_ele; 131 u8 ev_cfg_chan_shift; 132 u8 ev_src; 133 u8 ev_ths; 134 u8 ev_ths_mask; 135 u8 ev_count; 136 }; 137 138 static const struct mma8452_event_regs ev_regs_accel_falling = { 139 .ev_cfg = MMA8452_FF_MT_CFG, 140 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE, 141 .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT, 142 .ev_src = MMA8452_FF_MT_SRC, 143 .ev_ths = MMA8452_FF_MT_THS, 144 .ev_ths_mask = MMA8452_FF_MT_THS_MASK, 145 .ev_count = MMA8452_FF_MT_COUNT 146 }; 147 148 static const struct mma8452_event_regs ev_regs_accel_rising = { 149 .ev_cfg = MMA8452_TRANSIENT_CFG, 150 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE, 151 .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT, 152 .ev_src = MMA8452_TRANSIENT_SRC, 153 .ev_ths = MMA8452_TRANSIENT_THS, 154 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK, 155 .ev_count = MMA8452_TRANSIENT_COUNT, 156 }; 157 158 /** 159 * struct mma_chip_info - chip specific data 160 * @chip_id: WHO_AM_I register's value 161 * @channels: struct iio_chan_spec matching the device's 162 * capabilities 163 * @num_channels: number of channels 164 * @mma_scales: scale factors for converting register values 165 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers 166 * per mode: m/s^2 and micro m/s^2 167 * @all_events: all events supported by this chip 168 * @enabled_events: event flags enabled and handled by this driver 169 */ 170 struct mma_chip_info { 171 u8 chip_id; 172 const struct iio_chan_spec *channels; 173 int num_channels; 174 const int mma_scales[3][2]; 175 int all_events; 176 int enabled_events; 177 }; 178 179 enum { 180 idx_x, 181 idx_y, 182 idx_z, 183 idx_ts, 184 }; 185 186 static int mma8452_drdy(struct mma8452_data *data) 187 { 188 int tries = 150; 189 190 while (tries-- > 0) { 191 int ret = i2c_smbus_read_byte_data(data->client, 192 MMA8452_STATUS); 193 if (ret < 0) 194 return ret; 195 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY) 196 return 0; 197 198 msleep(20); 199 } 200 201 dev_err(&data->client->dev, "data not ready\n"); 202 203 return -EIO; 204 } 205 206 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on) 207 { 208 #ifdef CONFIG_PM 209 int ret; 210 211 if (on) { 212 ret = pm_runtime_get_sync(&client->dev); 213 } else { 214 pm_runtime_mark_last_busy(&client->dev); 215 ret = pm_runtime_put_autosuspend(&client->dev); 216 } 217 218 if (ret < 0) { 219 dev_err(&client->dev, 220 "failed to change power state to %d\n", on); 221 if (on) 222 pm_runtime_put_noidle(&client->dev); 223 224 return ret; 225 } 226 #endif 227 228 return 0; 229 } 230 231 static int mma8452_read(struct mma8452_data *data, __be16 buf[3]) 232 { 233 int ret = mma8452_drdy(data); 234 235 if (ret < 0) 236 return ret; 237 238 ret = mma8452_set_runtime_pm_state(data->client, true); 239 if (ret) 240 return ret; 241 242 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X, 243 3 * sizeof(__be16), (u8 *)buf); 244 245 ret = mma8452_set_runtime_pm_state(data->client, false); 246 247 return ret; 248 } 249 250 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2], 251 int n) 252 { 253 size_t len = 0; 254 255 while (n-- > 0) 256 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ", 257 vals[n][0], vals[n][1]); 258 259 /* replace trailing space by newline */ 260 buf[len - 1] = '\n'; 261 262 return len; 263 } 264 265 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n, 266 int val, int val2) 267 { 268 while (n-- > 0) 269 if (val == vals[n][0] && val2 == vals[n][1]) 270 return n; 271 272 return -EINVAL; 273 } 274 275 static unsigned int mma8452_get_odr_index(struct mma8452_data *data) 276 { 277 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >> 278 MMA8452_CTRL_DR_SHIFT; 279 } 280 281 static const int mma8452_samp_freq[8][2] = { 282 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000}, 283 {6, 250000}, {1, 560000} 284 }; 285 286 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */ 287 static const unsigned int mma8452_transient_time_step_us[4][8] = { 288 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */ 289 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */ 290 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/ 291 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */ 292 }; 293 294 /* Datasheet table "High-Pass Filter Cutoff Options" */ 295 static const int mma8452_hp_filter_cutoff[4][8][4][2] = { 296 { /* normal */ 297 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */ 298 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */ 299 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */ 300 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */ 301 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */ 302 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */ 303 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */ 304 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */ 305 }, 306 { /* low noise low power */ 307 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 308 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 309 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 310 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 311 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 312 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 313 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 314 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} } 315 }, 316 { /* high resolution */ 317 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 318 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 319 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 320 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 321 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 322 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 323 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 324 { {16, 0}, {8, 0}, {4, 0}, {2, 0} } 325 }, 326 { /* low power */ 327 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 328 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 329 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 330 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 331 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} }, 332 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 333 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 334 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} } 335 } 336 }; 337 338 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */ 339 static const u16 mma8452_os_ratio[4][8] = { 340 /* 800 Hz, 400 Hz, ... , 1.56 Hz */ 341 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */ 342 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */ 343 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */ 344 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */ 345 }; 346 347 static int mma8452_get_power_mode(struct mma8452_data *data) 348 { 349 int reg; 350 351 reg = i2c_smbus_read_byte_data(data->client, 352 MMA8452_CTRL_REG2); 353 if (reg < 0) 354 return reg; 355 356 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >> 357 MMA8452_CTRL_REG2_MODS_SHIFT); 358 } 359 360 static ssize_t mma8452_show_samp_freq_avail(struct device *dev, 361 struct device_attribute *attr, 362 char *buf) 363 { 364 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq, 365 ARRAY_SIZE(mma8452_samp_freq)); 366 } 367 368 static ssize_t mma8452_show_scale_avail(struct device *dev, 369 struct device_attribute *attr, 370 char *buf) 371 { 372 struct mma8452_data *data = iio_priv(i2c_get_clientdata( 373 to_i2c_client(dev))); 374 375 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales, 376 ARRAY_SIZE(data->chip_info->mma_scales)); 377 } 378 379 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev, 380 struct device_attribute *attr, 381 char *buf) 382 { 383 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 384 struct mma8452_data *data = iio_priv(indio_dev); 385 int i, j; 386 387 i = mma8452_get_odr_index(data); 388 j = mma8452_get_power_mode(data); 389 if (j < 0) 390 return j; 391 392 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i], 393 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0])); 394 } 395 396 static ssize_t mma8452_show_os_ratio_avail(struct device *dev, 397 struct device_attribute *attr, 398 char *buf) 399 { 400 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 401 struct mma8452_data *data = iio_priv(indio_dev); 402 int i = mma8452_get_odr_index(data); 403 int j; 404 u16 val = 0; 405 size_t len = 0; 406 407 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) { 408 if (val == mma8452_os_ratio[j][i]) 409 continue; 410 411 val = mma8452_os_ratio[j][i]; 412 413 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val); 414 } 415 buf[len - 1] = '\n'; 416 417 return len; 418 } 419 420 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail); 421 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444, 422 mma8452_show_scale_avail, NULL, 0); 423 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available, 424 0444, mma8452_show_hp_cutoff_avail, NULL, 0); 425 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444, 426 mma8452_show_os_ratio_avail, NULL, 0); 427 428 static int mma8452_get_samp_freq_index(struct mma8452_data *data, 429 int val, int val2) 430 { 431 return mma8452_get_int_plus_micros_index(mma8452_samp_freq, 432 ARRAY_SIZE(mma8452_samp_freq), 433 val, val2); 434 } 435 436 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2) 437 { 438 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales, 439 ARRAY_SIZE(data->chip_info->mma_scales), val, val2); 440 } 441 442 static int mma8452_get_hp_filter_index(struct mma8452_data *data, 443 int val, int val2) 444 { 445 int i, j; 446 447 i = mma8452_get_odr_index(data); 448 j = mma8452_get_power_mode(data); 449 if (j < 0) 450 return j; 451 452 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i], 453 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2); 454 } 455 456 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz) 457 { 458 int j, i, ret; 459 460 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF); 461 if (ret < 0) 462 return ret; 463 464 i = mma8452_get_odr_index(data); 465 j = mma8452_get_power_mode(data); 466 if (j < 0) 467 return j; 468 469 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 470 *hz = mma8452_hp_filter_cutoff[j][i][ret][0]; 471 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1]; 472 473 return 0; 474 } 475 476 static int mma8452_read_raw(struct iio_dev *indio_dev, 477 struct iio_chan_spec const *chan, 478 int *val, int *val2, long mask) 479 { 480 struct mma8452_data *data = iio_priv(indio_dev); 481 __be16 buffer[3]; 482 int i, ret; 483 484 switch (mask) { 485 case IIO_CHAN_INFO_RAW: 486 ret = iio_device_claim_direct_mode(indio_dev); 487 if (ret) 488 return ret; 489 490 mutex_lock(&data->lock); 491 ret = mma8452_read(data, buffer); 492 mutex_unlock(&data->lock); 493 iio_device_release_direct_mode(indio_dev); 494 if (ret < 0) 495 return ret; 496 497 *val = sign_extend32(be16_to_cpu( 498 buffer[chan->scan_index]) >> chan->scan_type.shift, 499 chan->scan_type.realbits - 1); 500 501 return IIO_VAL_INT; 502 case IIO_CHAN_INFO_SCALE: 503 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK; 504 *val = data->chip_info->mma_scales[i][0]; 505 *val2 = data->chip_info->mma_scales[i][1]; 506 507 return IIO_VAL_INT_PLUS_MICRO; 508 case IIO_CHAN_INFO_SAMP_FREQ: 509 i = mma8452_get_odr_index(data); 510 *val = mma8452_samp_freq[i][0]; 511 *val2 = mma8452_samp_freq[i][1]; 512 513 return IIO_VAL_INT_PLUS_MICRO; 514 case IIO_CHAN_INFO_CALIBBIAS: 515 ret = i2c_smbus_read_byte_data(data->client, 516 MMA8452_OFF_X + 517 chan->scan_index); 518 if (ret < 0) 519 return ret; 520 521 *val = sign_extend32(ret, 7); 522 523 return IIO_VAL_INT; 524 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 525 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) { 526 ret = mma8452_read_hp_filter(data, val, val2); 527 if (ret < 0) 528 return ret; 529 } else { 530 *val = 0; 531 *val2 = 0; 532 } 533 534 return IIO_VAL_INT_PLUS_MICRO; 535 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 536 ret = mma8452_get_power_mode(data); 537 if (ret < 0) 538 return ret; 539 540 i = mma8452_get_odr_index(data); 541 542 *val = mma8452_os_ratio[ret][i]; 543 return IIO_VAL_INT; 544 } 545 546 return -EINVAL; 547 } 548 549 static int mma8452_standby(struct mma8452_data *data) 550 { 551 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 552 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE); 553 } 554 555 static int mma8452_active(struct mma8452_data *data) 556 { 557 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 558 data->ctrl_reg1); 559 } 560 561 /* returns >0 if active, 0 if in standby and <0 on error */ 562 static int mma8452_is_active(struct mma8452_data *data) 563 { 564 int reg; 565 566 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1); 567 if (reg < 0) 568 return reg; 569 570 return reg & MMA8452_CTRL_ACTIVE; 571 } 572 573 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val) 574 { 575 int ret; 576 int is_active; 577 578 mutex_lock(&data->lock); 579 580 is_active = mma8452_is_active(data); 581 if (is_active < 0) { 582 ret = is_active; 583 goto fail; 584 } 585 586 /* config can only be changed when in standby */ 587 if (is_active > 0) { 588 ret = mma8452_standby(data); 589 if (ret < 0) 590 goto fail; 591 } 592 593 ret = i2c_smbus_write_byte_data(data->client, reg, val); 594 if (ret < 0) 595 goto fail; 596 597 if (is_active > 0) { 598 ret = mma8452_active(data); 599 if (ret < 0) 600 goto fail; 601 } 602 603 ret = 0; 604 fail: 605 mutex_unlock(&data->lock); 606 607 return ret; 608 } 609 610 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode) 611 { 612 int reg; 613 614 reg = i2c_smbus_read_byte_data(data->client, 615 MMA8452_CTRL_REG2); 616 if (reg < 0) 617 return reg; 618 619 reg &= ~MMA8452_CTRL_REG2_MODS_MASK; 620 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT; 621 622 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg); 623 } 624 625 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */ 626 static int mma8452_freefall_mode_enabled(struct mma8452_data *data) 627 { 628 int val; 629 630 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); 631 if (val < 0) 632 return val; 633 634 return !(val & MMA8452_FF_MT_CFG_OAE); 635 } 636 637 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state) 638 { 639 int val; 640 641 if ((state && mma8452_freefall_mode_enabled(data)) || 642 (!state && !(mma8452_freefall_mode_enabled(data)))) 643 return 0; 644 645 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); 646 if (val < 0) 647 return val; 648 649 if (state) { 650 val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); 651 val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); 652 val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); 653 val &= ~MMA8452_FF_MT_CFG_OAE; 654 } else { 655 val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); 656 val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); 657 val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); 658 val |= MMA8452_FF_MT_CFG_OAE; 659 } 660 661 return mma8452_change_config(data, MMA8452_FF_MT_CFG, val); 662 } 663 664 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data, 665 int val, int val2) 666 { 667 int i, reg; 668 669 i = mma8452_get_hp_filter_index(data, val, val2); 670 if (i < 0) 671 return i; 672 673 reg = i2c_smbus_read_byte_data(data->client, 674 MMA8452_HP_FILTER_CUTOFF); 675 if (reg < 0) 676 return reg; 677 678 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 679 reg |= i; 680 681 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg); 682 } 683 684 static int mma8452_write_raw(struct iio_dev *indio_dev, 685 struct iio_chan_spec const *chan, 686 int val, int val2, long mask) 687 { 688 struct mma8452_data *data = iio_priv(indio_dev); 689 int i, ret; 690 691 ret = iio_device_claim_direct_mode(indio_dev); 692 if (ret) 693 return ret; 694 695 switch (mask) { 696 case IIO_CHAN_INFO_SAMP_FREQ: 697 i = mma8452_get_samp_freq_index(data, val, val2); 698 if (i < 0) { 699 ret = i; 700 break; 701 } 702 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK; 703 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT; 704 705 ret = mma8452_change_config(data, MMA8452_CTRL_REG1, 706 data->ctrl_reg1); 707 break; 708 case IIO_CHAN_INFO_SCALE: 709 i = mma8452_get_scale_index(data, val, val2); 710 if (i < 0) { 711 ret = i; 712 break; 713 } 714 715 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK; 716 data->data_cfg |= i; 717 718 ret = mma8452_change_config(data, MMA8452_DATA_CFG, 719 data->data_cfg); 720 break; 721 case IIO_CHAN_INFO_CALIBBIAS: 722 if (val < -128 || val > 127) { 723 ret = -EINVAL; 724 break; 725 } 726 727 ret = mma8452_change_config(data, 728 MMA8452_OFF_X + chan->scan_index, 729 val); 730 break; 731 732 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 733 if (val == 0 && val2 == 0) { 734 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK; 735 } else { 736 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK; 737 ret = mma8452_set_hp_filter_frequency(data, val, val2); 738 if (ret < 0) 739 break; 740 } 741 742 ret = mma8452_change_config(data, MMA8452_DATA_CFG, 743 data->data_cfg); 744 break; 745 746 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 747 ret = mma8452_get_odr_index(data); 748 749 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) { 750 if (mma8452_os_ratio[i][ret] == val) { 751 ret = mma8452_set_power_mode(data, i); 752 break; 753 } 754 } 755 break; 756 default: 757 ret = -EINVAL; 758 break; 759 } 760 761 iio_device_release_direct_mode(indio_dev); 762 return ret; 763 } 764 765 static int mma8452_get_event_regs(struct mma8452_data *data, 766 const struct iio_chan_spec *chan, enum iio_event_direction dir, 767 const struct mma8452_event_regs **ev_reg) 768 { 769 if (!chan) 770 return -EINVAL; 771 772 switch (chan->type) { 773 case IIO_ACCEL: 774 switch (dir) { 775 case IIO_EV_DIR_RISING: 776 if ((data->chip_info->all_events 777 & MMA8452_INT_TRANS) && 778 (data->chip_info->enabled_events 779 & MMA8452_INT_TRANS)) 780 *ev_reg = &ev_regs_accel_rising; 781 else 782 *ev_reg = &ev_regs_accel_falling; 783 return 0; 784 case IIO_EV_DIR_FALLING: 785 *ev_reg = &ev_regs_accel_falling; 786 return 0; 787 default: 788 return -EINVAL; 789 } 790 default: 791 return -EINVAL; 792 } 793 } 794 795 static int mma8452_read_event_value(struct iio_dev *indio_dev, 796 const struct iio_chan_spec *chan, 797 enum iio_event_type type, 798 enum iio_event_direction dir, 799 enum iio_event_info info, 800 int *val, int *val2) 801 { 802 struct mma8452_data *data = iio_priv(indio_dev); 803 int ret, us, power_mode; 804 const struct mma8452_event_regs *ev_regs; 805 806 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 807 if (ret) 808 return ret; 809 810 switch (info) { 811 case IIO_EV_INFO_VALUE: 812 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths); 813 if (ret < 0) 814 return ret; 815 816 *val = ret & ev_regs->ev_ths_mask; 817 818 return IIO_VAL_INT; 819 820 case IIO_EV_INFO_PERIOD: 821 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count); 822 if (ret < 0) 823 return ret; 824 825 power_mode = mma8452_get_power_mode(data); 826 if (power_mode < 0) 827 return power_mode; 828 829 us = ret * mma8452_transient_time_step_us[power_mode][ 830 mma8452_get_odr_index(data)]; 831 *val = us / USEC_PER_SEC; 832 *val2 = us % USEC_PER_SEC; 833 834 return IIO_VAL_INT_PLUS_MICRO; 835 836 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 837 ret = i2c_smbus_read_byte_data(data->client, 838 MMA8452_TRANSIENT_CFG); 839 if (ret < 0) 840 return ret; 841 842 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) { 843 *val = 0; 844 *val2 = 0; 845 } else { 846 ret = mma8452_read_hp_filter(data, val, val2); 847 if (ret < 0) 848 return ret; 849 } 850 851 return IIO_VAL_INT_PLUS_MICRO; 852 853 default: 854 return -EINVAL; 855 } 856 } 857 858 static int mma8452_write_event_value(struct iio_dev *indio_dev, 859 const struct iio_chan_spec *chan, 860 enum iio_event_type type, 861 enum iio_event_direction dir, 862 enum iio_event_info info, 863 int val, int val2) 864 { 865 struct mma8452_data *data = iio_priv(indio_dev); 866 int ret, reg, steps; 867 const struct mma8452_event_regs *ev_regs; 868 869 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 870 if (ret) 871 return ret; 872 873 switch (info) { 874 case IIO_EV_INFO_VALUE: 875 if (val < 0 || val > ev_regs->ev_ths_mask) 876 return -EINVAL; 877 878 return mma8452_change_config(data, ev_regs->ev_ths, val); 879 880 case IIO_EV_INFO_PERIOD: 881 ret = mma8452_get_power_mode(data); 882 if (ret < 0) 883 return ret; 884 885 steps = (val * USEC_PER_SEC + val2) / 886 mma8452_transient_time_step_us[ret][ 887 mma8452_get_odr_index(data)]; 888 889 if (steps < 0 || steps > 0xff) 890 return -EINVAL; 891 892 return mma8452_change_config(data, ev_regs->ev_count, steps); 893 894 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 895 reg = i2c_smbus_read_byte_data(data->client, 896 MMA8452_TRANSIENT_CFG); 897 if (reg < 0) 898 return reg; 899 900 if (val == 0 && val2 == 0) { 901 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP; 902 } else { 903 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP; 904 ret = mma8452_set_hp_filter_frequency(data, val, val2); 905 if (ret < 0) 906 return ret; 907 } 908 909 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg); 910 911 default: 912 return -EINVAL; 913 } 914 } 915 916 static int mma8452_read_event_config(struct iio_dev *indio_dev, 917 const struct iio_chan_spec *chan, 918 enum iio_event_type type, 919 enum iio_event_direction dir) 920 { 921 struct mma8452_data *data = iio_priv(indio_dev); 922 int ret; 923 const struct mma8452_event_regs *ev_regs; 924 925 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 926 if (ret) 927 return ret; 928 929 switch (dir) { 930 case IIO_EV_DIR_FALLING: 931 return mma8452_freefall_mode_enabled(data); 932 case IIO_EV_DIR_RISING: 933 ret = i2c_smbus_read_byte_data(data->client, 934 ev_regs->ev_cfg); 935 if (ret < 0) 936 return ret; 937 938 return !!(ret & BIT(chan->scan_index + 939 ev_regs->ev_cfg_chan_shift)); 940 default: 941 return -EINVAL; 942 } 943 } 944 945 static int mma8452_write_event_config(struct iio_dev *indio_dev, 946 const struct iio_chan_spec *chan, 947 enum iio_event_type type, 948 enum iio_event_direction dir, 949 int state) 950 { 951 struct mma8452_data *data = iio_priv(indio_dev); 952 int val, ret; 953 const struct mma8452_event_regs *ev_regs; 954 955 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 956 if (ret) 957 return ret; 958 959 ret = mma8452_set_runtime_pm_state(data->client, state); 960 if (ret) 961 return ret; 962 963 switch (dir) { 964 case IIO_EV_DIR_FALLING: 965 return mma8452_set_freefall_mode(data, state); 966 case IIO_EV_DIR_RISING: 967 val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg); 968 if (val < 0) 969 return val; 970 971 if (state) { 972 if (mma8452_freefall_mode_enabled(data)) { 973 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift); 974 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift); 975 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift); 976 val |= MMA8452_FF_MT_CFG_OAE; 977 } 978 val |= BIT(chan->scan_index + 979 ev_regs->ev_cfg_chan_shift); 980 } else { 981 if (mma8452_freefall_mode_enabled(data)) 982 return 0; 983 984 val &= ~BIT(chan->scan_index + 985 ev_regs->ev_cfg_chan_shift); 986 } 987 988 val |= ev_regs->ev_cfg_ele; 989 990 return mma8452_change_config(data, ev_regs->ev_cfg, val); 991 default: 992 return -EINVAL; 993 } 994 } 995 996 static void mma8452_transient_interrupt(struct iio_dev *indio_dev) 997 { 998 struct mma8452_data *data = iio_priv(indio_dev); 999 s64 ts = iio_get_time_ns(indio_dev); 1000 int src; 1001 1002 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC); 1003 if (src < 0) 1004 return; 1005 1006 if (src & MMA8452_TRANSIENT_SRC_XTRANSE) 1007 iio_push_event(indio_dev, 1008 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1009 IIO_EV_TYPE_MAG, 1010 IIO_EV_DIR_RISING), 1011 ts); 1012 1013 if (src & MMA8452_TRANSIENT_SRC_YTRANSE) 1014 iio_push_event(indio_dev, 1015 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y, 1016 IIO_EV_TYPE_MAG, 1017 IIO_EV_DIR_RISING), 1018 ts); 1019 1020 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE) 1021 iio_push_event(indio_dev, 1022 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z, 1023 IIO_EV_TYPE_MAG, 1024 IIO_EV_DIR_RISING), 1025 ts); 1026 } 1027 1028 static irqreturn_t mma8452_interrupt(int irq, void *p) 1029 { 1030 struct iio_dev *indio_dev = p; 1031 struct mma8452_data *data = iio_priv(indio_dev); 1032 int ret = IRQ_NONE; 1033 int src; 1034 1035 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC); 1036 if (src < 0) 1037 return IRQ_NONE; 1038 1039 if (!(src & data->chip_info->enabled_events)) 1040 return IRQ_NONE; 1041 1042 if (src & MMA8452_INT_DRDY) { 1043 iio_trigger_poll_chained(indio_dev->trig); 1044 ret = IRQ_HANDLED; 1045 } 1046 1047 if (src & MMA8452_INT_FF_MT) { 1048 if (mma8452_freefall_mode_enabled(data)) { 1049 s64 ts = iio_get_time_ns(indio_dev); 1050 1051 iio_push_event(indio_dev, 1052 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 1053 IIO_MOD_X_AND_Y_AND_Z, 1054 IIO_EV_TYPE_MAG, 1055 IIO_EV_DIR_FALLING), 1056 ts); 1057 } 1058 ret = IRQ_HANDLED; 1059 } 1060 1061 if (src & MMA8452_INT_TRANS) { 1062 mma8452_transient_interrupt(indio_dev); 1063 ret = IRQ_HANDLED; 1064 } 1065 1066 return ret; 1067 } 1068 1069 static irqreturn_t mma8452_trigger_handler(int irq, void *p) 1070 { 1071 struct iio_poll_func *pf = p; 1072 struct iio_dev *indio_dev = pf->indio_dev; 1073 struct mma8452_data *data = iio_priv(indio_dev); 1074 u8 buffer[16]; /* 3 16-bit channels + padding + ts */ 1075 int ret; 1076 1077 ret = mma8452_read(data, (__be16 *)buffer); 1078 if (ret < 0) 1079 goto done; 1080 1081 iio_push_to_buffers_with_timestamp(indio_dev, buffer, 1082 iio_get_time_ns(indio_dev)); 1083 1084 done: 1085 iio_trigger_notify_done(indio_dev->trig); 1086 1087 return IRQ_HANDLED; 1088 } 1089 1090 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev, 1091 unsigned int reg, unsigned int writeval, 1092 unsigned int *readval) 1093 { 1094 int ret; 1095 struct mma8452_data *data = iio_priv(indio_dev); 1096 1097 if (reg > MMA8452_MAX_REG) 1098 return -EINVAL; 1099 1100 if (!readval) 1101 return mma8452_change_config(data, reg, writeval); 1102 1103 ret = i2c_smbus_read_byte_data(data->client, reg); 1104 if (ret < 0) 1105 return ret; 1106 1107 *readval = ret; 1108 1109 return 0; 1110 } 1111 1112 static const struct iio_event_spec mma8452_freefall_event[] = { 1113 { 1114 .type = IIO_EV_TYPE_MAG, 1115 .dir = IIO_EV_DIR_FALLING, 1116 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1117 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1118 BIT(IIO_EV_INFO_PERIOD) | 1119 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1120 }, 1121 }; 1122 1123 static const struct iio_event_spec mma8652_freefall_event[] = { 1124 { 1125 .type = IIO_EV_TYPE_MAG, 1126 .dir = IIO_EV_DIR_FALLING, 1127 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1128 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1129 BIT(IIO_EV_INFO_PERIOD) 1130 }, 1131 }; 1132 1133 static const struct iio_event_spec mma8452_transient_event[] = { 1134 { 1135 .type = IIO_EV_TYPE_MAG, 1136 .dir = IIO_EV_DIR_RISING, 1137 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1138 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1139 BIT(IIO_EV_INFO_PERIOD) | 1140 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1141 }, 1142 }; 1143 1144 static const struct iio_event_spec mma8452_motion_event[] = { 1145 { 1146 .type = IIO_EV_TYPE_MAG, 1147 .dir = IIO_EV_DIR_RISING, 1148 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1149 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1150 BIT(IIO_EV_INFO_PERIOD) 1151 }, 1152 }; 1153 1154 /* 1155 * Threshold is configured in fixed 8G/127 steps regardless of 1156 * currently selected scale for measurement. 1157 */ 1158 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742"); 1159 1160 static struct attribute *mma8452_event_attributes[] = { 1161 &iio_const_attr_accel_transient_scale.dev_attr.attr, 1162 NULL, 1163 }; 1164 1165 static struct attribute_group mma8452_event_attribute_group = { 1166 .attrs = mma8452_event_attributes, 1167 }; 1168 1169 #define MMA8452_FREEFALL_CHANNEL(modifier) { \ 1170 .type = IIO_ACCEL, \ 1171 .modified = 1, \ 1172 .channel2 = modifier, \ 1173 .scan_index = -1, \ 1174 .event_spec = mma8452_freefall_event, \ 1175 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \ 1176 } 1177 1178 #define MMA8652_FREEFALL_CHANNEL(modifier) { \ 1179 .type = IIO_ACCEL, \ 1180 .modified = 1, \ 1181 .channel2 = modifier, \ 1182 .scan_index = -1, \ 1183 .event_spec = mma8652_freefall_event, \ 1184 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \ 1185 } 1186 1187 #define MMA8452_CHANNEL(axis, idx, bits) { \ 1188 .type = IIO_ACCEL, \ 1189 .modified = 1, \ 1190 .channel2 = IIO_MOD_##axis, \ 1191 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1192 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1193 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1194 BIT(IIO_CHAN_INFO_SCALE) | \ 1195 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \ 1196 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1197 .scan_index = idx, \ 1198 .scan_type = { \ 1199 .sign = 's', \ 1200 .realbits = (bits), \ 1201 .storagebits = 16, \ 1202 .shift = 16 - (bits), \ 1203 .endianness = IIO_BE, \ 1204 }, \ 1205 .event_spec = mma8452_transient_event, \ 1206 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \ 1207 } 1208 1209 #define MMA8652_CHANNEL(axis, idx, bits) { \ 1210 .type = IIO_ACCEL, \ 1211 .modified = 1, \ 1212 .channel2 = IIO_MOD_##axis, \ 1213 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1214 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1215 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1216 BIT(IIO_CHAN_INFO_SCALE) | \ 1217 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1218 .scan_index = idx, \ 1219 .scan_type = { \ 1220 .sign = 's', \ 1221 .realbits = (bits), \ 1222 .storagebits = 16, \ 1223 .shift = 16 - (bits), \ 1224 .endianness = IIO_BE, \ 1225 }, \ 1226 .event_spec = mma8452_motion_event, \ 1227 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \ 1228 } 1229 1230 static const struct iio_chan_spec mma8451_channels[] = { 1231 MMA8452_CHANNEL(X, idx_x, 14), 1232 MMA8452_CHANNEL(Y, idx_y, 14), 1233 MMA8452_CHANNEL(Z, idx_z, 14), 1234 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1235 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1236 }; 1237 1238 static const struct iio_chan_spec mma8452_channels[] = { 1239 MMA8452_CHANNEL(X, idx_x, 12), 1240 MMA8452_CHANNEL(Y, idx_y, 12), 1241 MMA8452_CHANNEL(Z, idx_z, 12), 1242 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1243 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1244 }; 1245 1246 static const struct iio_chan_spec mma8453_channels[] = { 1247 MMA8452_CHANNEL(X, idx_x, 10), 1248 MMA8452_CHANNEL(Y, idx_y, 10), 1249 MMA8452_CHANNEL(Z, idx_z, 10), 1250 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1251 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1252 }; 1253 1254 static const struct iio_chan_spec mma8652_channels[] = { 1255 MMA8652_CHANNEL(X, idx_x, 12), 1256 MMA8652_CHANNEL(Y, idx_y, 12), 1257 MMA8652_CHANNEL(Z, idx_z, 12), 1258 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1259 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1260 }; 1261 1262 static const struct iio_chan_spec mma8653_channels[] = { 1263 MMA8652_CHANNEL(X, idx_x, 10), 1264 MMA8652_CHANNEL(Y, idx_y, 10), 1265 MMA8652_CHANNEL(Z, idx_z, 10), 1266 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1267 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1268 }; 1269 1270 enum { 1271 mma8451, 1272 mma8452, 1273 mma8453, 1274 mma8652, 1275 mma8653, 1276 fxls8471, 1277 }; 1278 1279 static const struct mma_chip_info mma_chip_info_table[] = { 1280 [mma8451] = { 1281 .chip_id = MMA8451_DEVICE_ID, 1282 .channels = mma8451_channels, 1283 .num_channels = ARRAY_SIZE(mma8451_channels), 1284 /* 1285 * Hardware has fullscale of -2G, -4G, -8G corresponding to 1286 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10 1287 * bit. 1288 * The userspace interface uses m/s^2 and we declare micro units 1289 * So scale factor for 12 bit here is given by: 1290 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665 1291 */ 1292 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1293 /* 1294 * Although we enable the interrupt sources once and for 1295 * all here the event detection itself is not enabled until 1296 * userspace asks for it by mma8452_write_event_config() 1297 */ 1298 .all_events = MMA8452_INT_DRDY | 1299 MMA8452_INT_TRANS | 1300 MMA8452_INT_FF_MT, 1301 .enabled_events = MMA8452_INT_TRANS | 1302 MMA8452_INT_FF_MT, 1303 }, 1304 [mma8452] = { 1305 .chip_id = MMA8452_DEVICE_ID, 1306 .channels = mma8452_channels, 1307 .num_channels = ARRAY_SIZE(mma8452_channels), 1308 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1309 /* 1310 * Although we enable the interrupt sources once and for 1311 * all here the event detection itself is not enabled until 1312 * userspace asks for it by mma8452_write_event_config() 1313 */ 1314 .all_events = MMA8452_INT_DRDY | 1315 MMA8452_INT_TRANS | 1316 MMA8452_INT_FF_MT, 1317 .enabled_events = MMA8452_INT_TRANS | 1318 MMA8452_INT_FF_MT, 1319 }, 1320 [mma8453] = { 1321 .chip_id = MMA8453_DEVICE_ID, 1322 .channels = mma8453_channels, 1323 .num_channels = ARRAY_SIZE(mma8453_channels), 1324 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1325 /* 1326 * Although we enable the interrupt sources once and for 1327 * all here the event detection itself is not enabled until 1328 * userspace asks for it by mma8452_write_event_config() 1329 */ 1330 .all_events = MMA8452_INT_DRDY | 1331 MMA8452_INT_TRANS | 1332 MMA8452_INT_FF_MT, 1333 .enabled_events = MMA8452_INT_TRANS | 1334 MMA8452_INT_FF_MT, 1335 }, 1336 [mma8652] = { 1337 .chip_id = MMA8652_DEVICE_ID, 1338 .channels = mma8652_channels, 1339 .num_channels = ARRAY_SIZE(mma8652_channels), 1340 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1341 .all_events = MMA8452_INT_DRDY | 1342 MMA8452_INT_FF_MT, 1343 .enabled_events = MMA8452_INT_FF_MT, 1344 }, 1345 [mma8653] = { 1346 .chip_id = MMA8653_DEVICE_ID, 1347 .channels = mma8653_channels, 1348 .num_channels = ARRAY_SIZE(mma8653_channels), 1349 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1350 /* 1351 * Although we enable the interrupt sources once and for 1352 * all here the event detection itself is not enabled until 1353 * userspace asks for it by mma8452_write_event_config() 1354 */ 1355 .all_events = MMA8452_INT_DRDY | 1356 MMA8452_INT_FF_MT, 1357 .enabled_events = MMA8452_INT_FF_MT, 1358 }, 1359 [fxls8471] = { 1360 .chip_id = FXLS8471_DEVICE_ID, 1361 .channels = mma8451_channels, 1362 .num_channels = ARRAY_SIZE(mma8451_channels), 1363 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1364 /* 1365 * Although we enable the interrupt sources once and for 1366 * all here the event detection itself is not enabled until 1367 * userspace asks for it by mma8452_write_event_config() 1368 */ 1369 .all_events = MMA8452_INT_DRDY | 1370 MMA8452_INT_TRANS | 1371 MMA8452_INT_FF_MT, 1372 .enabled_events = MMA8452_INT_TRANS | 1373 MMA8452_INT_FF_MT, 1374 }, 1375 }; 1376 1377 static struct attribute *mma8452_attributes[] = { 1378 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1379 &iio_dev_attr_in_accel_scale_available.dev_attr.attr, 1380 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr, 1381 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr, 1382 NULL 1383 }; 1384 1385 static const struct attribute_group mma8452_group = { 1386 .attrs = mma8452_attributes, 1387 }; 1388 1389 static const struct iio_info mma8452_info = { 1390 .attrs = &mma8452_group, 1391 .read_raw = &mma8452_read_raw, 1392 .write_raw = &mma8452_write_raw, 1393 .event_attrs = &mma8452_event_attribute_group, 1394 .read_event_value = &mma8452_read_event_value, 1395 .write_event_value = &mma8452_write_event_value, 1396 .read_event_config = &mma8452_read_event_config, 1397 .write_event_config = &mma8452_write_event_config, 1398 .debugfs_reg_access = &mma8452_reg_access_dbg, 1399 }; 1400 1401 static const unsigned long mma8452_scan_masks[] = {0x7, 0}; 1402 1403 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig, 1404 bool state) 1405 { 1406 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1407 struct mma8452_data *data = iio_priv(indio_dev); 1408 int reg, ret; 1409 1410 ret = mma8452_set_runtime_pm_state(data->client, state); 1411 if (ret) 1412 return ret; 1413 1414 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4); 1415 if (reg < 0) 1416 return reg; 1417 1418 if (state) 1419 reg |= MMA8452_INT_DRDY; 1420 else 1421 reg &= ~MMA8452_INT_DRDY; 1422 1423 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg); 1424 } 1425 1426 static const struct iio_trigger_ops mma8452_trigger_ops = { 1427 .set_trigger_state = mma8452_data_rdy_trigger_set_state, 1428 .validate_device = iio_trigger_validate_own_device, 1429 }; 1430 1431 static int mma8452_trigger_setup(struct iio_dev *indio_dev) 1432 { 1433 struct mma8452_data *data = iio_priv(indio_dev); 1434 struct iio_trigger *trig; 1435 int ret; 1436 1437 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d", 1438 indio_dev->name, 1439 indio_dev->id); 1440 if (!trig) 1441 return -ENOMEM; 1442 1443 trig->dev.parent = &data->client->dev; 1444 trig->ops = &mma8452_trigger_ops; 1445 iio_trigger_set_drvdata(trig, indio_dev); 1446 1447 ret = iio_trigger_register(trig); 1448 if (ret) 1449 return ret; 1450 1451 indio_dev->trig = trig; 1452 1453 return 0; 1454 } 1455 1456 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev) 1457 { 1458 if (indio_dev->trig) 1459 iio_trigger_unregister(indio_dev->trig); 1460 } 1461 1462 static int mma8452_reset(struct i2c_client *client) 1463 { 1464 int i; 1465 int ret; 1466 1467 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2, 1468 MMA8452_CTRL_REG2_RST); 1469 if (ret < 0) 1470 return ret; 1471 1472 for (i = 0; i < 10; i++) { 1473 usleep_range(100, 200); 1474 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2); 1475 if (ret == -EIO) 1476 continue; /* I2C comm reset */ 1477 if (ret < 0) 1478 return ret; 1479 if (!(ret & MMA8452_CTRL_REG2_RST)) 1480 return 0; 1481 } 1482 1483 return -ETIMEDOUT; 1484 } 1485 1486 static const struct of_device_id mma8452_dt_ids[] = { 1487 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] }, 1488 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] }, 1489 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] }, 1490 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] }, 1491 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] }, 1492 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] }, 1493 { } 1494 }; 1495 MODULE_DEVICE_TABLE(of, mma8452_dt_ids); 1496 1497 static int mma8452_probe(struct i2c_client *client, 1498 const struct i2c_device_id *id) 1499 { 1500 struct mma8452_data *data; 1501 struct iio_dev *indio_dev; 1502 int ret; 1503 const struct of_device_id *match; 1504 1505 match = of_match_device(mma8452_dt_ids, &client->dev); 1506 if (!match) { 1507 dev_err(&client->dev, "unknown device model\n"); 1508 return -ENODEV; 1509 } 1510 1511 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 1512 if (!indio_dev) 1513 return -ENOMEM; 1514 1515 data = iio_priv(indio_dev); 1516 data->client = client; 1517 mutex_init(&data->lock); 1518 data->chip_info = match->data; 1519 1520 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I); 1521 if (ret < 0) 1522 return ret; 1523 1524 switch (ret) { 1525 case MMA8451_DEVICE_ID: 1526 case MMA8452_DEVICE_ID: 1527 case MMA8453_DEVICE_ID: 1528 case MMA8652_DEVICE_ID: 1529 case MMA8653_DEVICE_ID: 1530 case FXLS8471_DEVICE_ID: 1531 if (ret == data->chip_info->chip_id) 1532 break; 1533 default: 1534 return -ENODEV; 1535 } 1536 1537 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n", 1538 match->compatible, data->chip_info->chip_id); 1539 1540 i2c_set_clientdata(client, indio_dev); 1541 indio_dev->info = &mma8452_info; 1542 indio_dev->name = id->name; 1543 indio_dev->dev.parent = &client->dev; 1544 indio_dev->modes = INDIO_DIRECT_MODE; 1545 indio_dev->channels = data->chip_info->channels; 1546 indio_dev->num_channels = data->chip_info->num_channels; 1547 indio_dev->available_scan_masks = mma8452_scan_masks; 1548 1549 ret = mma8452_reset(client); 1550 if (ret < 0) 1551 return ret; 1552 1553 data->data_cfg = MMA8452_DATA_CFG_FS_2G; 1554 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG, 1555 data->data_cfg); 1556 if (ret < 0) 1557 return ret; 1558 1559 /* 1560 * By default set transient threshold to max to avoid events if 1561 * enabling without configuring threshold. 1562 */ 1563 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS, 1564 MMA8452_TRANSIENT_THS_MASK); 1565 if (ret < 0) 1566 return ret; 1567 1568 if (client->irq) { 1569 int irq2; 1570 1571 irq2 = of_irq_get_byname(client->dev.of_node, "INT2"); 1572 1573 if (irq2 == client->irq) { 1574 dev_dbg(&client->dev, "using interrupt line INT2\n"); 1575 } else { 1576 ret = i2c_smbus_write_byte_data(client, 1577 MMA8452_CTRL_REG5, 1578 data->chip_info->all_events); 1579 if (ret < 0) 1580 return ret; 1581 1582 dev_dbg(&client->dev, "using interrupt line INT1\n"); 1583 } 1584 1585 ret = i2c_smbus_write_byte_data(client, 1586 MMA8452_CTRL_REG4, 1587 data->chip_info->enabled_events); 1588 if (ret < 0) 1589 return ret; 1590 1591 ret = mma8452_trigger_setup(indio_dev); 1592 if (ret < 0) 1593 return ret; 1594 } 1595 1596 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE | 1597 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT); 1598 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1, 1599 data->ctrl_reg1); 1600 if (ret < 0) 1601 goto trigger_cleanup; 1602 1603 ret = iio_triggered_buffer_setup(indio_dev, NULL, 1604 mma8452_trigger_handler, NULL); 1605 if (ret < 0) 1606 goto trigger_cleanup; 1607 1608 if (client->irq) { 1609 ret = devm_request_threaded_irq(&client->dev, 1610 client->irq, 1611 NULL, mma8452_interrupt, 1612 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1613 client->name, indio_dev); 1614 if (ret) 1615 goto buffer_cleanup; 1616 } 1617 1618 ret = pm_runtime_set_active(&client->dev); 1619 if (ret < 0) 1620 goto buffer_cleanup; 1621 1622 pm_runtime_enable(&client->dev); 1623 pm_runtime_set_autosuspend_delay(&client->dev, 1624 MMA8452_AUTO_SUSPEND_DELAY_MS); 1625 pm_runtime_use_autosuspend(&client->dev); 1626 1627 ret = iio_device_register(indio_dev); 1628 if (ret < 0) 1629 goto buffer_cleanup; 1630 1631 ret = mma8452_set_freefall_mode(data, false); 1632 if (ret < 0) 1633 goto buffer_cleanup; 1634 1635 return 0; 1636 1637 buffer_cleanup: 1638 iio_triggered_buffer_cleanup(indio_dev); 1639 1640 trigger_cleanup: 1641 mma8452_trigger_cleanup(indio_dev); 1642 1643 return ret; 1644 } 1645 1646 static int mma8452_remove(struct i2c_client *client) 1647 { 1648 struct iio_dev *indio_dev = i2c_get_clientdata(client); 1649 1650 iio_device_unregister(indio_dev); 1651 1652 pm_runtime_disable(&client->dev); 1653 pm_runtime_set_suspended(&client->dev); 1654 pm_runtime_put_noidle(&client->dev); 1655 1656 iio_triggered_buffer_cleanup(indio_dev); 1657 mma8452_trigger_cleanup(indio_dev); 1658 mma8452_standby(iio_priv(indio_dev)); 1659 1660 return 0; 1661 } 1662 1663 #ifdef CONFIG_PM 1664 static int mma8452_runtime_suspend(struct device *dev) 1665 { 1666 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1667 struct mma8452_data *data = iio_priv(indio_dev); 1668 int ret; 1669 1670 mutex_lock(&data->lock); 1671 ret = mma8452_standby(data); 1672 mutex_unlock(&data->lock); 1673 if (ret < 0) { 1674 dev_err(&data->client->dev, "powering off device failed\n"); 1675 return -EAGAIN; 1676 } 1677 1678 return 0; 1679 } 1680 1681 static int mma8452_runtime_resume(struct device *dev) 1682 { 1683 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1684 struct mma8452_data *data = iio_priv(indio_dev); 1685 int ret, sleep_val; 1686 1687 ret = mma8452_active(data); 1688 if (ret < 0) 1689 return ret; 1690 1691 ret = mma8452_get_odr_index(data); 1692 sleep_val = 1000 / mma8452_samp_freq[ret][0]; 1693 if (sleep_val < 20) 1694 usleep_range(sleep_val * 1000, 20000); 1695 else 1696 msleep_interruptible(sleep_val); 1697 1698 return 0; 1699 } 1700 #endif 1701 1702 #ifdef CONFIG_PM_SLEEP 1703 static int mma8452_suspend(struct device *dev) 1704 { 1705 return mma8452_standby(iio_priv(i2c_get_clientdata( 1706 to_i2c_client(dev)))); 1707 } 1708 1709 static int mma8452_resume(struct device *dev) 1710 { 1711 return mma8452_active(iio_priv(i2c_get_clientdata( 1712 to_i2c_client(dev)))); 1713 } 1714 #endif 1715 1716 static const struct dev_pm_ops mma8452_pm_ops = { 1717 SET_SYSTEM_SLEEP_PM_OPS(mma8452_suspend, mma8452_resume) 1718 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend, 1719 mma8452_runtime_resume, NULL) 1720 }; 1721 1722 static const struct i2c_device_id mma8452_id[] = { 1723 { "mma8451", mma8451 }, 1724 { "mma8452", mma8452 }, 1725 { "mma8453", mma8453 }, 1726 { "mma8652", mma8652 }, 1727 { "mma8653", mma8653 }, 1728 { "fxls8471", fxls8471 }, 1729 { } 1730 }; 1731 MODULE_DEVICE_TABLE(i2c, mma8452_id); 1732 1733 static struct i2c_driver mma8452_driver = { 1734 .driver = { 1735 .name = "mma8452", 1736 .of_match_table = of_match_ptr(mma8452_dt_ids), 1737 .pm = &mma8452_pm_ops, 1738 }, 1739 .probe = mma8452_probe, 1740 .remove = mma8452_remove, 1741 .id_table = mma8452_id, 1742 }; 1743 module_i2c_driver(mma8452_driver); 1744 1745 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>"); 1746 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver"); 1747 MODULE_LICENSE("GPL"); 1748