1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers: 4 * 5 * device name digital output 7-bit I2C slave address (pin selectable) 6 * --------------------------------------------------------------------- 7 * MMA8451Q 14 bit 0x1c / 0x1d 8 * MMA8452Q 12 bit 0x1c / 0x1d 9 * MMA8453Q 10 bit 0x1c / 0x1d 10 * MMA8652FC 12 bit 0x1d 11 * MMA8653FC 10 bit 0x1d 12 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f 13 * 14 * Copyright 2015 Martin Kepplinger <martink@posteo.de> 15 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net> 16 * 17 * 18 * TODO: orientation events 19 */ 20 21 #include <linux/module.h> 22 #include <linux/i2c.h> 23 #include <linux/iio/iio.h> 24 #include <linux/iio/sysfs.h> 25 #include <linux/iio/buffer.h> 26 #include <linux/iio/trigger.h> 27 #include <linux/iio/trigger_consumer.h> 28 #include <linux/iio/triggered_buffer.h> 29 #include <linux/iio/events.h> 30 #include <linux/delay.h> 31 #include <linux/of_device.h> 32 #include <linux/of_irq.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/regulator/consumer.h> 35 36 #define MMA8452_STATUS 0x00 37 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0)) 38 #define MMA8452_OUT_X 0x01 /* MSB first */ 39 #define MMA8452_OUT_Y 0x03 40 #define MMA8452_OUT_Z 0x05 41 #define MMA8452_INT_SRC 0x0c 42 #define MMA8452_WHO_AM_I 0x0d 43 #define MMA8452_DATA_CFG 0x0e 44 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0) 45 #define MMA8452_DATA_CFG_FS_2G 0 46 #define MMA8452_DATA_CFG_FS_4G 1 47 #define MMA8452_DATA_CFG_FS_8G 2 48 #define MMA8452_DATA_CFG_HPF_MASK BIT(4) 49 #define MMA8452_HP_FILTER_CUTOFF 0x0f 50 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0) 51 #define MMA8452_FF_MT_CFG 0x15 52 #define MMA8452_FF_MT_CFG_OAE BIT(6) 53 #define MMA8452_FF_MT_CFG_ELE BIT(7) 54 #define MMA8452_FF_MT_SRC 0x16 55 #define MMA8452_FF_MT_SRC_XHE BIT(1) 56 #define MMA8452_FF_MT_SRC_YHE BIT(3) 57 #define MMA8452_FF_MT_SRC_ZHE BIT(5) 58 #define MMA8452_FF_MT_THS 0x17 59 #define MMA8452_FF_MT_THS_MASK 0x7f 60 #define MMA8452_FF_MT_COUNT 0x18 61 #define MMA8452_FF_MT_CHAN_SHIFT 3 62 #define MMA8452_TRANSIENT_CFG 0x1d 63 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1) 64 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0) 65 #define MMA8452_TRANSIENT_CFG_ELE BIT(4) 66 #define MMA8452_TRANSIENT_SRC 0x1e 67 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1) 68 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3) 69 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5) 70 #define MMA8452_TRANSIENT_THS 0x1f 71 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0) 72 #define MMA8452_TRANSIENT_COUNT 0x20 73 #define MMA8452_TRANSIENT_CHAN_SHIFT 1 74 #define MMA8452_CTRL_REG1 0x2a 75 #define MMA8452_CTRL_ACTIVE BIT(0) 76 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3) 77 #define MMA8452_CTRL_DR_SHIFT 3 78 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */ 79 #define MMA8452_CTRL_REG2 0x2b 80 #define MMA8452_CTRL_REG2_RST BIT(6) 81 #define MMA8452_CTRL_REG2_MODS_SHIFT 3 82 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b 83 #define MMA8452_CTRL_REG4 0x2d 84 #define MMA8452_CTRL_REG5 0x2e 85 #define MMA8452_OFF_X 0x2f 86 #define MMA8452_OFF_Y 0x30 87 #define MMA8452_OFF_Z 0x31 88 89 #define MMA8452_MAX_REG 0x31 90 91 #define MMA8452_INT_DRDY BIT(0) 92 #define MMA8452_INT_FF_MT BIT(2) 93 #define MMA8452_INT_TRANS BIT(5) 94 95 #define MMA8451_DEVICE_ID 0x1a 96 #define MMA8452_DEVICE_ID 0x2a 97 #define MMA8453_DEVICE_ID 0x3a 98 #define MMA8652_DEVICE_ID 0x4a 99 #define MMA8653_DEVICE_ID 0x5a 100 #define FXLS8471_DEVICE_ID 0x6a 101 102 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000 103 104 struct mma8452_data { 105 struct i2c_client *client; 106 struct mutex lock; 107 u8 ctrl_reg1; 108 u8 data_cfg; 109 const struct mma_chip_info *chip_info; 110 int sleep_val; 111 struct regulator *vdd_reg; 112 struct regulator *vddio_reg; 113 114 /* Ensure correct alignment of time stamp when present */ 115 struct { 116 __be16 channels[3]; 117 s64 ts __aligned(8); 118 } buffer; 119 }; 120 121 /** 122 * struct mma8452_event_regs - chip specific data related to events 123 * @ev_cfg: event config register address 124 * @ev_cfg_ele: latch bit in event config register 125 * @ev_cfg_chan_shift: number of the bit to enable events in X 126 * direction; in event config register 127 * @ev_src: event source register address 128 * @ev_ths: event threshold register address 129 * @ev_ths_mask: mask for the threshold value 130 * @ev_count: event count (period) register address 131 * 132 * Since not all chips supported by the driver support comparing high pass 133 * filtered data for events (interrupts), different interrupt sources are 134 * used for different chips and the relevant registers are included here. 135 */ 136 struct mma8452_event_regs { 137 u8 ev_cfg; 138 u8 ev_cfg_ele; 139 u8 ev_cfg_chan_shift; 140 u8 ev_src; 141 u8 ev_ths; 142 u8 ev_ths_mask; 143 u8 ev_count; 144 }; 145 146 static const struct mma8452_event_regs ff_mt_ev_regs = { 147 .ev_cfg = MMA8452_FF_MT_CFG, 148 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE, 149 .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT, 150 .ev_src = MMA8452_FF_MT_SRC, 151 .ev_ths = MMA8452_FF_MT_THS, 152 .ev_ths_mask = MMA8452_FF_MT_THS_MASK, 153 .ev_count = MMA8452_FF_MT_COUNT 154 }; 155 156 static const struct mma8452_event_regs trans_ev_regs = { 157 .ev_cfg = MMA8452_TRANSIENT_CFG, 158 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE, 159 .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT, 160 .ev_src = MMA8452_TRANSIENT_SRC, 161 .ev_ths = MMA8452_TRANSIENT_THS, 162 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK, 163 .ev_count = MMA8452_TRANSIENT_COUNT, 164 }; 165 166 /** 167 * struct mma_chip_info - chip specific data 168 * @chip_id: WHO_AM_I register's value 169 * @channels: struct iio_chan_spec matching the device's 170 * capabilities 171 * @num_channels: number of channels 172 * @mma_scales: scale factors for converting register values 173 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers 174 * per mode: m/s^2 and micro m/s^2 175 * @all_events: all events supported by this chip 176 * @enabled_events: event flags enabled and handled by this driver 177 */ 178 struct mma_chip_info { 179 u8 chip_id; 180 const struct iio_chan_spec *channels; 181 int num_channels; 182 const int mma_scales[3][2]; 183 int all_events; 184 int enabled_events; 185 }; 186 187 enum { 188 idx_x, 189 idx_y, 190 idx_z, 191 idx_ts, 192 }; 193 194 static int mma8452_drdy(struct mma8452_data *data) 195 { 196 int tries = 150; 197 198 while (tries-- > 0) { 199 int ret = i2c_smbus_read_byte_data(data->client, 200 MMA8452_STATUS); 201 if (ret < 0) 202 return ret; 203 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY) 204 return 0; 205 206 if (data->sleep_val <= 20) 207 usleep_range(data->sleep_val * 250, 208 data->sleep_val * 500); 209 else 210 msleep(20); 211 } 212 213 dev_err(&data->client->dev, "data not ready\n"); 214 215 return -EIO; 216 } 217 218 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on) 219 { 220 #ifdef CONFIG_PM 221 int ret; 222 223 if (on) { 224 ret = pm_runtime_resume_and_get(&client->dev); 225 } else { 226 pm_runtime_mark_last_busy(&client->dev); 227 ret = pm_runtime_put_autosuspend(&client->dev); 228 } 229 230 if (ret < 0) { 231 dev_err(&client->dev, 232 "failed to change power state to %d\n", on); 233 234 return ret; 235 } 236 #endif 237 238 return 0; 239 } 240 241 static int mma8452_read(struct mma8452_data *data, __be16 buf[3]) 242 { 243 int ret = mma8452_drdy(data); 244 245 if (ret < 0) 246 return ret; 247 248 ret = mma8452_set_runtime_pm_state(data->client, true); 249 if (ret) 250 return ret; 251 252 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X, 253 3 * sizeof(__be16), (u8 *)buf); 254 255 ret = mma8452_set_runtime_pm_state(data->client, false); 256 257 return ret; 258 } 259 260 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2], 261 int n) 262 { 263 size_t len = 0; 264 265 while (n-- > 0) 266 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ", 267 vals[n][0], vals[n][1]); 268 269 /* replace trailing space by newline */ 270 buf[len - 1] = '\n'; 271 272 return len; 273 } 274 275 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n, 276 int val, int val2) 277 { 278 while (n-- > 0) 279 if (val == vals[n][0] && val2 == vals[n][1]) 280 return n; 281 282 return -EINVAL; 283 } 284 285 static unsigned int mma8452_get_odr_index(struct mma8452_data *data) 286 { 287 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >> 288 MMA8452_CTRL_DR_SHIFT; 289 } 290 291 static const int mma8452_samp_freq[8][2] = { 292 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000}, 293 {6, 250000}, {1, 560000} 294 }; 295 296 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */ 297 static const unsigned int mma8452_time_step_us[4][8] = { 298 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */ 299 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */ 300 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/ 301 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */ 302 }; 303 304 /* Datasheet table "High-Pass Filter Cutoff Options" */ 305 static const int mma8452_hp_filter_cutoff[4][8][4][2] = { 306 { /* normal */ 307 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */ 308 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */ 309 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */ 310 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */ 311 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */ 312 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */ 313 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */ 314 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */ 315 }, 316 { /* low noise low power */ 317 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 318 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 319 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 320 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 321 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 322 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 323 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 324 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} } 325 }, 326 { /* high resolution */ 327 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 328 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 329 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 330 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 331 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 332 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 333 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 334 { {16, 0}, {8, 0}, {4, 0}, {2, 0} } 335 }, 336 { /* low power */ 337 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 338 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 339 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 340 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 341 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} }, 342 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 343 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 344 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} } 345 } 346 }; 347 348 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */ 349 static const u16 mma8452_os_ratio[4][8] = { 350 /* 800 Hz, 400 Hz, ... , 1.56 Hz */ 351 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */ 352 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */ 353 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */ 354 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */ 355 }; 356 357 static int mma8452_get_power_mode(struct mma8452_data *data) 358 { 359 int reg; 360 361 reg = i2c_smbus_read_byte_data(data->client, 362 MMA8452_CTRL_REG2); 363 if (reg < 0) 364 return reg; 365 366 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >> 367 MMA8452_CTRL_REG2_MODS_SHIFT); 368 } 369 370 static ssize_t mma8452_show_samp_freq_avail(struct device *dev, 371 struct device_attribute *attr, 372 char *buf) 373 { 374 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq, 375 ARRAY_SIZE(mma8452_samp_freq)); 376 } 377 378 static ssize_t mma8452_show_scale_avail(struct device *dev, 379 struct device_attribute *attr, 380 char *buf) 381 { 382 struct mma8452_data *data = iio_priv(i2c_get_clientdata( 383 to_i2c_client(dev))); 384 385 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales, 386 ARRAY_SIZE(data->chip_info->mma_scales)); 387 } 388 389 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev, 390 struct device_attribute *attr, 391 char *buf) 392 { 393 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 394 struct mma8452_data *data = iio_priv(indio_dev); 395 int i, j; 396 397 i = mma8452_get_odr_index(data); 398 j = mma8452_get_power_mode(data); 399 if (j < 0) 400 return j; 401 402 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i], 403 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0])); 404 } 405 406 static ssize_t mma8452_show_os_ratio_avail(struct device *dev, 407 struct device_attribute *attr, 408 char *buf) 409 { 410 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 411 struct mma8452_data *data = iio_priv(indio_dev); 412 int i = mma8452_get_odr_index(data); 413 int j; 414 u16 val = 0; 415 size_t len = 0; 416 417 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) { 418 if (val == mma8452_os_ratio[j][i]) 419 continue; 420 421 val = mma8452_os_ratio[j][i]; 422 423 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val); 424 } 425 buf[len - 1] = '\n'; 426 427 return len; 428 } 429 430 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail); 431 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444, 432 mma8452_show_scale_avail, NULL, 0); 433 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available, 434 0444, mma8452_show_hp_cutoff_avail, NULL, 0); 435 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444, 436 mma8452_show_os_ratio_avail, NULL, 0); 437 438 static int mma8452_get_samp_freq_index(struct mma8452_data *data, 439 int val, int val2) 440 { 441 return mma8452_get_int_plus_micros_index(mma8452_samp_freq, 442 ARRAY_SIZE(mma8452_samp_freq), 443 val, val2); 444 } 445 446 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2) 447 { 448 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales, 449 ARRAY_SIZE(data->chip_info->mma_scales), val, val2); 450 } 451 452 static int mma8452_get_hp_filter_index(struct mma8452_data *data, 453 int val, int val2) 454 { 455 int i, j; 456 457 i = mma8452_get_odr_index(data); 458 j = mma8452_get_power_mode(data); 459 if (j < 0) 460 return j; 461 462 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i], 463 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2); 464 } 465 466 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz) 467 { 468 int j, i, ret; 469 470 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF); 471 if (ret < 0) 472 return ret; 473 474 i = mma8452_get_odr_index(data); 475 j = mma8452_get_power_mode(data); 476 if (j < 0) 477 return j; 478 479 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 480 *hz = mma8452_hp_filter_cutoff[j][i][ret][0]; 481 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1]; 482 483 return 0; 484 } 485 486 static int mma8452_read_raw(struct iio_dev *indio_dev, 487 struct iio_chan_spec const *chan, 488 int *val, int *val2, long mask) 489 { 490 struct mma8452_data *data = iio_priv(indio_dev); 491 __be16 buffer[3]; 492 int i, ret; 493 494 switch (mask) { 495 case IIO_CHAN_INFO_RAW: 496 ret = iio_device_claim_direct_mode(indio_dev); 497 if (ret) 498 return ret; 499 500 mutex_lock(&data->lock); 501 ret = mma8452_read(data, buffer); 502 mutex_unlock(&data->lock); 503 iio_device_release_direct_mode(indio_dev); 504 if (ret < 0) 505 return ret; 506 507 *val = sign_extend32(be16_to_cpu( 508 buffer[chan->scan_index]) >> chan->scan_type.shift, 509 chan->scan_type.realbits - 1); 510 511 return IIO_VAL_INT; 512 case IIO_CHAN_INFO_SCALE: 513 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK; 514 *val = data->chip_info->mma_scales[i][0]; 515 *val2 = data->chip_info->mma_scales[i][1]; 516 517 return IIO_VAL_INT_PLUS_MICRO; 518 case IIO_CHAN_INFO_SAMP_FREQ: 519 i = mma8452_get_odr_index(data); 520 *val = mma8452_samp_freq[i][0]; 521 *val2 = mma8452_samp_freq[i][1]; 522 523 return IIO_VAL_INT_PLUS_MICRO; 524 case IIO_CHAN_INFO_CALIBBIAS: 525 ret = i2c_smbus_read_byte_data(data->client, 526 MMA8452_OFF_X + 527 chan->scan_index); 528 if (ret < 0) 529 return ret; 530 531 *val = sign_extend32(ret, 7); 532 533 return IIO_VAL_INT; 534 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 535 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) { 536 ret = mma8452_read_hp_filter(data, val, val2); 537 if (ret < 0) 538 return ret; 539 } else { 540 *val = 0; 541 *val2 = 0; 542 } 543 544 return IIO_VAL_INT_PLUS_MICRO; 545 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 546 ret = mma8452_get_power_mode(data); 547 if (ret < 0) 548 return ret; 549 550 i = mma8452_get_odr_index(data); 551 552 *val = mma8452_os_ratio[ret][i]; 553 return IIO_VAL_INT; 554 } 555 556 return -EINVAL; 557 } 558 559 static int mma8452_calculate_sleep(struct mma8452_data *data) 560 { 561 int ret, i = mma8452_get_odr_index(data); 562 563 if (mma8452_samp_freq[i][0] > 0) 564 ret = 1000 / mma8452_samp_freq[i][0]; 565 else 566 ret = 1000; 567 568 return ret == 0 ? 1 : ret; 569 } 570 571 static int mma8452_standby(struct mma8452_data *data) 572 { 573 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 574 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE); 575 } 576 577 static int mma8452_active(struct mma8452_data *data) 578 { 579 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 580 data->ctrl_reg1); 581 } 582 583 /* returns >0 if active, 0 if in standby and <0 on error */ 584 static int mma8452_is_active(struct mma8452_data *data) 585 { 586 int reg; 587 588 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1); 589 if (reg < 0) 590 return reg; 591 592 return reg & MMA8452_CTRL_ACTIVE; 593 } 594 595 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val) 596 { 597 int ret; 598 int is_active; 599 600 mutex_lock(&data->lock); 601 602 is_active = mma8452_is_active(data); 603 if (is_active < 0) { 604 ret = is_active; 605 goto fail; 606 } 607 608 /* config can only be changed when in standby */ 609 if (is_active > 0) { 610 ret = mma8452_standby(data); 611 if (ret < 0) 612 goto fail; 613 } 614 615 ret = i2c_smbus_write_byte_data(data->client, reg, val); 616 if (ret < 0) 617 goto fail; 618 619 if (is_active > 0) { 620 ret = mma8452_active(data); 621 if (ret < 0) 622 goto fail; 623 } 624 625 ret = 0; 626 fail: 627 mutex_unlock(&data->lock); 628 629 return ret; 630 } 631 632 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode) 633 { 634 int reg; 635 636 reg = i2c_smbus_read_byte_data(data->client, 637 MMA8452_CTRL_REG2); 638 if (reg < 0) 639 return reg; 640 641 reg &= ~MMA8452_CTRL_REG2_MODS_MASK; 642 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT; 643 644 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg); 645 } 646 647 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */ 648 static int mma8452_freefall_mode_enabled(struct mma8452_data *data) 649 { 650 int val; 651 652 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); 653 if (val < 0) 654 return val; 655 656 return !(val & MMA8452_FF_MT_CFG_OAE); 657 } 658 659 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state) 660 { 661 int val; 662 663 if ((state && mma8452_freefall_mode_enabled(data)) || 664 (!state && !(mma8452_freefall_mode_enabled(data)))) 665 return 0; 666 667 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); 668 if (val < 0) 669 return val; 670 671 if (state) { 672 val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); 673 val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); 674 val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); 675 val &= ~MMA8452_FF_MT_CFG_OAE; 676 } else { 677 val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); 678 val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); 679 val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); 680 val |= MMA8452_FF_MT_CFG_OAE; 681 } 682 683 return mma8452_change_config(data, MMA8452_FF_MT_CFG, val); 684 } 685 686 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data, 687 int val, int val2) 688 { 689 int i, reg; 690 691 i = mma8452_get_hp_filter_index(data, val, val2); 692 if (i < 0) 693 return i; 694 695 reg = i2c_smbus_read_byte_data(data->client, 696 MMA8452_HP_FILTER_CUTOFF); 697 if (reg < 0) 698 return reg; 699 700 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 701 reg |= i; 702 703 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg); 704 } 705 706 static int mma8452_write_raw(struct iio_dev *indio_dev, 707 struct iio_chan_spec const *chan, 708 int val, int val2, long mask) 709 { 710 struct mma8452_data *data = iio_priv(indio_dev); 711 int i, ret; 712 713 ret = iio_device_claim_direct_mode(indio_dev); 714 if (ret) 715 return ret; 716 717 switch (mask) { 718 case IIO_CHAN_INFO_SAMP_FREQ: 719 i = mma8452_get_samp_freq_index(data, val, val2); 720 if (i < 0) { 721 ret = i; 722 break; 723 } 724 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK; 725 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT; 726 727 data->sleep_val = mma8452_calculate_sleep(data); 728 729 ret = mma8452_change_config(data, MMA8452_CTRL_REG1, 730 data->ctrl_reg1); 731 break; 732 case IIO_CHAN_INFO_SCALE: 733 i = mma8452_get_scale_index(data, val, val2); 734 if (i < 0) { 735 ret = i; 736 break; 737 } 738 739 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK; 740 data->data_cfg |= i; 741 742 ret = mma8452_change_config(data, MMA8452_DATA_CFG, 743 data->data_cfg); 744 break; 745 case IIO_CHAN_INFO_CALIBBIAS: 746 if (val < -128 || val > 127) { 747 ret = -EINVAL; 748 break; 749 } 750 751 ret = mma8452_change_config(data, 752 MMA8452_OFF_X + chan->scan_index, 753 val); 754 break; 755 756 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 757 if (val == 0 && val2 == 0) { 758 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK; 759 } else { 760 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK; 761 ret = mma8452_set_hp_filter_frequency(data, val, val2); 762 if (ret < 0) 763 break; 764 } 765 766 ret = mma8452_change_config(data, MMA8452_DATA_CFG, 767 data->data_cfg); 768 break; 769 770 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 771 ret = mma8452_get_odr_index(data); 772 773 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) { 774 if (mma8452_os_ratio[i][ret] == val) { 775 ret = mma8452_set_power_mode(data, i); 776 break; 777 } 778 } 779 break; 780 default: 781 ret = -EINVAL; 782 break; 783 } 784 785 iio_device_release_direct_mode(indio_dev); 786 return ret; 787 } 788 789 static int mma8452_get_event_regs(struct mma8452_data *data, 790 const struct iio_chan_spec *chan, enum iio_event_direction dir, 791 const struct mma8452_event_regs **ev_reg) 792 { 793 if (!chan) 794 return -EINVAL; 795 796 switch (chan->type) { 797 case IIO_ACCEL: 798 switch (dir) { 799 case IIO_EV_DIR_RISING: 800 if ((data->chip_info->all_events 801 & MMA8452_INT_TRANS) && 802 (data->chip_info->enabled_events 803 & MMA8452_INT_TRANS)) 804 *ev_reg = &trans_ev_regs; 805 else 806 *ev_reg = &ff_mt_ev_regs; 807 return 0; 808 case IIO_EV_DIR_FALLING: 809 *ev_reg = &ff_mt_ev_regs; 810 return 0; 811 default: 812 return -EINVAL; 813 } 814 default: 815 return -EINVAL; 816 } 817 } 818 819 static int mma8452_read_event_value(struct iio_dev *indio_dev, 820 const struct iio_chan_spec *chan, 821 enum iio_event_type type, 822 enum iio_event_direction dir, 823 enum iio_event_info info, 824 int *val, int *val2) 825 { 826 struct mma8452_data *data = iio_priv(indio_dev); 827 int ret, us, power_mode; 828 const struct mma8452_event_regs *ev_regs; 829 830 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 831 if (ret) 832 return ret; 833 834 switch (info) { 835 case IIO_EV_INFO_VALUE: 836 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths); 837 if (ret < 0) 838 return ret; 839 840 *val = ret & ev_regs->ev_ths_mask; 841 842 return IIO_VAL_INT; 843 844 case IIO_EV_INFO_PERIOD: 845 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count); 846 if (ret < 0) 847 return ret; 848 849 power_mode = mma8452_get_power_mode(data); 850 if (power_mode < 0) 851 return power_mode; 852 853 us = ret * mma8452_time_step_us[power_mode][ 854 mma8452_get_odr_index(data)]; 855 *val = us / USEC_PER_SEC; 856 *val2 = us % USEC_PER_SEC; 857 858 return IIO_VAL_INT_PLUS_MICRO; 859 860 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 861 ret = i2c_smbus_read_byte_data(data->client, 862 MMA8452_TRANSIENT_CFG); 863 if (ret < 0) 864 return ret; 865 866 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) { 867 *val = 0; 868 *val2 = 0; 869 } else { 870 ret = mma8452_read_hp_filter(data, val, val2); 871 if (ret < 0) 872 return ret; 873 } 874 875 return IIO_VAL_INT_PLUS_MICRO; 876 877 default: 878 return -EINVAL; 879 } 880 } 881 882 static int mma8452_write_event_value(struct iio_dev *indio_dev, 883 const struct iio_chan_spec *chan, 884 enum iio_event_type type, 885 enum iio_event_direction dir, 886 enum iio_event_info info, 887 int val, int val2) 888 { 889 struct mma8452_data *data = iio_priv(indio_dev); 890 int ret, reg, steps; 891 const struct mma8452_event_regs *ev_regs; 892 893 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 894 if (ret) 895 return ret; 896 897 switch (info) { 898 case IIO_EV_INFO_VALUE: 899 if (val < 0 || val > ev_regs->ev_ths_mask) 900 return -EINVAL; 901 902 return mma8452_change_config(data, ev_regs->ev_ths, val); 903 904 case IIO_EV_INFO_PERIOD: 905 ret = mma8452_get_power_mode(data); 906 if (ret < 0) 907 return ret; 908 909 steps = (val * USEC_PER_SEC + val2) / 910 mma8452_time_step_us[ret][ 911 mma8452_get_odr_index(data)]; 912 913 if (steps < 0 || steps > 0xff) 914 return -EINVAL; 915 916 return mma8452_change_config(data, ev_regs->ev_count, steps); 917 918 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 919 reg = i2c_smbus_read_byte_data(data->client, 920 MMA8452_TRANSIENT_CFG); 921 if (reg < 0) 922 return reg; 923 924 if (val == 0 && val2 == 0) { 925 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP; 926 } else { 927 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP; 928 ret = mma8452_set_hp_filter_frequency(data, val, val2); 929 if (ret < 0) 930 return ret; 931 } 932 933 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg); 934 935 default: 936 return -EINVAL; 937 } 938 } 939 940 static int mma8452_read_event_config(struct iio_dev *indio_dev, 941 const struct iio_chan_spec *chan, 942 enum iio_event_type type, 943 enum iio_event_direction dir) 944 { 945 struct mma8452_data *data = iio_priv(indio_dev); 946 int ret; 947 const struct mma8452_event_regs *ev_regs; 948 949 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 950 if (ret) 951 return ret; 952 953 switch (dir) { 954 case IIO_EV_DIR_FALLING: 955 return mma8452_freefall_mode_enabled(data); 956 case IIO_EV_DIR_RISING: 957 ret = i2c_smbus_read_byte_data(data->client, 958 ev_regs->ev_cfg); 959 if (ret < 0) 960 return ret; 961 962 return !!(ret & BIT(chan->scan_index + 963 ev_regs->ev_cfg_chan_shift)); 964 default: 965 return -EINVAL; 966 } 967 } 968 969 static int mma8452_write_event_config(struct iio_dev *indio_dev, 970 const struct iio_chan_spec *chan, 971 enum iio_event_type type, 972 enum iio_event_direction dir, 973 int state) 974 { 975 struct mma8452_data *data = iio_priv(indio_dev); 976 int val, ret; 977 const struct mma8452_event_regs *ev_regs; 978 979 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 980 if (ret) 981 return ret; 982 983 ret = mma8452_set_runtime_pm_state(data->client, state); 984 if (ret) 985 return ret; 986 987 switch (dir) { 988 case IIO_EV_DIR_FALLING: 989 return mma8452_set_freefall_mode(data, state); 990 case IIO_EV_DIR_RISING: 991 val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg); 992 if (val < 0) 993 return val; 994 995 if (state) { 996 if (mma8452_freefall_mode_enabled(data)) { 997 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift); 998 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift); 999 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift); 1000 val |= MMA8452_FF_MT_CFG_OAE; 1001 } 1002 val |= BIT(chan->scan_index + 1003 ev_regs->ev_cfg_chan_shift); 1004 } else { 1005 if (mma8452_freefall_mode_enabled(data)) 1006 return 0; 1007 1008 val &= ~BIT(chan->scan_index + 1009 ev_regs->ev_cfg_chan_shift); 1010 } 1011 1012 val |= ev_regs->ev_cfg_ele; 1013 1014 return mma8452_change_config(data, ev_regs->ev_cfg, val); 1015 default: 1016 return -EINVAL; 1017 } 1018 } 1019 1020 static void mma8452_transient_interrupt(struct iio_dev *indio_dev) 1021 { 1022 struct mma8452_data *data = iio_priv(indio_dev); 1023 s64 ts = iio_get_time_ns(indio_dev); 1024 int src; 1025 1026 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC); 1027 if (src < 0) 1028 return; 1029 1030 if (src & MMA8452_TRANSIENT_SRC_XTRANSE) 1031 iio_push_event(indio_dev, 1032 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1033 IIO_EV_TYPE_MAG, 1034 IIO_EV_DIR_RISING), 1035 ts); 1036 1037 if (src & MMA8452_TRANSIENT_SRC_YTRANSE) 1038 iio_push_event(indio_dev, 1039 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y, 1040 IIO_EV_TYPE_MAG, 1041 IIO_EV_DIR_RISING), 1042 ts); 1043 1044 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE) 1045 iio_push_event(indio_dev, 1046 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z, 1047 IIO_EV_TYPE_MAG, 1048 IIO_EV_DIR_RISING), 1049 ts); 1050 } 1051 1052 static irqreturn_t mma8452_interrupt(int irq, void *p) 1053 { 1054 struct iio_dev *indio_dev = p; 1055 struct mma8452_data *data = iio_priv(indio_dev); 1056 irqreturn_t ret = IRQ_NONE; 1057 int src; 1058 1059 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC); 1060 if (src < 0) 1061 return IRQ_NONE; 1062 1063 if (!(src & (data->chip_info->enabled_events | MMA8452_INT_DRDY))) 1064 return IRQ_NONE; 1065 1066 if (src & MMA8452_INT_DRDY) { 1067 iio_trigger_poll_chained(indio_dev->trig); 1068 ret = IRQ_HANDLED; 1069 } 1070 1071 if (src & MMA8452_INT_FF_MT) { 1072 if (mma8452_freefall_mode_enabled(data)) { 1073 s64 ts = iio_get_time_ns(indio_dev); 1074 1075 iio_push_event(indio_dev, 1076 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 1077 IIO_MOD_X_AND_Y_AND_Z, 1078 IIO_EV_TYPE_MAG, 1079 IIO_EV_DIR_FALLING), 1080 ts); 1081 } 1082 ret = IRQ_HANDLED; 1083 } 1084 1085 if (src & MMA8452_INT_TRANS) { 1086 mma8452_transient_interrupt(indio_dev); 1087 ret = IRQ_HANDLED; 1088 } 1089 1090 return ret; 1091 } 1092 1093 static irqreturn_t mma8452_trigger_handler(int irq, void *p) 1094 { 1095 struct iio_poll_func *pf = p; 1096 struct iio_dev *indio_dev = pf->indio_dev; 1097 struct mma8452_data *data = iio_priv(indio_dev); 1098 int ret; 1099 1100 ret = mma8452_read(data, data->buffer.channels); 1101 if (ret < 0) 1102 goto done; 1103 1104 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer, 1105 iio_get_time_ns(indio_dev)); 1106 1107 done: 1108 iio_trigger_notify_done(indio_dev->trig); 1109 1110 return IRQ_HANDLED; 1111 } 1112 1113 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev, 1114 unsigned int reg, unsigned int writeval, 1115 unsigned int *readval) 1116 { 1117 int ret; 1118 struct mma8452_data *data = iio_priv(indio_dev); 1119 1120 if (reg > MMA8452_MAX_REG) 1121 return -EINVAL; 1122 1123 if (!readval) 1124 return mma8452_change_config(data, reg, writeval); 1125 1126 ret = i2c_smbus_read_byte_data(data->client, reg); 1127 if (ret < 0) 1128 return ret; 1129 1130 *readval = ret; 1131 1132 return 0; 1133 } 1134 1135 static const struct iio_event_spec mma8452_freefall_event[] = { 1136 { 1137 .type = IIO_EV_TYPE_MAG, 1138 .dir = IIO_EV_DIR_FALLING, 1139 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1140 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1141 BIT(IIO_EV_INFO_PERIOD) | 1142 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1143 }, 1144 }; 1145 1146 static const struct iio_event_spec mma8652_freefall_event[] = { 1147 { 1148 .type = IIO_EV_TYPE_MAG, 1149 .dir = IIO_EV_DIR_FALLING, 1150 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1151 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1152 BIT(IIO_EV_INFO_PERIOD) 1153 }, 1154 }; 1155 1156 static const struct iio_event_spec mma8452_transient_event[] = { 1157 { 1158 .type = IIO_EV_TYPE_MAG, 1159 .dir = IIO_EV_DIR_RISING, 1160 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1161 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1162 BIT(IIO_EV_INFO_PERIOD) | 1163 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1164 }, 1165 }; 1166 1167 static const struct iio_event_spec mma8452_motion_event[] = { 1168 { 1169 .type = IIO_EV_TYPE_MAG, 1170 .dir = IIO_EV_DIR_RISING, 1171 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1172 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1173 BIT(IIO_EV_INFO_PERIOD) 1174 }, 1175 }; 1176 1177 /* 1178 * Threshold is configured in fixed 8G/127 steps regardless of 1179 * currently selected scale for measurement. 1180 */ 1181 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742"); 1182 1183 static struct attribute *mma8452_event_attributes[] = { 1184 &iio_const_attr_accel_transient_scale.dev_attr.attr, 1185 NULL, 1186 }; 1187 1188 static const struct attribute_group mma8452_event_attribute_group = { 1189 .attrs = mma8452_event_attributes, 1190 }; 1191 1192 #define MMA8452_FREEFALL_CHANNEL(modifier) { \ 1193 .type = IIO_ACCEL, \ 1194 .modified = 1, \ 1195 .channel2 = modifier, \ 1196 .scan_index = -1, \ 1197 .event_spec = mma8452_freefall_event, \ 1198 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \ 1199 } 1200 1201 #define MMA8652_FREEFALL_CHANNEL(modifier) { \ 1202 .type = IIO_ACCEL, \ 1203 .modified = 1, \ 1204 .channel2 = modifier, \ 1205 .scan_index = -1, \ 1206 .event_spec = mma8652_freefall_event, \ 1207 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \ 1208 } 1209 1210 #define MMA8452_CHANNEL(axis, idx, bits) { \ 1211 .type = IIO_ACCEL, \ 1212 .modified = 1, \ 1213 .channel2 = IIO_MOD_##axis, \ 1214 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1215 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1216 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1217 BIT(IIO_CHAN_INFO_SCALE) | \ 1218 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \ 1219 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1220 .scan_index = idx, \ 1221 .scan_type = { \ 1222 .sign = 's', \ 1223 .realbits = (bits), \ 1224 .storagebits = 16, \ 1225 .shift = 16 - (bits), \ 1226 .endianness = IIO_BE, \ 1227 }, \ 1228 .event_spec = mma8452_transient_event, \ 1229 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \ 1230 } 1231 1232 #define MMA8652_CHANNEL(axis, idx, bits) { \ 1233 .type = IIO_ACCEL, \ 1234 .modified = 1, \ 1235 .channel2 = IIO_MOD_##axis, \ 1236 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1237 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1238 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1239 BIT(IIO_CHAN_INFO_SCALE) | \ 1240 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1241 .scan_index = idx, \ 1242 .scan_type = { \ 1243 .sign = 's', \ 1244 .realbits = (bits), \ 1245 .storagebits = 16, \ 1246 .shift = 16 - (bits), \ 1247 .endianness = IIO_BE, \ 1248 }, \ 1249 .event_spec = mma8452_motion_event, \ 1250 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \ 1251 } 1252 1253 static const struct iio_chan_spec mma8451_channels[] = { 1254 MMA8452_CHANNEL(X, idx_x, 14), 1255 MMA8452_CHANNEL(Y, idx_y, 14), 1256 MMA8452_CHANNEL(Z, idx_z, 14), 1257 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1258 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1259 }; 1260 1261 static const struct iio_chan_spec mma8452_channels[] = { 1262 MMA8452_CHANNEL(X, idx_x, 12), 1263 MMA8452_CHANNEL(Y, idx_y, 12), 1264 MMA8452_CHANNEL(Z, idx_z, 12), 1265 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1266 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1267 }; 1268 1269 static const struct iio_chan_spec mma8453_channels[] = { 1270 MMA8452_CHANNEL(X, idx_x, 10), 1271 MMA8452_CHANNEL(Y, idx_y, 10), 1272 MMA8452_CHANNEL(Z, idx_z, 10), 1273 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1274 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1275 }; 1276 1277 static const struct iio_chan_spec mma8652_channels[] = { 1278 MMA8652_CHANNEL(X, idx_x, 12), 1279 MMA8652_CHANNEL(Y, idx_y, 12), 1280 MMA8652_CHANNEL(Z, idx_z, 12), 1281 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1282 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1283 }; 1284 1285 static const struct iio_chan_spec mma8653_channels[] = { 1286 MMA8652_CHANNEL(X, idx_x, 10), 1287 MMA8652_CHANNEL(Y, idx_y, 10), 1288 MMA8652_CHANNEL(Z, idx_z, 10), 1289 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1290 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1291 }; 1292 1293 enum { 1294 mma8451, 1295 mma8452, 1296 mma8453, 1297 mma8652, 1298 mma8653, 1299 fxls8471, 1300 }; 1301 1302 static const struct mma_chip_info mma_chip_info_table[] = { 1303 [mma8451] = { 1304 .chip_id = MMA8451_DEVICE_ID, 1305 .channels = mma8451_channels, 1306 .num_channels = ARRAY_SIZE(mma8451_channels), 1307 /* 1308 * Hardware has fullscale of -2G, -4G, -8G corresponding to 1309 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10 1310 * bit. 1311 * The userspace interface uses m/s^2 and we declare micro units 1312 * So scale factor for 12 bit here is given by: 1313 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665 1314 */ 1315 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1316 /* 1317 * Although we enable the interrupt sources once and for 1318 * all here the event detection itself is not enabled until 1319 * userspace asks for it by mma8452_write_event_config() 1320 */ 1321 .all_events = MMA8452_INT_DRDY | 1322 MMA8452_INT_TRANS | 1323 MMA8452_INT_FF_MT, 1324 .enabled_events = MMA8452_INT_TRANS | 1325 MMA8452_INT_FF_MT, 1326 }, 1327 [mma8452] = { 1328 .chip_id = MMA8452_DEVICE_ID, 1329 .channels = mma8452_channels, 1330 .num_channels = ARRAY_SIZE(mma8452_channels), 1331 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1332 /* 1333 * Although we enable the interrupt sources once and for 1334 * all here the event detection itself is not enabled until 1335 * userspace asks for it by mma8452_write_event_config() 1336 */ 1337 .all_events = MMA8452_INT_DRDY | 1338 MMA8452_INT_TRANS | 1339 MMA8452_INT_FF_MT, 1340 .enabled_events = MMA8452_INT_TRANS | 1341 MMA8452_INT_FF_MT, 1342 }, 1343 [mma8453] = { 1344 .chip_id = MMA8453_DEVICE_ID, 1345 .channels = mma8453_channels, 1346 .num_channels = ARRAY_SIZE(mma8453_channels), 1347 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1348 /* 1349 * Although we enable the interrupt sources once and for 1350 * all here the event detection itself is not enabled until 1351 * userspace asks for it by mma8452_write_event_config() 1352 */ 1353 .all_events = MMA8452_INT_DRDY | 1354 MMA8452_INT_TRANS | 1355 MMA8452_INT_FF_MT, 1356 .enabled_events = MMA8452_INT_TRANS | 1357 MMA8452_INT_FF_MT, 1358 }, 1359 [mma8652] = { 1360 .chip_id = MMA8652_DEVICE_ID, 1361 .channels = mma8652_channels, 1362 .num_channels = ARRAY_SIZE(mma8652_channels), 1363 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1364 .all_events = MMA8452_INT_DRDY | 1365 MMA8452_INT_FF_MT, 1366 .enabled_events = MMA8452_INT_FF_MT, 1367 }, 1368 [mma8653] = { 1369 .chip_id = MMA8653_DEVICE_ID, 1370 .channels = mma8653_channels, 1371 .num_channels = ARRAY_SIZE(mma8653_channels), 1372 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1373 /* 1374 * Although we enable the interrupt sources once and for 1375 * all here the event detection itself is not enabled until 1376 * userspace asks for it by mma8452_write_event_config() 1377 */ 1378 .all_events = MMA8452_INT_DRDY | 1379 MMA8452_INT_FF_MT, 1380 .enabled_events = MMA8452_INT_FF_MT, 1381 }, 1382 [fxls8471] = { 1383 .chip_id = FXLS8471_DEVICE_ID, 1384 .channels = mma8451_channels, 1385 .num_channels = ARRAY_SIZE(mma8451_channels), 1386 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1387 /* 1388 * Although we enable the interrupt sources once and for 1389 * all here the event detection itself is not enabled until 1390 * userspace asks for it by mma8452_write_event_config() 1391 */ 1392 .all_events = MMA8452_INT_DRDY | 1393 MMA8452_INT_TRANS | 1394 MMA8452_INT_FF_MT, 1395 .enabled_events = MMA8452_INT_TRANS | 1396 MMA8452_INT_FF_MT, 1397 }, 1398 }; 1399 1400 static struct attribute *mma8452_attributes[] = { 1401 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1402 &iio_dev_attr_in_accel_scale_available.dev_attr.attr, 1403 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr, 1404 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr, 1405 NULL 1406 }; 1407 1408 static const struct attribute_group mma8452_group = { 1409 .attrs = mma8452_attributes, 1410 }; 1411 1412 static const struct iio_info mma8452_info = { 1413 .attrs = &mma8452_group, 1414 .read_raw = &mma8452_read_raw, 1415 .write_raw = &mma8452_write_raw, 1416 .event_attrs = &mma8452_event_attribute_group, 1417 .read_event_value = &mma8452_read_event_value, 1418 .write_event_value = &mma8452_write_event_value, 1419 .read_event_config = &mma8452_read_event_config, 1420 .write_event_config = &mma8452_write_event_config, 1421 .debugfs_reg_access = &mma8452_reg_access_dbg, 1422 }; 1423 1424 static const unsigned long mma8452_scan_masks[] = {0x7, 0}; 1425 1426 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig, 1427 bool state) 1428 { 1429 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1430 struct mma8452_data *data = iio_priv(indio_dev); 1431 int reg, ret; 1432 1433 ret = mma8452_set_runtime_pm_state(data->client, state); 1434 if (ret) 1435 return ret; 1436 1437 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4); 1438 if (reg < 0) 1439 return reg; 1440 1441 if (state) 1442 reg |= MMA8452_INT_DRDY; 1443 else 1444 reg &= ~MMA8452_INT_DRDY; 1445 1446 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg); 1447 } 1448 1449 static const struct iio_trigger_ops mma8452_trigger_ops = { 1450 .set_trigger_state = mma8452_data_rdy_trigger_set_state, 1451 .validate_device = iio_trigger_validate_own_device, 1452 }; 1453 1454 static int mma8452_trigger_setup(struct iio_dev *indio_dev) 1455 { 1456 struct mma8452_data *data = iio_priv(indio_dev); 1457 struct iio_trigger *trig; 1458 int ret; 1459 1460 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d", 1461 indio_dev->name, 1462 iio_device_id(indio_dev)); 1463 if (!trig) 1464 return -ENOMEM; 1465 1466 trig->ops = &mma8452_trigger_ops; 1467 iio_trigger_set_drvdata(trig, indio_dev); 1468 1469 ret = iio_trigger_register(trig); 1470 if (ret) 1471 return ret; 1472 1473 indio_dev->trig = iio_trigger_get(trig); 1474 1475 return 0; 1476 } 1477 1478 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev) 1479 { 1480 if (indio_dev->trig) 1481 iio_trigger_unregister(indio_dev->trig); 1482 } 1483 1484 static int mma8452_reset(struct i2c_client *client) 1485 { 1486 int i; 1487 int ret; 1488 1489 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2, 1490 MMA8452_CTRL_REG2_RST); 1491 if (ret < 0) 1492 return ret; 1493 1494 for (i = 0; i < 10; i++) { 1495 usleep_range(100, 200); 1496 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2); 1497 if (ret == -EIO) 1498 continue; /* I2C comm reset */ 1499 if (ret < 0) 1500 return ret; 1501 if (!(ret & MMA8452_CTRL_REG2_RST)) 1502 return 0; 1503 } 1504 1505 return -ETIMEDOUT; 1506 } 1507 1508 static const struct of_device_id mma8452_dt_ids[] = { 1509 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] }, 1510 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] }, 1511 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] }, 1512 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] }, 1513 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] }, 1514 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] }, 1515 { } 1516 }; 1517 MODULE_DEVICE_TABLE(of, mma8452_dt_ids); 1518 1519 static int mma8452_probe(struct i2c_client *client, 1520 const struct i2c_device_id *id) 1521 { 1522 struct mma8452_data *data; 1523 struct iio_dev *indio_dev; 1524 int ret; 1525 const struct of_device_id *match; 1526 1527 match = of_match_device(mma8452_dt_ids, &client->dev); 1528 if (!match) { 1529 dev_err(&client->dev, "unknown device model\n"); 1530 return -ENODEV; 1531 } 1532 1533 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 1534 if (!indio_dev) 1535 return -ENOMEM; 1536 1537 data = iio_priv(indio_dev); 1538 data->client = client; 1539 mutex_init(&data->lock); 1540 data->chip_info = match->data; 1541 1542 data->vdd_reg = devm_regulator_get(&client->dev, "vdd"); 1543 if (IS_ERR(data->vdd_reg)) 1544 return dev_err_probe(&client->dev, PTR_ERR(data->vdd_reg), 1545 "failed to get VDD regulator!\n"); 1546 1547 data->vddio_reg = devm_regulator_get(&client->dev, "vddio"); 1548 if (IS_ERR(data->vddio_reg)) 1549 return dev_err_probe(&client->dev, PTR_ERR(data->vddio_reg), 1550 "failed to get VDDIO regulator!\n"); 1551 1552 ret = regulator_enable(data->vdd_reg); 1553 if (ret) { 1554 dev_err(&client->dev, "failed to enable VDD regulator!\n"); 1555 return ret; 1556 } 1557 1558 ret = regulator_enable(data->vddio_reg); 1559 if (ret) { 1560 dev_err(&client->dev, "failed to enable VDDIO regulator!\n"); 1561 goto disable_regulator_vdd; 1562 } 1563 1564 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I); 1565 if (ret < 0) 1566 goto disable_regulators; 1567 1568 switch (ret) { 1569 case MMA8451_DEVICE_ID: 1570 case MMA8452_DEVICE_ID: 1571 case MMA8453_DEVICE_ID: 1572 case MMA8652_DEVICE_ID: 1573 case MMA8653_DEVICE_ID: 1574 case FXLS8471_DEVICE_ID: 1575 if (ret == data->chip_info->chip_id) 1576 break; 1577 fallthrough; 1578 default: 1579 ret = -ENODEV; 1580 goto disable_regulators; 1581 } 1582 1583 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n", 1584 match->compatible, data->chip_info->chip_id); 1585 1586 i2c_set_clientdata(client, indio_dev); 1587 indio_dev->info = &mma8452_info; 1588 indio_dev->name = id->name; 1589 indio_dev->modes = INDIO_DIRECT_MODE; 1590 indio_dev->channels = data->chip_info->channels; 1591 indio_dev->num_channels = data->chip_info->num_channels; 1592 indio_dev->available_scan_masks = mma8452_scan_masks; 1593 1594 ret = mma8452_reset(client); 1595 if (ret < 0) 1596 goto disable_regulators; 1597 1598 data->data_cfg = MMA8452_DATA_CFG_FS_2G; 1599 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG, 1600 data->data_cfg); 1601 if (ret < 0) 1602 goto disable_regulators; 1603 1604 /* 1605 * By default set transient threshold to max to avoid events if 1606 * enabling without configuring threshold. 1607 */ 1608 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS, 1609 MMA8452_TRANSIENT_THS_MASK); 1610 if (ret < 0) 1611 goto disable_regulators; 1612 1613 if (client->irq) { 1614 int irq2; 1615 1616 irq2 = of_irq_get_byname(client->dev.of_node, "INT2"); 1617 1618 if (irq2 == client->irq) { 1619 dev_dbg(&client->dev, "using interrupt line INT2\n"); 1620 } else { 1621 ret = i2c_smbus_write_byte_data(client, 1622 MMA8452_CTRL_REG5, 1623 data->chip_info->all_events); 1624 if (ret < 0) 1625 goto disable_regulators; 1626 1627 dev_dbg(&client->dev, "using interrupt line INT1\n"); 1628 } 1629 1630 ret = i2c_smbus_write_byte_data(client, 1631 MMA8452_CTRL_REG4, 1632 data->chip_info->enabled_events); 1633 if (ret < 0) 1634 goto disable_regulators; 1635 1636 ret = mma8452_trigger_setup(indio_dev); 1637 if (ret < 0) 1638 goto disable_regulators; 1639 } 1640 1641 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE | 1642 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT); 1643 1644 data->sleep_val = mma8452_calculate_sleep(data); 1645 1646 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1, 1647 data->ctrl_reg1); 1648 if (ret < 0) 1649 goto trigger_cleanup; 1650 1651 ret = iio_triggered_buffer_setup(indio_dev, NULL, 1652 mma8452_trigger_handler, NULL); 1653 if (ret < 0) 1654 goto trigger_cleanup; 1655 1656 if (client->irq) { 1657 ret = devm_request_threaded_irq(&client->dev, 1658 client->irq, 1659 NULL, mma8452_interrupt, 1660 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1661 client->name, indio_dev); 1662 if (ret) 1663 goto buffer_cleanup; 1664 } 1665 1666 ret = pm_runtime_set_active(&client->dev); 1667 if (ret < 0) 1668 goto buffer_cleanup; 1669 1670 pm_runtime_enable(&client->dev); 1671 pm_runtime_set_autosuspend_delay(&client->dev, 1672 MMA8452_AUTO_SUSPEND_DELAY_MS); 1673 pm_runtime_use_autosuspend(&client->dev); 1674 1675 ret = iio_device_register(indio_dev); 1676 if (ret < 0) 1677 goto buffer_cleanup; 1678 1679 ret = mma8452_set_freefall_mode(data, false); 1680 if (ret < 0) 1681 goto unregister_device; 1682 1683 return 0; 1684 1685 unregister_device: 1686 iio_device_unregister(indio_dev); 1687 1688 buffer_cleanup: 1689 iio_triggered_buffer_cleanup(indio_dev); 1690 1691 trigger_cleanup: 1692 mma8452_trigger_cleanup(indio_dev); 1693 1694 disable_regulators: 1695 regulator_disable(data->vddio_reg); 1696 1697 disable_regulator_vdd: 1698 regulator_disable(data->vdd_reg); 1699 1700 return ret; 1701 } 1702 1703 static int mma8452_remove(struct i2c_client *client) 1704 { 1705 struct iio_dev *indio_dev = i2c_get_clientdata(client); 1706 struct mma8452_data *data = iio_priv(indio_dev); 1707 1708 iio_device_unregister(indio_dev); 1709 1710 pm_runtime_disable(&client->dev); 1711 pm_runtime_set_suspended(&client->dev); 1712 1713 iio_triggered_buffer_cleanup(indio_dev); 1714 mma8452_trigger_cleanup(indio_dev); 1715 mma8452_standby(iio_priv(indio_dev)); 1716 1717 regulator_disable(data->vddio_reg); 1718 regulator_disable(data->vdd_reg); 1719 1720 return 0; 1721 } 1722 1723 #ifdef CONFIG_PM 1724 static int mma8452_runtime_suspend(struct device *dev) 1725 { 1726 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1727 struct mma8452_data *data = iio_priv(indio_dev); 1728 int ret; 1729 1730 mutex_lock(&data->lock); 1731 ret = mma8452_standby(data); 1732 mutex_unlock(&data->lock); 1733 if (ret < 0) { 1734 dev_err(&data->client->dev, "powering off device failed\n"); 1735 return -EAGAIN; 1736 } 1737 1738 ret = regulator_disable(data->vddio_reg); 1739 if (ret) { 1740 dev_err(dev, "failed to disable VDDIO regulator\n"); 1741 return ret; 1742 } 1743 1744 ret = regulator_disable(data->vdd_reg); 1745 if (ret) { 1746 dev_err(dev, "failed to disable VDD regulator\n"); 1747 return ret; 1748 } 1749 1750 return 0; 1751 } 1752 1753 static int mma8452_runtime_resume(struct device *dev) 1754 { 1755 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1756 struct mma8452_data *data = iio_priv(indio_dev); 1757 int ret, sleep_val; 1758 1759 ret = regulator_enable(data->vdd_reg); 1760 if (ret) { 1761 dev_err(dev, "failed to enable VDD regulator\n"); 1762 return ret; 1763 } 1764 1765 ret = regulator_enable(data->vddio_reg); 1766 if (ret) { 1767 dev_err(dev, "failed to enable VDDIO regulator\n"); 1768 regulator_disable(data->vdd_reg); 1769 return ret; 1770 } 1771 1772 ret = mma8452_active(data); 1773 if (ret < 0) 1774 goto runtime_resume_failed; 1775 1776 ret = mma8452_get_odr_index(data); 1777 sleep_val = 1000 / mma8452_samp_freq[ret][0]; 1778 if (sleep_val < 20) 1779 usleep_range(sleep_val * 1000, 20000); 1780 else 1781 msleep_interruptible(sleep_val); 1782 1783 return 0; 1784 1785 runtime_resume_failed: 1786 regulator_disable(data->vddio_reg); 1787 regulator_disable(data->vdd_reg); 1788 1789 return ret; 1790 } 1791 #endif 1792 1793 static const struct dev_pm_ops mma8452_pm_ops = { 1794 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume) 1795 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend, 1796 mma8452_runtime_resume, NULL) 1797 }; 1798 1799 static const struct i2c_device_id mma8452_id[] = { 1800 { "mma8451", mma8451 }, 1801 { "mma8452", mma8452 }, 1802 { "mma8453", mma8453 }, 1803 { "mma8652", mma8652 }, 1804 { "mma8653", mma8653 }, 1805 { "fxls8471", fxls8471 }, 1806 { } 1807 }; 1808 MODULE_DEVICE_TABLE(i2c, mma8452_id); 1809 1810 static struct i2c_driver mma8452_driver = { 1811 .driver = { 1812 .name = "mma8452", 1813 .of_match_table = of_match_ptr(mma8452_dt_ids), 1814 .pm = &mma8452_pm_ops, 1815 }, 1816 .probe = mma8452_probe, 1817 .remove = mma8452_remove, 1818 .id_table = mma8452_id, 1819 }; 1820 module_i2c_driver(mma8452_driver); 1821 1822 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>"); 1823 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver"); 1824 MODULE_LICENSE("GPL"); 1825