1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers: 4 * 5 * device name digital output 7-bit I2C slave address (pin selectable) 6 * --------------------------------------------------------------------- 7 * MMA8451Q 14 bit 0x1c / 0x1d 8 * MMA8452Q 12 bit 0x1c / 0x1d 9 * MMA8453Q 10 bit 0x1c / 0x1d 10 * MMA8652FC 12 bit 0x1d 11 * MMA8653FC 10 bit 0x1d 12 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f 13 * 14 * Copyright 2015 Martin Kepplinger <martink@posteo.de> 15 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net> 16 * 17 * 18 * TODO: orientation events 19 */ 20 21 #include <linux/module.h> 22 #include <linux/i2c.h> 23 #include <linux/iio/iio.h> 24 #include <linux/iio/sysfs.h> 25 #include <linux/iio/buffer.h> 26 #include <linux/iio/trigger.h> 27 #include <linux/iio/trigger_consumer.h> 28 #include <linux/iio/triggered_buffer.h> 29 #include <linux/iio/events.h> 30 #include <linux/delay.h> 31 #include <linux/of_device.h> 32 #include <linux/of_irq.h> 33 #include <linux/pm_runtime.h> 34 35 #define MMA8452_STATUS 0x00 36 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0)) 37 #define MMA8452_OUT_X 0x01 /* MSB first */ 38 #define MMA8452_OUT_Y 0x03 39 #define MMA8452_OUT_Z 0x05 40 #define MMA8452_INT_SRC 0x0c 41 #define MMA8452_WHO_AM_I 0x0d 42 #define MMA8452_DATA_CFG 0x0e 43 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0) 44 #define MMA8452_DATA_CFG_FS_2G 0 45 #define MMA8452_DATA_CFG_FS_4G 1 46 #define MMA8452_DATA_CFG_FS_8G 2 47 #define MMA8452_DATA_CFG_HPF_MASK BIT(4) 48 #define MMA8452_HP_FILTER_CUTOFF 0x0f 49 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0) 50 #define MMA8452_FF_MT_CFG 0x15 51 #define MMA8452_FF_MT_CFG_OAE BIT(6) 52 #define MMA8452_FF_MT_CFG_ELE BIT(7) 53 #define MMA8452_FF_MT_SRC 0x16 54 #define MMA8452_FF_MT_SRC_XHE BIT(1) 55 #define MMA8452_FF_MT_SRC_YHE BIT(3) 56 #define MMA8452_FF_MT_SRC_ZHE BIT(5) 57 #define MMA8452_FF_MT_THS 0x17 58 #define MMA8452_FF_MT_THS_MASK 0x7f 59 #define MMA8452_FF_MT_COUNT 0x18 60 #define MMA8452_FF_MT_CHAN_SHIFT 3 61 #define MMA8452_TRANSIENT_CFG 0x1d 62 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1) 63 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0) 64 #define MMA8452_TRANSIENT_CFG_ELE BIT(4) 65 #define MMA8452_TRANSIENT_SRC 0x1e 66 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1) 67 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3) 68 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5) 69 #define MMA8452_TRANSIENT_THS 0x1f 70 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0) 71 #define MMA8452_TRANSIENT_COUNT 0x20 72 #define MMA8452_TRANSIENT_CHAN_SHIFT 1 73 #define MMA8452_CTRL_REG1 0x2a 74 #define MMA8452_CTRL_ACTIVE BIT(0) 75 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3) 76 #define MMA8452_CTRL_DR_SHIFT 3 77 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */ 78 #define MMA8452_CTRL_REG2 0x2b 79 #define MMA8452_CTRL_REG2_RST BIT(6) 80 #define MMA8452_CTRL_REG2_MODS_SHIFT 3 81 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b 82 #define MMA8452_CTRL_REG4 0x2d 83 #define MMA8452_CTRL_REG5 0x2e 84 #define MMA8452_OFF_X 0x2f 85 #define MMA8452_OFF_Y 0x30 86 #define MMA8452_OFF_Z 0x31 87 88 #define MMA8452_MAX_REG 0x31 89 90 #define MMA8452_INT_DRDY BIT(0) 91 #define MMA8452_INT_FF_MT BIT(2) 92 #define MMA8452_INT_TRANS BIT(5) 93 94 #define MMA8451_DEVICE_ID 0x1a 95 #define MMA8452_DEVICE_ID 0x2a 96 #define MMA8453_DEVICE_ID 0x3a 97 #define MMA8652_DEVICE_ID 0x4a 98 #define MMA8653_DEVICE_ID 0x5a 99 #define FXLS8471_DEVICE_ID 0x6a 100 101 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000 102 103 struct mma8452_data { 104 struct i2c_client *client; 105 struct mutex lock; 106 u8 ctrl_reg1; 107 u8 data_cfg; 108 const struct mma_chip_info *chip_info; 109 int sleep_val; 110 }; 111 112 /** 113 * struct mma8452_event_regs - chip specific data related to events 114 * @ev_cfg: event config register address 115 * @ev_cfg_ele: latch bit in event config register 116 * @ev_cfg_chan_shift: number of the bit to enable events in X 117 * direction; in event config register 118 * @ev_src: event source register address 119 * @ev_ths: event threshold register address 120 * @ev_ths_mask: mask for the threshold value 121 * @ev_count: event count (period) register address 122 * 123 * Since not all chips supported by the driver support comparing high pass 124 * filtered data for events (interrupts), different interrupt sources are 125 * used for different chips and the relevant registers are included here. 126 */ 127 struct mma8452_event_regs { 128 u8 ev_cfg; 129 u8 ev_cfg_ele; 130 u8 ev_cfg_chan_shift; 131 u8 ev_src; 132 u8 ev_ths; 133 u8 ev_ths_mask; 134 u8 ev_count; 135 }; 136 137 static const struct mma8452_event_regs ff_mt_ev_regs = { 138 .ev_cfg = MMA8452_FF_MT_CFG, 139 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE, 140 .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT, 141 .ev_src = MMA8452_FF_MT_SRC, 142 .ev_ths = MMA8452_FF_MT_THS, 143 .ev_ths_mask = MMA8452_FF_MT_THS_MASK, 144 .ev_count = MMA8452_FF_MT_COUNT 145 }; 146 147 static const struct mma8452_event_regs trans_ev_regs = { 148 .ev_cfg = MMA8452_TRANSIENT_CFG, 149 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE, 150 .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT, 151 .ev_src = MMA8452_TRANSIENT_SRC, 152 .ev_ths = MMA8452_TRANSIENT_THS, 153 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK, 154 .ev_count = MMA8452_TRANSIENT_COUNT, 155 }; 156 157 /** 158 * struct mma_chip_info - chip specific data 159 * @chip_id: WHO_AM_I register's value 160 * @channels: struct iio_chan_spec matching the device's 161 * capabilities 162 * @num_channels: number of channels 163 * @mma_scales: scale factors for converting register values 164 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers 165 * per mode: m/s^2 and micro m/s^2 166 * @all_events: all events supported by this chip 167 * @enabled_events: event flags enabled and handled by this driver 168 */ 169 struct mma_chip_info { 170 u8 chip_id; 171 const struct iio_chan_spec *channels; 172 int num_channels; 173 const int mma_scales[3][2]; 174 int all_events; 175 int enabled_events; 176 }; 177 178 enum { 179 idx_x, 180 idx_y, 181 idx_z, 182 idx_ts, 183 }; 184 185 static int mma8452_drdy(struct mma8452_data *data) 186 { 187 int tries = 150; 188 189 while (tries-- > 0) { 190 int ret = i2c_smbus_read_byte_data(data->client, 191 MMA8452_STATUS); 192 if (ret < 0) 193 return ret; 194 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY) 195 return 0; 196 197 if (data->sleep_val <= 20) 198 usleep_range(data->sleep_val * 250, 199 data->sleep_val * 500); 200 else 201 msleep(20); 202 } 203 204 dev_err(&data->client->dev, "data not ready\n"); 205 206 return -EIO; 207 } 208 209 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on) 210 { 211 #ifdef CONFIG_PM 212 int ret; 213 214 if (on) { 215 ret = pm_runtime_get_sync(&client->dev); 216 } else { 217 pm_runtime_mark_last_busy(&client->dev); 218 ret = pm_runtime_put_autosuspend(&client->dev); 219 } 220 221 if (ret < 0) { 222 dev_err(&client->dev, 223 "failed to change power state to %d\n", on); 224 if (on) 225 pm_runtime_put_noidle(&client->dev); 226 227 return ret; 228 } 229 #endif 230 231 return 0; 232 } 233 234 static int mma8452_read(struct mma8452_data *data, __be16 buf[3]) 235 { 236 int ret = mma8452_drdy(data); 237 238 if (ret < 0) 239 return ret; 240 241 ret = mma8452_set_runtime_pm_state(data->client, true); 242 if (ret) 243 return ret; 244 245 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X, 246 3 * sizeof(__be16), (u8 *)buf); 247 248 ret = mma8452_set_runtime_pm_state(data->client, false); 249 250 return ret; 251 } 252 253 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2], 254 int n) 255 { 256 size_t len = 0; 257 258 while (n-- > 0) 259 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ", 260 vals[n][0], vals[n][1]); 261 262 /* replace trailing space by newline */ 263 buf[len - 1] = '\n'; 264 265 return len; 266 } 267 268 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n, 269 int val, int val2) 270 { 271 while (n-- > 0) 272 if (val == vals[n][0] && val2 == vals[n][1]) 273 return n; 274 275 return -EINVAL; 276 } 277 278 static unsigned int mma8452_get_odr_index(struct mma8452_data *data) 279 { 280 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >> 281 MMA8452_CTRL_DR_SHIFT; 282 } 283 284 static const int mma8452_samp_freq[8][2] = { 285 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000}, 286 {6, 250000}, {1, 560000} 287 }; 288 289 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */ 290 static const unsigned int mma8452_time_step_us[4][8] = { 291 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */ 292 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */ 293 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/ 294 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */ 295 }; 296 297 /* Datasheet table "High-Pass Filter Cutoff Options" */ 298 static const int mma8452_hp_filter_cutoff[4][8][4][2] = { 299 { /* normal */ 300 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */ 301 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */ 302 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */ 303 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */ 304 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */ 305 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */ 306 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */ 307 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */ 308 }, 309 { /* low noise low power */ 310 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 311 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 312 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 313 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 314 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 315 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 316 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 317 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} } 318 }, 319 { /* high resolution */ 320 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 321 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 322 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 323 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 324 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 325 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 326 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 327 { {16, 0}, {8, 0}, {4, 0}, {2, 0} } 328 }, 329 { /* low power */ 330 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 331 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 332 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 333 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 334 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} }, 335 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 336 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 337 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} } 338 } 339 }; 340 341 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */ 342 static const u16 mma8452_os_ratio[4][8] = { 343 /* 800 Hz, 400 Hz, ... , 1.56 Hz */ 344 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */ 345 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */ 346 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */ 347 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */ 348 }; 349 350 static int mma8452_get_power_mode(struct mma8452_data *data) 351 { 352 int reg; 353 354 reg = i2c_smbus_read_byte_data(data->client, 355 MMA8452_CTRL_REG2); 356 if (reg < 0) 357 return reg; 358 359 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >> 360 MMA8452_CTRL_REG2_MODS_SHIFT); 361 } 362 363 static ssize_t mma8452_show_samp_freq_avail(struct device *dev, 364 struct device_attribute *attr, 365 char *buf) 366 { 367 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq, 368 ARRAY_SIZE(mma8452_samp_freq)); 369 } 370 371 static ssize_t mma8452_show_scale_avail(struct device *dev, 372 struct device_attribute *attr, 373 char *buf) 374 { 375 struct mma8452_data *data = iio_priv(i2c_get_clientdata( 376 to_i2c_client(dev))); 377 378 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales, 379 ARRAY_SIZE(data->chip_info->mma_scales)); 380 } 381 382 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev, 383 struct device_attribute *attr, 384 char *buf) 385 { 386 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 387 struct mma8452_data *data = iio_priv(indio_dev); 388 int i, j; 389 390 i = mma8452_get_odr_index(data); 391 j = mma8452_get_power_mode(data); 392 if (j < 0) 393 return j; 394 395 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i], 396 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0])); 397 } 398 399 static ssize_t mma8452_show_os_ratio_avail(struct device *dev, 400 struct device_attribute *attr, 401 char *buf) 402 { 403 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 404 struct mma8452_data *data = iio_priv(indio_dev); 405 int i = mma8452_get_odr_index(data); 406 int j; 407 u16 val = 0; 408 size_t len = 0; 409 410 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) { 411 if (val == mma8452_os_ratio[j][i]) 412 continue; 413 414 val = mma8452_os_ratio[j][i]; 415 416 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val); 417 } 418 buf[len - 1] = '\n'; 419 420 return len; 421 } 422 423 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail); 424 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444, 425 mma8452_show_scale_avail, NULL, 0); 426 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available, 427 0444, mma8452_show_hp_cutoff_avail, NULL, 0); 428 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444, 429 mma8452_show_os_ratio_avail, NULL, 0); 430 431 static int mma8452_get_samp_freq_index(struct mma8452_data *data, 432 int val, int val2) 433 { 434 return mma8452_get_int_plus_micros_index(mma8452_samp_freq, 435 ARRAY_SIZE(mma8452_samp_freq), 436 val, val2); 437 } 438 439 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2) 440 { 441 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales, 442 ARRAY_SIZE(data->chip_info->mma_scales), val, val2); 443 } 444 445 static int mma8452_get_hp_filter_index(struct mma8452_data *data, 446 int val, int val2) 447 { 448 int i, j; 449 450 i = mma8452_get_odr_index(data); 451 j = mma8452_get_power_mode(data); 452 if (j < 0) 453 return j; 454 455 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i], 456 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2); 457 } 458 459 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz) 460 { 461 int j, i, ret; 462 463 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF); 464 if (ret < 0) 465 return ret; 466 467 i = mma8452_get_odr_index(data); 468 j = mma8452_get_power_mode(data); 469 if (j < 0) 470 return j; 471 472 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 473 *hz = mma8452_hp_filter_cutoff[j][i][ret][0]; 474 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1]; 475 476 return 0; 477 } 478 479 static int mma8452_read_raw(struct iio_dev *indio_dev, 480 struct iio_chan_spec const *chan, 481 int *val, int *val2, long mask) 482 { 483 struct mma8452_data *data = iio_priv(indio_dev); 484 __be16 buffer[3]; 485 int i, ret; 486 487 switch (mask) { 488 case IIO_CHAN_INFO_RAW: 489 ret = iio_device_claim_direct_mode(indio_dev); 490 if (ret) 491 return ret; 492 493 mutex_lock(&data->lock); 494 ret = mma8452_read(data, buffer); 495 mutex_unlock(&data->lock); 496 iio_device_release_direct_mode(indio_dev); 497 if (ret < 0) 498 return ret; 499 500 *val = sign_extend32(be16_to_cpu( 501 buffer[chan->scan_index]) >> chan->scan_type.shift, 502 chan->scan_type.realbits - 1); 503 504 return IIO_VAL_INT; 505 case IIO_CHAN_INFO_SCALE: 506 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK; 507 *val = data->chip_info->mma_scales[i][0]; 508 *val2 = data->chip_info->mma_scales[i][1]; 509 510 return IIO_VAL_INT_PLUS_MICRO; 511 case IIO_CHAN_INFO_SAMP_FREQ: 512 i = mma8452_get_odr_index(data); 513 *val = mma8452_samp_freq[i][0]; 514 *val2 = mma8452_samp_freq[i][1]; 515 516 return IIO_VAL_INT_PLUS_MICRO; 517 case IIO_CHAN_INFO_CALIBBIAS: 518 ret = i2c_smbus_read_byte_data(data->client, 519 MMA8452_OFF_X + 520 chan->scan_index); 521 if (ret < 0) 522 return ret; 523 524 *val = sign_extend32(ret, 7); 525 526 return IIO_VAL_INT; 527 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 528 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) { 529 ret = mma8452_read_hp_filter(data, val, val2); 530 if (ret < 0) 531 return ret; 532 } else { 533 *val = 0; 534 *val2 = 0; 535 } 536 537 return IIO_VAL_INT_PLUS_MICRO; 538 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 539 ret = mma8452_get_power_mode(data); 540 if (ret < 0) 541 return ret; 542 543 i = mma8452_get_odr_index(data); 544 545 *val = mma8452_os_ratio[ret][i]; 546 return IIO_VAL_INT; 547 } 548 549 return -EINVAL; 550 } 551 552 static int mma8452_calculate_sleep(struct mma8452_data *data) 553 { 554 int ret, i = mma8452_get_odr_index(data); 555 556 if (mma8452_samp_freq[i][0] > 0) 557 ret = 1000 / mma8452_samp_freq[i][0]; 558 else 559 ret = 1000; 560 561 return ret == 0 ? 1 : ret; 562 } 563 564 static int mma8452_standby(struct mma8452_data *data) 565 { 566 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 567 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE); 568 } 569 570 static int mma8452_active(struct mma8452_data *data) 571 { 572 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 573 data->ctrl_reg1); 574 } 575 576 /* returns >0 if active, 0 if in standby and <0 on error */ 577 static int mma8452_is_active(struct mma8452_data *data) 578 { 579 int reg; 580 581 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1); 582 if (reg < 0) 583 return reg; 584 585 return reg & MMA8452_CTRL_ACTIVE; 586 } 587 588 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val) 589 { 590 int ret; 591 int is_active; 592 593 mutex_lock(&data->lock); 594 595 is_active = mma8452_is_active(data); 596 if (is_active < 0) { 597 ret = is_active; 598 goto fail; 599 } 600 601 /* config can only be changed when in standby */ 602 if (is_active > 0) { 603 ret = mma8452_standby(data); 604 if (ret < 0) 605 goto fail; 606 } 607 608 ret = i2c_smbus_write_byte_data(data->client, reg, val); 609 if (ret < 0) 610 goto fail; 611 612 if (is_active > 0) { 613 ret = mma8452_active(data); 614 if (ret < 0) 615 goto fail; 616 } 617 618 ret = 0; 619 fail: 620 mutex_unlock(&data->lock); 621 622 return ret; 623 } 624 625 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode) 626 { 627 int reg; 628 629 reg = i2c_smbus_read_byte_data(data->client, 630 MMA8452_CTRL_REG2); 631 if (reg < 0) 632 return reg; 633 634 reg &= ~MMA8452_CTRL_REG2_MODS_MASK; 635 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT; 636 637 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg); 638 } 639 640 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */ 641 static int mma8452_freefall_mode_enabled(struct mma8452_data *data) 642 { 643 int val; 644 645 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); 646 if (val < 0) 647 return val; 648 649 return !(val & MMA8452_FF_MT_CFG_OAE); 650 } 651 652 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state) 653 { 654 int val; 655 656 if ((state && mma8452_freefall_mode_enabled(data)) || 657 (!state && !(mma8452_freefall_mode_enabled(data)))) 658 return 0; 659 660 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG); 661 if (val < 0) 662 return val; 663 664 if (state) { 665 val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); 666 val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); 667 val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); 668 val &= ~MMA8452_FF_MT_CFG_OAE; 669 } else { 670 val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT); 671 val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT); 672 val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT); 673 val |= MMA8452_FF_MT_CFG_OAE; 674 } 675 676 return mma8452_change_config(data, MMA8452_FF_MT_CFG, val); 677 } 678 679 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data, 680 int val, int val2) 681 { 682 int i, reg; 683 684 i = mma8452_get_hp_filter_index(data, val, val2); 685 if (i < 0) 686 return i; 687 688 reg = i2c_smbus_read_byte_data(data->client, 689 MMA8452_HP_FILTER_CUTOFF); 690 if (reg < 0) 691 return reg; 692 693 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 694 reg |= i; 695 696 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg); 697 } 698 699 static int mma8452_write_raw(struct iio_dev *indio_dev, 700 struct iio_chan_spec const *chan, 701 int val, int val2, long mask) 702 { 703 struct mma8452_data *data = iio_priv(indio_dev); 704 int i, ret; 705 706 ret = iio_device_claim_direct_mode(indio_dev); 707 if (ret) 708 return ret; 709 710 switch (mask) { 711 case IIO_CHAN_INFO_SAMP_FREQ: 712 i = mma8452_get_samp_freq_index(data, val, val2); 713 if (i < 0) { 714 ret = i; 715 break; 716 } 717 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK; 718 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT; 719 720 data->sleep_val = mma8452_calculate_sleep(data); 721 722 ret = mma8452_change_config(data, MMA8452_CTRL_REG1, 723 data->ctrl_reg1); 724 break; 725 case IIO_CHAN_INFO_SCALE: 726 i = mma8452_get_scale_index(data, val, val2); 727 if (i < 0) { 728 ret = i; 729 break; 730 } 731 732 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK; 733 data->data_cfg |= i; 734 735 ret = mma8452_change_config(data, MMA8452_DATA_CFG, 736 data->data_cfg); 737 break; 738 case IIO_CHAN_INFO_CALIBBIAS: 739 if (val < -128 || val > 127) { 740 ret = -EINVAL; 741 break; 742 } 743 744 ret = mma8452_change_config(data, 745 MMA8452_OFF_X + chan->scan_index, 746 val); 747 break; 748 749 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 750 if (val == 0 && val2 == 0) { 751 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK; 752 } else { 753 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK; 754 ret = mma8452_set_hp_filter_frequency(data, val, val2); 755 if (ret < 0) 756 break; 757 } 758 759 ret = mma8452_change_config(data, MMA8452_DATA_CFG, 760 data->data_cfg); 761 break; 762 763 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 764 ret = mma8452_get_odr_index(data); 765 766 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) { 767 if (mma8452_os_ratio[i][ret] == val) { 768 ret = mma8452_set_power_mode(data, i); 769 break; 770 } 771 } 772 break; 773 default: 774 ret = -EINVAL; 775 break; 776 } 777 778 iio_device_release_direct_mode(indio_dev); 779 return ret; 780 } 781 782 static int mma8452_get_event_regs(struct mma8452_data *data, 783 const struct iio_chan_spec *chan, enum iio_event_direction dir, 784 const struct mma8452_event_regs **ev_reg) 785 { 786 if (!chan) 787 return -EINVAL; 788 789 switch (chan->type) { 790 case IIO_ACCEL: 791 switch (dir) { 792 case IIO_EV_DIR_RISING: 793 if ((data->chip_info->all_events 794 & MMA8452_INT_TRANS) && 795 (data->chip_info->enabled_events 796 & MMA8452_INT_TRANS)) 797 *ev_reg = &trans_ev_regs; 798 else 799 *ev_reg = &ff_mt_ev_regs; 800 return 0; 801 case IIO_EV_DIR_FALLING: 802 *ev_reg = &ff_mt_ev_regs; 803 return 0; 804 default: 805 return -EINVAL; 806 } 807 default: 808 return -EINVAL; 809 } 810 } 811 812 static int mma8452_read_event_value(struct iio_dev *indio_dev, 813 const struct iio_chan_spec *chan, 814 enum iio_event_type type, 815 enum iio_event_direction dir, 816 enum iio_event_info info, 817 int *val, int *val2) 818 { 819 struct mma8452_data *data = iio_priv(indio_dev); 820 int ret, us, power_mode; 821 const struct mma8452_event_regs *ev_regs; 822 823 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 824 if (ret) 825 return ret; 826 827 switch (info) { 828 case IIO_EV_INFO_VALUE: 829 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths); 830 if (ret < 0) 831 return ret; 832 833 *val = ret & ev_regs->ev_ths_mask; 834 835 return IIO_VAL_INT; 836 837 case IIO_EV_INFO_PERIOD: 838 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count); 839 if (ret < 0) 840 return ret; 841 842 power_mode = mma8452_get_power_mode(data); 843 if (power_mode < 0) 844 return power_mode; 845 846 us = ret * mma8452_time_step_us[power_mode][ 847 mma8452_get_odr_index(data)]; 848 *val = us / USEC_PER_SEC; 849 *val2 = us % USEC_PER_SEC; 850 851 return IIO_VAL_INT_PLUS_MICRO; 852 853 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 854 ret = i2c_smbus_read_byte_data(data->client, 855 MMA8452_TRANSIENT_CFG); 856 if (ret < 0) 857 return ret; 858 859 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) { 860 *val = 0; 861 *val2 = 0; 862 } else { 863 ret = mma8452_read_hp_filter(data, val, val2); 864 if (ret < 0) 865 return ret; 866 } 867 868 return IIO_VAL_INT_PLUS_MICRO; 869 870 default: 871 return -EINVAL; 872 } 873 } 874 875 static int mma8452_write_event_value(struct iio_dev *indio_dev, 876 const struct iio_chan_spec *chan, 877 enum iio_event_type type, 878 enum iio_event_direction dir, 879 enum iio_event_info info, 880 int val, int val2) 881 { 882 struct mma8452_data *data = iio_priv(indio_dev); 883 int ret, reg, steps; 884 const struct mma8452_event_regs *ev_regs; 885 886 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 887 if (ret) 888 return ret; 889 890 switch (info) { 891 case IIO_EV_INFO_VALUE: 892 if (val < 0 || val > ev_regs->ev_ths_mask) 893 return -EINVAL; 894 895 return mma8452_change_config(data, ev_regs->ev_ths, val); 896 897 case IIO_EV_INFO_PERIOD: 898 ret = mma8452_get_power_mode(data); 899 if (ret < 0) 900 return ret; 901 902 steps = (val * USEC_PER_SEC + val2) / 903 mma8452_time_step_us[ret][ 904 mma8452_get_odr_index(data)]; 905 906 if (steps < 0 || steps > 0xff) 907 return -EINVAL; 908 909 return mma8452_change_config(data, ev_regs->ev_count, steps); 910 911 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 912 reg = i2c_smbus_read_byte_data(data->client, 913 MMA8452_TRANSIENT_CFG); 914 if (reg < 0) 915 return reg; 916 917 if (val == 0 && val2 == 0) { 918 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP; 919 } else { 920 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP; 921 ret = mma8452_set_hp_filter_frequency(data, val, val2); 922 if (ret < 0) 923 return ret; 924 } 925 926 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg); 927 928 default: 929 return -EINVAL; 930 } 931 } 932 933 static int mma8452_read_event_config(struct iio_dev *indio_dev, 934 const struct iio_chan_spec *chan, 935 enum iio_event_type type, 936 enum iio_event_direction dir) 937 { 938 struct mma8452_data *data = iio_priv(indio_dev); 939 int ret; 940 const struct mma8452_event_regs *ev_regs; 941 942 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 943 if (ret) 944 return ret; 945 946 switch (dir) { 947 case IIO_EV_DIR_FALLING: 948 return mma8452_freefall_mode_enabled(data); 949 case IIO_EV_DIR_RISING: 950 ret = i2c_smbus_read_byte_data(data->client, 951 ev_regs->ev_cfg); 952 if (ret < 0) 953 return ret; 954 955 return !!(ret & BIT(chan->scan_index + 956 ev_regs->ev_cfg_chan_shift)); 957 default: 958 return -EINVAL; 959 } 960 } 961 962 static int mma8452_write_event_config(struct iio_dev *indio_dev, 963 const struct iio_chan_spec *chan, 964 enum iio_event_type type, 965 enum iio_event_direction dir, 966 int state) 967 { 968 struct mma8452_data *data = iio_priv(indio_dev); 969 int val, ret; 970 const struct mma8452_event_regs *ev_regs; 971 972 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs); 973 if (ret) 974 return ret; 975 976 ret = mma8452_set_runtime_pm_state(data->client, state); 977 if (ret) 978 return ret; 979 980 switch (dir) { 981 case IIO_EV_DIR_FALLING: 982 return mma8452_set_freefall_mode(data, state); 983 case IIO_EV_DIR_RISING: 984 val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg); 985 if (val < 0) 986 return val; 987 988 if (state) { 989 if (mma8452_freefall_mode_enabled(data)) { 990 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift); 991 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift); 992 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift); 993 val |= MMA8452_FF_MT_CFG_OAE; 994 } 995 val |= BIT(chan->scan_index + 996 ev_regs->ev_cfg_chan_shift); 997 } else { 998 if (mma8452_freefall_mode_enabled(data)) 999 return 0; 1000 1001 val &= ~BIT(chan->scan_index + 1002 ev_regs->ev_cfg_chan_shift); 1003 } 1004 1005 val |= ev_regs->ev_cfg_ele; 1006 1007 return mma8452_change_config(data, ev_regs->ev_cfg, val); 1008 default: 1009 return -EINVAL; 1010 } 1011 } 1012 1013 static void mma8452_transient_interrupt(struct iio_dev *indio_dev) 1014 { 1015 struct mma8452_data *data = iio_priv(indio_dev); 1016 s64 ts = iio_get_time_ns(indio_dev); 1017 int src; 1018 1019 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC); 1020 if (src < 0) 1021 return; 1022 1023 if (src & MMA8452_TRANSIENT_SRC_XTRANSE) 1024 iio_push_event(indio_dev, 1025 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1026 IIO_EV_TYPE_MAG, 1027 IIO_EV_DIR_RISING), 1028 ts); 1029 1030 if (src & MMA8452_TRANSIENT_SRC_YTRANSE) 1031 iio_push_event(indio_dev, 1032 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y, 1033 IIO_EV_TYPE_MAG, 1034 IIO_EV_DIR_RISING), 1035 ts); 1036 1037 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE) 1038 iio_push_event(indio_dev, 1039 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z, 1040 IIO_EV_TYPE_MAG, 1041 IIO_EV_DIR_RISING), 1042 ts); 1043 } 1044 1045 static irqreturn_t mma8452_interrupt(int irq, void *p) 1046 { 1047 struct iio_dev *indio_dev = p; 1048 struct mma8452_data *data = iio_priv(indio_dev); 1049 int ret = IRQ_NONE; 1050 int src; 1051 1052 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC); 1053 if (src < 0) 1054 return IRQ_NONE; 1055 1056 if (!(src & (data->chip_info->enabled_events | MMA8452_INT_DRDY))) 1057 return IRQ_NONE; 1058 1059 if (src & MMA8452_INT_DRDY) { 1060 iio_trigger_poll_chained(indio_dev->trig); 1061 ret = IRQ_HANDLED; 1062 } 1063 1064 if (src & MMA8452_INT_FF_MT) { 1065 if (mma8452_freefall_mode_enabled(data)) { 1066 s64 ts = iio_get_time_ns(indio_dev); 1067 1068 iio_push_event(indio_dev, 1069 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 1070 IIO_MOD_X_AND_Y_AND_Z, 1071 IIO_EV_TYPE_MAG, 1072 IIO_EV_DIR_FALLING), 1073 ts); 1074 } 1075 ret = IRQ_HANDLED; 1076 } 1077 1078 if (src & MMA8452_INT_TRANS) { 1079 mma8452_transient_interrupt(indio_dev); 1080 ret = IRQ_HANDLED; 1081 } 1082 1083 return ret; 1084 } 1085 1086 static irqreturn_t mma8452_trigger_handler(int irq, void *p) 1087 { 1088 struct iio_poll_func *pf = p; 1089 struct iio_dev *indio_dev = pf->indio_dev; 1090 struct mma8452_data *data = iio_priv(indio_dev); 1091 u8 buffer[16]; /* 3 16-bit channels + padding + ts */ 1092 int ret; 1093 1094 ret = mma8452_read(data, (__be16 *)buffer); 1095 if (ret < 0) 1096 goto done; 1097 1098 iio_push_to_buffers_with_timestamp(indio_dev, buffer, 1099 iio_get_time_ns(indio_dev)); 1100 1101 done: 1102 iio_trigger_notify_done(indio_dev->trig); 1103 1104 return IRQ_HANDLED; 1105 } 1106 1107 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev, 1108 unsigned int reg, unsigned int writeval, 1109 unsigned int *readval) 1110 { 1111 int ret; 1112 struct mma8452_data *data = iio_priv(indio_dev); 1113 1114 if (reg > MMA8452_MAX_REG) 1115 return -EINVAL; 1116 1117 if (!readval) 1118 return mma8452_change_config(data, reg, writeval); 1119 1120 ret = i2c_smbus_read_byte_data(data->client, reg); 1121 if (ret < 0) 1122 return ret; 1123 1124 *readval = ret; 1125 1126 return 0; 1127 } 1128 1129 static const struct iio_event_spec mma8452_freefall_event[] = { 1130 { 1131 .type = IIO_EV_TYPE_MAG, 1132 .dir = IIO_EV_DIR_FALLING, 1133 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1134 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1135 BIT(IIO_EV_INFO_PERIOD) | 1136 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1137 }, 1138 }; 1139 1140 static const struct iio_event_spec mma8652_freefall_event[] = { 1141 { 1142 .type = IIO_EV_TYPE_MAG, 1143 .dir = IIO_EV_DIR_FALLING, 1144 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1145 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1146 BIT(IIO_EV_INFO_PERIOD) 1147 }, 1148 }; 1149 1150 static const struct iio_event_spec mma8452_transient_event[] = { 1151 { 1152 .type = IIO_EV_TYPE_MAG, 1153 .dir = IIO_EV_DIR_RISING, 1154 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1155 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1156 BIT(IIO_EV_INFO_PERIOD) | 1157 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1158 }, 1159 }; 1160 1161 static const struct iio_event_spec mma8452_motion_event[] = { 1162 { 1163 .type = IIO_EV_TYPE_MAG, 1164 .dir = IIO_EV_DIR_RISING, 1165 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1166 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1167 BIT(IIO_EV_INFO_PERIOD) 1168 }, 1169 }; 1170 1171 /* 1172 * Threshold is configured in fixed 8G/127 steps regardless of 1173 * currently selected scale for measurement. 1174 */ 1175 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742"); 1176 1177 static struct attribute *mma8452_event_attributes[] = { 1178 &iio_const_attr_accel_transient_scale.dev_attr.attr, 1179 NULL, 1180 }; 1181 1182 static struct attribute_group mma8452_event_attribute_group = { 1183 .attrs = mma8452_event_attributes, 1184 }; 1185 1186 #define MMA8452_FREEFALL_CHANNEL(modifier) { \ 1187 .type = IIO_ACCEL, \ 1188 .modified = 1, \ 1189 .channel2 = modifier, \ 1190 .scan_index = -1, \ 1191 .event_spec = mma8452_freefall_event, \ 1192 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \ 1193 } 1194 1195 #define MMA8652_FREEFALL_CHANNEL(modifier) { \ 1196 .type = IIO_ACCEL, \ 1197 .modified = 1, \ 1198 .channel2 = modifier, \ 1199 .scan_index = -1, \ 1200 .event_spec = mma8652_freefall_event, \ 1201 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \ 1202 } 1203 1204 #define MMA8452_CHANNEL(axis, idx, bits) { \ 1205 .type = IIO_ACCEL, \ 1206 .modified = 1, \ 1207 .channel2 = IIO_MOD_##axis, \ 1208 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1209 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1210 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1211 BIT(IIO_CHAN_INFO_SCALE) | \ 1212 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \ 1213 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1214 .scan_index = idx, \ 1215 .scan_type = { \ 1216 .sign = 's', \ 1217 .realbits = (bits), \ 1218 .storagebits = 16, \ 1219 .shift = 16 - (bits), \ 1220 .endianness = IIO_BE, \ 1221 }, \ 1222 .event_spec = mma8452_transient_event, \ 1223 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \ 1224 } 1225 1226 #define MMA8652_CHANNEL(axis, idx, bits) { \ 1227 .type = IIO_ACCEL, \ 1228 .modified = 1, \ 1229 .channel2 = IIO_MOD_##axis, \ 1230 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1231 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1232 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1233 BIT(IIO_CHAN_INFO_SCALE) | \ 1234 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1235 .scan_index = idx, \ 1236 .scan_type = { \ 1237 .sign = 's', \ 1238 .realbits = (bits), \ 1239 .storagebits = 16, \ 1240 .shift = 16 - (bits), \ 1241 .endianness = IIO_BE, \ 1242 }, \ 1243 .event_spec = mma8452_motion_event, \ 1244 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \ 1245 } 1246 1247 static const struct iio_chan_spec mma8451_channels[] = { 1248 MMA8452_CHANNEL(X, idx_x, 14), 1249 MMA8452_CHANNEL(Y, idx_y, 14), 1250 MMA8452_CHANNEL(Z, idx_z, 14), 1251 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1252 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1253 }; 1254 1255 static const struct iio_chan_spec mma8452_channels[] = { 1256 MMA8452_CHANNEL(X, idx_x, 12), 1257 MMA8452_CHANNEL(Y, idx_y, 12), 1258 MMA8452_CHANNEL(Z, idx_z, 12), 1259 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1260 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1261 }; 1262 1263 static const struct iio_chan_spec mma8453_channels[] = { 1264 MMA8452_CHANNEL(X, idx_x, 10), 1265 MMA8452_CHANNEL(Y, idx_y, 10), 1266 MMA8452_CHANNEL(Z, idx_z, 10), 1267 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1268 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1269 }; 1270 1271 static const struct iio_chan_spec mma8652_channels[] = { 1272 MMA8652_CHANNEL(X, idx_x, 12), 1273 MMA8652_CHANNEL(Y, idx_y, 12), 1274 MMA8652_CHANNEL(Z, idx_z, 12), 1275 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1276 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1277 }; 1278 1279 static const struct iio_chan_spec mma8653_channels[] = { 1280 MMA8652_CHANNEL(X, idx_x, 10), 1281 MMA8652_CHANNEL(Y, idx_y, 10), 1282 MMA8652_CHANNEL(Z, idx_z, 10), 1283 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1284 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1285 }; 1286 1287 enum { 1288 mma8451, 1289 mma8452, 1290 mma8453, 1291 mma8652, 1292 mma8653, 1293 fxls8471, 1294 }; 1295 1296 static const struct mma_chip_info mma_chip_info_table[] = { 1297 [mma8451] = { 1298 .chip_id = MMA8451_DEVICE_ID, 1299 .channels = mma8451_channels, 1300 .num_channels = ARRAY_SIZE(mma8451_channels), 1301 /* 1302 * Hardware has fullscale of -2G, -4G, -8G corresponding to 1303 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10 1304 * bit. 1305 * The userspace interface uses m/s^2 and we declare micro units 1306 * So scale factor for 12 bit here is given by: 1307 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665 1308 */ 1309 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1310 /* 1311 * Although we enable the interrupt sources once and for 1312 * all here the event detection itself is not enabled until 1313 * userspace asks for it by mma8452_write_event_config() 1314 */ 1315 .all_events = MMA8452_INT_DRDY | 1316 MMA8452_INT_TRANS | 1317 MMA8452_INT_FF_MT, 1318 .enabled_events = MMA8452_INT_TRANS | 1319 MMA8452_INT_FF_MT, 1320 }, 1321 [mma8452] = { 1322 .chip_id = MMA8452_DEVICE_ID, 1323 .channels = mma8452_channels, 1324 .num_channels = ARRAY_SIZE(mma8452_channels), 1325 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1326 /* 1327 * Although we enable the interrupt sources once and for 1328 * all here the event detection itself is not enabled until 1329 * userspace asks for it by mma8452_write_event_config() 1330 */ 1331 .all_events = MMA8452_INT_DRDY | 1332 MMA8452_INT_TRANS | 1333 MMA8452_INT_FF_MT, 1334 .enabled_events = MMA8452_INT_TRANS | 1335 MMA8452_INT_FF_MT, 1336 }, 1337 [mma8453] = { 1338 .chip_id = MMA8453_DEVICE_ID, 1339 .channels = mma8453_channels, 1340 .num_channels = ARRAY_SIZE(mma8453_channels), 1341 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1342 /* 1343 * Although we enable the interrupt sources once and for 1344 * all here the event detection itself is not enabled until 1345 * userspace asks for it by mma8452_write_event_config() 1346 */ 1347 .all_events = MMA8452_INT_DRDY | 1348 MMA8452_INT_TRANS | 1349 MMA8452_INT_FF_MT, 1350 .enabled_events = MMA8452_INT_TRANS | 1351 MMA8452_INT_FF_MT, 1352 }, 1353 [mma8652] = { 1354 .chip_id = MMA8652_DEVICE_ID, 1355 .channels = mma8652_channels, 1356 .num_channels = ARRAY_SIZE(mma8652_channels), 1357 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1358 .all_events = MMA8452_INT_DRDY | 1359 MMA8452_INT_FF_MT, 1360 .enabled_events = MMA8452_INT_FF_MT, 1361 }, 1362 [mma8653] = { 1363 .chip_id = MMA8653_DEVICE_ID, 1364 .channels = mma8653_channels, 1365 .num_channels = ARRAY_SIZE(mma8653_channels), 1366 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1367 /* 1368 * Although we enable the interrupt sources once and for 1369 * all here the event detection itself is not enabled until 1370 * userspace asks for it by mma8452_write_event_config() 1371 */ 1372 .all_events = MMA8452_INT_DRDY | 1373 MMA8452_INT_FF_MT, 1374 .enabled_events = MMA8452_INT_FF_MT, 1375 }, 1376 [fxls8471] = { 1377 .chip_id = FXLS8471_DEVICE_ID, 1378 .channels = mma8451_channels, 1379 .num_channels = ARRAY_SIZE(mma8451_channels), 1380 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1381 /* 1382 * Although we enable the interrupt sources once and for 1383 * all here the event detection itself is not enabled until 1384 * userspace asks for it by mma8452_write_event_config() 1385 */ 1386 .all_events = MMA8452_INT_DRDY | 1387 MMA8452_INT_TRANS | 1388 MMA8452_INT_FF_MT, 1389 .enabled_events = MMA8452_INT_TRANS | 1390 MMA8452_INT_FF_MT, 1391 }, 1392 }; 1393 1394 static struct attribute *mma8452_attributes[] = { 1395 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1396 &iio_dev_attr_in_accel_scale_available.dev_attr.attr, 1397 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr, 1398 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr, 1399 NULL 1400 }; 1401 1402 static const struct attribute_group mma8452_group = { 1403 .attrs = mma8452_attributes, 1404 }; 1405 1406 static const struct iio_info mma8452_info = { 1407 .attrs = &mma8452_group, 1408 .read_raw = &mma8452_read_raw, 1409 .write_raw = &mma8452_write_raw, 1410 .event_attrs = &mma8452_event_attribute_group, 1411 .read_event_value = &mma8452_read_event_value, 1412 .write_event_value = &mma8452_write_event_value, 1413 .read_event_config = &mma8452_read_event_config, 1414 .write_event_config = &mma8452_write_event_config, 1415 .debugfs_reg_access = &mma8452_reg_access_dbg, 1416 }; 1417 1418 static const unsigned long mma8452_scan_masks[] = {0x7, 0}; 1419 1420 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig, 1421 bool state) 1422 { 1423 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1424 struct mma8452_data *data = iio_priv(indio_dev); 1425 int reg, ret; 1426 1427 ret = mma8452_set_runtime_pm_state(data->client, state); 1428 if (ret) 1429 return ret; 1430 1431 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4); 1432 if (reg < 0) 1433 return reg; 1434 1435 if (state) 1436 reg |= MMA8452_INT_DRDY; 1437 else 1438 reg &= ~MMA8452_INT_DRDY; 1439 1440 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg); 1441 } 1442 1443 static const struct iio_trigger_ops mma8452_trigger_ops = { 1444 .set_trigger_state = mma8452_data_rdy_trigger_set_state, 1445 .validate_device = iio_trigger_validate_own_device, 1446 }; 1447 1448 static int mma8452_trigger_setup(struct iio_dev *indio_dev) 1449 { 1450 struct mma8452_data *data = iio_priv(indio_dev); 1451 struct iio_trigger *trig; 1452 int ret; 1453 1454 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d", 1455 indio_dev->name, 1456 indio_dev->id); 1457 if (!trig) 1458 return -ENOMEM; 1459 1460 trig->dev.parent = &data->client->dev; 1461 trig->ops = &mma8452_trigger_ops; 1462 iio_trigger_set_drvdata(trig, indio_dev); 1463 1464 ret = iio_trigger_register(trig); 1465 if (ret) 1466 return ret; 1467 1468 indio_dev->trig = trig; 1469 1470 return 0; 1471 } 1472 1473 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev) 1474 { 1475 if (indio_dev->trig) 1476 iio_trigger_unregister(indio_dev->trig); 1477 } 1478 1479 static int mma8452_reset(struct i2c_client *client) 1480 { 1481 int i; 1482 int ret; 1483 1484 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2, 1485 MMA8452_CTRL_REG2_RST); 1486 if (ret < 0) 1487 return ret; 1488 1489 for (i = 0; i < 10; i++) { 1490 usleep_range(100, 200); 1491 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2); 1492 if (ret == -EIO) 1493 continue; /* I2C comm reset */ 1494 if (ret < 0) 1495 return ret; 1496 if (!(ret & MMA8452_CTRL_REG2_RST)) 1497 return 0; 1498 } 1499 1500 return -ETIMEDOUT; 1501 } 1502 1503 static const struct of_device_id mma8452_dt_ids[] = { 1504 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] }, 1505 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] }, 1506 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] }, 1507 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] }, 1508 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] }, 1509 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] }, 1510 { } 1511 }; 1512 MODULE_DEVICE_TABLE(of, mma8452_dt_ids); 1513 1514 static int mma8452_probe(struct i2c_client *client, 1515 const struct i2c_device_id *id) 1516 { 1517 struct mma8452_data *data; 1518 struct iio_dev *indio_dev; 1519 int ret; 1520 const struct of_device_id *match; 1521 1522 match = of_match_device(mma8452_dt_ids, &client->dev); 1523 if (!match) { 1524 dev_err(&client->dev, "unknown device model\n"); 1525 return -ENODEV; 1526 } 1527 1528 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 1529 if (!indio_dev) 1530 return -ENOMEM; 1531 1532 data = iio_priv(indio_dev); 1533 data->client = client; 1534 mutex_init(&data->lock); 1535 data->chip_info = match->data; 1536 1537 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I); 1538 if (ret < 0) 1539 return ret; 1540 1541 switch (ret) { 1542 case MMA8451_DEVICE_ID: 1543 case MMA8452_DEVICE_ID: 1544 case MMA8453_DEVICE_ID: 1545 case MMA8652_DEVICE_ID: 1546 case MMA8653_DEVICE_ID: 1547 case FXLS8471_DEVICE_ID: 1548 if (ret == data->chip_info->chip_id) 1549 break; 1550 /* else: fall through */ 1551 default: 1552 return -ENODEV; 1553 } 1554 1555 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n", 1556 match->compatible, data->chip_info->chip_id); 1557 1558 i2c_set_clientdata(client, indio_dev); 1559 indio_dev->info = &mma8452_info; 1560 indio_dev->name = id->name; 1561 indio_dev->dev.parent = &client->dev; 1562 indio_dev->modes = INDIO_DIRECT_MODE; 1563 indio_dev->channels = data->chip_info->channels; 1564 indio_dev->num_channels = data->chip_info->num_channels; 1565 indio_dev->available_scan_masks = mma8452_scan_masks; 1566 1567 ret = mma8452_reset(client); 1568 if (ret < 0) 1569 return ret; 1570 1571 data->data_cfg = MMA8452_DATA_CFG_FS_2G; 1572 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG, 1573 data->data_cfg); 1574 if (ret < 0) 1575 return ret; 1576 1577 /* 1578 * By default set transient threshold to max to avoid events if 1579 * enabling without configuring threshold. 1580 */ 1581 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS, 1582 MMA8452_TRANSIENT_THS_MASK); 1583 if (ret < 0) 1584 return ret; 1585 1586 if (client->irq) { 1587 int irq2; 1588 1589 irq2 = of_irq_get_byname(client->dev.of_node, "INT2"); 1590 1591 if (irq2 == client->irq) { 1592 dev_dbg(&client->dev, "using interrupt line INT2\n"); 1593 } else { 1594 ret = i2c_smbus_write_byte_data(client, 1595 MMA8452_CTRL_REG5, 1596 data->chip_info->all_events); 1597 if (ret < 0) 1598 return ret; 1599 1600 dev_dbg(&client->dev, "using interrupt line INT1\n"); 1601 } 1602 1603 ret = i2c_smbus_write_byte_data(client, 1604 MMA8452_CTRL_REG4, 1605 data->chip_info->enabled_events); 1606 if (ret < 0) 1607 return ret; 1608 1609 ret = mma8452_trigger_setup(indio_dev); 1610 if (ret < 0) 1611 return ret; 1612 } 1613 1614 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE | 1615 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT); 1616 1617 data->sleep_val = mma8452_calculate_sleep(data); 1618 1619 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1, 1620 data->ctrl_reg1); 1621 if (ret < 0) 1622 goto trigger_cleanup; 1623 1624 ret = iio_triggered_buffer_setup(indio_dev, NULL, 1625 mma8452_trigger_handler, NULL); 1626 if (ret < 0) 1627 goto trigger_cleanup; 1628 1629 if (client->irq) { 1630 ret = devm_request_threaded_irq(&client->dev, 1631 client->irq, 1632 NULL, mma8452_interrupt, 1633 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1634 client->name, indio_dev); 1635 if (ret) 1636 goto buffer_cleanup; 1637 } 1638 1639 ret = pm_runtime_set_active(&client->dev); 1640 if (ret < 0) 1641 goto buffer_cleanup; 1642 1643 pm_runtime_enable(&client->dev); 1644 pm_runtime_set_autosuspend_delay(&client->dev, 1645 MMA8452_AUTO_SUSPEND_DELAY_MS); 1646 pm_runtime_use_autosuspend(&client->dev); 1647 1648 ret = iio_device_register(indio_dev); 1649 if (ret < 0) 1650 goto buffer_cleanup; 1651 1652 ret = mma8452_set_freefall_mode(data, false); 1653 if (ret < 0) 1654 goto buffer_cleanup; 1655 1656 return 0; 1657 1658 buffer_cleanup: 1659 iio_triggered_buffer_cleanup(indio_dev); 1660 1661 trigger_cleanup: 1662 mma8452_trigger_cleanup(indio_dev); 1663 1664 return ret; 1665 } 1666 1667 static int mma8452_remove(struct i2c_client *client) 1668 { 1669 struct iio_dev *indio_dev = i2c_get_clientdata(client); 1670 1671 iio_device_unregister(indio_dev); 1672 1673 pm_runtime_disable(&client->dev); 1674 pm_runtime_set_suspended(&client->dev); 1675 pm_runtime_put_noidle(&client->dev); 1676 1677 iio_triggered_buffer_cleanup(indio_dev); 1678 mma8452_trigger_cleanup(indio_dev); 1679 mma8452_standby(iio_priv(indio_dev)); 1680 1681 return 0; 1682 } 1683 1684 #ifdef CONFIG_PM 1685 static int mma8452_runtime_suspend(struct device *dev) 1686 { 1687 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1688 struct mma8452_data *data = iio_priv(indio_dev); 1689 int ret; 1690 1691 mutex_lock(&data->lock); 1692 ret = mma8452_standby(data); 1693 mutex_unlock(&data->lock); 1694 if (ret < 0) { 1695 dev_err(&data->client->dev, "powering off device failed\n"); 1696 return -EAGAIN; 1697 } 1698 1699 return 0; 1700 } 1701 1702 static int mma8452_runtime_resume(struct device *dev) 1703 { 1704 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1705 struct mma8452_data *data = iio_priv(indio_dev); 1706 int ret, sleep_val; 1707 1708 ret = mma8452_active(data); 1709 if (ret < 0) 1710 return ret; 1711 1712 ret = mma8452_get_odr_index(data); 1713 sleep_val = 1000 / mma8452_samp_freq[ret][0]; 1714 if (sleep_val < 20) 1715 usleep_range(sleep_val * 1000, 20000); 1716 else 1717 msleep_interruptible(sleep_val); 1718 1719 return 0; 1720 } 1721 #endif 1722 1723 #ifdef CONFIG_PM_SLEEP 1724 static int mma8452_suspend(struct device *dev) 1725 { 1726 return mma8452_standby(iio_priv(i2c_get_clientdata( 1727 to_i2c_client(dev)))); 1728 } 1729 1730 static int mma8452_resume(struct device *dev) 1731 { 1732 return mma8452_active(iio_priv(i2c_get_clientdata( 1733 to_i2c_client(dev)))); 1734 } 1735 #endif 1736 1737 static const struct dev_pm_ops mma8452_pm_ops = { 1738 SET_SYSTEM_SLEEP_PM_OPS(mma8452_suspend, mma8452_resume) 1739 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend, 1740 mma8452_runtime_resume, NULL) 1741 }; 1742 1743 static const struct i2c_device_id mma8452_id[] = { 1744 { "mma8451", mma8451 }, 1745 { "mma8452", mma8452 }, 1746 { "mma8453", mma8453 }, 1747 { "mma8652", mma8652 }, 1748 { "mma8653", mma8653 }, 1749 { "fxls8471", fxls8471 }, 1750 { } 1751 }; 1752 MODULE_DEVICE_TABLE(i2c, mma8452_id); 1753 1754 static struct i2c_driver mma8452_driver = { 1755 .driver = { 1756 .name = "mma8452", 1757 .of_match_table = of_match_ptr(mma8452_dt_ids), 1758 .pm = &mma8452_pm_ops, 1759 }, 1760 .probe = mma8452_probe, 1761 .remove = mma8452_remove, 1762 .id_table = mma8452_id, 1763 }; 1764 module_i2c_driver(mma8452_driver); 1765 1766 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>"); 1767 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver"); 1768 MODULE_LICENSE("GPL"); 1769