1 /* 2 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers: 3 * 4 * device name digital output 7-bit I2C slave address (pin selectable) 5 * --------------------------------------------------------------------- 6 * MMA8451Q 14 bit 0x1c / 0x1d 7 * MMA8452Q 12 bit 0x1c / 0x1d 8 * MMA8453Q 10 bit 0x1c / 0x1d 9 * MMA8652FC 12 bit 0x1d 10 * MMA8653FC 10 bit 0x1d 11 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f 12 * 13 * Copyright 2015 Martin Kepplinger <martink@posteo.de> 14 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net> 15 * 16 * This file is subject to the terms and conditions of version 2 of 17 * the GNU General Public License. See the file COPYING in the main 18 * directory of this archive for more details. 19 * 20 * TODO: orientation events 21 */ 22 23 #include <linux/module.h> 24 #include <linux/i2c.h> 25 #include <linux/iio/iio.h> 26 #include <linux/iio/sysfs.h> 27 #include <linux/iio/buffer.h> 28 #include <linux/iio/trigger.h> 29 #include <linux/iio/trigger_consumer.h> 30 #include <linux/iio/triggered_buffer.h> 31 #include <linux/iio/events.h> 32 #include <linux/delay.h> 33 #include <linux/of_device.h> 34 #include <linux/of_irq.h> 35 #include <linux/pm_runtime.h> 36 37 #define MMA8452_STATUS 0x00 38 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0)) 39 #define MMA8452_OUT_X 0x01 /* MSB first */ 40 #define MMA8452_OUT_Y 0x03 41 #define MMA8452_OUT_Z 0x05 42 #define MMA8452_INT_SRC 0x0c 43 #define MMA8452_WHO_AM_I 0x0d 44 #define MMA8452_DATA_CFG 0x0e 45 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0) 46 #define MMA8452_DATA_CFG_FS_2G 0 47 #define MMA8452_DATA_CFG_FS_4G 1 48 #define MMA8452_DATA_CFG_FS_8G 2 49 #define MMA8452_DATA_CFG_HPF_MASK BIT(4) 50 #define MMA8452_HP_FILTER_CUTOFF 0x0f 51 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0) 52 #define MMA8452_FF_MT_CFG 0x15 53 #define MMA8452_FF_MT_CFG_OAE BIT(6) 54 #define MMA8452_FF_MT_CFG_ELE BIT(7) 55 #define MMA8452_FF_MT_SRC 0x16 56 #define MMA8452_FF_MT_SRC_XHE BIT(1) 57 #define MMA8452_FF_MT_SRC_YHE BIT(3) 58 #define MMA8452_FF_MT_SRC_ZHE BIT(5) 59 #define MMA8452_FF_MT_THS 0x17 60 #define MMA8452_FF_MT_THS_MASK 0x7f 61 #define MMA8452_FF_MT_COUNT 0x18 62 #define MMA8452_TRANSIENT_CFG 0x1d 63 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0) 64 #define MMA8452_TRANSIENT_CFG_ELE BIT(4) 65 #define MMA8452_TRANSIENT_SRC 0x1e 66 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1) 67 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3) 68 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5) 69 #define MMA8452_TRANSIENT_THS 0x1f 70 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0) 71 #define MMA8452_TRANSIENT_COUNT 0x20 72 #define MMA8452_CTRL_REG1 0x2a 73 #define MMA8452_CTRL_ACTIVE BIT(0) 74 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3) 75 #define MMA8452_CTRL_DR_SHIFT 3 76 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */ 77 #define MMA8452_CTRL_REG2 0x2b 78 #define MMA8452_CTRL_REG2_RST BIT(6) 79 #define MMA8452_CTRL_REG2_MODS_SHIFT 3 80 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b 81 #define MMA8452_CTRL_REG4 0x2d 82 #define MMA8452_CTRL_REG5 0x2e 83 #define MMA8452_OFF_X 0x2f 84 #define MMA8452_OFF_Y 0x30 85 #define MMA8452_OFF_Z 0x31 86 87 #define MMA8452_MAX_REG 0x31 88 89 #define MMA8452_INT_DRDY BIT(0) 90 #define MMA8452_INT_FF_MT BIT(2) 91 #define MMA8452_INT_TRANS BIT(5) 92 93 #define MMA8451_DEVICE_ID 0x1a 94 #define MMA8452_DEVICE_ID 0x2a 95 #define MMA8453_DEVICE_ID 0x3a 96 #define MMA8652_DEVICE_ID 0x4a 97 #define MMA8653_DEVICE_ID 0x5a 98 #define FXLS8471_DEVICE_ID 0x6a 99 100 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000 101 102 struct mma8452_data { 103 struct i2c_client *client; 104 struct mutex lock; 105 u8 ctrl_reg1; 106 u8 data_cfg; 107 const struct mma_chip_info *chip_info; 108 }; 109 110 /** 111 * struct mma_chip_info - chip specific data 112 * @chip_id: WHO_AM_I register's value 113 * @channels: struct iio_chan_spec matching the device's 114 * capabilities 115 * @num_channels: number of channels 116 * @mma_scales: scale factors for converting register values 117 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers 118 * per mode: m/s^2 and micro m/s^2 119 * @ev_cfg: event config register address 120 * @ev_cfg_ele: latch bit in event config register 121 * @ev_cfg_chan_shift: number of the bit to enable events in X 122 * direction; in event config register 123 * @ev_src: event source register address 124 * @ev_src_xe: bit in event source register that indicates 125 * an event in X direction 126 * @ev_src_ye: bit in event source register that indicates 127 * an event in Y direction 128 * @ev_src_ze: bit in event source register that indicates 129 * an event in Z direction 130 * @ev_ths: event threshold register address 131 * @ev_ths_mask: mask for the threshold value 132 * @ev_count: event count (period) register address 133 * 134 * Since not all chips supported by the driver support comparing high pass 135 * filtered data for events (interrupts), different interrupt sources are 136 * used for different chips and the relevant registers are included here. 137 */ 138 struct mma_chip_info { 139 u8 chip_id; 140 const struct iio_chan_spec *channels; 141 int num_channels; 142 const int mma_scales[3][2]; 143 u8 ev_cfg; 144 u8 ev_cfg_ele; 145 u8 ev_cfg_chan_shift; 146 u8 ev_src; 147 u8 ev_src_xe; 148 u8 ev_src_ye; 149 u8 ev_src_ze; 150 u8 ev_ths; 151 u8 ev_ths_mask; 152 u8 ev_count; 153 }; 154 155 enum { 156 idx_x, 157 idx_y, 158 idx_z, 159 idx_ts, 160 }; 161 162 static int mma8452_drdy(struct mma8452_data *data) 163 { 164 int tries = 150; 165 166 while (tries-- > 0) { 167 int ret = i2c_smbus_read_byte_data(data->client, 168 MMA8452_STATUS); 169 if (ret < 0) 170 return ret; 171 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY) 172 return 0; 173 174 msleep(20); 175 } 176 177 dev_err(&data->client->dev, "data not ready\n"); 178 179 return -EIO; 180 } 181 182 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on) 183 { 184 #ifdef CONFIG_PM 185 int ret; 186 187 if (on) { 188 ret = pm_runtime_get_sync(&client->dev); 189 } else { 190 pm_runtime_mark_last_busy(&client->dev); 191 ret = pm_runtime_put_autosuspend(&client->dev); 192 } 193 194 if (ret < 0) { 195 dev_err(&client->dev, 196 "failed to change power state to %d\n", on); 197 if (on) 198 pm_runtime_put_noidle(&client->dev); 199 200 return ret; 201 } 202 #endif 203 204 return 0; 205 } 206 207 static int mma8452_read(struct mma8452_data *data, __be16 buf[3]) 208 { 209 int ret = mma8452_drdy(data); 210 211 if (ret < 0) 212 return ret; 213 214 ret = mma8452_set_runtime_pm_state(data->client, true); 215 if (ret) 216 return ret; 217 218 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X, 219 3 * sizeof(__be16), (u8 *)buf); 220 221 ret = mma8452_set_runtime_pm_state(data->client, false); 222 223 return ret; 224 } 225 226 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2], 227 int n) 228 { 229 size_t len = 0; 230 231 while (n-- > 0) 232 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ", 233 vals[n][0], vals[n][1]); 234 235 /* replace trailing space by newline */ 236 buf[len - 1] = '\n'; 237 238 return len; 239 } 240 241 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n, 242 int val, int val2) 243 { 244 while (n-- > 0) 245 if (val == vals[n][0] && val2 == vals[n][1]) 246 return n; 247 248 return -EINVAL; 249 } 250 251 static int mma8452_get_odr_index(struct mma8452_data *data) 252 { 253 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >> 254 MMA8452_CTRL_DR_SHIFT; 255 } 256 257 static const int mma8452_samp_freq[8][2] = { 258 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000}, 259 {6, 250000}, {1, 560000} 260 }; 261 262 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */ 263 static const int mma8452_transient_time_step_us[4][8] = { 264 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */ 265 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */ 266 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/ 267 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */ 268 }; 269 270 /* Datasheet table "High-Pass Filter Cutoff Options" */ 271 static const int mma8452_hp_filter_cutoff[4][8][4][2] = { 272 { /* normal */ 273 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */ 274 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */ 275 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */ 276 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */ 277 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */ 278 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */ 279 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */ 280 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */ 281 }, 282 { /* low noise low power */ 283 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 284 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 285 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 286 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 287 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 288 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 289 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }, 290 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} } 291 }, 292 { /* high resolution */ 293 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 294 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 295 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 296 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 297 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 298 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 299 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 300 { {16, 0}, {8, 0}, {4, 0}, {2, 0} } 301 }, 302 { /* low power */ 303 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, 304 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, 305 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, 306 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, 307 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} }, 308 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 309 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }, 310 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} } 311 } 312 }; 313 314 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */ 315 static const u16 mma8452_os_ratio[4][8] = { 316 /* 800 Hz, 400 Hz, ... , 1.56 Hz */ 317 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */ 318 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */ 319 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */ 320 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */ 321 }; 322 323 static int mma8452_get_power_mode(struct mma8452_data *data) 324 { 325 int reg; 326 327 reg = i2c_smbus_read_byte_data(data->client, 328 MMA8452_CTRL_REG2); 329 if (reg < 0) 330 return reg; 331 332 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >> 333 MMA8452_CTRL_REG2_MODS_SHIFT); 334 } 335 336 static ssize_t mma8452_show_samp_freq_avail(struct device *dev, 337 struct device_attribute *attr, 338 char *buf) 339 { 340 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq, 341 ARRAY_SIZE(mma8452_samp_freq)); 342 } 343 344 static ssize_t mma8452_show_scale_avail(struct device *dev, 345 struct device_attribute *attr, 346 char *buf) 347 { 348 struct mma8452_data *data = iio_priv(i2c_get_clientdata( 349 to_i2c_client(dev))); 350 351 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales, 352 ARRAY_SIZE(data->chip_info->mma_scales)); 353 } 354 355 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev, 356 struct device_attribute *attr, 357 char *buf) 358 { 359 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 360 struct mma8452_data *data = iio_priv(indio_dev); 361 int i, j; 362 363 i = mma8452_get_odr_index(data); 364 j = mma8452_get_power_mode(data); 365 if (j < 0) 366 return j; 367 368 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i], 369 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0])); 370 } 371 372 static ssize_t mma8452_show_os_ratio_avail(struct device *dev, 373 struct device_attribute *attr, 374 char *buf) 375 { 376 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 377 struct mma8452_data *data = iio_priv(indio_dev); 378 int i = mma8452_get_odr_index(data); 379 int j; 380 u16 val = 0; 381 size_t len = 0; 382 383 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) { 384 if (val == mma8452_os_ratio[j][i]) 385 continue; 386 387 val = mma8452_os_ratio[j][i]; 388 389 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val); 390 } 391 buf[len - 1] = '\n'; 392 393 return len; 394 } 395 396 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail); 397 static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO, 398 mma8452_show_scale_avail, NULL, 0); 399 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available, 400 S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0); 401 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, S_IRUGO, 402 mma8452_show_os_ratio_avail, NULL, 0); 403 404 static int mma8452_get_samp_freq_index(struct mma8452_data *data, 405 int val, int val2) 406 { 407 return mma8452_get_int_plus_micros_index(mma8452_samp_freq, 408 ARRAY_SIZE(mma8452_samp_freq), 409 val, val2); 410 } 411 412 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2) 413 { 414 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales, 415 ARRAY_SIZE(data->chip_info->mma_scales), val, val2); 416 } 417 418 static int mma8452_get_hp_filter_index(struct mma8452_data *data, 419 int val, int val2) 420 { 421 int i, j; 422 423 i = mma8452_get_odr_index(data); 424 j = mma8452_get_power_mode(data); 425 if (j < 0) 426 return j; 427 428 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i], 429 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2); 430 } 431 432 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz) 433 { 434 int j, i, ret; 435 436 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF); 437 if (ret < 0) 438 return ret; 439 440 i = mma8452_get_odr_index(data); 441 j = mma8452_get_power_mode(data); 442 if (j < 0) 443 return j; 444 445 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 446 *hz = mma8452_hp_filter_cutoff[j][i][ret][0]; 447 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1]; 448 449 return 0; 450 } 451 452 static int mma8452_read_raw(struct iio_dev *indio_dev, 453 struct iio_chan_spec const *chan, 454 int *val, int *val2, long mask) 455 { 456 struct mma8452_data *data = iio_priv(indio_dev); 457 __be16 buffer[3]; 458 int i, ret; 459 460 switch (mask) { 461 case IIO_CHAN_INFO_RAW: 462 if (iio_buffer_enabled(indio_dev)) 463 return -EBUSY; 464 465 mutex_lock(&data->lock); 466 ret = mma8452_read(data, buffer); 467 mutex_unlock(&data->lock); 468 if (ret < 0) 469 return ret; 470 471 *val = sign_extend32(be16_to_cpu( 472 buffer[chan->scan_index]) >> chan->scan_type.shift, 473 chan->scan_type.realbits - 1); 474 475 return IIO_VAL_INT; 476 case IIO_CHAN_INFO_SCALE: 477 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK; 478 *val = data->chip_info->mma_scales[i][0]; 479 *val2 = data->chip_info->mma_scales[i][1]; 480 481 return IIO_VAL_INT_PLUS_MICRO; 482 case IIO_CHAN_INFO_SAMP_FREQ: 483 i = mma8452_get_odr_index(data); 484 *val = mma8452_samp_freq[i][0]; 485 *val2 = mma8452_samp_freq[i][1]; 486 487 return IIO_VAL_INT_PLUS_MICRO; 488 case IIO_CHAN_INFO_CALIBBIAS: 489 ret = i2c_smbus_read_byte_data(data->client, 490 MMA8452_OFF_X + 491 chan->scan_index); 492 if (ret < 0) 493 return ret; 494 495 *val = sign_extend32(ret, 7); 496 497 return IIO_VAL_INT; 498 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 499 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) { 500 ret = mma8452_read_hp_filter(data, val, val2); 501 if (ret < 0) 502 return ret; 503 } else { 504 *val = 0; 505 *val2 = 0; 506 } 507 508 return IIO_VAL_INT_PLUS_MICRO; 509 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 510 ret = mma8452_get_power_mode(data); 511 if (ret < 0) 512 return ret; 513 514 i = mma8452_get_odr_index(data); 515 516 *val = mma8452_os_ratio[ret][i]; 517 return IIO_VAL_INT; 518 } 519 520 return -EINVAL; 521 } 522 523 static int mma8452_standby(struct mma8452_data *data) 524 { 525 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 526 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE); 527 } 528 529 static int mma8452_active(struct mma8452_data *data) 530 { 531 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1, 532 data->ctrl_reg1); 533 } 534 535 /* returns >0 if active, 0 if in standby and <0 on error */ 536 static int mma8452_is_active(struct mma8452_data *data) 537 { 538 int reg; 539 540 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1); 541 if (reg < 0) 542 return reg; 543 544 return reg & MMA8452_CTRL_ACTIVE; 545 } 546 547 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val) 548 { 549 int ret; 550 int is_active; 551 552 mutex_lock(&data->lock); 553 554 is_active = mma8452_is_active(data); 555 if (is_active < 0) { 556 ret = is_active; 557 goto fail; 558 } 559 560 /* config can only be changed when in standby */ 561 if (is_active > 0) { 562 ret = mma8452_standby(data); 563 if (ret < 0) 564 goto fail; 565 } 566 567 ret = i2c_smbus_write_byte_data(data->client, reg, val); 568 if (ret < 0) 569 goto fail; 570 571 if (is_active > 0) { 572 ret = mma8452_active(data); 573 if (ret < 0) 574 goto fail; 575 } 576 577 ret = 0; 578 fail: 579 mutex_unlock(&data->lock); 580 581 return ret; 582 } 583 584 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode) 585 { 586 int reg; 587 588 reg = i2c_smbus_read_byte_data(data->client, 589 MMA8452_CTRL_REG2); 590 if (reg < 0) 591 return reg; 592 593 reg &= ~MMA8452_CTRL_REG2_MODS_MASK; 594 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT; 595 596 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg); 597 } 598 599 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */ 600 static int mma8452_freefall_mode_enabled(struct mma8452_data *data) 601 { 602 int val; 603 const struct mma_chip_info *chip = data->chip_info; 604 605 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg); 606 if (val < 0) 607 return val; 608 609 return !(val & MMA8452_FF_MT_CFG_OAE); 610 } 611 612 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state) 613 { 614 int val; 615 const struct mma_chip_info *chip = data->chip_info; 616 617 if ((state && mma8452_freefall_mode_enabled(data)) || 618 (!state && !(mma8452_freefall_mode_enabled(data)))) 619 return 0; 620 621 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg); 622 if (val < 0) 623 return val; 624 625 if (state) { 626 val |= BIT(idx_x + chip->ev_cfg_chan_shift); 627 val |= BIT(idx_y + chip->ev_cfg_chan_shift); 628 val |= BIT(idx_z + chip->ev_cfg_chan_shift); 629 val &= ~MMA8452_FF_MT_CFG_OAE; 630 } else { 631 val &= ~BIT(idx_x + chip->ev_cfg_chan_shift); 632 val &= ~BIT(idx_y + chip->ev_cfg_chan_shift); 633 val &= ~BIT(idx_z + chip->ev_cfg_chan_shift); 634 val |= MMA8452_FF_MT_CFG_OAE; 635 } 636 637 return mma8452_change_config(data, chip->ev_cfg, val); 638 } 639 640 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data, 641 int val, int val2) 642 { 643 int i, reg; 644 645 i = mma8452_get_hp_filter_index(data, val, val2); 646 if (i < 0) 647 return i; 648 649 reg = i2c_smbus_read_byte_data(data->client, 650 MMA8452_HP_FILTER_CUTOFF); 651 if (reg < 0) 652 return reg; 653 654 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK; 655 reg |= i; 656 657 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg); 658 } 659 660 static int mma8452_write_raw(struct iio_dev *indio_dev, 661 struct iio_chan_spec const *chan, 662 int val, int val2, long mask) 663 { 664 struct mma8452_data *data = iio_priv(indio_dev); 665 int i, ret; 666 667 if (iio_buffer_enabled(indio_dev)) 668 return -EBUSY; 669 670 switch (mask) { 671 case IIO_CHAN_INFO_SAMP_FREQ: 672 i = mma8452_get_samp_freq_index(data, val, val2); 673 if (i < 0) 674 return i; 675 676 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK; 677 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT; 678 679 return mma8452_change_config(data, MMA8452_CTRL_REG1, 680 data->ctrl_reg1); 681 case IIO_CHAN_INFO_SCALE: 682 i = mma8452_get_scale_index(data, val, val2); 683 if (i < 0) 684 return i; 685 686 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK; 687 data->data_cfg |= i; 688 689 return mma8452_change_config(data, MMA8452_DATA_CFG, 690 data->data_cfg); 691 case IIO_CHAN_INFO_CALIBBIAS: 692 if (val < -128 || val > 127) 693 return -EINVAL; 694 695 return mma8452_change_config(data, 696 MMA8452_OFF_X + chan->scan_index, 697 val); 698 699 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY: 700 if (val == 0 && val2 == 0) { 701 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK; 702 } else { 703 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK; 704 ret = mma8452_set_hp_filter_frequency(data, val, val2); 705 if (ret < 0) 706 return ret; 707 } 708 709 return mma8452_change_config(data, MMA8452_DATA_CFG, 710 data->data_cfg); 711 712 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 713 ret = mma8452_get_odr_index(data); 714 715 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) { 716 if (mma8452_os_ratio[i][ret] == val) 717 return mma8452_set_power_mode(data, i); 718 } 719 720 default: 721 return -EINVAL; 722 } 723 } 724 725 static int mma8452_read_thresh(struct iio_dev *indio_dev, 726 const struct iio_chan_spec *chan, 727 enum iio_event_type type, 728 enum iio_event_direction dir, 729 enum iio_event_info info, 730 int *val, int *val2) 731 { 732 struct mma8452_data *data = iio_priv(indio_dev); 733 int ret, us, power_mode; 734 735 switch (info) { 736 case IIO_EV_INFO_VALUE: 737 ret = i2c_smbus_read_byte_data(data->client, 738 data->chip_info->ev_ths); 739 if (ret < 0) 740 return ret; 741 742 *val = ret & data->chip_info->ev_ths_mask; 743 744 return IIO_VAL_INT; 745 746 case IIO_EV_INFO_PERIOD: 747 ret = i2c_smbus_read_byte_data(data->client, 748 data->chip_info->ev_count); 749 if (ret < 0) 750 return ret; 751 752 power_mode = mma8452_get_power_mode(data); 753 if (power_mode < 0) 754 return power_mode; 755 756 us = ret * mma8452_transient_time_step_us[power_mode][ 757 mma8452_get_odr_index(data)]; 758 *val = us / USEC_PER_SEC; 759 *val2 = us % USEC_PER_SEC; 760 761 return IIO_VAL_INT_PLUS_MICRO; 762 763 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 764 ret = i2c_smbus_read_byte_data(data->client, 765 MMA8452_TRANSIENT_CFG); 766 if (ret < 0) 767 return ret; 768 769 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) { 770 *val = 0; 771 *val2 = 0; 772 } else { 773 ret = mma8452_read_hp_filter(data, val, val2); 774 if (ret < 0) 775 return ret; 776 } 777 778 return IIO_VAL_INT_PLUS_MICRO; 779 780 default: 781 return -EINVAL; 782 } 783 } 784 785 static int mma8452_write_thresh(struct iio_dev *indio_dev, 786 const struct iio_chan_spec *chan, 787 enum iio_event_type type, 788 enum iio_event_direction dir, 789 enum iio_event_info info, 790 int val, int val2) 791 { 792 struct mma8452_data *data = iio_priv(indio_dev); 793 int ret, reg, steps; 794 795 switch (info) { 796 case IIO_EV_INFO_VALUE: 797 if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK) 798 return -EINVAL; 799 800 return mma8452_change_config(data, data->chip_info->ev_ths, 801 val); 802 803 case IIO_EV_INFO_PERIOD: 804 ret = mma8452_get_power_mode(data); 805 if (ret < 0) 806 return ret; 807 808 steps = (val * USEC_PER_SEC + val2) / 809 mma8452_transient_time_step_us[ret][ 810 mma8452_get_odr_index(data)]; 811 812 if (steps < 0 || steps > 0xff) 813 return -EINVAL; 814 815 return mma8452_change_config(data, data->chip_info->ev_count, 816 steps); 817 818 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB: 819 reg = i2c_smbus_read_byte_data(data->client, 820 MMA8452_TRANSIENT_CFG); 821 if (reg < 0) 822 return reg; 823 824 if (val == 0 && val2 == 0) { 825 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP; 826 } else { 827 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP; 828 ret = mma8452_set_hp_filter_frequency(data, val, val2); 829 if (ret < 0) 830 return ret; 831 } 832 833 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg); 834 835 default: 836 return -EINVAL; 837 } 838 } 839 840 static int mma8452_read_event_config(struct iio_dev *indio_dev, 841 const struct iio_chan_spec *chan, 842 enum iio_event_type type, 843 enum iio_event_direction dir) 844 { 845 struct mma8452_data *data = iio_priv(indio_dev); 846 const struct mma_chip_info *chip = data->chip_info; 847 int ret; 848 849 switch (dir) { 850 case IIO_EV_DIR_FALLING: 851 return mma8452_freefall_mode_enabled(data); 852 case IIO_EV_DIR_RISING: 853 if (mma8452_freefall_mode_enabled(data)) 854 return 0; 855 856 ret = i2c_smbus_read_byte_data(data->client, 857 data->chip_info->ev_cfg); 858 if (ret < 0) 859 return ret; 860 861 return !!(ret & BIT(chan->scan_index + 862 chip->ev_cfg_chan_shift)); 863 default: 864 return -EINVAL; 865 } 866 } 867 868 static int mma8452_write_event_config(struct iio_dev *indio_dev, 869 const struct iio_chan_spec *chan, 870 enum iio_event_type type, 871 enum iio_event_direction dir, 872 int state) 873 { 874 struct mma8452_data *data = iio_priv(indio_dev); 875 const struct mma_chip_info *chip = data->chip_info; 876 int val, ret; 877 878 ret = mma8452_set_runtime_pm_state(data->client, state); 879 if (ret) 880 return ret; 881 882 switch (dir) { 883 case IIO_EV_DIR_FALLING: 884 return mma8452_set_freefall_mode(data, state); 885 case IIO_EV_DIR_RISING: 886 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg); 887 if (val < 0) 888 return val; 889 890 if (state) { 891 if (mma8452_freefall_mode_enabled(data)) { 892 val &= ~BIT(idx_x + chip->ev_cfg_chan_shift); 893 val &= ~BIT(idx_y + chip->ev_cfg_chan_shift); 894 val &= ~BIT(idx_z + chip->ev_cfg_chan_shift); 895 val |= MMA8452_FF_MT_CFG_OAE; 896 } 897 val |= BIT(chan->scan_index + chip->ev_cfg_chan_shift); 898 } else { 899 if (mma8452_freefall_mode_enabled(data)) 900 return 0; 901 902 val &= ~BIT(chan->scan_index + chip->ev_cfg_chan_shift); 903 } 904 905 val |= chip->ev_cfg_ele; 906 907 return mma8452_change_config(data, chip->ev_cfg, val); 908 default: 909 return -EINVAL; 910 } 911 } 912 913 static void mma8452_transient_interrupt(struct iio_dev *indio_dev) 914 { 915 struct mma8452_data *data = iio_priv(indio_dev); 916 s64 ts = iio_get_time_ns(indio_dev); 917 int src; 918 919 src = i2c_smbus_read_byte_data(data->client, data->chip_info->ev_src); 920 if (src < 0) 921 return; 922 923 if (mma8452_freefall_mode_enabled(data)) { 924 iio_push_event(indio_dev, 925 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, 926 IIO_MOD_X_AND_Y_AND_Z, 927 IIO_EV_TYPE_MAG, 928 IIO_EV_DIR_FALLING), 929 ts); 930 return; 931 } 932 933 if (src & data->chip_info->ev_src_xe) 934 iio_push_event(indio_dev, 935 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 936 IIO_EV_TYPE_MAG, 937 IIO_EV_DIR_RISING), 938 ts); 939 940 if (src & data->chip_info->ev_src_ye) 941 iio_push_event(indio_dev, 942 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y, 943 IIO_EV_TYPE_MAG, 944 IIO_EV_DIR_RISING), 945 ts); 946 947 if (src & data->chip_info->ev_src_ze) 948 iio_push_event(indio_dev, 949 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z, 950 IIO_EV_TYPE_MAG, 951 IIO_EV_DIR_RISING), 952 ts); 953 } 954 955 static irqreturn_t mma8452_interrupt(int irq, void *p) 956 { 957 struct iio_dev *indio_dev = p; 958 struct mma8452_data *data = iio_priv(indio_dev); 959 const struct mma_chip_info *chip = data->chip_info; 960 int ret = IRQ_NONE; 961 int src; 962 963 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC); 964 if (src < 0) 965 return IRQ_NONE; 966 967 if (src & MMA8452_INT_DRDY) { 968 iio_trigger_poll_chained(indio_dev->trig); 969 ret = IRQ_HANDLED; 970 } 971 972 if ((src & MMA8452_INT_TRANS && 973 chip->ev_src == MMA8452_TRANSIENT_SRC) || 974 (src & MMA8452_INT_FF_MT && 975 chip->ev_src == MMA8452_FF_MT_SRC)) { 976 mma8452_transient_interrupt(indio_dev); 977 ret = IRQ_HANDLED; 978 } 979 980 return ret; 981 } 982 983 static irqreturn_t mma8452_trigger_handler(int irq, void *p) 984 { 985 struct iio_poll_func *pf = p; 986 struct iio_dev *indio_dev = pf->indio_dev; 987 struct mma8452_data *data = iio_priv(indio_dev); 988 u8 buffer[16]; /* 3 16-bit channels + padding + ts */ 989 int ret; 990 991 ret = mma8452_read(data, (__be16 *)buffer); 992 if (ret < 0) 993 goto done; 994 995 iio_push_to_buffers_with_timestamp(indio_dev, buffer, 996 iio_get_time_ns(indio_dev)); 997 998 done: 999 iio_trigger_notify_done(indio_dev->trig); 1000 1001 return IRQ_HANDLED; 1002 } 1003 1004 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev, 1005 unsigned reg, unsigned writeval, 1006 unsigned *readval) 1007 { 1008 int ret; 1009 struct mma8452_data *data = iio_priv(indio_dev); 1010 1011 if (reg > MMA8452_MAX_REG) 1012 return -EINVAL; 1013 1014 if (!readval) 1015 return mma8452_change_config(data, reg, writeval); 1016 1017 ret = i2c_smbus_read_byte_data(data->client, reg); 1018 if (ret < 0) 1019 return ret; 1020 1021 *readval = ret; 1022 1023 return 0; 1024 } 1025 1026 static const struct iio_event_spec mma8452_freefall_event[] = { 1027 { 1028 .type = IIO_EV_TYPE_MAG, 1029 .dir = IIO_EV_DIR_FALLING, 1030 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1031 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1032 BIT(IIO_EV_INFO_PERIOD) | 1033 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1034 }, 1035 }; 1036 1037 static const struct iio_event_spec mma8652_freefall_event[] = { 1038 { 1039 .type = IIO_EV_TYPE_MAG, 1040 .dir = IIO_EV_DIR_FALLING, 1041 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1042 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1043 BIT(IIO_EV_INFO_PERIOD) 1044 }, 1045 }; 1046 1047 static const struct iio_event_spec mma8452_transient_event[] = { 1048 { 1049 .type = IIO_EV_TYPE_MAG, 1050 .dir = IIO_EV_DIR_RISING, 1051 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1052 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1053 BIT(IIO_EV_INFO_PERIOD) | 1054 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB) 1055 }, 1056 }; 1057 1058 static const struct iio_event_spec mma8452_motion_event[] = { 1059 { 1060 .type = IIO_EV_TYPE_MAG, 1061 .dir = IIO_EV_DIR_RISING, 1062 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 1063 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) | 1064 BIT(IIO_EV_INFO_PERIOD) 1065 }, 1066 }; 1067 1068 /* 1069 * Threshold is configured in fixed 8G/127 steps regardless of 1070 * currently selected scale for measurement. 1071 */ 1072 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742"); 1073 1074 static struct attribute *mma8452_event_attributes[] = { 1075 &iio_const_attr_accel_transient_scale.dev_attr.attr, 1076 NULL, 1077 }; 1078 1079 static struct attribute_group mma8452_event_attribute_group = { 1080 .attrs = mma8452_event_attributes, 1081 }; 1082 1083 #define MMA8452_FREEFALL_CHANNEL(modifier) { \ 1084 .type = IIO_ACCEL, \ 1085 .modified = 1, \ 1086 .channel2 = modifier, \ 1087 .scan_index = -1, \ 1088 .event_spec = mma8452_freefall_event, \ 1089 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \ 1090 } 1091 1092 #define MMA8652_FREEFALL_CHANNEL(modifier) { \ 1093 .type = IIO_ACCEL, \ 1094 .modified = 1, \ 1095 .channel2 = modifier, \ 1096 .scan_index = -1, \ 1097 .event_spec = mma8652_freefall_event, \ 1098 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \ 1099 } 1100 1101 #define MMA8452_CHANNEL(axis, idx, bits) { \ 1102 .type = IIO_ACCEL, \ 1103 .modified = 1, \ 1104 .channel2 = IIO_MOD_##axis, \ 1105 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1106 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1107 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1108 BIT(IIO_CHAN_INFO_SCALE) | \ 1109 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \ 1110 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1111 .scan_index = idx, \ 1112 .scan_type = { \ 1113 .sign = 's', \ 1114 .realbits = (bits), \ 1115 .storagebits = 16, \ 1116 .shift = 16 - (bits), \ 1117 .endianness = IIO_BE, \ 1118 }, \ 1119 .event_spec = mma8452_transient_event, \ 1120 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \ 1121 } 1122 1123 #define MMA8652_CHANNEL(axis, idx, bits) { \ 1124 .type = IIO_ACCEL, \ 1125 .modified = 1, \ 1126 .channel2 = IIO_MOD_##axis, \ 1127 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1128 BIT(IIO_CHAN_INFO_CALIBBIAS), \ 1129 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \ 1130 BIT(IIO_CHAN_INFO_SCALE) | \ 1131 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 1132 .scan_index = idx, \ 1133 .scan_type = { \ 1134 .sign = 's', \ 1135 .realbits = (bits), \ 1136 .storagebits = 16, \ 1137 .shift = 16 - (bits), \ 1138 .endianness = IIO_BE, \ 1139 }, \ 1140 .event_spec = mma8452_motion_event, \ 1141 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \ 1142 } 1143 1144 static const struct iio_chan_spec mma8451_channels[] = { 1145 MMA8452_CHANNEL(X, idx_x, 14), 1146 MMA8452_CHANNEL(Y, idx_y, 14), 1147 MMA8452_CHANNEL(Z, idx_z, 14), 1148 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1149 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1150 }; 1151 1152 static const struct iio_chan_spec mma8452_channels[] = { 1153 MMA8452_CHANNEL(X, idx_x, 12), 1154 MMA8452_CHANNEL(Y, idx_y, 12), 1155 MMA8452_CHANNEL(Z, idx_z, 12), 1156 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1157 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1158 }; 1159 1160 static const struct iio_chan_spec mma8453_channels[] = { 1161 MMA8452_CHANNEL(X, idx_x, 10), 1162 MMA8452_CHANNEL(Y, idx_y, 10), 1163 MMA8452_CHANNEL(Z, idx_z, 10), 1164 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1165 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1166 }; 1167 1168 static const struct iio_chan_spec mma8652_channels[] = { 1169 MMA8652_CHANNEL(X, idx_x, 12), 1170 MMA8652_CHANNEL(Y, idx_y, 12), 1171 MMA8652_CHANNEL(Z, idx_z, 12), 1172 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1173 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1174 }; 1175 1176 static const struct iio_chan_spec mma8653_channels[] = { 1177 MMA8652_CHANNEL(X, idx_x, 10), 1178 MMA8652_CHANNEL(Y, idx_y, 10), 1179 MMA8652_CHANNEL(Z, idx_z, 10), 1180 IIO_CHAN_SOFT_TIMESTAMP(idx_ts), 1181 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z), 1182 }; 1183 1184 enum { 1185 mma8451, 1186 mma8452, 1187 mma8453, 1188 mma8652, 1189 mma8653, 1190 fxls8471, 1191 }; 1192 1193 static const struct mma_chip_info mma_chip_info_table[] = { 1194 [mma8451] = { 1195 .chip_id = MMA8451_DEVICE_ID, 1196 .channels = mma8451_channels, 1197 .num_channels = ARRAY_SIZE(mma8451_channels), 1198 /* 1199 * Hardware has fullscale of -2G, -4G, -8G corresponding to 1200 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10 1201 * bit. 1202 * The userspace interface uses m/s^2 and we declare micro units 1203 * So scale factor for 12 bit here is given by: 1204 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665 1205 */ 1206 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1207 .ev_cfg = MMA8452_TRANSIENT_CFG, 1208 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE, 1209 .ev_cfg_chan_shift = 1, 1210 .ev_src = MMA8452_TRANSIENT_SRC, 1211 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE, 1212 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE, 1213 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE, 1214 .ev_ths = MMA8452_TRANSIENT_THS, 1215 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK, 1216 .ev_count = MMA8452_TRANSIENT_COUNT, 1217 }, 1218 [mma8452] = { 1219 .chip_id = MMA8452_DEVICE_ID, 1220 .channels = mma8452_channels, 1221 .num_channels = ARRAY_SIZE(mma8452_channels), 1222 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1223 .ev_cfg = MMA8452_TRANSIENT_CFG, 1224 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE, 1225 .ev_cfg_chan_shift = 1, 1226 .ev_src = MMA8452_TRANSIENT_SRC, 1227 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE, 1228 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE, 1229 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE, 1230 .ev_ths = MMA8452_TRANSIENT_THS, 1231 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK, 1232 .ev_count = MMA8452_TRANSIENT_COUNT, 1233 }, 1234 [mma8453] = { 1235 .chip_id = MMA8453_DEVICE_ID, 1236 .channels = mma8453_channels, 1237 .num_channels = ARRAY_SIZE(mma8453_channels), 1238 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1239 .ev_cfg = MMA8452_TRANSIENT_CFG, 1240 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE, 1241 .ev_cfg_chan_shift = 1, 1242 .ev_src = MMA8452_TRANSIENT_SRC, 1243 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE, 1244 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE, 1245 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE, 1246 .ev_ths = MMA8452_TRANSIENT_THS, 1247 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK, 1248 .ev_count = MMA8452_TRANSIENT_COUNT, 1249 }, 1250 [mma8652] = { 1251 .chip_id = MMA8652_DEVICE_ID, 1252 .channels = mma8652_channels, 1253 .num_channels = ARRAY_SIZE(mma8652_channels), 1254 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} }, 1255 .ev_cfg = MMA8452_FF_MT_CFG, 1256 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE, 1257 .ev_cfg_chan_shift = 3, 1258 .ev_src = MMA8452_FF_MT_SRC, 1259 .ev_src_xe = MMA8452_FF_MT_SRC_XHE, 1260 .ev_src_ye = MMA8452_FF_MT_SRC_YHE, 1261 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE, 1262 .ev_ths = MMA8452_FF_MT_THS, 1263 .ev_ths_mask = MMA8452_FF_MT_THS_MASK, 1264 .ev_count = MMA8452_FF_MT_COUNT, 1265 }, 1266 [mma8653] = { 1267 .chip_id = MMA8653_DEVICE_ID, 1268 .channels = mma8653_channels, 1269 .num_channels = ARRAY_SIZE(mma8653_channels), 1270 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} }, 1271 .ev_cfg = MMA8452_FF_MT_CFG, 1272 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE, 1273 .ev_cfg_chan_shift = 3, 1274 .ev_src = MMA8452_FF_MT_SRC, 1275 .ev_src_xe = MMA8452_FF_MT_SRC_XHE, 1276 .ev_src_ye = MMA8452_FF_MT_SRC_YHE, 1277 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE, 1278 .ev_ths = MMA8452_FF_MT_THS, 1279 .ev_ths_mask = MMA8452_FF_MT_THS_MASK, 1280 .ev_count = MMA8452_FF_MT_COUNT, 1281 }, 1282 [fxls8471] = { 1283 .chip_id = FXLS8471_DEVICE_ID, 1284 .channels = mma8451_channels, 1285 .num_channels = ARRAY_SIZE(mma8451_channels), 1286 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} }, 1287 .ev_cfg = MMA8452_TRANSIENT_CFG, 1288 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE, 1289 .ev_cfg_chan_shift = 1, 1290 .ev_src = MMA8452_TRANSIENT_SRC, 1291 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE, 1292 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE, 1293 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE, 1294 .ev_ths = MMA8452_TRANSIENT_THS, 1295 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK, 1296 .ev_count = MMA8452_TRANSIENT_COUNT, 1297 }, 1298 }; 1299 1300 static struct attribute *mma8452_attributes[] = { 1301 &iio_dev_attr_sampling_frequency_available.dev_attr.attr, 1302 &iio_dev_attr_in_accel_scale_available.dev_attr.attr, 1303 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr, 1304 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr, 1305 NULL 1306 }; 1307 1308 static const struct attribute_group mma8452_group = { 1309 .attrs = mma8452_attributes, 1310 }; 1311 1312 static const struct iio_info mma8452_info = { 1313 .attrs = &mma8452_group, 1314 .read_raw = &mma8452_read_raw, 1315 .write_raw = &mma8452_write_raw, 1316 .event_attrs = &mma8452_event_attribute_group, 1317 .read_event_value = &mma8452_read_thresh, 1318 .write_event_value = &mma8452_write_thresh, 1319 .read_event_config = &mma8452_read_event_config, 1320 .write_event_config = &mma8452_write_event_config, 1321 .debugfs_reg_access = &mma8452_reg_access_dbg, 1322 .driver_module = THIS_MODULE, 1323 }; 1324 1325 static const unsigned long mma8452_scan_masks[] = {0x7, 0}; 1326 1327 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig, 1328 bool state) 1329 { 1330 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig); 1331 struct mma8452_data *data = iio_priv(indio_dev); 1332 int reg, ret; 1333 1334 ret = mma8452_set_runtime_pm_state(data->client, state); 1335 if (ret) 1336 return ret; 1337 1338 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4); 1339 if (reg < 0) 1340 return reg; 1341 1342 if (state) 1343 reg |= MMA8452_INT_DRDY; 1344 else 1345 reg &= ~MMA8452_INT_DRDY; 1346 1347 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg); 1348 } 1349 1350 static int mma8452_validate_device(struct iio_trigger *trig, 1351 struct iio_dev *indio_dev) 1352 { 1353 struct iio_dev *indio = iio_trigger_get_drvdata(trig); 1354 1355 if (indio != indio_dev) 1356 return -EINVAL; 1357 1358 return 0; 1359 } 1360 1361 static const struct iio_trigger_ops mma8452_trigger_ops = { 1362 .set_trigger_state = mma8452_data_rdy_trigger_set_state, 1363 .validate_device = mma8452_validate_device, 1364 .owner = THIS_MODULE, 1365 }; 1366 1367 static int mma8452_trigger_setup(struct iio_dev *indio_dev) 1368 { 1369 struct mma8452_data *data = iio_priv(indio_dev); 1370 struct iio_trigger *trig; 1371 int ret; 1372 1373 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d", 1374 indio_dev->name, 1375 indio_dev->id); 1376 if (!trig) 1377 return -ENOMEM; 1378 1379 trig->dev.parent = &data->client->dev; 1380 trig->ops = &mma8452_trigger_ops; 1381 iio_trigger_set_drvdata(trig, indio_dev); 1382 1383 ret = iio_trigger_register(trig); 1384 if (ret) 1385 return ret; 1386 1387 indio_dev->trig = trig; 1388 1389 return 0; 1390 } 1391 1392 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev) 1393 { 1394 if (indio_dev->trig) 1395 iio_trigger_unregister(indio_dev->trig); 1396 } 1397 1398 static int mma8452_reset(struct i2c_client *client) 1399 { 1400 int i; 1401 int ret; 1402 1403 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2, 1404 MMA8452_CTRL_REG2_RST); 1405 if (ret < 0) 1406 return ret; 1407 1408 for (i = 0; i < 10; i++) { 1409 usleep_range(100, 200); 1410 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2); 1411 if (ret == -EIO) 1412 continue; /* I2C comm reset */ 1413 if (ret < 0) 1414 return ret; 1415 if (!(ret & MMA8452_CTRL_REG2_RST)) 1416 return 0; 1417 } 1418 1419 return -ETIMEDOUT; 1420 } 1421 1422 static const struct of_device_id mma8452_dt_ids[] = { 1423 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] }, 1424 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] }, 1425 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] }, 1426 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] }, 1427 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] }, 1428 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] }, 1429 { } 1430 }; 1431 MODULE_DEVICE_TABLE(of, mma8452_dt_ids); 1432 1433 static int mma8452_probe(struct i2c_client *client, 1434 const struct i2c_device_id *id) 1435 { 1436 struct mma8452_data *data; 1437 struct iio_dev *indio_dev; 1438 int ret; 1439 const struct of_device_id *match; 1440 1441 match = of_match_device(mma8452_dt_ids, &client->dev); 1442 if (!match) { 1443 dev_err(&client->dev, "unknown device model\n"); 1444 return -ENODEV; 1445 } 1446 1447 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data)); 1448 if (!indio_dev) 1449 return -ENOMEM; 1450 1451 data = iio_priv(indio_dev); 1452 data->client = client; 1453 mutex_init(&data->lock); 1454 data->chip_info = match->data; 1455 1456 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I); 1457 if (ret < 0) 1458 return ret; 1459 1460 switch (ret) { 1461 case MMA8451_DEVICE_ID: 1462 case MMA8452_DEVICE_ID: 1463 case MMA8453_DEVICE_ID: 1464 case MMA8652_DEVICE_ID: 1465 case MMA8653_DEVICE_ID: 1466 case FXLS8471_DEVICE_ID: 1467 if (ret == data->chip_info->chip_id) 1468 break; 1469 default: 1470 return -ENODEV; 1471 } 1472 1473 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n", 1474 match->compatible, data->chip_info->chip_id); 1475 1476 i2c_set_clientdata(client, indio_dev); 1477 indio_dev->info = &mma8452_info; 1478 indio_dev->name = id->name; 1479 indio_dev->dev.parent = &client->dev; 1480 indio_dev->modes = INDIO_DIRECT_MODE; 1481 indio_dev->channels = data->chip_info->channels; 1482 indio_dev->num_channels = data->chip_info->num_channels; 1483 indio_dev->available_scan_masks = mma8452_scan_masks; 1484 1485 ret = mma8452_reset(client); 1486 if (ret < 0) 1487 return ret; 1488 1489 data->data_cfg = MMA8452_DATA_CFG_FS_2G; 1490 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG, 1491 data->data_cfg); 1492 if (ret < 0) 1493 return ret; 1494 1495 /* 1496 * By default set transient threshold to max to avoid events if 1497 * enabling without configuring threshold. 1498 */ 1499 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS, 1500 MMA8452_TRANSIENT_THS_MASK); 1501 if (ret < 0) 1502 return ret; 1503 1504 if (client->irq) { 1505 /* 1506 * Although we enable the interrupt sources once and for 1507 * all here the event detection itself is not enabled until 1508 * userspace asks for it by mma8452_write_event_config() 1509 */ 1510 int supported_interrupts = MMA8452_INT_DRDY | 1511 MMA8452_INT_TRANS | 1512 MMA8452_INT_FF_MT; 1513 int enabled_interrupts = MMA8452_INT_TRANS | 1514 MMA8452_INT_FF_MT; 1515 int irq2; 1516 1517 irq2 = of_irq_get_byname(client->dev.of_node, "INT2"); 1518 1519 if (irq2 == client->irq) { 1520 dev_dbg(&client->dev, "using interrupt line INT2\n"); 1521 } else { 1522 ret = i2c_smbus_write_byte_data(client, 1523 MMA8452_CTRL_REG5, 1524 supported_interrupts); 1525 if (ret < 0) 1526 return ret; 1527 1528 dev_dbg(&client->dev, "using interrupt line INT1\n"); 1529 } 1530 1531 ret = i2c_smbus_write_byte_data(client, 1532 MMA8452_CTRL_REG4, 1533 enabled_interrupts); 1534 if (ret < 0) 1535 return ret; 1536 1537 ret = mma8452_trigger_setup(indio_dev); 1538 if (ret < 0) 1539 return ret; 1540 } 1541 1542 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE | 1543 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT); 1544 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1, 1545 data->ctrl_reg1); 1546 if (ret < 0) 1547 goto trigger_cleanup; 1548 1549 ret = iio_triggered_buffer_setup(indio_dev, NULL, 1550 mma8452_trigger_handler, NULL); 1551 if (ret < 0) 1552 goto trigger_cleanup; 1553 1554 if (client->irq) { 1555 ret = devm_request_threaded_irq(&client->dev, 1556 client->irq, 1557 NULL, mma8452_interrupt, 1558 IRQF_TRIGGER_LOW | IRQF_ONESHOT, 1559 client->name, indio_dev); 1560 if (ret) 1561 goto buffer_cleanup; 1562 } 1563 1564 ret = pm_runtime_set_active(&client->dev); 1565 if (ret < 0) 1566 goto buffer_cleanup; 1567 1568 pm_runtime_enable(&client->dev); 1569 pm_runtime_set_autosuspend_delay(&client->dev, 1570 MMA8452_AUTO_SUSPEND_DELAY_MS); 1571 pm_runtime_use_autosuspend(&client->dev); 1572 1573 ret = iio_device_register(indio_dev); 1574 if (ret < 0) 1575 goto buffer_cleanup; 1576 1577 ret = mma8452_set_freefall_mode(data, false); 1578 if (ret < 0) 1579 goto buffer_cleanup; 1580 1581 return 0; 1582 1583 buffer_cleanup: 1584 iio_triggered_buffer_cleanup(indio_dev); 1585 1586 trigger_cleanup: 1587 mma8452_trigger_cleanup(indio_dev); 1588 1589 return ret; 1590 } 1591 1592 static int mma8452_remove(struct i2c_client *client) 1593 { 1594 struct iio_dev *indio_dev = i2c_get_clientdata(client); 1595 1596 iio_device_unregister(indio_dev); 1597 1598 pm_runtime_disable(&client->dev); 1599 pm_runtime_set_suspended(&client->dev); 1600 pm_runtime_put_noidle(&client->dev); 1601 1602 iio_triggered_buffer_cleanup(indio_dev); 1603 mma8452_trigger_cleanup(indio_dev); 1604 mma8452_standby(iio_priv(indio_dev)); 1605 1606 return 0; 1607 } 1608 1609 #ifdef CONFIG_PM 1610 static int mma8452_runtime_suspend(struct device *dev) 1611 { 1612 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1613 struct mma8452_data *data = iio_priv(indio_dev); 1614 int ret; 1615 1616 mutex_lock(&data->lock); 1617 ret = mma8452_standby(data); 1618 mutex_unlock(&data->lock); 1619 if (ret < 0) { 1620 dev_err(&data->client->dev, "powering off device failed\n"); 1621 return -EAGAIN; 1622 } 1623 1624 return 0; 1625 } 1626 1627 static int mma8452_runtime_resume(struct device *dev) 1628 { 1629 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev)); 1630 struct mma8452_data *data = iio_priv(indio_dev); 1631 int ret, sleep_val; 1632 1633 ret = mma8452_active(data); 1634 if (ret < 0) 1635 return ret; 1636 1637 ret = mma8452_get_odr_index(data); 1638 sleep_val = 1000 / mma8452_samp_freq[ret][0]; 1639 if (sleep_val < 20) 1640 usleep_range(sleep_val * 1000, 20000); 1641 else 1642 msleep_interruptible(sleep_val); 1643 1644 return 0; 1645 } 1646 #endif 1647 1648 #ifdef CONFIG_PM_SLEEP 1649 static int mma8452_suspend(struct device *dev) 1650 { 1651 return mma8452_standby(iio_priv(i2c_get_clientdata( 1652 to_i2c_client(dev)))); 1653 } 1654 1655 static int mma8452_resume(struct device *dev) 1656 { 1657 return mma8452_active(iio_priv(i2c_get_clientdata( 1658 to_i2c_client(dev)))); 1659 } 1660 #endif 1661 1662 static const struct dev_pm_ops mma8452_pm_ops = { 1663 SET_SYSTEM_SLEEP_PM_OPS(mma8452_suspend, mma8452_resume) 1664 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend, 1665 mma8452_runtime_resume, NULL) 1666 }; 1667 1668 static const struct i2c_device_id mma8452_id[] = { 1669 { "mma8451", mma8451 }, 1670 { "mma8452", mma8452 }, 1671 { "mma8453", mma8453 }, 1672 { "mma8652", mma8652 }, 1673 { "mma8653", mma8653 }, 1674 { "fxls8471", fxls8471 }, 1675 { } 1676 }; 1677 MODULE_DEVICE_TABLE(i2c, mma8452_id); 1678 1679 static struct i2c_driver mma8452_driver = { 1680 .driver = { 1681 .name = "mma8452", 1682 .of_match_table = of_match_ptr(mma8452_dt_ids), 1683 .pm = &mma8452_pm_ops, 1684 }, 1685 .probe = mma8452_probe, 1686 .remove = mma8452_remove, 1687 .id_table = mma8452_id, 1688 }; 1689 module_i2c_driver(mma8452_driver); 1690 1691 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>"); 1692 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver"); 1693 MODULE_LICENSE("GPL"); 1694