1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NXP FXLS8962AF/FXLS8964AF Accelerometer Core Driver 4 * 5 * Copyright 2021 Connected Cars A/S 6 * 7 * Datasheet: 8 * https://www.nxp.com/docs/en/data-sheet/FXLS8962AF.pdf 9 * https://www.nxp.com/docs/en/data-sheet/FXLS8964AF.pdf 10 * 11 * Errata: 12 * https://www.nxp.com/docs/en/errata/ES_FXLS8962AF.pdf 13 */ 14 15 #include <linux/bits.h> 16 #include <linux/bitfield.h> 17 #include <linux/i2c.h> 18 #include <linux/module.h> 19 #include <linux/of_irq.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/regmap.h> 23 24 #include <linux/iio/buffer.h> 25 #include <linux/iio/iio.h> 26 #include <linux/iio/kfifo_buf.h> 27 #include <linux/iio/sysfs.h> 28 29 #include "fxls8962af.h" 30 31 #define FXLS8962AF_INT_STATUS 0x00 32 #define FXLS8962AF_INT_STATUS_SRC_BOOT BIT(0) 33 #define FXLS8962AF_INT_STATUS_SRC_BUF BIT(5) 34 #define FXLS8962AF_INT_STATUS_SRC_DRDY BIT(7) 35 #define FXLS8962AF_TEMP_OUT 0x01 36 #define FXLS8962AF_VECM_LSB 0x02 37 #define FXLS8962AF_OUT_X_LSB 0x04 38 #define FXLS8962AF_OUT_Y_LSB 0x06 39 #define FXLS8962AF_OUT_Z_LSB 0x08 40 #define FXLS8962AF_BUF_STATUS 0x0b 41 #define FXLS8962AF_BUF_STATUS_BUF_CNT GENMASK(5, 0) 42 #define FXLS8962AF_BUF_STATUS_BUF_OVF BIT(6) 43 #define FXLS8962AF_BUF_STATUS_BUF_WMRK BIT(7) 44 #define FXLS8962AF_BUF_X_LSB 0x0c 45 #define FXLS8962AF_BUF_Y_LSB 0x0e 46 #define FXLS8962AF_BUF_Z_LSB 0x10 47 48 #define FXLS8962AF_PROD_REV 0x12 49 #define FXLS8962AF_WHO_AM_I 0x13 50 51 #define FXLS8962AF_SYS_MODE 0x14 52 #define FXLS8962AF_SENS_CONFIG1 0x15 53 #define FXLS8962AF_SENS_CONFIG1_ACTIVE BIT(0) 54 #define FXLS8962AF_SENS_CONFIG1_RST BIT(7) 55 #define FXLS8962AF_SC1_FSR_MASK GENMASK(2, 1) 56 #define FXLS8962AF_SC1_FSR_PREP(x) FIELD_PREP(FXLS8962AF_SC1_FSR_MASK, (x)) 57 #define FXLS8962AF_SC1_FSR_GET(x) FIELD_GET(FXLS8962AF_SC1_FSR_MASK, (x)) 58 59 #define FXLS8962AF_SENS_CONFIG2 0x16 60 #define FXLS8962AF_SENS_CONFIG3 0x17 61 #define FXLS8962AF_SC3_WAKE_ODR_MASK GENMASK(7, 4) 62 #define FXLS8962AF_SC3_WAKE_ODR_PREP(x) FIELD_PREP(FXLS8962AF_SC3_WAKE_ODR_MASK, (x)) 63 #define FXLS8962AF_SC3_WAKE_ODR_GET(x) FIELD_GET(FXLS8962AF_SC3_WAKE_ODR_MASK, (x)) 64 #define FXLS8962AF_SENS_CONFIG4 0x18 65 #define FXLS8962AF_SC4_INT_PP_OD_MASK BIT(1) 66 #define FXLS8962AF_SC4_INT_PP_OD_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_PP_OD_MASK, (x)) 67 #define FXLS8962AF_SC4_INT_POL_MASK BIT(0) 68 #define FXLS8962AF_SC4_INT_POL_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_POL_MASK, (x)) 69 #define FXLS8962AF_SENS_CONFIG5 0x19 70 71 #define FXLS8962AF_WAKE_IDLE_LSB 0x1b 72 #define FXLS8962AF_SLEEP_IDLE_LSB 0x1c 73 #define FXLS8962AF_ASLP_COUNT_LSB 0x1e 74 75 #define FXLS8962AF_INT_EN 0x20 76 #define FXLS8962AF_INT_EN_BUF_EN BIT(6) 77 #define FXLS8962AF_INT_PIN_SEL 0x21 78 #define FXLS8962AF_INT_PIN_SEL_MASK GENMASK(7, 0) 79 #define FXLS8962AF_INT_PIN_SEL_INT1 0x00 80 #define FXLS8962AF_INT_PIN_SEL_INT2 GENMASK(7, 0) 81 82 #define FXLS8962AF_OFF_X 0x22 83 #define FXLS8962AF_OFF_Y 0x23 84 #define FXLS8962AF_OFF_Z 0x24 85 86 #define FXLS8962AF_BUF_CONFIG1 0x26 87 #define FXLS8962AF_BC1_BUF_MODE_MASK GENMASK(6, 5) 88 #define FXLS8962AF_BC1_BUF_MODE_PREP(x) FIELD_PREP(FXLS8962AF_BC1_BUF_MODE_MASK, (x)) 89 #define FXLS8962AF_BUF_CONFIG2 0x27 90 #define FXLS8962AF_BUF_CONFIG2_BUF_WMRK GENMASK(5, 0) 91 92 #define FXLS8962AF_ORIENT_STATUS 0x28 93 #define FXLS8962AF_ORIENT_CONFIG 0x29 94 #define FXLS8962AF_ORIENT_DBCOUNT 0x2a 95 #define FXLS8962AF_ORIENT_BF_ZCOMP 0x2b 96 #define FXLS8962AF_ORIENT_THS_REG 0x2c 97 98 #define FXLS8962AF_SDCD_INT_SRC1 0x2d 99 #define FXLS8962AF_SDCD_INT_SRC2 0x2e 100 #define FXLS8962AF_SDCD_CONFIG1 0x2f 101 #define FXLS8962AF_SDCD_CONFIG2 0x30 102 #define FXLS8962AF_SDCD_OT_DBCNT 0x31 103 #define FXLS8962AF_SDCD_WT_DBCNT 0x32 104 #define FXLS8962AF_SDCD_LTHS_LSB 0x33 105 #define FXLS8962AF_SDCD_UTHS_LSB 0x35 106 107 #define FXLS8962AF_SELF_TEST_CONFIG1 0x37 108 #define FXLS8962AF_SELF_TEST_CONFIG2 0x38 109 110 #define FXLS8962AF_MAX_REG 0x38 111 112 #define FXLS8962AF_DEVICE_ID 0x62 113 #define FXLS8964AF_DEVICE_ID 0x84 114 115 /* Raw temp channel offset */ 116 #define FXLS8962AF_TEMP_CENTER_VAL 25 117 118 #define FXLS8962AF_AUTO_SUSPEND_DELAY_MS 2000 119 120 #define FXLS8962AF_FIFO_LENGTH 32 121 #define FXLS8962AF_SCALE_TABLE_LEN 4 122 #define FXLS8962AF_SAMP_FREQ_TABLE_LEN 13 123 124 static const int fxls8962af_scale_table[FXLS8962AF_SCALE_TABLE_LEN][2] = { 125 {0, IIO_G_TO_M_S_2(980000)}, 126 {0, IIO_G_TO_M_S_2(1950000)}, 127 {0, IIO_G_TO_M_S_2(3910000)}, 128 {0, IIO_G_TO_M_S_2(7810000)}, 129 }; 130 131 static const int fxls8962af_samp_freq_table[FXLS8962AF_SAMP_FREQ_TABLE_LEN][2] = { 132 {3200, 0}, {1600, 0}, {800, 0}, {400, 0}, {200, 0}, {100, 0}, 133 {50, 0}, {25, 0}, {12, 500000}, {6, 250000}, {3, 125000}, 134 {1, 563000}, {0, 781000}, 135 }; 136 137 struct fxls8962af_chip_info { 138 const char *name; 139 const struct iio_chan_spec *channels; 140 int num_channels; 141 u8 chip_id; 142 }; 143 144 struct fxls8962af_data { 145 struct regmap *regmap; 146 const struct fxls8962af_chip_info *chip_info; 147 struct regulator *vdd_reg; 148 struct { 149 __le16 channels[3]; 150 s64 ts __aligned(8); 151 } scan; 152 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */ 153 struct iio_mount_matrix orientation; 154 u8 watermark; 155 }; 156 157 const struct regmap_config fxls8962af_regmap_conf = { 158 .reg_bits = 8, 159 .val_bits = 8, 160 .max_register = FXLS8962AF_MAX_REG, 161 }; 162 EXPORT_SYMBOL_GPL(fxls8962af_regmap_conf); 163 164 enum { 165 fxls8962af_idx_x, 166 fxls8962af_idx_y, 167 fxls8962af_idx_z, 168 fxls8962af_idx_ts, 169 }; 170 171 enum fxls8962af_int_pin { 172 FXLS8962AF_PIN_INT1, 173 FXLS8962AF_PIN_INT2, 174 }; 175 176 static int fxls8962af_power_on(struct fxls8962af_data *data) 177 { 178 struct device *dev = regmap_get_device(data->regmap); 179 int ret; 180 181 ret = pm_runtime_resume_and_get(dev); 182 if (ret) 183 dev_err(dev, "failed to power on\n"); 184 185 return ret; 186 } 187 188 static int fxls8962af_power_off(struct fxls8962af_data *data) 189 { 190 struct device *dev = regmap_get_device(data->regmap); 191 int ret; 192 193 pm_runtime_mark_last_busy(dev); 194 ret = pm_runtime_put_autosuspend(dev); 195 if (ret) 196 dev_err(dev, "failed to power off\n"); 197 198 return ret; 199 } 200 201 static int fxls8962af_standby(struct fxls8962af_data *data) 202 { 203 return regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 204 FXLS8962AF_SENS_CONFIG1_ACTIVE, 0); 205 } 206 207 static int fxls8962af_active(struct fxls8962af_data *data) 208 { 209 return regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 210 FXLS8962AF_SENS_CONFIG1_ACTIVE, 1); 211 } 212 213 static int fxls8962af_is_active(struct fxls8962af_data *data) 214 { 215 unsigned int reg; 216 int ret; 217 218 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, ®); 219 if (ret) 220 return ret; 221 222 return reg & FXLS8962AF_SENS_CONFIG1_ACTIVE; 223 } 224 225 static int fxls8962af_get_out(struct fxls8962af_data *data, 226 struct iio_chan_spec const *chan, int *val) 227 { 228 struct device *dev = regmap_get_device(data->regmap); 229 __le16 raw_val; 230 int is_active; 231 int ret; 232 233 is_active = fxls8962af_is_active(data); 234 if (!is_active) { 235 ret = fxls8962af_power_on(data); 236 if (ret) 237 return ret; 238 } 239 240 ret = regmap_bulk_read(data->regmap, chan->address, 241 &raw_val, (chan->scan_type.storagebits / 8)); 242 243 if (!is_active) 244 fxls8962af_power_off(data); 245 246 if (ret) { 247 dev_err(dev, "failed to get out reg 0x%lx\n", chan->address); 248 return ret; 249 } 250 251 *val = sign_extend32(le16_to_cpu(raw_val), 252 chan->scan_type.realbits - 1); 253 254 return IIO_VAL_INT; 255 } 256 257 static int fxls8962af_read_avail(struct iio_dev *indio_dev, 258 struct iio_chan_spec const *chan, 259 const int **vals, int *type, int *length, 260 long mask) 261 { 262 switch (mask) { 263 case IIO_CHAN_INFO_SCALE: 264 *type = IIO_VAL_INT_PLUS_NANO; 265 *vals = (int *)fxls8962af_scale_table; 266 *length = ARRAY_SIZE(fxls8962af_scale_table) * 2; 267 return IIO_AVAIL_LIST; 268 case IIO_CHAN_INFO_SAMP_FREQ: 269 *type = IIO_VAL_INT_PLUS_MICRO; 270 *vals = (int *)fxls8962af_samp_freq_table; 271 *length = ARRAY_SIZE(fxls8962af_samp_freq_table) * 2; 272 return IIO_AVAIL_LIST; 273 default: 274 return -EINVAL; 275 } 276 } 277 278 static int fxls8962af_write_raw_get_fmt(struct iio_dev *indio_dev, 279 struct iio_chan_spec const *chan, 280 long mask) 281 { 282 switch (mask) { 283 case IIO_CHAN_INFO_SCALE: 284 return IIO_VAL_INT_PLUS_NANO; 285 case IIO_CHAN_INFO_SAMP_FREQ: 286 return IIO_VAL_INT_PLUS_MICRO; 287 default: 288 return IIO_VAL_INT_PLUS_NANO; 289 } 290 } 291 292 static int fxls8962af_update_config(struct fxls8962af_data *data, u8 reg, 293 u8 mask, u8 val) 294 { 295 int ret; 296 int is_active; 297 298 is_active = fxls8962af_is_active(data); 299 if (is_active) { 300 ret = fxls8962af_standby(data); 301 if (ret) 302 return ret; 303 } 304 305 ret = regmap_update_bits(data->regmap, reg, mask, val); 306 if (ret) 307 return ret; 308 309 if (is_active) { 310 ret = fxls8962af_active(data); 311 if (ret) 312 return ret; 313 } 314 315 return 0; 316 } 317 318 static int fxls8962af_set_full_scale(struct fxls8962af_data *data, u32 scale) 319 { 320 int i; 321 322 for (i = 0; i < ARRAY_SIZE(fxls8962af_scale_table); i++) 323 if (scale == fxls8962af_scale_table[i][1]) 324 break; 325 326 if (i == ARRAY_SIZE(fxls8962af_scale_table)) 327 return -EINVAL; 328 329 return fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG1, 330 FXLS8962AF_SC1_FSR_MASK, 331 FXLS8962AF_SC1_FSR_PREP(i)); 332 } 333 334 static unsigned int fxls8962af_read_full_scale(struct fxls8962af_data *data, 335 int *val) 336 { 337 int ret; 338 unsigned int reg; 339 u8 range_idx; 340 341 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, ®); 342 if (ret) 343 return ret; 344 345 range_idx = FXLS8962AF_SC1_FSR_GET(reg); 346 347 *val = fxls8962af_scale_table[range_idx][1]; 348 349 return IIO_VAL_INT_PLUS_NANO; 350 } 351 352 static int fxls8962af_set_samp_freq(struct fxls8962af_data *data, u32 val, 353 u32 val2) 354 { 355 int i; 356 357 for (i = 0; i < ARRAY_SIZE(fxls8962af_samp_freq_table); i++) 358 if (val == fxls8962af_samp_freq_table[i][0] && 359 val2 == fxls8962af_samp_freq_table[i][1]) 360 break; 361 362 if (i == ARRAY_SIZE(fxls8962af_samp_freq_table)) 363 return -EINVAL; 364 365 return fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG3, 366 FXLS8962AF_SC3_WAKE_ODR_MASK, 367 FXLS8962AF_SC3_WAKE_ODR_PREP(i)); 368 } 369 370 static unsigned int fxls8962af_read_samp_freq(struct fxls8962af_data *data, 371 int *val, int *val2) 372 { 373 int ret; 374 unsigned int reg; 375 u8 range_idx; 376 377 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG3, ®); 378 if (ret) 379 return ret; 380 381 range_idx = FXLS8962AF_SC3_WAKE_ODR_GET(reg); 382 383 *val = fxls8962af_samp_freq_table[range_idx][0]; 384 *val2 = fxls8962af_samp_freq_table[range_idx][1]; 385 386 return IIO_VAL_INT_PLUS_MICRO; 387 } 388 389 static int fxls8962af_read_raw(struct iio_dev *indio_dev, 390 struct iio_chan_spec const *chan, 391 int *val, int *val2, long mask) 392 { 393 struct fxls8962af_data *data = iio_priv(indio_dev); 394 395 switch (mask) { 396 case IIO_CHAN_INFO_RAW: 397 switch (chan->type) { 398 case IIO_TEMP: 399 case IIO_ACCEL: 400 return fxls8962af_get_out(data, chan, val); 401 default: 402 return -EINVAL; 403 } 404 case IIO_CHAN_INFO_OFFSET: 405 if (chan->type != IIO_TEMP) 406 return -EINVAL; 407 408 *val = FXLS8962AF_TEMP_CENTER_VAL; 409 return IIO_VAL_INT; 410 case IIO_CHAN_INFO_SCALE: 411 *val = 0; 412 return fxls8962af_read_full_scale(data, val2); 413 case IIO_CHAN_INFO_SAMP_FREQ: 414 return fxls8962af_read_samp_freq(data, val, val2); 415 default: 416 return -EINVAL; 417 } 418 } 419 420 static int fxls8962af_write_raw(struct iio_dev *indio_dev, 421 struct iio_chan_spec const *chan, 422 int val, int val2, long mask) 423 { 424 struct fxls8962af_data *data = iio_priv(indio_dev); 425 int ret; 426 427 switch (mask) { 428 case IIO_CHAN_INFO_SCALE: 429 if (val != 0) 430 return -EINVAL; 431 432 ret = iio_device_claim_direct_mode(indio_dev); 433 if (ret) 434 return ret; 435 436 ret = fxls8962af_set_full_scale(data, val2); 437 438 iio_device_release_direct_mode(indio_dev); 439 return ret; 440 case IIO_CHAN_INFO_SAMP_FREQ: 441 ret = iio_device_claim_direct_mode(indio_dev); 442 if (ret) 443 return ret; 444 445 ret = fxls8962af_set_samp_freq(data, val, val2); 446 447 iio_device_release_direct_mode(indio_dev); 448 return ret; 449 default: 450 return -EINVAL; 451 } 452 } 453 454 static int fxls8962af_set_watermark(struct iio_dev *indio_dev, unsigned val) 455 { 456 struct fxls8962af_data *data = iio_priv(indio_dev); 457 458 if (val > FXLS8962AF_FIFO_LENGTH) 459 val = FXLS8962AF_FIFO_LENGTH; 460 461 data->watermark = val; 462 463 return 0; 464 } 465 466 #define FXLS8962AF_CHANNEL(axis, reg, idx) { \ 467 .type = IIO_ACCEL, \ 468 .address = reg, \ 469 .modified = 1, \ 470 .channel2 = IIO_MOD_##axis, \ 471 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 472 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 473 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 474 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) | \ 475 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 476 .scan_index = idx, \ 477 .scan_type = { \ 478 .sign = 's', \ 479 .realbits = 12, \ 480 .storagebits = 16, \ 481 .shift = 4, \ 482 .endianness = IIO_BE, \ 483 }, \ 484 } 485 486 #define FXLS8962AF_TEMP_CHANNEL { \ 487 .type = IIO_TEMP, \ 488 .address = FXLS8962AF_TEMP_OUT, \ 489 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 490 BIT(IIO_CHAN_INFO_OFFSET),\ 491 .scan_index = -1, \ 492 .scan_type = { \ 493 .realbits = 8, \ 494 .storagebits = 8, \ 495 }, \ 496 } 497 498 static const struct iio_chan_spec fxls8962af_channels[] = { 499 FXLS8962AF_CHANNEL(X, FXLS8962AF_OUT_X_LSB, fxls8962af_idx_x), 500 FXLS8962AF_CHANNEL(Y, FXLS8962AF_OUT_Y_LSB, fxls8962af_idx_y), 501 FXLS8962AF_CHANNEL(Z, FXLS8962AF_OUT_Z_LSB, fxls8962af_idx_z), 502 IIO_CHAN_SOFT_TIMESTAMP(fxls8962af_idx_ts), 503 FXLS8962AF_TEMP_CHANNEL, 504 }; 505 506 static const struct fxls8962af_chip_info fxls_chip_info_table[] = { 507 [fxls8962af] = { 508 .chip_id = FXLS8962AF_DEVICE_ID, 509 .name = "fxls8962af", 510 .channels = fxls8962af_channels, 511 .num_channels = ARRAY_SIZE(fxls8962af_channels), 512 }, 513 [fxls8964af] = { 514 .chip_id = FXLS8964AF_DEVICE_ID, 515 .name = "fxls8964af", 516 .channels = fxls8962af_channels, 517 .num_channels = ARRAY_SIZE(fxls8962af_channels), 518 }, 519 }; 520 521 static const struct iio_info fxls8962af_info = { 522 .read_raw = &fxls8962af_read_raw, 523 .write_raw = &fxls8962af_write_raw, 524 .write_raw_get_fmt = fxls8962af_write_raw_get_fmt, 525 .read_avail = fxls8962af_read_avail, 526 .hwfifo_set_watermark = fxls8962af_set_watermark, 527 }; 528 529 static int fxls8962af_reset(struct fxls8962af_data *data) 530 { 531 struct device *dev = regmap_get_device(data->regmap); 532 unsigned int reg; 533 int ret; 534 535 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 536 FXLS8962AF_SENS_CONFIG1_RST, 537 FXLS8962AF_SENS_CONFIG1_RST); 538 if (ret) 539 return ret; 540 541 /* TBOOT1, TBOOT2, specifies we have to wait between 1 - 17.7ms */ 542 ret = regmap_read_poll_timeout(data->regmap, FXLS8962AF_INT_STATUS, reg, 543 (reg & FXLS8962AF_INT_STATUS_SRC_BOOT), 544 1000, 18000); 545 if (ret == -ETIMEDOUT) 546 dev_err(dev, "reset timeout, int_status = 0x%x\n", reg); 547 548 return ret; 549 } 550 551 static int __fxls8962af_fifo_set_mode(struct fxls8962af_data *data, bool onoff) 552 { 553 int ret; 554 555 /* Enable watermark at max fifo size */ 556 ret = regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG2, 557 FXLS8962AF_BUF_CONFIG2_BUF_WMRK, 558 data->watermark); 559 if (ret) 560 return ret; 561 562 return regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG1, 563 FXLS8962AF_BC1_BUF_MODE_MASK, 564 FXLS8962AF_BC1_BUF_MODE_PREP(onoff)); 565 } 566 567 static int fxls8962af_buffer_preenable(struct iio_dev *indio_dev) 568 { 569 return fxls8962af_power_on(iio_priv(indio_dev)); 570 } 571 572 static int fxls8962af_buffer_postenable(struct iio_dev *indio_dev) 573 { 574 struct fxls8962af_data *data = iio_priv(indio_dev); 575 int ret; 576 577 fxls8962af_standby(data); 578 579 /* Enable buffer interrupt */ 580 ret = regmap_update_bits(data->regmap, FXLS8962AF_INT_EN, 581 FXLS8962AF_INT_EN_BUF_EN, 582 FXLS8962AF_INT_EN_BUF_EN); 583 if (ret) 584 return ret; 585 586 ret = __fxls8962af_fifo_set_mode(data, true); 587 588 fxls8962af_active(data); 589 590 return ret; 591 } 592 593 static int fxls8962af_buffer_predisable(struct iio_dev *indio_dev) 594 { 595 struct fxls8962af_data *data = iio_priv(indio_dev); 596 int ret; 597 598 fxls8962af_standby(data); 599 600 /* Disable buffer interrupt */ 601 ret = regmap_update_bits(data->regmap, FXLS8962AF_INT_EN, 602 FXLS8962AF_INT_EN_BUF_EN, 0); 603 if (ret) 604 return ret; 605 606 ret = __fxls8962af_fifo_set_mode(data, false); 607 608 fxls8962af_active(data); 609 610 return ret; 611 } 612 613 static int fxls8962af_buffer_postdisable(struct iio_dev *indio_dev) 614 { 615 struct fxls8962af_data *data = iio_priv(indio_dev); 616 617 return fxls8962af_power_off(data); 618 } 619 620 static const struct iio_buffer_setup_ops fxls8962af_buffer_ops = { 621 .preenable = fxls8962af_buffer_preenable, 622 .postenable = fxls8962af_buffer_postenable, 623 .predisable = fxls8962af_buffer_predisable, 624 .postdisable = fxls8962af_buffer_postdisable, 625 }; 626 627 static int fxls8962af_i2c_raw_read_errata3(struct fxls8962af_data *data, 628 u16 *buffer, int samples, 629 int sample_length) 630 { 631 int i, ret; 632 633 for (i = 0; i < samples; i++) { 634 ret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB, 635 &buffer[i * 3], sample_length); 636 if (ret) 637 return ret; 638 } 639 640 return ret; 641 } 642 643 static int fxls8962af_fifo_transfer(struct fxls8962af_data *data, 644 u16 *buffer, int samples) 645 { 646 struct device *dev = regmap_get_device(data->regmap); 647 int sample_length = 3 * sizeof(*buffer); 648 int total_length = samples * sample_length; 649 int ret; 650 651 if (i2c_verify_client(dev)) 652 /* 653 * Due to errata bug: 654 * E3: FIFO burst read operation error using I2C interface 655 * We have to avoid burst reads on I2C.. 656 */ 657 ret = fxls8962af_i2c_raw_read_errata3(data, buffer, samples, 658 sample_length); 659 else 660 ret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB, buffer, 661 total_length); 662 663 if (ret) 664 dev_err(dev, "Error transferring data from fifo: %d\n", ret); 665 666 return ret; 667 } 668 669 static int fxls8962af_fifo_flush(struct iio_dev *indio_dev) 670 { 671 struct fxls8962af_data *data = iio_priv(indio_dev); 672 struct device *dev = regmap_get_device(data->regmap); 673 u16 buffer[FXLS8962AF_FIFO_LENGTH * 3]; 674 uint64_t sample_period; 675 unsigned int reg; 676 int64_t tstamp; 677 int ret, i; 678 u8 count; 679 680 ret = regmap_read(data->regmap, FXLS8962AF_BUF_STATUS, ®); 681 if (ret) 682 return ret; 683 684 if (reg & FXLS8962AF_BUF_STATUS_BUF_OVF) { 685 dev_err(dev, "Buffer overflow"); 686 return -EOVERFLOW; 687 } 688 689 count = reg & FXLS8962AF_BUF_STATUS_BUF_CNT; 690 if (!count) 691 return 0; 692 693 data->old_timestamp = data->timestamp; 694 data->timestamp = iio_get_time_ns(indio_dev); 695 696 /* 697 * Approximate timestamps for each of the sample based on the sampling, 698 * frequency, timestamp for last sample and number of samples. 699 */ 700 sample_period = (data->timestamp - data->old_timestamp); 701 do_div(sample_period, count); 702 tstamp = data->timestamp - (count - 1) * sample_period; 703 704 ret = fxls8962af_fifo_transfer(data, buffer, count); 705 if (ret) 706 return ret; 707 708 /* Demux hw FIFO into kfifo. */ 709 for (i = 0; i < count; i++) { 710 int j, bit; 711 712 j = 0; 713 for_each_set_bit(bit, indio_dev->active_scan_mask, 714 indio_dev->masklength) { 715 memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit], 716 sizeof(data->scan.channels[0])); 717 } 718 719 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan, 720 tstamp); 721 722 tstamp += sample_period; 723 } 724 725 return count; 726 } 727 728 static irqreturn_t fxls8962af_interrupt(int irq, void *p) 729 { 730 struct iio_dev *indio_dev = p; 731 struct fxls8962af_data *data = iio_priv(indio_dev); 732 unsigned int reg; 733 int ret; 734 735 ret = regmap_read(data->regmap, FXLS8962AF_INT_STATUS, ®); 736 if (ret) 737 return IRQ_NONE; 738 739 if (reg & FXLS8962AF_INT_STATUS_SRC_BUF) { 740 ret = fxls8962af_fifo_flush(indio_dev); 741 if (ret) 742 return IRQ_NONE; 743 744 return IRQ_HANDLED; 745 } 746 747 return IRQ_NONE; 748 } 749 750 static void fxls8962af_regulator_disable(void *data_ptr) 751 { 752 struct fxls8962af_data *data = data_ptr; 753 754 regulator_disable(data->vdd_reg); 755 } 756 757 static void fxls8962af_pm_disable(void *dev_ptr) 758 { 759 struct device *dev = dev_ptr; 760 struct iio_dev *indio_dev = dev_get_drvdata(dev); 761 762 pm_runtime_disable(dev); 763 pm_runtime_set_suspended(dev); 764 pm_runtime_put_noidle(dev); 765 766 fxls8962af_standby(iio_priv(indio_dev)); 767 } 768 769 static void fxls8962af_get_irq(struct device_node *of_node, 770 enum fxls8962af_int_pin *pin) 771 { 772 int irq; 773 774 irq = of_irq_get_byname(of_node, "INT2"); 775 if (irq > 0) { 776 *pin = FXLS8962AF_PIN_INT2; 777 return; 778 } 779 780 *pin = FXLS8962AF_PIN_INT1; 781 } 782 783 static int fxls8962af_irq_setup(struct iio_dev *indio_dev, int irq) 784 { 785 struct fxls8962af_data *data = iio_priv(indio_dev); 786 struct device *dev = regmap_get_device(data->regmap); 787 unsigned long irq_type; 788 bool irq_active_high; 789 enum fxls8962af_int_pin int_pin; 790 u8 int_pin_sel; 791 int ret; 792 793 fxls8962af_get_irq(dev->of_node, &int_pin); 794 switch (int_pin) { 795 case FXLS8962AF_PIN_INT1: 796 int_pin_sel = FXLS8962AF_INT_PIN_SEL_INT1; 797 break; 798 case FXLS8962AF_PIN_INT2: 799 int_pin_sel = FXLS8962AF_INT_PIN_SEL_INT2; 800 break; 801 default: 802 dev_err(dev, "unsupported int pin selected\n"); 803 return -EINVAL; 804 } 805 806 ret = regmap_update_bits(data->regmap, FXLS8962AF_INT_PIN_SEL, 807 FXLS8962AF_INT_PIN_SEL_MASK, int_pin_sel); 808 if (ret) 809 return ret; 810 811 irq_type = irqd_get_trigger_type(irq_get_irq_data(irq)); 812 813 switch (irq_type) { 814 case IRQF_TRIGGER_HIGH: 815 case IRQF_TRIGGER_RISING: 816 irq_active_high = true; 817 break; 818 case IRQF_TRIGGER_LOW: 819 case IRQF_TRIGGER_FALLING: 820 irq_active_high = false; 821 break; 822 default: 823 dev_info(dev, "mode %lx unsupported\n", irq_type); 824 return -EINVAL; 825 } 826 827 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4, 828 FXLS8962AF_SC4_INT_POL_MASK, 829 FXLS8962AF_SC4_INT_POL_PREP(irq_active_high)); 830 if (ret) 831 return ret; 832 833 if (device_property_read_bool(dev, "drive-open-drain")) { 834 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4, 835 FXLS8962AF_SC4_INT_PP_OD_MASK, 836 FXLS8962AF_SC4_INT_PP_OD_PREP(1)); 837 if (ret) 838 return ret; 839 840 irq_type |= IRQF_SHARED; 841 } 842 843 return devm_request_threaded_irq(dev, 844 irq, 845 NULL, fxls8962af_interrupt, 846 irq_type | IRQF_ONESHOT, 847 indio_dev->name, indio_dev); 848 } 849 850 int fxls8962af_core_probe(struct device *dev, struct regmap *regmap, int irq) 851 { 852 struct fxls8962af_data *data; 853 struct iio_dev *indio_dev; 854 unsigned int reg; 855 int ret, i; 856 857 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 858 if (!indio_dev) 859 return -ENOMEM; 860 861 data = iio_priv(indio_dev); 862 dev_set_drvdata(dev, indio_dev); 863 data->regmap = regmap; 864 865 ret = iio_read_mount_matrix(dev, &data->orientation); 866 if (ret) 867 return ret; 868 869 data->vdd_reg = devm_regulator_get(dev, "vdd"); 870 if (IS_ERR(data->vdd_reg)) 871 return dev_err_probe(dev, PTR_ERR(data->vdd_reg), 872 "Failed to get vdd regulator\n"); 873 874 ret = regulator_enable(data->vdd_reg); 875 if (ret) { 876 dev_err(dev, "Failed to enable vdd regulator: %d\n", ret); 877 return ret; 878 } 879 880 ret = devm_add_action_or_reset(dev, fxls8962af_regulator_disable, data); 881 if (ret) 882 return ret; 883 884 ret = regmap_read(data->regmap, FXLS8962AF_WHO_AM_I, ®); 885 if (ret) 886 return ret; 887 888 for (i = 0; i < ARRAY_SIZE(fxls_chip_info_table); i++) { 889 if (fxls_chip_info_table[i].chip_id == reg) { 890 data->chip_info = &fxls_chip_info_table[i]; 891 break; 892 } 893 } 894 if (i == ARRAY_SIZE(fxls_chip_info_table)) { 895 dev_err(dev, "failed to match device in table\n"); 896 return -ENXIO; 897 } 898 899 indio_dev->channels = data->chip_info->channels; 900 indio_dev->num_channels = data->chip_info->num_channels; 901 indio_dev->name = data->chip_info->name; 902 indio_dev->info = &fxls8962af_info; 903 indio_dev->modes = INDIO_DIRECT_MODE; 904 905 ret = fxls8962af_reset(data); 906 if (ret) 907 return ret; 908 909 if (irq) { 910 ret = fxls8962af_irq_setup(indio_dev, irq); 911 if (ret) 912 return ret; 913 914 ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, 915 INDIO_BUFFER_SOFTWARE, 916 &fxls8962af_buffer_ops); 917 if (ret) 918 return ret; 919 } 920 921 ret = pm_runtime_set_active(dev); 922 if (ret) 923 return ret; 924 925 pm_runtime_enable(dev); 926 pm_runtime_set_autosuspend_delay(dev, FXLS8962AF_AUTO_SUSPEND_DELAY_MS); 927 pm_runtime_use_autosuspend(dev); 928 929 ret = devm_add_action_or_reset(dev, fxls8962af_pm_disable, dev); 930 if (ret) 931 return ret; 932 933 return devm_iio_device_register(dev, indio_dev); 934 } 935 EXPORT_SYMBOL_GPL(fxls8962af_core_probe); 936 937 static int __maybe_unused fxls8962af_runtime_suspend(struct device *dev) 938 { 939 struct fxls8962af_data *data = iio_priv(dev_get_drvdata(dev)); 940 int ret; 941 942 ret = fxls8962af_standby(data); 943 if (ret) { 944 dev_err(dev, "powering off device failed\n"); 945 return ret; 946 } 947 948 return 0; 949 } 950 951 static int __maybe_unused fxls8962af_runtime_resume(struct device *dev) 952 { 953 struct fxls8962af_data *data = iio_priv(dev_get_drvdata(dev)); 954 955 return fxls8962af_active(data); 956 } 957 958 const struct dev_pm_ops fxls8962af_pm_ops = { 959 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 960 pm_runtime_force_resume) 961 SET_RUNTIME_PM_OPS(fxls8962af_runtime_suspend, 962 fxls8962af_runtime_resume, NULL) 963 }; 964 EXPORT_SYMBOL_GPL(fxls8962af_pm_ops); 965 966 MODULE_AUTHOR("Sean Nyekjaer <sean@geanix.com>"); 967 MODULE_DESCRIPTION("NXP FXLS8962AF/FXLS8964AF accelerometer driver"); 968 MODULE_LICENSE("GPL v2"); 969