1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * NXP FXLS8962AF/FXLS8964AF Accelerometer Core Driver 4 * 5 * Copyright 2021 Connected Cars A/S 6 * 7 * Datasheet: 8 * https://www.nxp.com/docs/en/data-sheet/FXLS8962AF.pdf 9 * https://www.nxp.com/docs/en/data-sheet/FXLS8964AF.pdf 10 * 11 * Errata: 12 * https://www.nxp.com/docs/en/errata/ES_FXLS8962AF.pdf 13 */ 14 15 #include <linux/bits.h> 16 #include <linux/bitfield.h> 17 #include <linux/i2c.h> 18 #include <linux/module.h> 19 #include <linux/of_irq.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/regmap.h> 23 24 #include <linux/iio/buffer.h> 25 #include <linux/iio/events.h> 26 #include <linux/iio/iio.h> 27 #include <linux/iio/kfifo_buf.h> 28 #include <linux/iio/sysfs.h> 29 30 #include "fxls8962af.h" 31 32 #define FXLS8962AF_INT_STATUS 0x00 33 #define FXLS8962AF_INT_STATUS_SRC_BOOT BIT(0) 34 #define FXLS8962AF_INT_STATUS_SRC_SDCD_OT BIT(4) 35 #define FXLS8962AF_INT_STATUS_SRC_BUF BIT(5) 36 #define FXLS8962AF_INT_STATUS_SRC_DRDY BIT(7) 37 #define FXLS8962AF_TEMP_OUT 0x01 38 #define FXLS8962AF_VECM_LSB 0x02 39 #define FXLS8962AF_OUT_X_LSB 0x04 40 #define FXLS8962AF_OUT_Y_LSB 0x06 41 #define FXLS8962AF_OUT_Z_LSB 0x08 42 #define FXLS8962AF_BUF_STATUS 0x0b 43 #define FXLS8962AF_BUF_STATUS_BUF_CNT GENMASK(5, 0) 44 #define FXLS8962AF_BUF_STATUS_BUF_OVF BIT(6) 45 #define FXLS8962AF_BUF_STATUS_BUF_WMRK BIT(7) 46 #define FXLS8962AF_BUF_X_LSB 0x0c 47 #define FXLS8962AF_BUF_Y_LSB 0x0e 48 #define FXLS8962AF_BUF_Z_LSB 0x10 49 50 #define FXLS8962AF_PROD_REV 0x12 51 #define FXLS8962AF_WHO_AM_I 0x13 52 53 #define FXLS8962AF_SYS_MODE 0x14 54 #define FXLS8962AF_SENS_CONFIG1 0x15 55 #define FXLS8962AF_SENS_CONFIG1_ACTIVE BIT(0) 56 #define FXLS8962AF_SENS_CONFIG1_RST BIT(7) 57 #define FXLS8962AF_SC1_FSR_MASK GENMASK(2, 1) 58 #define FXLS8962AF_SC1_FSR_PREP(x) FIELD_PREP(FXLS8962AF_SC1_FSR_MASK, (x)) 59 #define FXLS8962AF_SC1_FSR_GET(x) FIELD_GET(FXLS8962AF_SC1_FSR_MASK, (x)) 60 61 #define FXLS8962AF_SENS_CONFIG2 0x16 62 #define FXLS8962AF_SENS_CONFIG3 0x17 63 #define FXLS8962AF_SC3_WAKE_ODR_MASK GENMASK(7, 4) 64 #define FXLS8962AF_SC3_WAKE_ODR_PREP(x) FIELD_PREP(FXLS8962AF_SC3_WAKE_ODR_MASK, (x)) 65 #define FXLS8962AF_SC3_WAKE_ODR_GET(x) FIELD_GET(FXLS8962AF_SC3_WAKE_ODR_MASK, (x)) 66 #define FXLS8962AF_SENS_CONFIG4 0x18 67 #define FXLS8962AF_SC4_INT_PP_OD_MASK BIT(1) 68 #define FXLS8962AF_SC4_INT_PP_OD_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_PP_OD_MASK, (x)) 69 #define FXLS8962AF_SC4_INT_POL_MASK BIT(0) 70 #define FXLS8962AF_SC4_INT_POL_PREP(x) FIELD_PREP(FXLS8962AF_SC4_INT_POL_MASK, (x)) 71 #define FXLS8962AF_SENS_CONFIG5 0x19 72 73 #define FXLS8962AF_WAKE_IDLE_LSB 0x1b 74 #define FXLS8962AF_SLEEP_IDLE_LSB 0x1c 75 #define FXLS8962AF_ASLP_COUNT_LSB 0x1e 76 77 #define FXLS8962AF_INT_EN 0x20 78 #define FXLS8962AF_INT_EN_SDCD_OT_EN BIT(5) 79 #define FXLS8962AF_INT_EN_BUF_EN BIT(6) 80 #define FXLS8962AF_INT_PIN_SEL 0x21 81 #define FXLS8962AF_INT_PIN_SEL_MASK GENMASK(7, 0) 82 #define FXLS8962AF_INT_PIN_SEL_INT1 0x00 83 #define FXLS8962AF_INT_PIN_SEL_INT2 GENMASK(7, 0) 84 85 #define FXLS8962AF_OFF_X 0x22 86 #define FXLS8962AF_OFF_Y 0x23 87 #define FXLS8962AF_OFF_Z 0x24 88 89 #define FXLS8962AF_BUF_CONFIG1 0x26 90 #define FXLS8962AF_BC1_BUF_MODE_MASK GENMASK(6, 5) 91 #define FXLS8962AF_BC1_BUF_MODE_PREP(x) FIELD_PREP(FXLS8962AF_BC1_BUF_MODE_MASK, (x)) 92 #define FXLS8962AF_BUF_CONFIG2 0x27 93 #define FXLS8962AF_BUF_CONFIG2_BUF_WMRK GENMASK(5, 0) 94 95 #define FXLS8962AF_ORIENT_STATUS 0x28 96 #define FXLS8962AF_ORIENT_CONFIG 0x29 97 #define FXLS8962AF_ORIENT_DBCOUNT 0x2a 98 #define FXLS8962AF_ORIENT_BF_ZCOMP 0x2b 99 #define FXLS8962AF_ORIENT_THS_REG 0x2c 100 101 #define FXLS8962AF_SDCD_INT_SRC1 0x2d 102 #define FXLS8962AF_SDCD_INT_SRC1_X_OT BIT(5) 103 #define FXLS8962AF_SDCD_INT_SRC1_X_POL BIT(4) 104 #define FXLS8962AF_SDCD_INT_SRC1_Y_OT BIT(3) 105 #define FXLS8962AF_SDCD_INT_SRC1_Y_POL BIT(2) 106 #define FXLS8962AF_SDCD_INT_SRC1_Z_OT BIT(1) 107 #define FXLS8962AF_SDCD_INT_SRC1_Z_POL BIT(0) 108 #define FXLS8962AF_SDCD_INT_SRC2 0x2e 109 #define FXLS8962AF_SDCD_CONFIG1 0x2f 110 #define FXLS8962AF_SDCD_CONFIG1_Z_OT_EN BIT(3) 111 #define FXLS8962AF_SDCD_CONFIG1_Y_OT_EN BIT(4) 112 #define FXLS8962AF_SDCD_CONFIG1_X_OT_EN BIT(5) 113 #define FXLS8962AF_SDCD_CONFIG1_OT_ELE BIT(7) 114 #define FXLS8962AF_SDCD_CONFIG2 0x30 115 #define FXLS8962AF_SDCD_CONFIG2_SDCD_EN BIT(7) 116 #define FXLS8962AF_SC2_REF_UPDM_AC GENMASK(6, 5) 117 #define FXLS8962AF_SDCD_OT_DBCNT 0x31 118 #define FXLS8962AF_SDCD_WT_DBCNT 0x32 119 #define FXLS8962AF_SDCD_LTHS_LSB 0x33 120 #define FXLS8962AF_SDCD_UTHS_LSB 0x35 121 122 #define FXLS8962AF_SELF_TEST_CONFIG1 0x37 123 #define FXLS8962AF_SELF_TEST_CONFIG2 0x38 124 125 #define FXLS8962AF_MAX_REG 0x38 126 127 #define FXLS8962AF_DEVICE_ID 0x62 128 #define FXLS8964AF_DEVICE_ID 0x84 129 130 /* Raw temp channel offset */ 131 #define FXLS8962AF_TEMP_CENTER_VAL 25 132 133 #define FXLS8962AF_AUTO_SUSPEND_DELAY_MS 2000 134 135 #define FXLS8962AF_FIFO_LENGTH 32 136 #define FXLS8962AF_SCALE_TABLE_LEN 4 137 #define FXLS8962AF_SAMP_FREQ_TABLE_LEN 13 138 139 static const int fxls8962af_scale_table[FXLS8962AF_SCALE_TABLE_LEN][2] = { 140 {0, IIO_G_TO_M_S_2(980000)}, 141 {0, IIO_G_TO_M_S_2(1950000)}, 142 {0, IIO_G_TO_M_S_2(3910000)}, 143 {0, IIO_G_TO_M_S_2(7810000)}, 144 }; 145 146 static const int fxls8962af_samp_freq_table[FXLS8962AF_SAMP_FREQ_TABLE_LEN][2] = { 147 {3200, 0}, {1600, 0}, {800, 0}, {400, 0}, {200, 0}, {100, 0}, 148 {50, 0}, {25, 0}, {12, 500000}, {6, 250000}, {3, 125000}, 149 {1, 563000}, {0, 781000}, 150 }; 151 152 struct fxls8962af_chip_info { 153 const char *name; 154 const struct iio_chan_spec *channels; 155 int num_channels; 156 u8 chip_id; 157 }; 158 159 struct fxls8962af_data { 160 struct regmap *regmap; 161 const struct fxls8962af_chip_info *chip_info; 162 struct regulator *vdd_reg; 163 struct { 164 __le16 channels[3]; 165 s64 ts __aligned(8); 166 } scan; 167 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */ 168 struct iio_mount_matrix orientation; 169 int irq; 170 u8 watermark; 171 u8 enable_event; 172 u16 lower_thres; 173 u16 upper_thres; 174 }; 175 176 const struct regmap_config fxls8962af_i2c_regmap_conf = { 177 .reg_bits = 8, 178 .val_bits = 8, 179 .max_register = FXLS8962AF_MAX_REG, 180 }; 181 EXPORT_SYMBOL_GPL(fxls8962af_i2c_regmap_conf); 182 183 const struct regmap_config fxls8962af_spi_regmap_conf = { 184 .reg_bits = 8, 185 .pad_bits = 8, 186 .val_bits = 8, 187 .max_register = FXLS8962AF_MAX_REG, 188 }; 189 EXPORT_SYMBOL_GPL(fxls8962af_spi_regmap_conf); 190 191 enum { 192 fxls8962af_idx_x, 193 fxls8962af_idx_y, 194 fxls8962af_idx_z, 195 fxls8962af_idx_ts, 196 }; 197 198 enum fxls8962af_int_pin { 199 FXLS8962AF_PIN_INT1, 200 FXLS8962AF_PIN_INT2, 201 }; 202 203 static int fxls8962af_power_on(struct fxls8962af_data *data) 204 { 205 struct device *dev = regmap_get_device(data->regmap); 206 int ret; 207 208 ret = pm_runtime_resume_and_get(dev); 209 if (ret) 210 dev_err(dev, "failed to power on\n"); 211 212 return ret; 213 } 214 215 static int fxls8962af_power_off(struct fxls8962af_data *data) 216 { 217 struct device *dev = regmap_get_device(data->regmap); 218 int ret; 219 220 pm_runtime_mark_last_busy(dev); 221 ret = pm_runtime_put_autosuspend(dev); 222 if (ret) 223 dev_err(dev, "failed to power off\n"); 224 225 return ret; 226 } 227 228 static int fxls8962af_standby(struct fxls8962af_data *data) 229 { 230 return regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 231 FXLS8962AF_SENS_CONFIG1_ACTIVE, 0); 232 } 233 234 static int fxls8962af_active(struct fxls8962af_data *data) 235 { 236 return regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 237 FXLS8962AF_SENS_CONFIG1_ACTIVE, 1); 238 } 239 240 static int fxls8962af_is_active(struct fxls8962af_data *data) 241 { 242 unsigned int reg; 243 int ret; 244 245 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, ®); 246 if (ret) 247 return ret; 248 249 return reg & FXLS8962AF_SENS_CONFIG1_ACTIVE; 250 } 251 252 static int fxls8962af_get_out(struct fxls8962af_data *data, 253 struct iio_chan_spec const *chan, int *val) 254 { 255 struct device *dev = regmap_get_device(data->regmap); 256 __le16 raw_val; 257 int is_active; 258 int ret; 259 260 is_active = fxls8962af_is_active(data); 261 if (!is_active) { 262 ret = fxls8962af_power_on(data); 263 if (ret) 264 return ret; 265 } 266 267 ret = regmap_bulk_read(data->regmap, chan->address, 268 &raw_val, sizeof(data->lower_thres)); 269 270 if (!is_active) 271 fxls8962af_power_off(data); 272 273 if (ret) { 274 dev_err(dev, "failed to get out reg 0x%lx\n", chan->address); 275 return ret; 276 } 277 278 *val = sign_extend32(le16_to_cpu(raw_val), 279 chan->scan_type.realbits - 1); 280 281 return IIO_VAL_INT; 282 } 283 284 static int fxls8962af_read_avail(struct iio_dev *indio_dev, 285 struct iio_chan_spec const *chan, 286 const int **vals, int *type, int *length, 287 long mask) 288 { 289 switch (mask) { 290 case IIO_CHAN_INFO_SCALE: 291 *type = IIO_VAL_INT_PLUS_NANO; 292 *vals = (int *)fxls8962af_scale_table; 293 *length = ARRAY_SIZE(fxls8962af_scale_table) * 2; 294 return IIO_AVAIL_LIST; 295 case IIO_CHAN_INFO_SAMP_FREQ: 296 *type = IIO_VAL_INT_PLUS_MICRO; 297 *vals = (int *)fxls8962af_samp_freq_table; 298 *length = ARRAY_SIZE(fxls8962af_samp_freq_table) * 2; 299 return IIO_AVAIL_LIST; 300 default: 301 return -EINVAL; 302 } 303 } 304 305 static int fxls8962af_write_raw_get_fmt(struct iio_dev *indio_dev, 306 struct iio_chan_spec const *chan, 307 long mask) 308 { 309 switch (mask) { 310 case IIO_CHAN_INFO_SCALE: 311 return IIO_VAL_INT_PLUS_NANO; 312 case IIO_CHAN_INFO_SAMP_FREQ: 313 return IIO_VAL_INT_PLUS_MICRO; 314 default: 315 return IIO_VAL_INT_PLUS_NANO; 316 } 317 } 318 319 static int fxls8962af_update_config(struct fxls8962af_data *data, u8 reg, 320 u8 mask, u8 val) 321 { 322 int ret; 323 int is_active; 324 325 is_active = fxls8962af_is_active(data); 326 if (is_active) { 327 ret = fxls8962af_standby(data); 328 if (ret) 329 return ret; 330 } 331 332 ret = regmap_update_bits(data->regmap, reg, mask, val); 333 if (ret) 334 return ret; 335 336 if (is_active) { 337 ret = fxls8962af_active(data); 338 if (ret) 339 return ret; 340 } 341 342 return 0; 343 } 344 345 static int fxls8962af_set_full_scale(struct fxls8962af_data *data, u32 scale) 346 { 347 int i; 348 349 for (i = 0; i < ARRAY_SIZE(fxls8962af_scale_table); i++) 350 if (scale == fxls8962af_scale_table[i][1]) 351 break; 352 353 if (i == ARRAY_SIZE(fxls8962af_scale_table)) 354 return -EINVAL; 355 356 return fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG1, 357 FXLS8962AF_SC1_FSR_MASK, 358 FXLS8962AF_SC1_FSR_PREP(i)); 359 } 360 361 static unsigned int fxls8962af_read_full_scale(struct fxls8962af_data *data, 362 int *val) 363 { 364 int ret; 365 unsigned int reg; 366 u8 range_idx; 367 368 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG1, ®); 369 if (ret) 370 return ret; 371 372 range_idx = FXLS8962AF_SC1_FSR_GET(reg); 373 374 *val = fxls8962af_scale_table[range_idx][1]; 375 376 return IIO_VAL_INT_PLUS_NANO; 377 } 378 379 static int fxls8962af_set_samp_freq(struct fxls8962af_data *data, u32 val, 380 u32 val2) 381 { 382 int i; 383 384 for (i = 0; i < ARRAY_SIZE(fxls8962af_samp_freq_table); i++) 385 if (val == fxls8962af_samp_freq_table[i][0] && 386 val2 == fxls8962af_samp_freq_table[i][1]) 387 break; 388 389 if (i == ARRAY_SIZE(fxls8962af_samp_freq_table)) 390 return -EINVAL; 391 392 return fxls8962af_update_config(data, FXLS8962AF_SENS_CONFIG3, 393 FXLS8962AF_SC3_WAKE_ODR_MASK, 394 FXLS8962AF_SC3_WAKE_ODR_PREP(i)); 395 } 396 397 static unsigned int fxls8962af_read_samp_freq(struct fxls8962af_data *data, 398 int *val, int *val2) 399 { 400 int ret; 401 unsigned int reg; 402 u8 range_idx; 403 404 ret = regmap_read(data->regmap, FXLS8962AF_SENS_CONFIG3, ®); 405 if (ret) 406 return ret; 407 408 range_idx = FXLS8962AF_SC3_WAKE_ODR_GET(reg); 409 410 *val = fxls8962af_samp_freq_table[range_idx][0]; 411 *val2 = fxls8962af_samp_freq_table[range_idx][1]; 412 413 return IIO_VAL_INT_PLUS_MICRO; 414 } 415 416 static int fxls8962af_read_raw(struct iio_dev *indio_dev, 417 struct iio_chan_spec const *chan, 418 int *val, int *val2, long mask) 419 { 420 struct fxls8962af_data *data = iio_priv(indio_dev); 421 422 switch (mask) { 423 case IIO_CHAN_INFO_RAW: 424 switch (chan->type) { 425 case IIO_TEMP: 426 case IIO_ACCEL: 427 return fxls8962af_get_out(data, chan, val); 428 default: 429 return -EINVAL; 430 } 431 case IIO_CHAN_INFO_OFFSET: 432 if (chan->type != IIO_TEMP) 433 return -EINVAL; 434 435 *val = FXLS8962AF_TEMP_CENTER_VAL; 436 return IIO_VAL_INT; 437 case IIO_CHAN_INFO_SCALE: 438 *val = 0; 439 return fxls8962af_read_full_scale(data, val2); 440 case IIO_CHAN_INFO_SAMP_FREQ: 441 return fxls8962af_read_samp_freq(data, val, val2); 442 default: 443 return -EINVAL; 444 } 445 } 446 447 static int fxls8962af_write_raw(struct iio_dev *indio_dev, 448 struct iio_chan_spec const *chan, 449 int val, int val2, long mask) 450 { 451 struct fxls8962af_data *data = iio_priv(indio_dev); 452 int ret; 453 454 switch (mask) { 455 case IIO_CHAN_INFO_SCALE: 456 if (val != 0) 457 return -EINVAL; 458 459 ret = iio_device_claim_direct_mode(indio_dev); 460 if (ret) 461 return ret; 462 463 ret = fxls8962af_set_full_scale(data, val2); 464 465 iio_device_release_direct_mode(indio_dev); 466 return ret; 467 case IIO_CHAN_INFO_SAMP_FREQ: 468 ret = iio_device_claim_direct_mode(indio_dev); 469 if (ret) 470 return ret; 471 472 ret = fxls8962af_set_samp_freq(data, val, val2); 473 474 iio_device_release_direct_mode(indio_dev); 475 return ret; 476 default: 477 return -EINVAL; 478 } 479 } 480 481 static int fxls8962af_event_setup(struct fxls8962af_data *data, int state) 482 { 483 /* Enable wakeup interrupt */ 484 int mask = FXLS8962AF_INT_EN_SDCD_OT_EN; 485 int value = state ? mask : 0; 486 487 return regmap_update_bits(data->regmap, FXLS8962AF_INT_EN, mask, value); 488 } 489 490 static int fxls8962af_set_watermark(struct iio_dev *indio_dev, unsigned val) 491 { 492 struct fxls8962af_data *data = iio_priv(indio_dev); 493 494 if (val > FXLS8962AF_FIFO_LENGTH) 495 val = FXLS8962AF_FIFO_LENGTH; 496 497 data->watermark = val; 498 499 return 0; 500 } 501 502 static int __fxls8962af_set_thresholds(struct fxls8962af_data *data, 503 const struct iio_chan_spec *chan, 504 enum iio_event_direction dir, 505 int val) 506 { 507 switch (dir) { 508 case IIO_EV_DIR_FALLING: 509 data->lower_thres = val; 510 return regmap_bulk_write(data->regmap, FXLS8962AF_SDCD_LTHS_LSB, 511 &data->lower_thres, sizeof(data->lower_thres)); 512 case IIO_EV_DIR_RISING: 513 data->upper_thres = val; 514 return regmap_bulk_write(data->regmap, FXLS8962AF_SDCD_UTHS_LSB, 515 &data->upper_thres, sizeof(data->upper_thres)); 516 default: 517 return -EINVAL; 518 } 519 } 520 521 static int fxls8962af_read_event(struct iio_dev *indio_dev, 522 const struct iio_chan_spec *chan, 523 enum iio_event_type type, 524 enum iio_event_direction dir, 525 enum iio_event_info info, 526 int *val, int *val2) 527 { 528 struct fxls8962af_data *data = iio_priv(indio_dev); 529 int ret; 530 531 if (type != IIO_EV_TYPE_THRESH) 532 return -EINVAL; 533 534 switch (dir) { 535 case IIO_EV_DIR_FALLING: 536 ret = regmap_bulk_read(data->regmap, FXLS8962AF_SDCD_LTHS_LSB, 537 &data->lower_thres, sizeof(data->lower_thres)); 538 if (ret) 539 return ret; 540 541 *val = sign_extend32(data->lower_thres, chan->scan_type.realbits - 1); 542 return IIO_VAL_INT; 543 case IIO_EV_DIR_RISING: 544 ret = regmap_bulk_read(data->regmap, FXLS8962AF_SDCD_UTHS_LSB, 545 &data->upper_thres, sizeof(data->upper_thres)); 546 if (ret) 547 return ret; 548 549 *val = sign_extend32(data->upper_thres, chan->scan_type.realbits - 1); 550 return IIO_VAL_INT; 551 default: 552 return -EINVAL; 553 } 554 } 555 556 static int fxls8962af_write_event(struct iio_dev *indio_dev, 557 const struct iio_chan_spec *chan, 558 enum iio_event_type type, 559 enum iio_event_direction dir, 560 enum iio_event_info info, 561 int val, int val2) 562 { 563 struct fxls8962af_data *data = iio_priv(indio_dev); 564 int ret, val_masked; 565 566 if (type != IIO_EV_TYPE_THRESH) 567 return -EINVAL; 568 569 if (val < -2048 || val > 2047) 570 return -EINVAL; 571 572 if (data->enable_event) 573 return -EBUSY; 574 575 val_masked = val & GENMASK(11, 0); 576 if (fxls8962af_is_active(data)) { 577 ret = fxls8962af_standby(data); 578 if (ret) 579 return ret; 580 581 ret = __fxls8962af_set_thresholds(data, chan, dir, val_masked); 582 if (ret) 583 return ret; 584 585 return fxls8962af_active(data); 586 } else { 587 return __fxls8962af_set_thresholds(data, chan, dir, val_masked); 588 } 589 } 590 591 static int 592 fxls8962af_read_event_config(struct iio_dev *indio_dev, 593 const struct iio_chan_spec *chan, 594 enum iio_event_type type, 595 enum iio_event_direction dir) 596 { 597 struct fxls8962af_data *data = iio_priv(indio_dev); 598 599 if (type != IIO_EV_TYPE_THRESH) 600 return -EINVAL; 601 602 switch (chan->channel2) { 603 case IIO_MOD_X: 604 return !!(FXLS8962AF_SDCD_CONFIG1_X_OT_EN & data->enable_event); 605 case IIO_MOD_Y: 606 return !!(FXLS8962AF_SDCD_CONFIG1_Y_OT_EN & data->enable_event); 607 case IIO_MOD_Z: 608 return !!(FXLS8962AF_SDCD_CONFIG1_Z_OT_EN & data->enable_event); 609 default: 610 return -EINVAL; 611 } 612 } 613 614 static int 615 fxls8962af_write_event_config(struct iio_dev *indio_dev, 616 const struct iio_chan_spec *chan, 617 enum iio_event_type type, 618 enum iio_event_direction dir, int state) 619 { 620 struct fxls8962af_data *data = iio_priv(indio_dev); 621 u8 enable_event, enable_bits; 622 int ret, value; 623 624 if (type != IIO_EV_TYPE_THRESH) 625 return -EINVAL; 626 627 switch (chan->channel2) { 628 case IIO_MOD_X: 629 enable_bits = FXLS8962AF_SDCD_CONFIG1_X_OT_EN; 630 break; 631 case IIO_MOD_Y: 632 enable_bits = FXLS8962AF_SDCD_CONFIG1_Y_OT_EN; 633 break; 634 case IIO_MOD_Z: 635 enable_bits = FXLS8962AF_SDCD_CONFIG1_Z_OT_EN; 636 break; 637 default: 638 return -EINVAL; 639 } 640 641 if (state) 642 enable_event = data->enable_event | enable_bits; 643 else 644 enable_event = data->enable_event & ~enable_bits; 645 646 if (data->enable_event == enable_event) 647 return 0; 648 649 ret = fxls8962af_standby(data); 650 if (ret) 651 return ret; 652 653 /* Enable events */ 654 value = enable_event | FXLS8962AF_SDCD_CONFIG1_OT_ELE; 655 ret = regmap_write(data->regmap, FXLS8962AF_SDCD_CONFIG1, value); 656 if (ret) 657 return ret; 658 659 /* 660 * Enable update of SDCD_REF_X/Y/Z values with the current decimated and 661 * trimmed X/Y/Z acceleration input data. This allows for acceleration 662 * slope detection with Data(n) to Data(n–1) always used as the input 663 * to the window comparator. 664 */ 665 value = enable_event ? 666 FXLS8962AF_SDCD_CONFIG2_SDCD_EN | FXLS8962AF_SC2_REF_UPDM_AC : 667 0x00; 668 ret = regmap_write(data->regmap, FXLS8962AF_SDCD_CONFIG2, value); 669 if (ret) 670 return ret; 671 672 ret = fxls8962af_event_setup(data, state); 673 if (ret) 674 return ret; 675 676 data->enable_event = enable_event; 677 678 if (data->enable_event) { 679 fxls8962af_active(data); 680 ret = fxls8962af_power_on(data); 681 } else { 682 ret = iio_device_claim_direct_mode(indio_dev); 683 if (ret) 684 return ret; 685 686 /* Not in buffered mode so disable power */ 687 ret = fxls8962af_power_off(data); 688 689 iio_device_release_direct_mode(indio_dev); 690 } 691 692 return ret; 693 } 694 695 static const struct iio_event_spec fxls8962af_event[] = { 696 { 697 .type = IIO_EV_TYPE_THRESH, 698 .dir = IIO_EV_DIR_EITHER, 699 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 700 }, 701 { 702 .type = IIO_EV_TYPE_THRESH, 703 .dir = IIO_EV_DIR_FALLING, 704 .mask_separate = BIT(IIO_EV_INFO_VALUE), 705 }, 706 { 707 .type = IIO_EV_TYPE_THRESH, 708 .dir = IIO_EV_DIR_RISING, 709 .mask_separate = BIT(IIO_EV_INFO_VALUE), 710 }, 711 }; 712 713 #define FXLS8962AF_CHANNEL(axis, reg, idx) { \ 714 .type = IIO_ACCEL, \ 715 .address = reg, \ 716 .modified = 1, \ 717 .channel2 = IIO_MOD_##axis, \ 718 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 719 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 720 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 721 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) | \ 722 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 723 .scan_index = idx, \ 724 .scan_type = { \ 725 .sign = 's', \ 726 .realbits = 12, \ 727 .storagebits = 16, \ 728 .shift = 4, \ 729 .endianness = IIO_BE, \ 730 }, \ 731 .event_spec = fxls8962af_event, \ 732 .num_event_specs = ARRAY_SIZE(fxls8962af_event), \ 733 } 734 735 #define FXLS8962AF_TEMP_CHANNEL { \ 736 .type = IIO_TEMP, \ 737 .address = FXLS8962AF_TEMP_OUT, \ 738 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 739 BIT(IIO_CHAN_INFO_OFFSET),\ 740 .scan_index = -1, \ 741 .scan_type = { \ 742 .realbits = 8, \ 743 .storagebits = 8, \ 744 }, \ 745 } 746 747 static const struct iio_chan_spec fxls8962af_channels[] = { 748 FXLS8962AF_CHANNEL(X, FXLS8962AF_OUT_X_LSB, fxls8962af_idx_x), 749 FXLS8962AF_CHANNEL(Y, FXLS8962AF_OUT_Y_LSB, fxls8962af_idx_y), 750 FXLS8962AF_CHANNEL(Z, FXLS8962AF_OUT_Z_LSB, fxls8962af_idx_z), 751 IIO_CHAN_SOFT_TIMESTAMP(fxls8962af_idx_ts), 752 FXLS8962AF_TEMP_CHANNEL, 753 }; 754 755 static const struct fxls8962af_chip_info fxls_chip_info_table[] = { 756 [fxls8962af] = { 757 .chip_id = FXLS8962AF_DEVICE_ID, 758 .name = "fxls8962af", 759 .channels = fxls8962af_channels, 760 .num_channels = ARRAY_SIZE(fxls8962af_channels), 761 }, 762 [fxls8964af] = { 763 .chip_id = FXLS8964AF_DEVICE_ID, 764 .name = "fxls8964af", 765 .channels = fxls8962af_channels, 766 .num_channels = ARRAY_SIZE(fxls8962af_channels), 767 }, 768 }; 769 770 static const struct iio_info fxls8962af_info = { 771 .read_raw = &fxls8962af_read_raw, 772 .write_raw = &fxls8962af_write_raw, 773 .write_raw_get_fmt = fxls8962af_write_raw_get_fmt, 774 .read_event_value = fxls8962af_read_event, 775 .write_event_value = fxls8962af_write_event, 776 .read_event_config = fxls8962af_read_event_config, 777 .write_event_config = fxls8962af_write_event_config, 778 .read_avail = fxls8962af_read_avail, 779 .hwfifo_set_watermark = fxls8962af_set_watermark, 780 }; 781 782 static int fxls8962af_reset(struct fxls8962af_data *data) 783 { 784 struct device *dev = regmap_get_device(data->regmap); 785 unsigned int reg; 786 int ret; 787 788 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG1, 789 FXLS8962AF_SENS_CONFIG1_RST, 790 FXLS8962AF_SENS_CONFIG1_RST); 791 if (ret) 792 return ret; 793 794 /* TBOOT1, TBOOT2, specifies we have to wait between 1 - 17.7ms */ 795 ret = regmap_read_poll_timeout(data->regmap, FXLS8962AF_INT_STATUS, reg, 796 (reg & FXLS8962AF_INT_STATUS_SRC_BOOT), 797 1000, 18000); 798 if (ret == -ETIMEDOUT) 799 dev_err(dev, "reset timeout, int_status = 0x%x\n", reg); 800 801 return ret; 802 } 803 804 static int __fxls8962af_fifo_set_mode(struct fxls8962af_data *data, bool onoff) 805 { 806 int ret; 807 808 /* Enable watermark at max fifo size */ 809 ret = regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG2, 810 FXLS8962AF_BUF_CONFIG2_BUF_WMRK, 811 data->watermark); 812 if (ret) 813 return ret; 814 815 return regmap_update_bits(data->regmap, FXLS8962AF_BUF_CONFIG1, 816 FXLS8962AF_BC1_BUF_MODE_MASK, 817 FXLS8962AF_BC1_BUF_MODE_PREP(onoff)); 818 } 819 820 static int fxls8962af_buffer_preenable(struct iio_dev *indio_dev) 821 { 822 return fxls8962af_power_on(iio_priv(indio_dev)); 823 } 824 825 static int fxls8962af_buffer_postenable(struct iio_dev *indio_dev) 826 { 827 struct fxls8962af_data *data = iio_priv(indio_dev); 828 int ret; 829 830 fxls8962af_standby(data); 831 832 /* Enable buffer interrupt */ 833 ret = regmap_update_bits(data->regmap, FXLS8962AF_INT_EN, 834 FXLS8962AF_INT_EN_BUF_EN, 835 FXLS8962AF_INT_EN_BUF_EN); 836 if (ret) 837 return ret; 838 839 ret = __fxls8962af_fifo_set_mode(data, true); 840 841 fxls8962af_active(data); 842 843 return ret; 844 } 845 846 static int fxls8962af_buffer_predisable(struct iio_dev *indio_dev) 847 { 848 struct fxls8962af_data *data = iio_priv(indio_dev); 849 int ret; 850 851 fxls8962af_standby(data); 852 853 /* Disable buffer interrupt */ 854 ret = regmap_update_bits(data->regmap, FXLS8962AF_INT_EN, 855 FXLS8962AF_INT_EN_BUF_EN, 0); 856 if (ret) 857 return ret; 858 859 ret = __fxls8962af_fifo_set_mode(data, false); 860 861 if (data->enable_event) 862 fxls8962af_active(data); 863 864 return ret; 865 } 866 867 static int fxls8962af_buffer_postdisable(struct iio_dev *indio_dev) 868 { 869 struct fxls8962af_data *data = iio_priv(indio_dev); 870 871 if (!data->enable_event) 872 fxls8962af_power_off(data); 873 874 return 0; 875 } 876 877 static const struct iio_buffer_setup_ops fxls8962af_buffer_ops = { 878 .preenable = fxls8962af_buffer_preenable, 879 .postenable = fxls8962af_buffer_postenable, 880 .predisable = fxls8962af_buffer_predisable, 881 .postdisable = fxls8962af_buffer_postdisable, 882 }; 883 884 static int fxls8962af_i2c_raw_read_errata3(struct fxls8962af_data *data, 885 u16 *buffer, int samples, 886 int sample_length) 887 { 888 int i, ret; 889 890 for (i = 0; i < samples; i++) { 891 ret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB, 892 &buffer[i * 3], sample_length); 893 if (ret) 894 return ret; 895 } 896 897 return 0; 898 } 899 900 static int fxls8962af_fifo_transfer(struct fxls8962af_data *data, 901 u16 *buffer, int samples) 902 { 903 struct device *dev = regmap_get_device(data->regmap); 904 int sample_length = 3 * sizeof(*buffer); 905 int total_length = samples * sample_length; 906 int ret; 907 908 if (i2c_verify_client(dev)) 909 /* 910 * Due to errata bug: 911 * E3: FIFO burst read operation error using I2C interface 912 * We have to avoid burst reads on I2C.. 913 */ 914 ret = fxls8962af_i2c_raw_read_errata3(data, buffer, samples, 915 sample_length); 916 else 917 ret = regmap_raw_read(data->regmap, FXLS8962AF_BUF_X_LSB, buffer, 918 total_length); 919 920 if (ret) 921 dev_err(dev, "Error transferring data from fifo: %d\n", ret); 922 923 return ret; 924 } 925 926 static int fxls8962af_fifo_flush(struct iio_dev *indio_dev) 927 { 928 struct fxls8962af_data *data = iio_priv(indio_dev); 929 struct device *dev = regmap_get_device(data->regmap); 930 u16 buffer[FXLS8962AF_FIFO_LENGTH * 3]; 931 uint64_t sample_period; 932 unsigned int reg; 933 int64_t tstamp; 934 int ret, i; 935 u8 count; 936 937 ret = regmap_read(data->regmap, FXLS8962AF_BUF_STATUS, ®); 938 if (ret) 939 return ret; 940 941 if (reg & FXLS8962AF_BUF_STATUS_BUF_OVF) { 942 dev_err(dev, "Buffer overflow"); 943 return -EOVERFLOW; 944 } 945 946 count = reg & FXLS8962AF_BUF_STATUS_BUF_CNT; 947 if (!count) 948 return 0; 949 950 data->old_timestamp = data->timestamp; 951 data->timestamp = iio_get_time_ns(indio_dev); 952 953 /* 954 * Approximate timestamps for each of the sample based on the sampling, 955 * frequency, timestamp for last sample and number of samples. 956 */ 957 sample_period = (data->timestamp - data->old_timestamp); 958 do_div(sample_period, count); 959 tstamp = data->timestamp - (count - 1) * sample_period; 960 961 ret = fxls8962af_fifo_transfer(data, buffer, count); 962 if (ret) 963 return ret; 964 965 /* Demux hw FIFO into kfifo. */ 966 for (i = 0; i < count; i++) { 967 int j, bit; 968 969 j = 0; 970 for_each_set_bit(bit, indio_dev->active_scan_mask, 971 indio_dev->masklength) { 972 memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit], 973 sizeof(data->scan.channels[0])); 974 } 975 976 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan, 977 tstamp); 978 979 tstamp += sample_period; 980 } 981 982 return count; 983 } 984 985 static int fxls8962af_event_interrupt(struct iio_dev *indio_dev) 986 { 987 struct fxls8962af_data *data = iio_priv(indio_dev); 988 s64 ts = iio_get_time_ns(indio_dev); 989 unsigned int reg; 990 u64 ev_code; 991 int ret; 992 993 ret = regmap_read(data->regmap, FXLS8962AF_SDCD_INT_SRC1, ®); 994 if (ret) 995 return ret; 996 997 if (reg & FXLS8962AF_SDCD_INT_SRC1_X_OT) { 998 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_X_POL ? 999 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING; 1000 iio_push_event(indio_dev, 1001 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1002 IIO_EV_TYPE_THRESH, ev_code), ts); 1003 } 1004 1005 if (reg & FXLS8962AF_SDCD_INT_SRC1_Y_OT) { 1006 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_Y_POL ? 1007 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING; 1008 iio_push_event(indio_dev, 1009 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1010 IIO_EV_TYPE_THRESH, ev_code), ts); 1011 } 1012 1013 if (reg & FXLS8962AF_SDCD_INT_SRC1_Z_OT) { 1014 ev_code = reg & FXLS8962AF_SDCD_INT_SRC1_Z_POL ? 1015 IIO_EV_DIR_RISING : IIO_EV_DIR_FALLING; 1016 iio_push_event(indio_dev, 1017 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X, 1018 IIO_EV_TYPE_THRESH, ev_code), ts); 1019 } 1020 1021 return 0; 1022 } 1023 1024 static irqreturn_t fxls8962af_interrupt(int irq, void *p) 1025 { 1026 struct iio_dev *indio_dev = p; 1027 struct fxls8962af_data *data = iio_priv(indio_dev); 1028 unsigned int reg; 1029 int ret; 1030 1031 ret = regmap_read(data->regmap, FXLS8962AF_INT_STATUS, ®); 1032 if (ret) 1033 return IRQ_NONE; 1034 1035 if (reg & FXLS8962AF_INT_STATUS_SRC_BUF) { 1036 ret = fxls8962af_fifo_flush(indio_dev); 1037 if (ret < 0) 1038 return IRQ_NONE; 1039 1040 return IRQ_HANDLED; 1041 } 1042 1043 if (reg & FXLS8962AF_INT_STATUS_SRC_SDCD_OT) { 1044 ret = fxls8962af_event_interrupt(indio_dev); 1045 if (ret < 0) 1046 return IRQ_NONE; 1047 1048 return IRQ_HANDLED; 1049 } 1050 1051 return IRQ_NONE; 1052 } 1053 1054 static void fxls8962af_regulator_disable(void *data_ptr) 1055 { 1056 struct fxls8962af_data *data = data_ptr; 1057 1058 regulator_disable(data->vdd_reg); 1059 } 1060 1061 static void fxls8962af_pm_disable(void *dev_ptr) 1062 { 1063 struct device *dev = dev_ptr; 1064 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1065 1066 pm_runtime_disable(dev); 1067 pm_runtime_set_suspended(dev); 1068 pm_runtime_put_noidle(dev); 1069 1070 fxls8962af_standby(iio_priv(indio_dev)); 1071 } 1072 1073 static void fxls8962af_get_irq(struct device_node *of_node, 1074 enum fxls8962af_int_pin *pin) 1075 { 1076 int irq; 1077 1078 irq = of_irq_get_byname(of_node, "INT2"); 1079 if (irq > 0) { 1080 *pin = FXLS8962AF_PIN_INT2; 1081 return; 1082 } 1083 1084 *pin = FXLS8962AF_PIN_INT1; 1085 } 1086 1087 static int fxls8962af_irq_setup(struct iio_dev *indio_dev, int irq) 1088 { 1089 struct fxls8962af_data *data = iio_priv(indio_dev); 1090 struct device *dev = regmap_get_device(data->regmap); 1091 unsigned long irq_type; 1092 bool irq_active_high; 1093 enum fxls8962af_int_pin int_pin; 1094 u8 int_pin_sel; 1095 int ret; 1096 1097 fxls8962af_get_irq(dev->of_node, &int_pin); 1098 switch (int_pin) { 1099 case FXLS8962AF_PIN_INT1: 1100 int_pin_sel = FXLS8962AF_INT_PIN_SEL_INT1; 1101 break; 1102 case FXLS8962AF_PIN_INT2: 1103 int_pin_sel = FXLS8962AF_INT_PIN_SEL_INT2; 1104 break; 1105 default: 1106 dev_err(dev, "unsupported int pin selected\n"); 1107 return -EINVAL; 1108 } 1109 1110 ret = regmap_update_bits(data->regmap, FXLS8962AF_INT_PIN_SEL, 1111 FXLS8962AF_INT_PIN_SEL_MASK, int_pin_sel); 1112 if (ret) 1113 return ret; 1114 1115 irq_type = irqd_get_trigger_type(irq_get_irq_data(irq)); 1116 1117 switch (irq_type) { 1118 case IRQF_TRIGGER_HIGH: 1119 case IRQF_TRIGGER_RISING: 1120 irq_active_high = true; 1121 break; 1122 case IRQF_TRIGGER_LOW: 1123 case IRQF_TRIGGER_FALLING: 1124 irq_active_high = false; 1125 break; 1126 default: 1127 dev_info(dev, "mode %lx unsupported\n", irq_type); 1128 return -EINVAL; 1129 } 1130 1131 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4, 1132 FXLS8962AF_SC4_INT_POL_MASK, 1133 FXLS8962AF_SC4_INT_POL_PREP(irq_active_high)); 1134 if (ret) 1135 return ret; 1136 1137 if (device_property_read_bool(dev, "drive-open-drain")) { 1138 ret = regmap_update_bits(data->regmap, FXLS8962AF_SENS_CONFIG4, 1139 FXLS8962AF_SC4_INT_PP_OD_MASK, 1140 FXLS8962AF_SC4_INT_PP_OD_PREP(1)); 1141 if (ret) 1142 return ret; 1143 1144 irq_type |= IRQF_SHARED; 1145 } 1146 1147 return devm_request_threaded_irq(dev, 1148 irq, 1149 NULL, fxls8962af_interrupt, 1150 irq_type | IRQF_ONESHOT, 1151 indio_dev->name, indio_dev); 1152 } 1153 1154 int fxls8962af_core_probe(struct device *dev, struct regmap *regmap, int irq) 1155 { 1156 struct fxls8962af_data *data; 1157 struct iio_dev *indio_dev; 1158 unsigned int reg; 1159 int ret, i; 1160 1161 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1162 if (!indio_dev) 1163 return -ENOMEM; 1164 1165 data = iio_priv(indio_dev); 1166 dev_set_drvdata(dev, indio_dev); 1167 data->regmap = regmap; 1168 data->irq = irq; 1169 1170 ret = iio_read_mount_matrix(dev, &data->orientation); 1171 if (ret) 1172 return ret; 1173 1174 data->vdd_reg = devm_regulator_get(dev, "vdd"); 1175 if (IS_ERR(data->vdd_reg)) 1176 return dev_err_probe(dev, PTR_ERR(data->vdd_reg), 1177 "Failed to get vdd regulator\n"); 1178 1179 ret = regulator_enable(data->vdd_reg); 1180 if (ret) { 1181 dev_err(dev, "Failed to enable vdd regulator: %d\n", ret); 1182 return ret; 1183 } 1184 1185 ret = devm_add_action_or_reset(dev, fxls8962af_regulator_disable, data); 1186 if (ret) 1187 return ret; 1188 1189 ret = regmap_read(data->regmap, FXLS8962AF_WHO_AM_I, ®); 1190 if (ret) 1191 return ret; 1192 1193 for (i = 0; i < ARRAY_SIZE(fxls_chip_info_table); i++) { 1194 if (fxls_chip_info_table[i].chip_id == reg) { 1195 data->chip_info = &fxls_chip_info_table[i]; 1196 break; 1197 } 1198 } 1199 if (i == ARRAY_SIZE(fxls_chip_info_table)) { 1200 dev_err(dev, "failed to match device in table\n"); 1201 return -ENXIO; 1202 } 1203 1204 indio_dev->channels = data->chip_info->channels; 1205 indio_dev->num_channels = data->chip_info->num_channels; 1206 indio_dev->name = data->chip_info->name; 1207 indio_dev->info = &fxls8962af_info; 1208 indio_dev->modes = INDIO_DIRECT_MODE; 1209 1210 ret = fxls8962af_reset(data); 1211 if (ret) 1212 return ret; 1213 1214 if (irq) { 1215 ret = fxls8962af_irq_setup(indio_dev, irq); 1216 if (ret) 1217 return ret; 1218 1219 ret = devm_iio_kfifo_buffer_setup(dev, indio_dev, 1220 INDIO_BUFFER_SOFTWARE, 1221 &fxls8962af_buffer_ops); 1222 if (ret) 1223 return ret; 1224 } 1225 1226 ret = pm_runtime_set_active(dev); 1227 if (ret) 1228 return ret; 1229 1230 pm_runtime_enable(dev); 1231 pm_runtime_set_autosuspend_delay(dev, FXLS8962AF_AUTO_SUSPEND_DELAY_MS); 1232 pm_runtime_use_autosuspend(dev); 1233 1234 ret = devm_add_action_or_reset(dev, fxls8962af_pm_disable, dev); 1235 if (ret) 1236 return ret; 1237 1238 if (device_property_read_bool(dev, "wakeup-source")) 1239 device_init_wakeup(dev, true); 1240 1241 return devm_iio_device_register(dev, indio_dev); 1242 } 1243 EXPORT_SYMBOL_GPL(fxls8962af_core_probe); 1244 1245 static int __maybe_unused fxls8962af_runtime_suspend(struct device *dev) 1246 { 1247 struct fxls8962af_data *data = iio_priv(dev_get_drvdata(dev)); 1248 int ret; 1249 1250 ret = fxls8962af_standby(data); 1251 if (ret) { 1252 dev_err(dev, "powering off device failed\n"); 1253 return ret; 1254 } 1255 1256 return 0; 1257 } 1258 1259 static int __maybe_unused fxls8962af_runtime_resume(struct device *dev) 1260 { 1261 struct fxls8962af_data *data = iio_priv(dev_get_drvdata(dev)); 1262 1263 return fxls8962af_active(data); 1264 } 1265 1266 static int __maybe_unused fxls8962af_suspend(struct device *dev) 1267 { 1268 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1269 struct fxls8962af_data *data = iio_priv(indio_dev); 1270 1271 if (device_may_wakeup(dev) && data->enable_event) { 1272 enable_irq_wake(data->irq); 1273 1274 /* 1275 * Disable buffer, as the buffer is so small the device will wake 1276 * almost immediately. 1277 */ 1278 if (iio_buffer_enabled(indio_dev)) 1279 fxls8962af_buffer_predisable(indio_dev); 1280 } else { 1281 fxls8962af_runtime_suspend(dev); 1282 } 1283 1284 return 0; 1285 } 1286 1287 static int __maybe_unused fxls8962af_resume(struct device *dev) 1288 { 1289 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1290 struct fxls8962af_data *data = iio_priv(indio_dev); 1291 1292 if (device_may_wakeup(dev) && data->enable_event) { 1293 disable_irq_wake(data->irq); 1294 1295 if (iio_buffer_enabled(indio_dev)) 1296 fxls8962af_buffer_postenable(indio_dev); 1297 } else { 1298 fxls8962af_runtime_resume(dev); 1299 } 1300 1301 return 0; 1302 } 1303 1304 const struct dev_pm_ops fxls8962af_pm_ops = { 1305 SET_SYSTEM_SLEEP_PM_OPS(fxls8962af_suspend, fxls8962af_resume) 1306 SET_RUNTIME_PM_OPS(fxls8962af_runtime_suspend, 1307 fxls8962af_runtime_resume, NULL) 1308 }; 1309 EXPORT_SYMBOL_GPL(fxls8962af_pm_ops); 1310 1311 MODULE_AUTHOR("Sean Nyekjaer <sean@geanix.com>"); 1312 MODULE_DESCRIPTION("NXP FXLS8962AF/FXLS8964AF accelerometer driver"); 1313 MODULE_LICENSE("GPL v2"); 1314