1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
4  *  - BMI088
5  *
6  * Copyright (c) 2018-2021, Topic Embedded Products
7  */
8 
9 #include <linux/bitfield.h>
10 #include <linux/delay.h>
11 #include <linux/iio/iio.h>
12 #include <linux/iio/sysfs.h>
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/pm.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regmap.h>
18 #include <linux/slab.h>
19 #include <asm/unaligned.h>
20 
21 #include "bmi088-accel.h"
22 
23 #define BMI088_ACCEL_REG_CHIP_ID			0x00
24 #define BMI088_ACCEL_REG_ERROR				0x02
25 
26 #define BMI088_ACCEL_REG_INT_STATUS			0x1D
27 #define BMI088_ACCEL_INT_STATUS_BIT_DRDY		BIT(7)
28 
29 #define BMI088_ACCEL_REG_RESET				0x7E
30 #define BMI088_ACCEL_RESET_VAL				0xB6
31 
32 #define BMI088_ACCEL_REG_PWR_CTRL			0x7D
33 #define BMI088_ACCEL_REG_PWR_CONF			0x7C
34 
35 #define BMI088_ACCEL_REG_INT_MAP_DATA			0x58
36 #define BMI088_ACCEL_INT_MAP_DATA_BIT_INT1_DRDY		BIT(2)
37 #define BMI088_ACCEL_INT_MAP_DATA_BIT_INT2_FWM		BIT(5)
38 
39 #define BMI088_ACCEL_REG_INT1_IO_CONF			0x53
40 #define BMI088_ACCEL_INT1_IO_CONF_BIT_ENABLE_OUT	BIT(3)
41 #define BMI088_ACCEL_INT1_IO_CONF_BIT_LVL		BIT(1)
42 
43 #define BMI088_ACCEL_REG_INT2_IO_CONF			0x54
44 #define BMI088_ACCEL_INT2_IO_CONF_BIT_ENABLE_OUT	BIT(3)
45 #define BMI088_ACCEL_INT2_IO_CONF_BIT_LVL		BIT(1)
46 
47 #define BMI088_ACCEL_REG_ACC_CONF			0x40
48 #define BMI088_ACCEL_MODE_ODR_MASK			0x0f
49 
50 #define BMI088_ACCEL_REG_ACC_RANGE			0x41
51 #define BMI088_ACCEL_RANGE_3G				0x00
52 #define BMI088_ACCEL_RANGE_6G				0x01
53 #define BMI088_ACCEL_RANGE_12G				0x02
54 #define BMI088_ACCEL_RANGE_24G				0x03
55 
56 #define BMI088_ACCEL_REG_TEMP				0x22
57 #define BMI088_ACCEL_REG_TEMP_SHIFT			5
58 #define BMI088_ACCEL_TEMP_UNIT				125
59 #define BMI088_ACCEL_TEMP_OFFSET			23000
60 
61 #define BMI088_ACCEL_REG_XOUT_L				0x12
62 #define BMI088_ACCEL_AXIS_TO_REG(axis) \
63 	(BMI088_ACCEL_REG_XOUT_L + (axis * 2))
64 
65 #define BMI088_ACCEL_MAX_STARTUP_TIME_US		1000
66 #define BMI088_AUTO_SUSPEND_DELAY_MS			2000
67 
68 #define BMI088_ACCEL_REG_FIFO_STATUS			0x0E
69 #define BMI088_ACCEL_REG_FIFO_CONFIG0			0x48
70 #define BMI088_ACCEL_REG_FIFO_CONFIG1			0x49
71 #define BMI088_ACCEL_REG_FIFO_DATA			0x3F
72 #define BMI088_ACCEL_FIFO_LENGTH			100
73 
74 #define BMI088_ACCEL_FIFO_MODE_FIFO			0x40
75 #define BMI088_ACCEL_FIFO_MODE_STREAM			0x80
76 
77 #define BMIO088_ACCEL_ACC_RANGE_MSK			GENMASK(1, 0)
78 
79 enum bmi088_accel_axis {
80 	AXIS_X,
81 	AXIS_Y,
82 	AXIS_Z,
83 };
84 
85 static const int bmi088_sample_freqs[] = {
86 	12, 500000,
87 	25, 0,
88 	50, 0,
89 	100, 0,
90 	200, 0,
91 	400, 0,
92 	800, 0,
93 	1600, 0,
94 };
95 
96 /* Available OSR (over sampling rate) sets the 3dB cut-off frequency */
97 enum bmi088_osr_modes {
98 	BMI088_ACCEL_MODE_OSR_NORMAL = 0xA,
99 	BMI088_ACCEL_MODE_OSR_2 = 0x9,
100 	BMI088_ACCEL_MODE_OSR_4 = 0x8,
101 };
102 
103 /* Available ODR (output data rates) in Hz */
104 enum bmi088_odr_modes {
105 	BMI088_ACCEL_MODE_ODR_12_5 = 0x5,
106 	BMI088_ACCEL_MODE_ODR_25 = 0x6,
107 	BMI088_ACCEL_MODE_ODR_50 = 0x7,
108 	BMI088_ACCEL_MODE_ODR_100 = 0x8,
109 	BMI088_ACCEL_MODE_ODR_200 = 0x9,
110 	BMI088_ACCEL_MODE_ODR_400 = 0xa,
111 	BMI088_ACCEL_MODE_ODR_800 = 0xb,
112 	BMI088_ACCEL_MODE_ODR_1600 = 0xc,
113 };
114 
115 struct bmi088_scale_info {
116 	int scale;
117 	u8 reg_range;
118 };
119 
120 struct bmi088_accel_chip_info {
121 	const char *name;
122 	u8 chip_id;
123 	const struct iio_chan_spec *channels;
124 	int num_channels;
125 	const int scale_table[4][2];
126 };
127 
128 struct bmi088_accel_data {
129 	struct regmap *regmap;
130 	const struct bmi088_accel_chip_info *chip_info;
131 	u8 buffer[2] __aligned(IIO_DMA_MINALIGN); /* shared DMA safe buffer */
132 };
133 
134 static const struct regmap_range bmi088_volatile_ranges[] = {
135 	/* All registers below 0x40 are volatile, except the CHIP ID. */
136 	regmap_reg_range(BMI088_ACCEL_REG_ERROR, 0x3f),
137 	/* Mark the RESET as volatile too, it is self-clearing */
138 	regmap_reg_range(BMI088_ACCEL_REG_RESET, BMI088_ACCEL_REG_RESET),
139 };
140 
141 static const struct regmap_access_table bmi088_volatile_table = {
142 	.yes_ranges	= bmi088_volatile_ranges,
143 	.n_yes_ranges	= ARRAY_SIZE(bmi088_volatile_ranges),
144 };
145 
146 const struct regmap_config bmi088_regmap_conf = {
147 	.reg_bits = 8,
148 	.val_bits = 8,
149 	.max_register = 0x7E,
150 	.volatile_table = &bmi088_volatile_table,
151 	.cache_type = REGCACHE_RBTREE,
152 };
153 EXPORT_SYMBOL_NS_GPL(bmi088_regmap_conf, IIO_BMI088);
154 
155 static int bmi088_accel_power_up(struct bmi088_accel_data *data)
156 {
157 	int ret;
158 
159 	/* Enable accelerometer and temperature sensor */
160 	ret = regmap_write(data->regmap, BMI088_ACCEL_REG_PWR_CTRL, 0x4);
161 	if (ret)
162 		return ret;
163 
164 	/* Datasheet recommends to wait at least 5ms before communication */
165 	usleep_range(5000, 6000);
166 
167 	/* Disable suspend mode */
168 	ret = regmap_write(data->regmap, BMI088_ACCEL_REG_PWR_CONF, 0x0);
169 	if (ret)
170 		return ret;
171 
172 	/* Recommended at least 1ms before further communication */
173 	usleep_range(1000, 1200);
174 
175 	return 0;
176 }
177 
178 static int bmi088_accel_power_down(struct bmi088_accel_data *data)
179 {
180 	int ret;
181 
182 	/* Enable suspend mode */
183 	ret = regmap_write(data->regmap, BMI088_ACCEL_REG_PWR_CONF, 0x3);
184 	if (ret)
185 		return ret;
186 
187 	/* Recommended at least 1ms before further communication */
188 	usleep_range(1000, 1200);
189 
190 	/* Disable accelerometer and temperature sensor */
191 	ret = regmap_write(data->regmap, BMI088_ACCEL_REG_PWR_CTRL, 0x0);
192 	if (ret)
193 		return ret;
194 
195 	/* Datasheet recommends to wait at least 5ms before communication */
196 	usleep_range(5000, 6000);
197 
198 	return 0;
199 }
200 
201 static int bmi088_accel_get_sample_freq(struct bmi088_accel_data *data,
202 					int *val, int *val2)
203 {
204 	unsigned int value;
205 	int ret;
206 
207 	ret = regmap_read(data->regmap, BMI088_ACCEL_REG_ACC_CONF,
208 			  &value);
209 	if (ret)
210 		return ret;
211 
212 	value &= BMI088_ACCEL_MODE_ODR_MASK;
213 	value -= BMI088_ACCEL_MODE_ODR_12_5;
214 	value <<= 1;
215 
216 	if (value >= ARRAY_SIZE(bmi088_sample_freqs) - 1)
217 		return -EINVAL;
218 
219 	*val = bmi088_sample_freqs[value];
220 	*val2 = bmi088_sample_freqs[value + 1];
221 
222 	return IIO_VAL_INT_PLUS_MICRO;
223 }
224 
225 static int bmi088_accel_set_sample_freq(struct bmi088_accel_data *data, int val)
226 {
227 	unsigned int regval;
228 	int index = 0;
229 
230 	while (index < ARRAY_SIZE(bmi088_sample_freqs) &&
231 	       bmi088_sample_freqs[index] != val)
232 		index += 2;
233 
234 	if (index >= ARRAY_SIZE(bmi088_sample_freqs))
235 		return -EINVAL;
236 
237 	regval = (index >> 1) + BMI088_ACCEL_MODE_ODR_12_5;
238 
239 	return regmap_update_bits(data->regmap, BMI088_ACCEL_REG_ACC_CONF,
240 				  BMI088_ACCEL_MODE_ODR_MASK, regval);
241 }
242 
243 static int bmi088_accel_set_scale(struct bmi088_accel_data *data, int val, int val2)
244 {
245 	unsigned int i;
246 
247 	for (i = 0; i < 4; i++)
248 		if (val  == data->chip_info->scale_table[i][0] &&
249 		    val2 == data->chip_info->scale_table[i][1])
250 			break;
251 
252 	if (i == 4)
253 		return -EINVAL;
254 
255 	return regmap_write(data->regmap, BMI088_ACCEL_REG_ACC_RANGE, i);
256 }
257 
258 static int bmi088_accel_get_temp(struct bmi088_accel_data *data, int *val)
259 {
260 	int ret;
261 	s16 temp;
262 
263 	ret = regmap_bulk_read(data->regmap, BMI088_ACCEL_REG_TEMP,
264 			       &data->buffer, sizeof(__be16));
265 	if (ret)
266 		return ret;
267 
268 	/* data->buffer is cacheline aligned */
269 	temp = be16_to_cpu(*(__be16 *)data->buffer);
270 
271 	*val = temp >> BMI088_ACCEL_REG_TEMP_SHIFT;
272 
273 	return IIO_VAL_INT;
274 }
275 
276 static int bmi088_accel_get_axis(struct bmi088_accel_data *data,
277 				 struct iio_chan_spec const *chan,
278 				 int *val)
279 {
280 	int ret;
281 	s16 raw_val;
282 
283 	ret = regmap_bulk_read(data->regmap,
284 			       BMI088_ACCEL_AXIS_TO_REG(chan->scan_index),
285 			       data->buffer, sizeof(__le16));
286 	if (ret)
287 		return ret;
288 
289 	raw_val = le16_to_cpu(*(__le16 *)data->buffer);
290 	*val = raw_val;
291 
292 	return IIO_VAL_INT;
293 }
294 
295 static int bmi088_accel_read_raw(struct iio_dev *indio_dev,
296 				 struct iio_chan_spec const *chan,
297 				 int *val, int *val2, long mask)
298 {
299 	struct bmi088_accel_data *data = iio_priv(indio_dev);
300 	struct device *dev = regmap_get_device(data->regmap);
301 	int ret;
302 	int reg;
303 
304 	switch (mask) {
305 	case IIO_CHAN_INFO_RAW:
306 		switch (chan->type) {
307 		case IIO_TEMP:
308 			ret = pm_runtime_resume_and_get(dev);
309 			if (ret)
310 				return ret;
311 
312 			ret = bmi088_accel_get_temp(data, val);
313 			goto out_read_raw_pm_put;
314 		case IIO_ACCEL:
315 			ret = pm_runtime_resume_and_get(dev);
316 			if (ret)
317 				return ret;
318 
319 			ret = iio_device_claim_direct_mode(indio_dev);
320 			if (ret)
321 				goto out_read_raw_pm_put;
322 
323 			ret = bmi088_accel_get_axis(data, chan, val);
324 			iio_device_release_direct_mode(indio_dev);
325 			if (!ret)
326 				ret = IIO_VAL_INT;
327 
328 			goto out_read_raw_pm_put;
329 		default:
330 			return -EINVAL;
331 		}
332 	case IIO_CHAN_INFO_OFFSET:
333 		switch (chan->type) {
334 		case IIO_TEMP:
335 			/* Offset applies before scale */
336 			*val = BMI088_ACCEL_TEMP_OFFSET/BMI088_ACCEL_TEMP_UNIT;
337 			return IIO_VAL_INT;
338 		default:
339 			return -EINVAL;
340 		}
341 	case IIO_CHAN_INFO_SCALE:
342 		switch (chan->type) {
343 		case IIO_TEMP:
344 			/* 0.125 degrees per LSB */
345 			*val = BMI088_ACCEL_TEMP_UNIT;
346 			return IIO_VAL_INT;
347 		case IIO_ACCEL:
348 			ret = pm_runtime_resume_and_get(dev);
349 			if (ret)
350 				return ret;
351 
352 			ret = regmap_read(data->regmap,
353 					  BMI088_ACCEL_REG_ACC_RANGE, &reg);
354 			if (ret)
355 				goto out_read_raw_pm_put;
356 
357 			reg = FIELD_GET(BMIO088_ACCEL_ACC_RANGE_MSK, reg);
358 			*val  = data->chip_info->scale_table[reg][0];
359 			*val2 = data->chip_info->scale_table[reg][1];
360 			ret = IIO_VAL_INT_PLUS_MICRO;
361 
362 			goto out_read_raw_pm_put;
363 		default:
364 			return -EINVAL;
365 		}
366 	case IIO_CHAN_INFO_SAMP_FREQ:
367 		ret = pm_runtime_resume_and_get(dev);
368 		if (ret)
369 			return ret;
370 
371 		ret = bmi088_accel_get_sample_freq(data, val, val2);
372 		goto out_read_raw_pm_put;
373 	default:
374 		break;
375 	}
376 
377 	return -EINVAL;
378 
379 out_read_raw_pm_put:
380 	pm_runtime_mark_last_busy(dev);
381 	pm_runtime_put_autosuspend(dev);
382 
383 	return ret;
384 }
385 
386 static int bmi088_accel_read_avail(struct iio_dev *indio_dev,
387 			     struct iio_chan_spec const *chan,
388 			     const int **vals, int *type, int *length,
389 			     long mask)
390 {
391 	struct bmi088_accel_data *data = iio_priv(indio_dev);
392 
393 	switch (mask) {
394 	case IIO_CHAN_INFO_SCALE:
395 		*vals = (const int *)data->chip_info->scale_table;
396 		*length = 8;
397 		*type = IIO_VAL_INT_PLUS_MICRO;
398 		return IIO_AVAIL_LIST;
399 	case IIO_CHAN_INFO_SAMP_FREQ:
400 		*type = IIO_VAL_INT_PLUS_MICRO;
401 		*vals = bmi088_sample_freqs;
402 		*length = ARRAY_SIZE(bmi088_sample_freqs);
403 		return IIO_AVAIL_LIST;
404 	default:
405 		return -EINVAL;
406 	}
407 }
408 
409 static int bmi088_accel_write_raw(struct iio_dev *indio_dev,
410 				  struct iio_chan_spec const *chan,
411 				  int val, int val2, long mask)
412 {
413 	struct bmi088_accel_data *data = iio_priv(indio_dev);
414 	struct device *dev = regmap_get_device(data->regmap);
415 	int ret;
416 
417 	switch (mask) {
418 	case IIO_CHAN_INFO_SCALE:
419 		ret = pm_runtime_resume_and_get(dev);
420 		if (ret)
421 			return ret;
422 
423 		ret = bmi088_accel_set_scale(data, val, val2);
424 		pm_runtime_mark_last_busy(dev);
425 		pm_runtime_put_autosuspend(dev);
426 		return ret;
427 	case IIO_CHAN_INFO_SAMP_FREQ:
428 		ret = pm_runtime_resume_and_get(dev);
429 		if (ret)
430 			return ret;
431 
432 		ret = bmi088_accel_set_sample_freq(data, val);
433 		pm_runtime_mark_last_busy(dev);
434 		pm_runtime_put_autosuspend(dev);
435 		return ret;
436 	default:
437 		return -EINVAL;
438 	}
439 }
440 
441 #define BMI088_ACCEL_CHANNEL(_axis) { \
442 	.type = IIO_ACCEL, \
443 	.modified = 1, \
444 	.channel2 = IIO_MOD_##_axis, \
445 	.info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
446 	.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
447 				BIT(IIO_CHAN_INFO_SAMP_FREQ), \
448 	.info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
449 				BIT(IIO_CHAN_INFO_SCALE), \
450 	.scan_index = AXIS_##_axis, \
451 }
452 
453 static const struct iio_chan_spec bmi088_accel_channels[] = {
454 	{
455 		.type = IIO_TEMP,
456 		.info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
457 				      BIT(IIO_CHAN_INFO_SCALE) |
458 				      BIT(IIO_CHAN_INFO_OFFSET),
459 		.scan_index = -1,
460 	},
461 	BMI088_ACCEL_CHANNEL(X),
462 	BMI088_ACCEL_CHANNEL(Y),
463 	BMI088_ACCEL_CHANNEL(Z),
464 	IIO_CHAN_SOFT_TIMESTAMP(3),
465 };
466 
467 static const struct bmi088_accel_chip_info bmi088_accel_chip_info_tbl[] = {
468 	[BOSCH_BMI085] = {
469 		.name = "bmi085-accel",
470 		.chip_id = 0x1F,
471 		.channels = bmi088_accel_channels,
472 		.num_channels = ARRAY_SIZE(bmi088_accel_channels),
473 		.scale_table = {{0, 598}, {0, 1196}, {0, 2393}, {0, 4785}},
474 	},
475 	[BOSCH_BMI088] = {
476 		.name = "bmi088-accel",
477 		.chip_id = 0x1E,
478 		.channels = bmi088_accel_channels,
479 		.num_channels = ARRAY_SIZE(bmi088_accel_channels),
480 		.scale_table = {{0, 897}, {0, 1794}, {0, 3589}, {0, 7178}},
481 	},
482 	[BOSCH_BMI090L] = {
483 		.name = "bmi090l-accel",
484 		.chip_id = 0x1A,
485 		.channels = bmi088_accel_channels,
486 		.num_channels = ARRAY_SIZE(bmi088_accel_channels),
487 		.scale_table = {{0, 897}, {0, 1794}, {0, 3589}, {0, 7178}},
488 	},
489 };
490 
491 static const struct iio_info bmi088_accel_info = {
492 	.read_raw	= bmi088_accel_read_raw,
493 	.write_raw	= bmi088_accel_write_raw,
494 	.read_avail	= bmi088_accel_read_avail,
495 };
496 
497 static const unsigned long bmi088_accel_scan_masks[] = {
498 	BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
499 	0
500 };
501 
502 static int bmi088_accel_chip_init(struct bmi088_accel_data *data, enum bmi_device_type type)
503 {
504 	struct device *dev = regmap_get_device(data->regmap);
505 	int ret, i;
506 	unsigned int val;
507 
508 	if (type >= BOSCH_UNKNOWN)
509 		return -ENODEV;
510 
511 	/* Do a dummy read to enable SPI interface, won't harm I2C */
512 	regmap_read(data->regmap, BMI088_ACCEL_REG_INT_STATUS, &val);
513 
514 	/*
515 	 * Reset chip to get it in a known good state. A delay of 1ms after
516 	 * reset is required according to the data sheet
517 	 */
518 	ret = regmap_write(data->regmap, BMI088_ACCEL_REG_RESET,
519 			   BMI088_ACCEL_RESET_VAL);
520 	if (ret)
521 		return ret;
522 
523 	usleep_range(1000, 2000);
524 
525 	/* Do a dummy read again after a reset to enable the SPI interface */
526 	regmap_read(data->regmap, BMI088_ACCEL_REG_INT_STATUS, &val);
527 
528 	/* Read chip ID */
529 	ret = regmap_read(data->regmap, BMI088_ACCEL_REG_CHIP_ID, &val);
530 	if (ret) {
531 		dev_err(dev, "Error: Reading chip id\n");
532 		return ret;
533 	}
534 
535 	/* Validate chip ID */
536 	for (i = 0; i < ARRAY_SIZE(bmi088_accel_chip_info_tbl); i++)
537 		if (bmi088_accel_chip_info_tbl[i].chip_id == val)
538 			break;
539 
540 	if (i == ARRAY_SIZE(bmi088_accel_chip_info_tbl))
541 		data->chip_info = &bmi088_accel_chip_info_tbl[type];
542 	else
543 		data->chip_info = &bmi088_accel_chip_info_tbl[i];
544 
545 	if (i != type)
546 		dev_warn(dev, "unexpected chip id 0x%X\n", val);
547 
548 	return 0;
549 }
550 
551 int bmi088_accel_core_probe(struct device *dev, struct regmap *regmap,
552 	int irq, enum bmi_device_type type)
553 {
554 	struct bmi088_accel_data *data;
555 	struct iio_dev *indio_dev;
556 	int ret;
557 
558 	indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
559 	if (!indio_dev)
560 		return -ENOMEM;
561 
562 	data = iio_priv(indio_dev);
563 	dev_set_drvdata(dev, indio_dev);
564 
565 	data->regmap = regmap;
566 
567 	ret = bmi088_accel_chip_init(data, type);
568 	if (ret)
569 		return ret;
570 
571 	indio_dev->channels = data->chip_info->channels;
572 	indio_dev->num_channels = data->chip_info->num_channels;
573 	indio_dev->name = data->chip_info->name;
574 	indio_dev->available_scan_masks = bmi088_accel_scan_masks;
575 	indio_dev->modes = INDIO_DIRECT_MODE;
576 	indio_dev->info = &bmi088_accel_info;
577 
578 	/* Enable runtime PM */
579 	pm_runtime_get_noresume(dev);
580 	pm_runtime_set_suspended(dev);
581 	pm_runtime_enable(dev);
582 	/* We need ~6ms to startup, so set the delay to 6 seconds */
583 	pm_runtime_set_autosuspend_delay(dev, 6000);
584 	pm_runtime_use_autosuspend(dev);
585 	pm_runtime_put(dev);
586 
587 	ret = iio_device_register(indio_dev);
588 	if (ret)
589 		dev_err(dev, "Unable to register iio device\n");
590 
591 	return ret;
592 }
593 EXPORT_SYMBOL_NS_GPL(bmi088_accel_core_probe, IIO_BMI088);
594 
595 
596 void bmi088_accel_core_remove(struct device *dev)
597 {
598 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
599 	struct bmi088_accel_data *data = iio_priv(indio_dev);
600 
601 	iio_device_unregister(indio_dev);
602 
603 	pm_runtime_disable(dev);
604 	pm_runtime_set_suspended(dev);
605 	bmi088_accel_power_down(data);
606 }
607 EXPORT_SYMBOL_NS_GPL(bmi088_accel_core_remove, IIO_BMI088);
608 
609 static int bmi088_accel_runtime_suspend(struct device *dev)
610 {
611 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
612 	struct bmi088_accel_data *data = iio_priv(indio_dev);
613 
614 	return bmi088_accel_power_down(data);
615 }
616 
617 static int bmi088_accel_runtime_resume(struct device *dev)
618 {
619 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
620 	struct bmi088_accel_data *data = iio_priv(indio_dev);
621 
622 	return bmi088_accel_power_up(data);
623 }
624 
625 EXPORT_NS_GPL_RUNTIME_DEV_PM_OPS(bmi088_accel_pm_ops,
626 				 bmi088_accel_runtime_suspend,
627 				 bmi088_accel_runtime_resume, NULL,
628 				 IIO_BMI088);
629 
630 MODULE_AUTHOR("Niek van Agt <niek.van.agt@topicproducts.com>");
631 MODULE_LICENSE("GPL v2");
632 MODULE_DESCRIPTION("BMI088 accelerometer driver (core)");
633