1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips: 4 * - BMC150 5 * - BMI055 6 * - BMA255 7 * - BMA250E 8 * - BMA222E 9 * - BMA280 10 * 11 * Copyright (c) 2014, Intel Corporation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/i2c.h> 16 #include <linux/interrupt.h> 17 #include <linux/delay.h> 18 #include <linux/slab.h> 19 #include <linux/acpi.h> 20 #include <linux/pm.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/iio/iio.h> 23 #include <linux/iio/sysfs.h> 24 #include <linux/iio/buffer.h> 25 #include <linux/iio/events.h> 26 #include <linux/iio/trigger.h> 27 #include <linux/iio/trigger_consumer.h> 28 #include <linux/iio/triggered_buffer.h> 29 #include <linux/regmap.h> 30 31 #include "bmc150-accel.h" 32 33 #define BMC150_ACCEL_DRV_NAME "bmc150_accel" 34 #define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event" 35 36 #define BMC150_ACCEL_REG_CHIP_ID 0x00 37 38 #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B 39 #define BMC150_ACCEL_ANY_MOTION_MASK 0x07 40 #define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0) 41 #define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1) 42 #define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2) 43 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3) 44 45 #define BMC150_ACCEL_REG_PMU_LPW 0x11 46 #define BMC150_ACCEL_PMU_MODE_MASK 0xE0 47 #define BMC150_ACCEL_PMU_MODE_SHIFT 5 48 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17 49 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1 50 51 #define BMC150_ACCEL_REG_PMU_RANGE 0x0F 52 53 #define BMC150_ACCEL_DEF_RANGE_2G 0x03 54 #define BMC150_ACCEL_DEF_RANGE_4G 0x05 55 #define BMC150_ACCEL_DEF_RANGE_8G 0x08 56 #define BMC150_ACCEL_DEF_RANGE_16G 0x0C 57 58 /* Default BW: 125Hz */ 59 #define BMC150_ACCEL_REG_PMU_BW 0x10 60 #define BMC150_ACCEL_DEF_BW 125 61 62 #define BMC150_ACCEL_REG_RESET 0x14 63 #define BMC150_ACCEL_RESET_VAL 0xB6 64 65 #define BMC150_ACCEL_REG_INT_MAP_0 0x19 66 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2) 67 68 #define BMC150_ACCEL_REG_INT_MAP_1 0x1A 69 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0) 70 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1) 71 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2) 72 73 #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21 74 #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80 75 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F 76 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00 77 78 #define BMC150_ACCEL_REG_INT_EN_0 0x16 79 #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0) 80 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1) 81 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2) 82 83 #define BMC150_ACCEL_REG_INT_EN_1 0x17 84 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4) 85 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5) 86 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6) 87 88 #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20 89 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0) 90 91 #define BMC150_ACCEL_REG_INT_5 0x27 92 #define BMC150_ACCEL_SLOPE_DUR_MASK 0x03 93 94 #define BMC150_ACCEL_REG_INT_6 0x28 95 #define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF 96 97 /* Slope duration in terms of number of samples */ 98 #define BMC150_ACCEL_DEF_SLOPE_DURATION 1 99 /* in terms of multiples of g's/LSB, based on range */ 100 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1 101 102 #define BMC150_ACCEL_REG_XOUT_L 0x02 103 104 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100 105 106 /* Sleep Duration values */ 107 #define BMC150_ACCEL_SLEEP_500_MICRO 0x05 108 #define BMC150_ACCEL_SLEEP_1_MS 0x06 109 #define BMC150_ACCEL_SLEEP_2_MS 0x07 110 #define BMC150_ACCEL_SLEEP_4_MS 0x08 111 #define BMC150_ACCEL_SLEEP_6_MS 0x09 112 #define BMC150_ACCEL_SLEEP_10_MS 0x0A 113 #define BMC150_ACCEL_SLEEP_25_MS 0x0B 114 #define BMC150_ACCEL_SLEEP_50_MS 0x0C 115 #define BMC150_ACCEL_SLEEP_100_MS 0x0D 116 #define BMC150_ACCEL_SLEEP_500_MS 0x0E 117 #define BMC150_ACCEL_SLEEP_1_SEC 0x0F 118 119 #define BMC150_ACCEL_REG_TEMP 0x08 120 #define BMC150_ACCEL_TEMP_CENTER_VAL 23 121 122 #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2)) 123 #define BMC150_AUTO_SUSPEND_DELAY_MS 2000 124 125 #define BMC150_ACCEL_REG_FIFO_STATUS 0x0E 126 #define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30 127 #define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E 128 #define BMC150_ACCEL_REG_FIFO_DATA 0x3F 129 #define BMC150_ACCEL_FIFO_LENGTH 32 130 131 enum bmc150_accel_axis { 132 AXIS_X, 133 AXIS_Y, 134 AXIS_Z, 135 AXIS_MAX, 136 }; 137 138 enum bmc150_power_modes { 139 BMC150_ACCEL_SLEEP_MODE_NORMAL, 140 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 141 BMC150_ACCEL_SLEEP_MODE_LPM, 142 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04, 143 }; 144 145 struct bmc150_scale_info { 146 int scale; 147 u8 reg_range; 148 }; 149 150 struct bmc150_accel_chip_info { 151 const char *name; 152 u8 chip_id; 153 const struct iio_chan_spec *channels; 154 int num_channels; 155 const struct bmc150_scale_info scale_table[4]; 156 }; 157 158 struct bmc150_accel_interrupt { 159 const struct bmc150_accel_interrupt_info *info; 160 atomic_t users; 161 }; 162 163 struct bmc150_accel_trigger { 164 struct bmc150_accel_data *data; 165 struct iio_trigger *indio_trig; 166 int (*setup)(struct bmc150_accel_trigger *t, bool state); 167 int intr; 168 bool enabled; 169 }; 170 171 enum bmc150_accel_interrupt_id { 172 BMC150_ACCEL_INT_DATA_READY, 173 BMC150_ACCEL_INT_ANY_MOTION, 174 BMC150_ACCEL_INT_WATERMARK, 175 BMC150_ACCEL_INTERRUPTS, 176 }; 177 178 enum bmc150_accel_trigger_id { 179 BMC150_ACCEL_TRIGGER_DATA_READY, 180 BMC150_ACCEL_TRIGGER_ANY_MOTION, 181 BMC150_ACCEL_TRIGGERS, 182 }; 183 184 struct bmc150_accel_data { 185 struct regmap *regmap; 186 int irq; 187 struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS]; 188 struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS]; 189 struct mutex mutex; 190 u8 fifo_mode, watermark; 191 s16 buffer[8]; 192 /* 193 * Ensure there is sufficient space and correct alignment for 194 * the timestamp if enabled 195 */ 196 struct { 197 __le16 channels[3]; 198 s64 ts __aligned(8); 199 } scan; 200 u8 bw_bits; 201 u32 slope_dur; 202 u32 slope_thres; 203 u32 range; 204 int ev_enable_state; 205 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */ 206 const struct bmc150_accel_chip_info *chip_info; 207 struct iio_mount_matrix orientation; 208 }; 209 210 static const struct { 211 int val; 212 int val2; 213 u8 bw_bits; 214 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08}, 215 {31, 260000, 0x09}, 216 {62, 500000, 0x0A}, 217 {125, 0, 0x0B}, 218 {250, 0, 0x0C}, 219 {500, 0, 0x0D}, 220 {1000, 0, 0x0E}, 221 {2000, 0, 0x0F} }; 222 223 static const struct { 224 int bw_bits; 225 int msec; 226 } bmc150_accel_sample_upd_time[] = { {0x08, 64}, 227 {0x09, 32}, 228 {0x0A, 16}, 229 {0x0B, 8}, 230 {0x0C, 4}, 231 {0x0D, 2}, 232 {0x0E, 1}, 233 {0x0F, 1} }; 234 235 static const struct { 236 int sleep_dur; 237 u8 reg_value; 238 } bmc150_accel_sleep_value_table[] = { {0, 0}, 239 {500, BMC150_ACCEL_SLEEP_500_MICRO}, 240 {1000, BMC150_ACCEL_SLEEP_1_MS}, 241 {2000, BMC150_ACCEL_SLEEP_2_MS}, 242 {4000, BMC150_ACCEL_SLEEP_4_MS}, 243 {6000, BMC150_ACCEL_SLEEP_6_MS}, 244 {10000, BMC150_ACCEL_SLEEP_10_MS}, 245 {25000, BMC150_ACCEL_SLEEP_25_MS}, 246 {50000, BMC150_ACCEL_SLEEP_50_MS}, 247 {100000, BMC150_ACCEL_SLEEP_100_MS}, 248 {500000, BMC150_ACCEL_SLEEP_500_MS}, 249 {1000000, BMC150_ACCEL_SLEEP_1_SEC} }; 250 251 const struct regmap_config bmc150_regmap_conf = { 252 .reg_bits = 8, 253 .val_bits = 8, 254 .max_register = 0x3f, 255 }; 256 EXPORT_SYMBOL_GPL(bmc150_regmap_conf); 257 258 static int bmc150_accel_set_mode(struct bmc150_accel_data *data, 259 enum bmc150_power_modes mode, 260 int dur_us) 261 { 262 struct device *dev = regmap_get_device(data->regmap); 263 int i; 264 int ret; 265 u8 lpw_bits; 266 int dur_val = -1; 267 268 if (dur_us > 0) { 269 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table); 270 ++i) { 271 if (bmc150_accel_sleep_value_table[i].sleep_dur == 272 dur_us) 273 dur_val = 274 bmc150_accel_sleep_value_table[i].reg_value; 275 } 276 } else { 277 dur_val = 0; 278 } 279 280 if (dur_val < 0) 281 return -EINVAL; 282 283 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT; 284 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT); 285 286 dev_dbg(dev, "Set Mode bits %x\n", lpw_bits); 287 288 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits); 289 if (ret < 0) { 290 dev_err(dev, "Error writing reg_pmu_lpw\n"); 291 return ret; 292 } 293 294 return 0; 295 } 296 297 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val, 298 int val2) 299 { 300 int i; 301 int ret; 302 303 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) { 304 if (bmc150_accel_samp_freq_table[i].val == val && 305 bmc150_accel_samp_freq_table[i].val2 == val2) { 306 ret = regmap_write(data->regmap, 307 BMC150_ACCEL_REG_PMU_BW, 308 bmc150_accel_samp_freq_table[i].bw_bits); 309 if (ret < 0) 310 return ret; 311 312 data->bw_bits = 313 bmc150_accel_samp_freq_table[i].bw_bits; 314 return 0; 315 } 316 } 317 318 return -EINVAL; 319 } 320 321 static int bmc150_accel_update_slope(struct bmc150_accel_data *data) 322 { 323 struct device *dev = regmap_get_device(data->regmap); 324 int ret; 325 326 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6, 327 data->slope_thres); 328 if (ret < 0) { 329 dev_err(dev, "Error writing reg_int_6\n"); 330 return ret; 331 } 332 333 ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5, 334 BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur); 335 if (ret < 0) { 336 dev_err(dev, "Error updating reg_int_5\n"); 337 return ret; 338 } 339 340 dev_dbg(dev, "%x %x\n", data->slope_thres, data->slope_dur); 341 342 return ret; 343 } 344 345 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t, 346 bool state) 347 { 348 if (state) 349 return bmc150_accel_update_slope(t->data); 350 351 return 0; 352 } 353 354 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val, 355 int *val2) 356 { 357 int i; 358 359 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) { 360 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) { 361 *val = bmc150_accel_samp_freq_table[i].val; 362 *val2 = bmc150_accel_samp_freq_table[i].val2; 363 return IIO_VAL_INT_PLUS_MICRO; 364 } 365 } 366 367 return -EINVAL; 368 } 369 370 #ifdef CONFIG_PM 371 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data) 372 { 373 int i; 374 375 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) { 376 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits) 377 return bmc150_accel_sample_upd_time[i].msec; 378 } 379 380 return BMC150_ACCEL_MAX_STARTUP_TIME_MS; 381 } 382 383 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on) 384 { 385 struct device *dev = regmap_get_device(data->regmap); 386 int ret; 387 388 if (on) { 389 ret = pm_runtime_get_sync(dev); 390 } else { 391 pm_runtime_mark_last_busy(dev); 392 ret = pm_runtime_put_autosuspend(dev); 393 } 394 395 if (ret < 0) { 396 dev_err(dev, 397 "Failed: %s for %d\n", __func__, on); 398 if (on) 399 pm_runtime_put_noidle(dev); 400 401 return ret; 402 } 403 404 return 0; 405 } 406 #else 407 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on) 408 { 409 return 0; 410 } 411 #endif 412 413 static const struct bmc150_accel_interrupt_info { 414 u8 map_reg; 415 u8 map_bitmask; 416 u8 en_reg; 417 u8 en_bitmask; 418 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = { 419 { /* data ready interrupt */ 420 .map_reg = BMC150_ACCEL_REG_INT_MAP_1, 421 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA, 422 .en_reg = BMC150_ACCEL_REG_INT_EN_1, 423 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN, 424 }, 425 { /* motion interrupt */ 426 .map_reg = BMC150_ACCEL_REG_INT_MAP_0, 427 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE, 428 .en_reg = BMC150_ACCEL_REG_INT_EN_0, 429 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X | 430 BMC150_ACCEL_INT_EN_BIT_SLP_Y | 431 BMC150_ACCEL_INT_EN_BIT_SLP_Z 432 }, 433 { /* fifo watermark interrupt */ 434 .map_reg = BMC150_ACCEL_REG_INT_MAP_1, 435 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM, 436 .en_reg = BMC150_ACCEL_REG_INT_EN_1, 437 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN, 438 }, 439 }; 440 441 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev, 442 struct bmc150_accel_data *data) 443 { 444 int i; 445 446 for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++) 447 data->interrupts[i].info = &bmc150_accel_interrupts[i]; 448 } 449 450 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i, 451 bool state) 452 { 453 struct device *dev = regmap_get_device(data->regmap); 454 struct bmc150_accel_interrupt *intr = &data->interrupts[i]; 455 const struct bmc150_accel_interrupt_info *info = intr->info; 456 int ret; 457 458 if (state) { 459 if (atomic_inc_return(&intr->users) > 1) 460 return 0; 461 } else { 462 if (atomic_dec_return(&intr->users) > 0) 463 return 0; 464 } 465 466 /* 467 * We will expect the enable and disable to do operation in reverse 468 * order. This will happen here anyway, as our resume operation uses 469 * sync mode runtime pm calls. The suspend operation will be delayed 470 * by autosuspend delay. 471 * So the disable operation will still happen in reverse order of 472 * enable operation. When runtime pm is disabled the mode is always on, 473 * so sequence doesn't matter. 474 */ 475 ret = bmc150_accel_set_power_state(data, state); 476 if (ret < 0) 477 return ret; 478 479 /* map the interrupt to the appropriate pins */ 480 ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask, 481 (state ? info->map_bitmask : 0)); 482 if (ret < 0) { 483 dev_err(dev, "Error updating reg_int_map\n"); 484 goto out_fix_power_state; 485 } 486 487 /* enable/disable the interrupt */ 488 ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask, 489 (state ? info->en_bitmask : 0)); 490 if (ret < 0) { 491 dev_err(dev, "Error updating reg_int_en\n"); 492 goto out_fix_power_state; 493 } 494 495 return 0; 496 497 out_fix_power_state: 498 bmc150_accel_set_power_state(data, false); 499 return ret; 500 } 501 502 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val) 503 { 504 struct device *dev = regmap_get_device(data->regmap); 505 int ret, i; 506 507 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) { 508 if (data->chip_info->scale_table[i].scale == val) { 509 ret = regmap_write(data->regmap, 510 BMC150_ACCEL_REG_PMU_RANGE, 511 data->chip_info->scale_table[i].reg_range); 512 if (ret < 0) { 513 dev_err(dev, "Error writing pmu_range\n"); 514 return ret; 515 } 516 517 data->range = data->chip_info->scale_table[i].reg_range; 518 return 0; 519 } 520 } 521 522 return -EINVAL; 523 } 524 525 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val) 526 { 527 struct device *dev = regmap_get_device(data->regmap); 528 int ret; 529 unsigned int value; 530 531 mutex_lock(&data->mutex); 532 533 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value); 534 if (ret < 0) { 535 dev_err(dev, "Error reading reg_temp\n"); 536 mutex_unlock(&data->mutex); 537 return ret; 538 } 539 *val = sign_extend32(value, 7); 540 541 mutex_unlock(&data->mutex); 542 543 return IIO_VAL_INT; 544 } 545 546 static int bmc150_accel_get_axis(struct bmc150_accel_data *data, 547 struct iio_chan_spec const *chan, 548 int *val) 549 { 550 struct device *dev = regmap_get_device(data->regmap); 551 int ret; 552 int axis = chan->scan_index; 553 __le16 raw_val; 554 555 mutex_lock(&data->mutex); 556 ret = bmc150_accel_set_power_state(data, true); 557 if (ret < 0) { 558 mutex_unlock(&data->mutex); 559 return ret; 560 } 561 562 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis), 563 &raw_val, sizeof(raw_val)); 564 if (ret < 0) { 565 dev_err(dev, "Error reading axis %d\n", axis); 566 bmc150_accel_set_power_state(data, false); 567 mutex_unlock(&data->mutex); 568 return ret; 569 } 570 *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift, 571 chan->scan_type.realbits - 1); 572 ret = bmc150_accel_set_power_state(data, false); 573 mutex_unlock(&data->mutex); 574 if (ret < 0) 575 return ret; 576 577 return IIO_VAL_INT; 578 } 579 580 static int bmc150_accel_read_raw(struct iio_dev *indio_dev, 581 struct iio_chan_spec const *chan, 582 int *val, int *val2, long mask) 583 { 584 struct bmc150_accel_data *data = iio_priv(indio_dev); 585 int ret; 586 587 switch (mask) { 588 case IIO_CHAN_INFO_RAW: 589 switch (chan->type) { 590 case IIO_TEMP: 591 return bmc150_accel_get_temp(data, val); 592 case IIO_ACCEL: 593 if (iio_buffer_enabled(indio_dev)) 594 return -EBUSY; 595 else 596 return bmc150_accel_get_axis(data, chan, val); 597 default: 598 return -EINVAL; 599 } 600 case IIO_CHAN_INFO_OFFSET: 601 if (chan->type == IIO_TEMP) { 602 *val = BMC150_ACCEL_TEMP_CENTER_VAL; 603 return IIO_VAL_INT; 604 } else { 605 return -EINVAL; 606 } 607 case IIO_CHAN_INFO_SCALE: 608 *val = 0; 609 switch (chan->type) { 610 case IIO_TEMP: 611 *val2 = 500000; 612 return IIO_VAL_INT_PLUS_MICRO; 613 case IIO_ACCEL: 614 { 615 int i; 616 const struct bmc150_scale_info *si; 617 int st_size = ARRAY_SIZE(data->chip_info->scale_table); 618 619 for (i = 0; i < st_size; ++i) { 620 si = &data->chip_info->scale_table[i]; 621 if (si->reg_range == data->range) { 622 *val2 = si->scale; 623 return IIO_VAL_INT_PLUS_MICRO; 624 } 625 } 626 return -EINVAL; 627 } 628 default: 629 return -EINVAL; 630 } 631 case IIO_CHAN_INFO_SAMP_FREQ: 632 mutex_lock(&data->mutex); 633 ret = bmc150_accel_get_bw(data, val, val2); 634 mutex_unlock(&data->mutex); 635 return ret; 636 default: 637 return -EINVAL; 638 } 639 } 640 641 static int bmc150_accel_write_raw(struct iio_dev *indio_dev, 642 struct iio_chan_spec const *chan, 643 int val, int val2, long mask) 644 { 645 struct bmc150_accel_data *data = iio_priv(indio_dev); 646 int ret; 647 648 switch (mask) { 649 case IIO_CHAN_INFO_SAMP_FREQ: 650 mutex_lock(&data->mutex); 651 ret = bmc150_accel_set_bw(data, val, val2); 652 mutex_unlock(&data->mutex); 653 break; 654 case IIO_CHAN_INFO_SCALE: 655 if (val) 656 return -EINVAL; 657 658 mutex_lock(&data->mutex); 659 ret = bmc150_accel_set_scale(data, val2); 660 mutex_unlock(&data->mutex); 661 return ret; 662 default: 663 ret = -EINVAL; 664 } 665 666 return ret; 667 } 668 669 static int bmc150_accel_read_event(struct iio_dev *indio_dev, 670 const struct iio_chan_spec *chan, 671 enum iio_event_type type, 672 enum iio_event_direction dir, 673 enum iio_event_info info, 674 int *val, int *val2) 675 { 676 struct bmc150_accel_data *data = iio_priv(indio_dev); 677 678 *val2 = 0; 679 switch (info) { 680 case IIO_EV_INFO_VALUE: 681 *val = data->slope_thres; 682 break; 683 case IIO_EV_INFO_PERIOD: 684 *val = data->slope_dur; 685 break; 686 default: 687 return -EINVAL; 688 } 689 690 return IIO_VAL_INT; 691 } 692 693 static int bmc150_accel_write_event(struct iio_dev *indio_dev, 694 const struct iio_chan_spec *chan, 695 enum iio_event_type type, 696 enum iio_event_direction dir, 697 enum iio_event_info info, 698 int val, int val2) 699 { 700 struct bmc150_accel_data *data = iio_priv(indio_dev); 701 702 if (data->ev_enable_state) 703 return -EBUSY; 704 705 switch (info) { 706 case IIO_EV_INFO_VALUE: 707 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK; 708 break; 709 case IIO_EV_INFO_PERIOD: 710 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK; 711 break; 712 default: 713 return -EINVAL; 714 } 715 716 return 0; 717 } 718 719 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev, 720 const struct iio_chan_spec *chan, 721 enum iio_event_type type, 722 enum iio_event_direction dir) 723 { 724 struct bmc150_accel_data *data = iio_priv(indio_dev); 725 726 return data->ev_enable_state; 727 } 728 729 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev, 730 const struct iio_chan_spec *chan, 731 enum iio_event_type type, 732 enum iio_event_direction dir, 733 int state) 734 { 735 struct bmc150_accel_data *data = iio_priv(indio_dev); 736 int ret; 737 738 if (state == data->ev_enable_state) 739 return 0; 740 741 mutex_lock(&data->mutex); 742 743 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION, 744 state); 745 if (ret < 0) { 746 mutex_unlock(&data->mutex); 747 return ret; 748 } 749 750 data->ev_enable_state = state; 751 mutex_unlock(&data->mutex); 752 753 return 0; 754 } 755 756 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev, 757 struct iio_trigger *trig) 758 { 759 struct bmc150_accel_data *data = iio_priv(indio_dev); 760 int i; 761 762 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { 763 if (data->triggers[i].indio_trig == trig) 764 return 0; 765 } 766 767 return -EINVAL; 768 } 769 770 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev, 771 struct device_attribute *attr, 772 char *buf) 773 { 774 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 775 struct bmc150_accel_data *data = iio_priv(indio_dev); 776 int wm; 777 778 mutex_lock(&data->mutex); 779 wm = data->watermark; 780 mutex_unlock(&data->mutex); 781 782 return sprintf(buf, "%d\n", wm); 783 } 784 785 static ssize_t bmc150_accel_get_fifo_state(struct device *dev, 786 struct device_attribute *attr, 787 char *buf) 788 { 789 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 790 struct bmc150_accel_data *data = iio_priv(indio_dev); 791 bool state; 792 793 mutex_lock(&data->mutex); 794 state = data->fifo_mode; 795 mutex_unlock(&data->mutex); 796 797 return sprintf(buf, "%d\n", state); 798 } 799 800 static const struct iio_mount_matrix * 801 bmc150_accel_get_mount_matrix(const struct iio_dev *indio_dev, 802 const struct iio_chan_spec *chan) 803 { 804 struct bmc150_accel_data *data = iio_priv(indio_dev); 805 806 return &data->orientation; 807 } 808 809 static const struct iio_chan_spec_ext_info bmc150_accel_ext_info[] = { 810 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmc150_accel_get_mount_matrix), 811 { } 812 }; 813 814 static IIO_CONST_ATTR(hwfifo_watermark_min, "1"); 815 static IIO_CONST_ATTR(hwfifo_watermark_max, 816 __stringify(BMC150_ACCEL_FIFO_LENGTH)); 817 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO, 818 bmc150_accel_get_fifo_state, NULL, 0); 819 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO, 820 bmc150_accel_get_fifo_watermark, NULL, 0); 821 822 static const struct attribute *bmc150_accel_fifo_attributes[] = { 823 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr, 824 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr, 825 &iio_dev_attr_hwfifo_watermark.dev_attr.attr, 826 &iio_dev_attr_hwfifo_enabled.dev_attr.attr, 827 NULL, 828 }; 829 830 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val) 831 { 832 struct bmc150_accel_data *data = iio_priv(indio_dev); 833 834 if (val > BMC150_ACCEL_FIFO_LENGTH) 835 val = BMC150_ACCEL_FIFO_LENGTH; 836 837 mutex_lock(&data->mutex); 838 data->watermark = val; 839 mutex_unlock(&data->mutex); 840 841 return 0; 842 } 843 844 /* 845 * We must read at least one full frame in one burst, otherwise the rest of the 846 * frame data is discarded. 847 */ 848 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data, 849 char *buffer, int samples) 850 { 851 struct device *dev = regmap_get_device(data->regmap); 852 int sample_length = 3 * 2; 853 int ret; 854 int total_length = samples * sample_length; 855 856 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA, 857 buffer, total_length); 858 if (ret) 859 dev_err(dev, 860 "Error transferring data from fifo: %d\n", ret); 861 862 return ret; 863 } 864 865 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev, 866 unsigned samples, bool irq) 867 { 868 struct bmc150_accel_data *data = iio_priv(indio_dev); 869 struct device *dev = regmap_get_device(data->regmap); 870 int ret, i; 871 u8 count; 872 u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3]; 873 int64_t tstamp; 874 uint64_t sample_period; 875 unsigned int val; 876 877 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val); 878 if (ret < 0) { 879 dev_err(dev, "Error reading reg_fifo_status\n"); 880 return ret; 881 } 882 883 count = val & 0x7F; 884 885 if (!count) 886 return 0; 887 888 /* 889 * If we getting called from IRQ handler we know the stored timestamp is 890 * fairly accurate for the last stored sample. Otherwise, if we are 891 * called as a result of a read operation from userspace and hence 892 * before the watermark interrupt was triggered, take a timestamp 893 * now. We can fall anywhere in between two samples so the error in this 894 * case is at most one sample period. 895 */ 896 if (!irq) { 897 data->old_timestamp = data->timestamp; 898 data->timestamp = iio_get_time_ns(indio_dev); 899 } 900 901 /* 902 * Approximate timestamps for each of the sample based on the sampling 903 * frequency, timestamp for last sample and number of samples. 904 * 905 * Note that we can't use the current bandwidth settings to compute the 906 * sample period because the sample rate varies with the device 907 * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That 908 * small variation adds when we store a large number of samples and 909 * creates significant jitter between the last and first samples in 910 * different batches (e.g. 32ms vs 21ms). 911 * 912 * To avoid this issue we compute the actual sample period ourselves 913 * based on the timestamp delta between the last two flush operations. 914 */ 915 sample_period = (data->timestamp - data->old_timestamp); 916 do_div(sample_period, count); 917 tstamp = data->timestamp - (count - 1) * sample_period; 918 919 if (samples && count > samples) 920 count = samples; 921 922 ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count); 923 if (ret) 924 return ret; 925 926 /* 927 * Ideally we want the IIO core to handle the demux when running in fifo 928 * mode but not when running in triggered buffer mode. Unfortunately 929 * this does not seem to be possible, so stick with driver demux for 930 * now. 931 */ 932 for (i = 0; i < count; i++) { 933 int j, bit; 934 935 j = 0; 936 for_each_set_bit(bit, indio_dev->active_scan_mask, 937 indio_dev->masklength) 938 memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit], 939 sizeof(data->scan.channels[0])); 940 941 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan, 942 tstamp); 943 944 tstamp += sample_period; 945 } 946 947 return count; 948 } 949 950 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples) 951 { 952 struct bmc150_accel_data *data = iio_priv(indio_dev); 953 int ret; 954 955 mutex_lock(&data->mutex); 956 ret = __bmc150_accel_fifo_flush(indio_dev, samples, false); 957 mutex_unlock(&data->mutex); 958 959 return ret; 960 } 961 962 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL( 963 "15.620000 31.260000 62.50000 125 250 500 1000 2000"); 964 965 static struct attribute *bmc150_accel_attributes[] = { 966 &iio_const_attr_sampling_frequency_available.dev_attr.attr, 967 NULL, 968 }; 969 970 static const struct attribute_group bmc150_accel_attrs_group = { 971 .attrs = bmc150_accel_attributes, 972 }; 973 974 static const struct iio_event_spec bmc150_accel_event = { 975 .type = IIO_EV_TYPE_ROC, 976 .dir = IIO_EV_DIR_EITHER, 977 .mask_separate = BIT(IIO_EV_INFO_VALUE) | 978 BIT(IIO_EV_INFO_ENABLE) | 979 BIT(IIO_EV_INFO_PERIOD) 980 }; 981 982 #define BMC150_ACCEL_CHANNEL(_axis, bits) { \ 983 .type = IIO_ACCEL, \ 984 .modified = 1, \ 985 .channel2 = IIO_MOD_##_axis, \ 986 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 987 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \ 988 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 989 .scan_index = AXIS_##_axis, \ 990 .scan_type = { \ 991 .sign = 's', \ 992 .realbits = (bits), \ 993 .storagebits = 16, \ 994 .shift = 16 - (bits), \ 995 .endianness = IIO_LE, \ 996 }, \ 997 .ext_info = bmc150_accel_ext_info, \ 998 .event_spec = &bmc150_accel_event, \ 999 .num_event_specs = 1 \ 1000 } 1001 1002 #define BMC150_ACCEL_CHANNELS(bits) { \ 1003 { \ 1004 .type = IIO_TEMP, \ 1005 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 1006 BIT(IIO_CHAN_INFO_SCALE) | \ 1007 BIT(IIO_CHAN_INFO_OFFSET), \ 1008 .scan_index = -1, \ 1009 }, \ 1010 BMC150_ACCEL_CHANNEL(X, bits), \ 1011 BMC150_ACCEL_CHANNEL(Y, bits), \ 1012 BMC150_ACCEL_CHANNEL(Z, bits), \ 1013 IIO_CHAN_SOFT_TIMESTAMP(3), \ 1014 } 1015 1016 static const struct iio_chan_spec bma222e_accel_channels[] = 1017 BMC150_ACCEL_CHANNELS(8); 1018 static const struct iio_chan_spec bma250e_accel_channels[] = 1019 BMC150_ACCEL_CHANNELS(10); 1020 static const struct iio_chan_spec bmc150_accel_channels[] = 1021 BMC150_ACCEL_CHANNELS(12); 1022 static const struct iio_chan_spec bma280_accel_channels[] = 1023 BMC150_ACCEL_CHANNELS(14); 1024 1025 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = { 1026 [bmc150] = { 1027 .name = "BMC150A", 1028 .chip_id = 0xFA, 1029 .channels = bmc150_accel_channels, 1030 .num_channels = ARRAY_SIZE(bmc150_accel_channels), 1031 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, 1032 {19122, BMC150_ACCEL_DEF_RANGE_4G}, 1033 {38344, BMC150_ACCEL_DEF_RANGE_8G}, 1034 {76590, BMC150_ACCEL_DEF_RANGE_16G} }, 1035 }, 1036 [bmi055] = { 1037 .name = "BMI055A", 1038 .chip_id = 0xFA, 1039 .channels = bmc150_accel_channels, 1040 .num_channels = ARRAY_SIZE(bmc150_accel_channels), 1041 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, 1042 {19122, BMC150_ACCEL_DEF_RANGE_4G}, 1043 {38344, BMC150_ACCEL_DEF_RANGE_8G}, 1044 {76590, BMC150_ACCEL_DEF_RANGE_16G} }, 1045 }, 1046 [bma255] = { 1047 .name = "BMA0255", 1048 .chip_id = 0xFA, 1049 .channels = bmc150_accel_channels, 1050 .num_channels = ARRAY_SIZE(bmc150_accel_channels), 1051 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G}, 1052 {19122, BMC150_ACCEL_DEF_RANGE_4G}, 1053 {38344, BMC150_ACCEL_DEF_RANGE_8G}, 1054 {76590, BMC150_ACCEL_DEF_RANGE_16G} }, 1055 }, 1056 [bma250e] = { 1057 .name = "BMA250E", 1058 .chip_id = 0xF9, 1059 .channels = bma250e_accel_channels, 1060 .num_channels = ARRAY_SIZE(bma250e_accel_channels), 1061 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G}, 1062 {76590, BMC150_ACCEL_DEF_RANGE_4G}, 1063 {153277, BMC150_ACCEL_DEF_RANGE_8G}, 1064 {306457, BMC150_ACCEL_DEF_RANGE_16G} }, 1065 }, 1066 [bma222e] = { 1067 .name = "BMA222E", 1068 .chip_id = 0xF8, 1069 .channels = bma222e_accel_channels, 1070 .num_channels = ARRAY_SIZE(bma222e_accel_channels), 1071 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G}, 1072 {306457, BMC150_ACCEL_DEF_RANGE_4G}, 1073 {612915, BMC150_ACCEL_DEF_RANGE_8G}, 1074 {1225831, BMC150_ACCEL_DEF_RANGE_16G} }, 1075 }, 1076 [bma280] = { 1077 .name = "BMA0280", 1078 .chip_id = 0xFB, 1079 .channels = bma280_accel_channels, 1080 .num_channels = ARRAY_SIZE(bma280_accel_channels), 1081 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G}, 1082 {4785, BMC150_ACCEL_DEF_RANGE_4G}, 1083 {9581, BMC150_ACCEL_DEF_RANGE_8G}, 1084 {19152, BMC150_ACCEL_DEF_RANGE_16G} }, 1085 }, 1086 }; 1087 1088 static const struct iio_info bmc150_accel_info = { 1089 .attrs = &bmc150_accel_attrs_group, 1090 .read_raw = bmc150_accel_read_raw, 1091 .write_raw = bmc150_accel_write_raw, 1092 .read_event_value = bmc150_accel_read_event, 1093 .write_event_value = bmc150_accel_write_event, 1094 .write_event_config = bmc150_accel_write_event_config, 1095 .read_event_config = bmc150_accel_read_event_config, 1096 }; 1097 1098 static const struct iio_info bmc150_accel_info_fifo = { 1099 .attrs = &bmc150_accel_attrs_group, 1100 .read_raw = bmc150_accel_read_raw, 1101 .write_raw = bmc150_accel_write_raw, 1102 .read_event_value = bmc150_accel_read_event, 1103 .write_event_value = bmc150_accel_write_event, 1104 .write_event_config = bmc150_accel_write_event_config, 1105 .read_event_config = bmc150_accel_read_event_config, 1106 .validate_trigger = bmc150_accel_validate_trigger, 1107 .hwfifo_set_watermark = bmc150_accel_set_watermark, 1108 .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush, 1109 }; 1110 1111 static const unsigned long bmc150_accel_scan_masks[] = { 1112 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z), 1113 0}; 1114 1115 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p) 1116 { 1117 struct iio_poll_func *pf = p; 1118 struct iio_dev *indio_dev = pf->indio_dev; 1119 struct bmc150_accel_data *data = iio_priv(indio_dev); 1120 int ret; 1121 1122 mutex_lock(&data->mutex); 1123 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_REG_XOUT_L, 1124 data->buffer, AXIS_MAX * 2); 1125 mutex_unlock(&data->mutex); 1126 if (ret < 0) 1127 goto err_read; 1128 1129 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer, 1130 pf->timestamp); 1131 err_read: 1132 iio_trigger_notify_done(indio_dev->trig); 1133 1134 return IRQ_HANDLED; 1135 } 1136 1137 static int bmc150_accel_trig_try_reen(struct iio_trigger *trig) 1138 { 1139 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig); 1140 struct bmc150_accel_data *data = t->data; 1141 struct device *dev = regmap_get_device(data->regmap); 1142 int ret; 1143 1144 /* new data interrupts don't need ack */ 1145 if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY]) 1146 return 0; 1147 1148 mutex_lock(&data->mutex); 1149 /* clear any latched interrupt */ 1150 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1151 BMC150_ACCEL_INT_MODE_LATCH_INT | 1152 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1153 mutex_unlock(&data->mutex); 1154 if (ret < 0) { 1155 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1156 return ret; 1157 } 1158 1159 return 0; 1160 } 1161 1162 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig, 1163 bool state) 1164 { 1165 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig); 1166 struct bmc150_accel_data *data = t->data; 1167 int ret; 1168 1169 mutex_lock(&data->mutex); 1170 1171 if (t->enabled == state) { 1172 mutex_unlock(&data->mutex); 1173 return 0; 1174 } 1175 1176 if (t->setup) { 1177 ret = t->setup(t, state); 1178 if (ret < 0) { 1179 mutex_unlock(&data->mutex); 1180 return ret; 1181 } 1182 } 1183 1184 ret = bmc150_accel_set_interrupt(data, t->intr, state); 1185 if (ret < 0) { 1186 mutex_unlock(&data->mutex); 1187 return ret; 1188 } 1189 1190 t->enabled = state; 1191 1192 mutex_unlock(&data->mutex); 1193 1194 return ret; 1195 } 1196 1197 static const struct iio_trigger_ops bmc150_accel_trigger_ops = { 1198 .set_trigger_state = bmc150_accel_trigger_set_state, 1199 .try_reenable = bmc150_accel_trig_try_reen, 1200 }; 1201 1202 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev) 1203 { 1204 struct bmc150_accel_data *data = iio_priv(indio_dev); 1205 struct device *dev = regmap_get_device(data->regmap); 1206 int dir; 1207 int ret; 1208 unsigned int val; 1209 1210 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val); 1211 if (ret < 0) { 1212 dev_err(dev, "Error reading reg_int_status_2\n"); 1213 return ret; 1214 } 1215 1216 if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN) 1217 dir = IIO_EV_DIR_FALLING; 1218 else 1219 dir = IIO_EV_DIR_RISING; 1220 1221 if (val & BMC150_ACCEL_ANY_MOTION_BIT_X) 1222 iio_push_event(indio_dev, 1223 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1224 0, 1225 IIO_MOD_X, 1226 IIO_EV_TYPE_ROC, 1227 dir), 1228 data->timestamp); 1229 1230 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y) 1231 iio_push_event(indio_dev, 1232 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1233 0, 1234 IIO_MOD_Y, 1235 IIO_EV_TYPE_ROC, 1236 dir), 1237 data->timestamp); 1238 1239 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z) 1240 iio_push_event(indio_dev, 1241 IIO_MOD_EVENT_CODE(IIO_ACCEL, 1242 0, 1243 IIO_MOD_Z, 1244 IIO_EV_TYPE_ROC, 1245 dir), 1246 data->timestamp); 1247 1248 return ret; 1249 } 1250 1251 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private) 1252 { 1253 struct iio_dev *indio_dev = private; 1254 struct bmc150_accel_data *data = iio_priv(indio_dev); 1255 struct device *dev = regmap_get_device(data->regmap); 1256 bool ack = false; 1257 int ret; 1258 1259 mutex_lock(&data->mutex); 1260 1261 if (data->fifo_mode) { 1262 ret = __bmc150_accel_fifo_flush(indio_dev, 1263 BMC150_ACCEL_FIFO_LENGTH, true); 1264 if (ret > 0) 1265 ack = true; 1266 } 1267 1268 if (data->ev_enable_state) { 1269 ret = bmc150_accel_handle_roc_event(indio_dev); 1270 if (ret > 0) 1271 ack = true; 1272 } 1273 1274 if (ack) { 1275 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1276 BMC150_ACCEL_INT_MODE_LATCH_INT | 1277 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1278 if (ret) 1279 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1280 1281 ret = IRQ_HANDLED; 1282 } else { 1283 ret = IRQ_NONE; 1284 } 1285 1286 mutex_unlock(&data->mutex); 1287 1288 return ret; 1289 } 1290 1291 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private) 1292 { 1293 struct iio_dev *indio_dev = private; 1294 struct bmc150_accel_data *data = iio_priv(indio_dev); 1295 bool ack = false; 1296 int i; 1297 1298 data->old_timestamp = data->timestamp; 1299 data->timestamp = iio_get_time_ns(indio_dev); 1300 1301 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { 1302 if (data->triggers[i].enabled) { 1303 iio_trigger_poll(data->triggers[i].indio_trig); 1304 ack = true; 1305 break; 1306 } 1307 } 1308 1309 if (data->ev_enable_state || data->fifo_mode) 1310 return IRQ_WAKE_THREAD; 1311 1312 if (ack) 1313 return IRQ_HANDLED; 1314 1315 return IRQ_NONE; 1316 } 1317 1318 static const struct { 1319 int intr; 1320 const char *name; 1321 int (*setup)(struct bmc150_accel_trigger *t, bool state); 1322 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = { 1323 { 1324 .intr = 0, 1325 .name = "%s-dev%d", 1326 }, 1327 { 1328 .intr = 1, 1329 .name = "%s-any-motion-dev%d", 1330 .setup = bmc150_accel_any_motion_setup, 1331 }, 1332 }; 1333 1334 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data, 1335 int from) 1336 { 1337 int i; 1338 1339 for (i = from; i >= 0; i--) { 1340 if (data->triggers[i].indio_trig) { 1341 iio_trigger_unregister(data->triggers[i].indio_trig); 1342 data->triggers[i].indio_trig = NULL; 1343 } 1344 } 1345 } 1346 1347 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev, 1348 struct bmc150_accel_data *data) 1349 { 1350 struct device *dev = regmap_get_device(data->regmap); 1351 int i, ret; 1352 1353 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) { 1354 struct bmc150_accel_trigger *t = &data->triggers[i]; 1355 1356 t->indio_trig = devm_iio_trigger_alloc(dev, 1357 bmc150_accel_triggers[i].name, 1358 indio_dev->name, 1359 indio_dev->id); 1360 if (!t->indio_trig) { 1361 ret = -ENOMEM; 1362 break; 1363 } 1364 1365 t->indio_trig->dev.parent = dev; 1366 t->indio_trig->ops = &bmc150_accel_trigger_ops; 1367 t->intr = bmc150_accel_triggers[i].intr; 1368 t->data = data; 1369 t->setup = bmc150_accel_triggers[i].setup; 1370 iio_trigger_set_drvdata(t->indio_trig, t); 1371 1372 ret = iio_trigger_register(t->indio_trig); 1373 if (ret) 1374 break; 1375 } 1376 1377 if (ret) 1378 bmc150_accel_unregister_triggers(data, i - 1); 1379 1380 return ret; 1381 } 1382 1383 #define BMC150_ACCEL_FIFO_MODE_STREAM 0x80 1384 #define BMC150_ACCEL_FIFO_MODE_FIFO 0x40 1385 #define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00 1386 1387 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data) 1388 { 1389 struct device *dev = regmap_get_device(data->regmap); 1390 u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1; 1391 int ret; 1392 1393 ret = regmap_write(data->regmap, reg, data->fifo_mode); 1394 if (ret < 0) { 1395 dev_err(dev, "Error writing reg_fifo_config1\n"); 1396 return ret; 1397 } 1398 1399 if (!data->fifo_mode) 1400 return 0; 1401 1402 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0, 1403 data->watermark); 1404 if (ret < 0) 1405 dev_err(dev, "Error writing reg_fifo_config0\n"); 1406 1407 return ret; 1408 } 1409 1410 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev) 1411 { 1412 struct bmc150_accel_data *data = iio_priv(indio_dev); 1413 1414 return bmc150_accel_set_power_state(data, true); 1415 } 1416 1417 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev) 1418 { 1419 struct bmc150_accel_data *data = iio_priv(indio_dev); 1420 int ret = 0; 1421 1422 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) 1423 return 0; 1424 1425 mutex_lock(&data->mutex); 1426 1427 if (!data->watermark) 1428 goto out; 1429 1430 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, 1431 true); 1432 if (ret) 1433 goto out; 1434 1435 data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO; 1436 1437 ret = bmc150_accel_fifo_set_mode(data); 1438 if (ret) { 1439 data->fifo_mode = 0; 1440 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, 1441 false); 1442 } 1443 1444 out: 1445 mutex_unlock(&data->mutex); 1446 1447 return ret; 1448 } 1449 1450 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev) 1451 { 1452 struct bmc150_accel_data *data = iio_priv(indio_dev); 1453 1454 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED) 1455 return 0; 1456 1457 mutex_lock(&data->mutex); 1458 1459 if (!data->fifo_mode) 1460 goto out; 1461 1462 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false); 1463 __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false); 1464 data->fifo_mode = 0; 1465 bmc150_accel_fifo_set_mode(data); 1466 1467 out: 1468 mutex_unlock(&data->mutex); 1469 1470 return 0; 1471 } 1472 1473 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev) 1474 { 1475 struct bmc150_accel_data *data = iio_priv(indio_dev); 1476 1477 return bmc150_accel_set_power_state(data, false); 1478 } 1479 1480 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = { 1481 .preenable = bmc150_accel_buffer_preenable, 1482 .postenable = bmc150_accel_buffer_postenable, 1483 .predisable = bmc150_accel_buffer_predisable, 1484 .postdisable = bmc150_accel_buffer_postdisable, 1485 }; 1486 1487 static int bmc150_accel_chip_init(struct bmc150_accel_data *data) 1488 { 1489 struct device *dev = regmap_get_device(data->regmap); 1490 int ret, i; 1491 unsigned int val; 1492 1493 /* 1494 * Reset chip to get it in a known good state. A delay of 1.8ms after 1495 * reset is required according to the data sheets of supported chips. 1496 */ 1497 regmap_write(data->regmap, BMC150_ACCEL_REG_RESET, 1498 BMC150_ACCEL_RESET_VAL); 1499 usleep_range(1800, 2500); 1500 1501 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val); 1502 if (ret < 0) { 1503 dev_err(dev, "Error: Reading chip id\n"); 1504 return ret; 1505 } 1506 1507 dev_dbg(dev, "Chip Id %x\n", val); 1508 for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) { 1509 if (bmc150_accel_chip_info_tbl[i].chip_id == val) { 1510 data->chip_info = &bmc150_accel_chip_info_tbl[i]; 1511 break; 1512 } 1513 } 1514 1515 if (!data->chip_info) { 1516 dev_err(dev, "Invalid chip %x\n", val); 1517 return -ENODEV; 1518 } 1519 1520 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1521 if (ret < 0) 1522 return ret; 1523 1524 /* Set Bandwidth */ 1525 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0); 1526 if (ret < 0) 1527 return ret; 1528 1529 /* Set Default Range */ 1530 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE, 1531 BMC150_ACCEL_DEF_RANGE_4G); 1532 if (ret < 0) { 1533 dev_err(dev, "Error writing reg_pmu_range\n"); 1534 return ret; 1535 } 1536 1537 data->range = BMC150_ACCEL_DEF_RANGE_4G; 1538 1539 /* Set default slope duration and thresholds */ 1540 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD; 1541 data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION; 1542 ret = bmc150_accel_update_slope(data); 1543 if (ret < 0) 1544 return ret; 1545 1546 /* Set default as latched interrupts */ 1547 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1548 BMC150_ACCEL_INT_MODE_LATCH_INT | 1549 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1550 if (ret < 0) { 1551 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1552 return ret; 1553 } 1554 1555 return 0; 1556 } 1557 1558 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq, 1559 const char *name, bool block_supported) 1560 { 1561 const struct attribute **fifo_attrs; 1562 struct bmc150_accel_data *data; 1563 struct iio_dev *indio_dev; 1564 int ret; 1565 1566 indio_dev = devm_iio_device_alloc(dev, sizeof(*data)); 1567 if (!indio_dev) 1568 return -ENOMEM; 1569 1570 data = iio_priv(indio_dev); 1571 dev_set_drvdata(dev, indio_dev); 1572 data->irq = irq; 1573 1574 data->regmap = regmap; 1575 1576 ret = iio_read_mount_matrix(dev, "mount-matrix", 1577 &data->orientation); 1578 if (ret) 1579 return ret; 1580 1581 ret = bmc150_accel_chip_init(data); 1582 if (ret < 0) 1583 return ret; 1584 1585 mutex_init(&data->mutex); 1586 1587 indio_dev->channels = data->chip_info->channels; 1588 indio_dev->num_channels = data->chip_info->num_channels; 1589 indio_dev->name = name ? name : data->chip_info->name; 1590 indio_dev->available_scan_masks = bmc150_accel_scan_masks; 1591 indio_dev->modes = INDIO_DIRECT_MODE; 1592 indio_dev->info = &bmc150_accel_info; 1593 1594 if (block_supported) { 1595 indio_dev->modes |= INDIO_BUFFER_SOFTWARE; 1596 indio_dev->info = &bmc150_accel_info_fifo; 1597 fifo_attrs = bmc150_accel_fifo_attributes; 1598 } else { 1599 fifo_attrs = NULL; 1600 } 1601 1602 ret = iio_triggered_buffer_setup_ext(indio_dev, 1603 &iio_pollfunc_store_time, 1604 bmc150_accel_trigger_handler, 1605 &bmc150_accel_buffer_ops, 1606 fifo_attrs); 1607 if (ret < 0) { 1608 dev_err(dev, "Failed: iio triggered buffer setup\n"); 1609 return ret; 1610 } 1611 1612 if (data->irq > 0) { 1613 ret = devm_request_threaded_irq( 1614 dev, data->irq, 1615 bmc150_accel_irq_handler, 1616 bmc150_accel_irq_thread_handler, 1617 IRQF_TRIGGER_RISING, 1618 BMC150_ACCEL_IRQ_NAME, 1619 indio_dev); 1620 if (ret) 1621 goto err_buffer_cleanup; 1622 1623 /* 1624 * Set latched mode interrupt. While certain interrupts are 1625 * non-latched regardless of this settings (e.g. new data) we 1626 * want to use latch mode when we can to prevent interrupt 1627 * flooding. 1628 */ 1629 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH, 1630 BMC150_ACCEL_INT_MODE_LATCH_RESET); 1631 if (ret < 0) { 1632 dev_err(dev, "Error writing reg_int_rst_latch\n"); 1633 goto err_buffer_cleanup; 1634 } 1635 1636 bmc150_accel_interrupts_setup(indio_dev, data); 1637 1638 ret = bmc150_accel_triggers_setup(indio_dev, data); 1639 if (ret) 1640 goto err_buffer_cleanup; 1641 } 1642 1643 ret = pm_runtime_set_active(dev); 1644 if (ret) 1645 goto err_trigger_unregister; 1646 1647 pm_runtime_enable(dev); 1648 pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS); 1649 pm_runtime_use_autosuspend(dev); 1650 1651 ret = iio_device_register(indio_dev); 1652 if (ret < 0) { 1653 dev_err(dev, "Unable to register iio device\n"); 1654 goto err_trigger_unregister; 1655 } 1656 1657 return 0; 1658 1659 err_trigger_unregister: 1660 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1); 1661 err_buffer_cleanup: 1662 iio_triggered_buffer_cleanup(indio_dev); 1663 1664 return ret; 1665 } 1666 EXPORT_SYMBOL_GPL(bmc150_accel_core_probe); 1667 1668 int bmc150_accel_core_remove(struct device *dev) 1669 { 1670 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1671 struct bmc150_accel_data *data = iio_priv(indio_dev); 1672 1673 iio_device_unregister(indio_dev); 1674 1675 pm_runtime_disable(dev); 1676 pm_runtime_set_suspended(dev); 1677 pm_runtime_put_noidle(dev); 1678 1679 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1); 1680 1681 iio_triggered_buffer_cleanup(indio_dev); 1682 1683 mutex_lock(&data->mutex); 1684 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0); 1685 mutex_unlock(&data->mutex); 1686 1687 return 0; 1688 } 1689 EXPORT_SYMBOL_GPL(bmc150_accel_core_remove); 1690 1691 #ifdef CONFIG_PM_SLEEP 1692 static int bmc150_accel_suspend(struct device *dev) 1693 { 1694 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1695 struct bmc150_accel_data *data = iio_priv(indio_dev); 1696 1697 mutex_lock(&data->mutex); 1698 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0); 1699 mutex_unlock(&data->mutex); 1700 1701 return 0; 1702 } 1703 1704 static int bmc150_accel_resume(struct device *dev) 1705 { 1706 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1707 struct bmc150_accel_data *data = iio_priv(indio_dev); 1708 1709 mutex_lock(&data->mutex); 1710 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1711 bmc150_accel_fifo_set_mode(data); 1712 mutex_unlock(&data->mutex); 1713 1714 return 0; 1715 } 1716 #endif 1717 1718 #ifdef CONFIG_PM 1719 static int bmc150_accel_runtime_suspend(struct device *dev) 1720 { 1721 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1722 struct bmc150_accel_data *data = iio_priv(indio_dev); 1723 int ret; 1724 1725 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0); 1726 if (ret < 0) 1727 return -EAGAIN; 1728 1729 return 0; 1730 } 1731 1732 static int bmc150_accel_runtime_resume(struct device *dev) 1733 { 1734 struct iio_dev *indio_dev = dev_get_drvdata(dev); 1735 struct bmc150_accel_data *data = iio_priv(indio_dev); 1736 int ret; 1737 int sleep_val; 1738 1739 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0); 1740 if (ret < 0) 1741 return ret; 1742 ret = bmc150_accel_fifo_set_mode(data); 1743 if (ret < 0) 1744 return ret; 1745 1746 sleep_val = bmc150_accel_get_startup_times(data); 1747 if (sleep_val < 20) 1748 usleep_range(sleep_val * 1000, 20000); 1749 else 1750 msleep_interruptible(sleep_val); 1751 1752 return 0; 1753 } 1754 #endif 1755 1756 const struct dev_pm_ops bmc150_accel_pm_ops = { 1757 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume) 1758 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend, 1759 bmc150_accel_runtime_resume, NULL) 1760 }; 1761 EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops); 1762 1763 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>"); 1764 MODULE_LICENSE("GPL v2"); 1765 MODULE_DESCRIPTION("BMC150 accelerometer driver"); 1766